CN100395696C - Static memorizer interface device and data transmitting method thereof - Google Patents
Static memorizer interface device and data transmitting method thereof Download PDFInfo
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- CN100395696C CN100395696C CNB2006101097847A CN200610109784A CN100395696C CN 100395696 C CN100395696 C CN 100395696C CN B2006101097847 A CNB2006101097847 A CN B2006101097847A CN 200610109784 A CN200610109784 A CN 200610109784A CN 100395696 C CN100395696 C CN 100395696C
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Abstract
The provided static memory interface device comprises a logic control module and an address decoding module. The data transmission method comprises: the interface device monitors the read-write state of pipeline framework bus and the address state to generate corresponding signal; the former bus exchanges data with the memory according to generated signal. This invention allows the pipeline framework bus access the static memory by burst data transmission.
Description
Technical field
The present invention relates to digital ASIC (special IC) design and SOC (System-On-Chip, SOC (system on a chip)) field in the electronic technology field, relate in particular to a kind of static memorizer interface device and data transmission method thereof.
Background technology
Ahb bus (Advanced High-performance bus, Advanced High-performance Bus) is AMBA (Advanced Microcontroller Bus Architecture, advanced microprocessor bus framework) a kind of efficiently based on the bus of pipelined architecture in the standard is used to connect the high performance system module.It supports single (individual data transmission) mode and burst (bursty data transmission) mode, and all sequential of ahb bus are benchmark with the cycle of single clock all.
In large scale integrated circuit in order to utilize SRAM (Static Random AccessMemory, static memory) to be tended at the integrated static memory of chip internal by the characteristics of high speed access.But the individual data access mode is only supported in the visit to static memory usually, does not support the bursty data access mode.Therefore the pipeline bus of similar AHB can reduce the access efficiency of bus if only with the individual data access mode static memory is operated, and influences the overall performance of system.The low phenomenon of this total line use ratio exists during static memory outside bus on chip visit sheet too.
A kind of method of access static storer is in the prior art: the individual data access mode access static storer that adopts AHB.In the method, static memory write the sequential synoptic diagram as shown in Figure 1, when carrying out write operation, write enable, sheet choosing, write address, write data alignment, data write appropriate address in a clock; Static memory read the sequential synoptic diagram as shown in Figure 2, when carrying out read operation, read to enable, sheet choosing, read address align, the data delay of appropriate address was sent after a clock period, so the SRAM interface delay just can be read correct data after a clock period.
The shortcoming of the method for the access static storer of above-mentioned prior art is:
1, this method has reduced the performance of read operation.
In the method, write operation has wherein taken place 5 times in IMI under the single mode (internal memory interface, internal storage interface) module to the sequential synoptic diagram of SRAM module write data as shown in Figure 3 altogether, has to be invalid write operation 1 time.Haddr has sent address A1 to A5 respectively, hwdata sends data D1-D5 respectively in the following one-period of address, address A is through latching imi_addr and the imi_hwdata that exports the IMI interface with data D to, the hreadyout signal is high at the imi_hwdata data write cycle, and hresp is effective at this moment.During the 5th write operation, the undesirable generation mistake of hsize, wren invalidating signal, hreadyout drag down a clock period, and hresp becomes Error and continued for two cycles.
5 read operations have wherein taken place in the sequential synoptic diagram of IMI module read data from the SRAM module as shown in Figure 4 altogether under the single mode, and having 1 time is invalid read operation.After sent the A1 address of haddr, through to imi_addr, imi_rdata provided D1 after clapping through 2.D1 is through to hrdata, and hreadyout was dragged down in the effectively next clock period of the A1 of imi_addr, was effectively put height up to the D1 of imi_rdata, and hreadyout has waited for a clock period among Fig. 4.Haddr changed when hreadyout was effective, and the A2 address is issued to the SRAM of static memory, repeated read procedure.Imi_rden is a combinational logic, is low, hready and hsel (hready and hsel are the signal that ahb bus is brought, and do not express among Fig. 4) when all being high at hwrite, provides high level.Because read operation is under the single pattern, back hreadyout is sent in each read command all will postpone a clock period, waits pending data to read from the SRAM of static memory.In A5 address read when operation,, owing to provided the unsupported byte manipulation of IMI, so imi_rden is invalid, sense data invalid (among Fig. 4 * shown in part), and hresp responds the error in 2 cycles.
Therefore as seen, in the method, for reading the SRAM operation, the single mode when read operation at every turn, the stand-by period that all can produce one-period; For write operation, there is not the influence of this respect.When system took place frequently to read the content operation of SRAM, the time that ahb bus will be spent more Fei Yibei was used for waiting pending data to read from SRAM, has had a strong impact on system performance.
2, for some specific modules such as baseband processing module etc., register file and static memory unified addressing often, the data bit width of static memory is just fixing when producing, but but the data bit width of register file requires dynamic-configuration, for example an interface should carry out 16 visits, can carry out 32 visits again, for the visit of 32 bit data, 32 high 16 should be visited separately, low 16 can be visited again separately.Like this, single static memory interface just can not satisfy this demand.
Summary of the invention
The purpose of this invention is to provide a kind of static memorizer interface device and data transmission method thereof, thereby can go out the reference address of current static memory in the static memorizer interface device internal calculation, the bus that realizes pipelined architecture is with bursty data load mode access static storer.
The objective of the invention is to be achieved through the following technical solutions:
A kind of static memorizer interface device, the bus of pipelined architecture is carried out data interaction by this static memorizer interface device and static memory, and described static memorizer interface device specifically comprises:
Control logic module: the read-write state of the bus of monitoring pipelined architecture also carries out judgment processing, the bus and the static memory that produce pipelined architecture carry out mutual needed read-write control signal, and the read-write control signal that produces is passed to the address decoding module;
Address decoding module:, produce the address signal that carries out mutual data stream with static memory according to the address state of the bus of pipelined architecture and the read-write control signal that control logic module passes over.
Described static memorizer interface device also comprises:
Byte is selected module: carry out the total byte data bit width output byte selection marker of mutual data stream to static memory according to the address signal of address decoding module generation with static memory.
The total byte data bit width of described data stream is: 8 or 16 or 32 or 64 or 128.
Described static memorizer interface device also comprises read-write enable module and data transmission module,
Read-write enable module: the read-write control signal that passes over according to control logic module, the bus and the static memory that produce pipelined architecture carry out mutual reading enable signal or write enable signal, this are read enable signal or write enable signal to pass to static memory and data transmission module;
Data transmission module: read enable signal, bus from the static memory output data to pipelined architecture according to what the read-write enable module passed over; Perhaps, write enable signal according to what the read-write enable module passed over, from the bus output data of pipelined architecture to static memory.
Described static memorizer interface device also comprises:
Responsive feedback module: according to the conflict control signal that control logic module produces and passes over, feed back corresponding collision signal, make the bus of pipelined architecture not carry out the read operation of current period to the bus of pipelined architecture; According to the wrong control signal that control logic module produces and passes over, feed back the corresponding error signal to the bus of pipelined architecture.
Described control logic module comprises:
Transmission type mistake discrimination module: after the bus of pipelined architecture sends a write operation, when the back to back next clock period sends a read operation, send the conflict control signal to the responsive feedback module; And/or, when the bus generation error of transmission of pipelined architecture, send wrong control signal to the responsive feedback module.
Described address decoding module:
Computing module, the read-write control signal that first address that passes over according to the bus of pipelined architecture and control logic module pass over, utilize address counter, address adder, calculate with static memory and carry out the current address of mutual data stream and export to static memory; Perhaps
Delivery module, directly the first address that the pipelined architecture bus is passed over exports static memory to.
Described static memorizer interface device is applicable to bursty data load mode or individual data load mode.
Described static memorizer interface device is articulated on the bus of pipelined architecture or is embedded into static memory inside.
The bus of described pipelined architecture is: the subclass of advanced high-performance ahb bus or advanced extensive interface AXI bus or ahb bus.
Described steering logic submodule and described responsive feedback submodule are formed bus state machine, and described address decoding submodule and described read-write enable submodule and form address and read-write control state machine.
A kind of data transmission method of static memorizer interface device comprises:
The read-write state and the address state of the bus of static memorizer interface device monitoring pipelined architecture produce corresponding address signal; Address state according to the bus of described address signal and described pipelined architecture carries out data interaction according to setting data load mode and static memory.
Described method specifically comprises:
When ahb bus carries out data interaction with bursty data load mode and described static memory, the Data Receiving ratio of reading first address that ahb bus sends is read the address and is sent late two clock period, after, the read data that ahb bus sends receives than reading the address and sends a late clock period; The write data that ahb bus sends is than a late clock period of write address.
Described method also comprises:
After sending a write operation on the ahb bus, when the back to back next clock period sends a read operation, ahb bus is set to busy state, with static memorizer interface device wait condition feedback signal hreadyout signal clock period of zero clearing to ahb bus output, static memorizer interface device produces in this clock period, and to read enable signal invalid, after this clock period finished, ahb bus and hreadyout signal were set to normal condition.
As seen from the above technical solution provided by the invention, the present invention has designed a kind of multifunctional static memory interface arrangement, certainly increase the reference address that mechanism calculates current static memory in multifunctional static memory interface arrangement inside by the address, the bus that has realized pipelined architecture such as AHB is with bursty data load mode access static storer.Compare with prior art, have following advantage:
1, the static memory interface read data receives than reading the address and sends (and read control signal) late two clock period; Write data and write address send with sending, and the write address of static memory interface sent than a late clock period of write address of AHB interface.Under the burst mode, read the Data Receiving ratio of first address and read address transmission (and read control signal) late two clock period, all read continuously later on; Write data is than a late clock period of write address; When having reduced the burst read operation like this, reading the stand-by period of pipelined architecture bus (as ahb bus) access static storer improves bus access efficient.
2, special disposal has been made in read-write conversion, can have been eliminated the wait of the extra clock cycle that read-after-write brings, improved the access efficiency of pipelined architecture bus (as ahb bus) for static memory.
3, in the output signal of static memorizer interface device, increase byte and selected signal, thereby make this static memorizer interface device can support the visit of multidata position simultaneously, the visit of support custom data makes the adaptive surface of static memorizer interface device wider.
4, as the design of an IP unit, address wire of the present invention and data line can dispose or expand on demand, can external polytype static memory, and static storage can be positioned at chip internal, can be positioned at chip exterior.
Description of drawings
Fig. 1 is the synchronized sram sequential synoptic diagram of writing in the prior art;
Fig. 2 is the synchronized sram sequential synoptic diagram of reading in the prior art;
Fig. 3 is the write operation sequential synoptic diagram of IMI module interface under the single mode in the prior art;
Fig. 4 is the read operation sequential synoptic diagram of IMI module interface under the single mode in the prior art;
Fig. 5 is a system architecture synoptic diagram of having used static memorizer interface device of the present invention;
Fig. 6 is the interface synoptic diagram of the embodiment of static memorizer interface device of the present invention;
Fig. 7 is the structural representation of the embodiment of static memorizer interface device of the present invention;
Fig. 8 is that the inside read-write of static memorizer interface device of the present invention replaces the sequential synoptic diagram;
Fig. 9 replaces the read-write sequence synoptic diagram for the connection of static memorizer interface device of the present invention;
Figure 10 writes the sequential synoptic diagram of data to static memory for static memorizer interface device of the present invention under the burst mode;
When Figure 11 is the zero-address counter under the burst mode static memorizer interface device of the present invention from the static memory sense data time the sequential synoptic diagram;
Figure 12 is the sequential synoptic diagram when static memorizer interface device of the present invention was from the static memory sense data under the burst mode when address counter was arranged;
Figure 13 writes the sequential synoptic diagram for of static memorizer interface device of the present invention inside under the burst mode;
Figure 14 reads the sequential synoptic diagram for of static memorizer interface device of the present invention inside under the burst mode.
Embodiment
The invention provides a kind of static memorizer interface device and data transmission method thereof, core of the present invention is: the reference address that calculates current static memory in the address state and the corresponding read-write control signal of the bus of multifunctional static memory interface arrangement internal condition pipelined architecture.
Describe the present invention in detail below in conjunction with accompanying drawing, the described static memorizer interface device of this method has multiple function, used static memorizer interface device of the present invention system typical structure as shown in Figure 5.This multifunctional static memory interface arrangement can be articulated on the ahb bus of system together with arm processor, miscellaneous equipment (such as equipment O, equipment 1 and equipment 2), links to each other with register file with SRAM again.Ahb bus visits SRAM and register file by this multifunctional static memory interface arrangement.In actual applications, above-mentioned ahb bus can be used any subclass of AXI (advanced extensive interface) bus or ahb bus, replaces as AHB Lite bus.
The interface synoptic diagram of the embodiment of static memorizer interface device of the present invention as shown in Figure 6.AHB Slave bus interface signal links to each other with ahb bus, is used for ahb bus this static memorizer interface device is carried out read and write access, and SRAM and register file interface signal are used for this module accesses SRAM or register file.The Imi_addr signal is an address signal, Imi_rdata signal and Imi_wdata signal are respectively reading data signal and write data signal, Imi_rden signal and Imi_wren signal are respectively to read enable signal and write enable signal, the Imi_hwls signal is that byte is selected signal, be used for selecting the effective byte that reads and writes data, the Imi_hwls signal is invalid for the static memory of fixed data bit wide.
The structure of the embodiment of static memorizer interface device of the present invention as shown in Figure 7, specifically comprise: control logic module, address decoding module, byte are selected module, read-write enable module, responsive feedback module and data transmission module, introduce the function of above-mentioned each module below respectively.
1, control logic module.
Control logic module comprises: modules such as transmission type mistake discrimination module, bus monitor logic module, comparer.When ahb bus carries out data interaction by above-mentioned static memorizer interface device and static memory, control logic module is mainly monitored the read-write state of ahb bus, finish comparer by burst and carry out judgment processing, produce ahb bus and static memory and carry out mutual needed read-write control signal, and the data flow con-trol signal that produces is passed to the address decoding module.Control logic module produces the conflict control signal, and passes to the responsive feedback module also according to the read-write state of ahb bus current period and last one-period.Control logic module also produces wrong control signal, and passes to the responsive feedback module.
Transmission type mistake discrimination module: when ahb bus generation read/write conflict, promptly after ahb bus sends a write operation, when the back to back next clock period sends a read operation, described ahb bus is set to busy state, and be provided with that to read enable signal accordingly be invalid, send the conflict control signal to the responsive feedback module; After read/write conflict finishes, be provided with and read enable signal accordingly for effective;
When ahb bus generation error of transmission, send wrong control signal to the responsive feedback module.The condition that the mistake control signal produces is that ahb bus has sent unsupported burst transmission type of above-mentioned static memorizer interface device and unsupported data bit width.
In above-mentioned static memorizer interface device shown in Figure 7, the concrete processing procedure of control logic module is as follows:
The inside read-write of static memorizer interface device of the present invention replaces sequential chart as shown in Figure 8.At first, the bus monitor logic module in the control logic module judges whether the current period of ahb bus begins to carry out once new effective read-write operation, if meet read-write transmission condition, then new_read or new_write are effective.If meet the transport-type condition of makeing mistakes, then error is effective.
In said n ew_read or effective while of new_write, the bus monitor logic module produces simultaneously reads start signal read_start, represents that current AHB is that burst reads start address operation (perhaps single read operation).If last one-period is write operation (write_busy is effective), and and then this one-period is read operation, then read/write conflict has taken place in this one-period, read-write read_during_write signal simultaneously is set, task is finished clock period such as hreadyout signal demand, reads start signal read_start invalidating signal; By the time read_during_write is invalid following one-period, and reads then to write the read_after_write signal when effective, could be with imi_rden set, and this moment, read_start became effectively.
Burst read-write sign steering logic produces burst Status Flag burst_proc, reads burst Status Flag burst_rdproc, writes burst Status Flag burst_wrproc.Because the single mode can be regarded the operation of burst mode to first address as, so the single mode is also handled as a kind of special burst operation.Whether Burst finishes comparer and produces burst end mark burst_end, finish in order to control burst operation.The Burst termination condition be burst counter burst_cnt equal counter completely be worth the sign burst_cntmax.
The sequential synoptic diagram that the connection of static memorizer interface device of the present invention is is alternately read and write as shown in Figure 9.A1 to A2, A4 to A5 are all static memorizer interface device and write the sequential switching of reading.Because during write operation, write data will postpone a bat and provide, this moment the address of static memory interface and control signal belong to write operation all, therefore the hreadyout signal sends one in following one-period and claps invalid (output because hreadyout is a register, so can only just provide invalid signals in following one-period), show that this moment, bus was done, go up a write operation of clapping, the read operation of back to back second data must postpone one claps, and causes imi_rden to postpone a bat at last.
A2 to A3 is that static memorizer interface device is read the sequential switching of writing.Owing to read to be issued to static memory interface from the imi_addr address in the sequential, read the delays that two bats are arranged itself from static memory interface to data, therefore hreadyout continues to drag down a bat after imi_rden is effective, to set apart from the static memory reading of data.It is constant that this moment, ahb bus kept address and the control signal of A3, by the time hreadyout writes D3 when high once more, and reads A4.A4 is a write operation, and A5, A6 are read operation, the same A1 of principle of work, A2, A3.
2, address decoding module.
The read-write control signal that the address decoding module mainly passes over according to the steering logic submodule is carried out the address signal of mutual data stream and is passed to static memory with static memory from increasing the function generation by address prefetch mechanisms and address.The process of address prefetch mechanisms is that after start signal read_start was read in one of generation, MUX directly exported the address on the bus, to save a clock period.The address from the process that increases mechanism is, when producing a new read-write (the new_read/new_write signal is effective), the address on the bus is loaded into initial address register start_addr.The data flow con-trol signal that first address that address counter passes over according to the bus of pipelined architecture and control logic module pass over calculates the side-play amount burst_cnt of current operation address; Address adder obtains start address start_addr and address offset amount burst_cnt addition to carry out the current address of mutual data stream and be transferred to static memory with static memory.The address decoding module also passes to byte with the address signal that produces and selects module.
In above-mentioned static memorizer interface device shown in Figure 7, the address prefetch mechanisms of address decoding module and address are as follows from the concrete processing procedure that increases function:
The address prefetch mechanisms: for satisfy the maximum count condition (hsize=WORD, burst time number is 16; Hsize=INCR, INCR represent the not data of specified length., burst time number is maximum identical with address limit, is 1K), burst counter burst_cnt should be the counter of one 10 bit wide.When new_write or read_during_write are effective, the burst counter O reset is (when read_during_write effectively is read/write conflict, the read operation address should be carried the previous clock period and be written into, that exports the previous clock period when effective with convenient read_after_write reads address A2, rather than the address of current ahb bus, this moment, haddr changed over the address A3 of next clock period).Be written into the read operation initial value when new_read is effective, hsize is 2 during for WORD, and hsize is 1 during for HWORD.Burst_cnt counts the progression value when WORD be 2, and counting progression value is 1 when HWORD, does not count when htrans is BUSY.
Because the read operation meeting of static memorizer interface device postpones two clock period, therefore read start signal read_start when effective, directly the haddr address is sent, to reduce by a clock period latent period; When writing burst second count operation, perhaps just burst_addr is sent during write operation.Burst_addr changes at the clock edge, so the burst_addr during write operation is always the address that postpones a clock period on the bus.Also carry out read operation just because of will do sth. in advance a clock period, burst_cnt read burst during first clock period the value of being written into should be 1 or 2, with when the second count directly with 1 or 2 outputs.
The address is from increasing mechanism: start address produces the start address start_addr that logic produces the burst operation, is written into address haddr from AHB when new_read or new_write are effective, all the other the time remain unchanged.Address adder obtains the address burst_addr of current burst operational access internal memory with the low level addition of burst_cnt and start address start_addr.In order to guarantee the address within the 1K scope, and satisfy WRAP operation requirement, the burst_cnt addition rule with start_addr that moves to left after is as follows:
Hburst=xx1, low 10 additions (INCR, scope 1K)
Hburst=000, the single mode, burst_cnt is always 0
Hburst=010, low 4 additions (WRAP4, scope 4*HSIZE/8)
Hburst=100, low 5 additions (WRAP8, scope 8*HSIZE/8)
Hburst=110, low 6 additions (WRAP16, scope 16*HSIZE/8)
In order to raise the efficiency, during the burst mode, in module, increase address counter, carry out progression counting or cycle count according to the hburst signal.When providing, first address need judge its legitimacy according to haddr, hburst signal and hsize signal.
The sequential synoptic diagram that static memorizer interface device of the present invention writes data to static memory under the burst mode as shown in figure 10.This pattern and single mode class of operation seemingly, this is because write operation need not extra latent period, the effect of address counter is performance not.
Sequential synoptic diagram when static memorizer interface device is from the static memory sense data under the burst mode during zero-address counter as shown in figure 11.During the burst read operation, because the address need be provided by ahb bus, although imi_rden shifts to an earlier date effectively with reading of data at the 2nd and 5 clock, this moment, hreadyout still must insert 1 latent period, arrive with wait A3 address, and reading D1 and D3.Burst time number is many more, the latent period of insertion also many (the 8th cycle also will be inserted latent period).So whenever, read two secondary data, the centre just has a latent period, the running time=burst several * 1.5+1.And under the single mode, whenever read a secondary data, just have a latent period, the running time=burst several * 2+1.
Sequential synoptic diagram when static memorizer interface device was from the static memory sense data under the burst mode when address counter was arranged as shown in figure 12.Produce by static memorizer interface device is inner owing to read the address, so hreadyout only need insert latent period when reading D1, At All Other Times all can the continuous-reading certificate, burst number is many more like this, and efficient is also just high more.The operating cycle=burst number+2.Static memorizer interface device adopts this kind mode.When burst number was 16, the former IMI module operation cycle was 33, and the static memorizer interface device operating cycle of zero-address counter is 25, and it is 18 that the IMI module static memorizer interface device operating cycle of address counter is arranged, than original raising 83.3%.Existing IMI module, that the static memorizer interface device that does not contain the static memorizer interface device of Burst counter and contain the Burst counter is read the Burst operating efficiency is more as shown in table 1.
Table 1:IMI module is read the Burst operating efficiency relatively
| Burst number | Existing IMI module life cycle is counted X | The static memorizer interface device life cycle that does not contain the Burst counter is counted Y | The static memorizer interface device life cycle that contains the Burst counter is counted Z | Efficient improves (X-Z)/ |
| 4 | 9 | 7 | 6 | 50％ |
| Burst number | Existing IMI module life cycle is counted X | The static memorizer interface device life cycle that does not contain the Burst counter is counted Y | The static memorizer interface device life cycle that contains the Burst counter is counted Z | Efficient improves (X-Z)/ |
| 8 | 17 | 13 | 10 | 70％ |
| 16 | 33 | 25 | 18 | 83.3％ |
3, byte is selected module.
Byte is selected module: the address signal that produces according to the address decoding module and give static memory with the total byte data bit width output byte selection marker that static memory carries out mutual data stream, this byte selection marker is in order to determine the effective byte of described data stream.The total byte data bit width of described data stream is: 8 or 16 or 32 or 64 or 128.
In above-mentioned static memorizer interface device shown in Figure 7, byte selects the concrete processing procedure of module as follows:
Byte is selected logical foundation hsize and imi_addr output byte selection marker imi_hwls, is used for indicating which byte of data of current read-write operation is effective.Imi_hwls and read-write enable signal same-phase, signal definition can change to some extent according to concrete application requirements.For example, if IMI only requires to support 16 or 32, imi_hwls can define according to the following rules:
(the expression data are 32): imi_hwls[1:0 when 1, hsize is WORD] be output as 11;
When 2, hsize is HWORD (the expression data are 16):
When system is little endian mode:
If the 1st imi_addr[1 of the address signal on the bus]=1, imi_hwls[1:0 then] be output as 10 (content on the expression data bus is that last half-word is effective);
If the 1st imi_addr[1 of the address signal on the bus]=0, imi_hwls[1:0 then] be output as 01 (content on the expression data bus is for half-word is effective down);
When system is big end pattern:
If the 1st imi_addr[1 of the address signal on the bus]=1 o'clock, imi_hwls[1:0 then]=01 (content on the expression data bus is for half-word is effective down);
If the 1st imi_addr[1 of the address signal on the bus]=0 o'clock, imi_hwls[1:0 then]=10 (content on the expression data bus is that last half-word is effective);
When 3, hsize is worth for other: imi_hwls[1:0] output 00 (content on the expression data bus is invalid always).
For 8,64, perhaps higher data bit width can copy above-mentioned example to make different regulations as 128, but ultimate principle is all the same, adopt coherent signal represent one read and write data in which or several byte be effective.
4, read-write enable module.
The read-write control signal that the read-write enable module mainly produces according to control logic module produces reading enable signal or writing enable signal of access static storer, this is read enable signal or write enable signal to pass to static memory and data transmission module.
In above-mentioned static memorizer interface device shown in Figure 7, the concrete processing procedure of read-write enable module is as follows:
Write and enable after AHB sends write signal to postpone a clock period and produce, align, in the burst process, remain valid always, and enable invalid (delay provides) when htrans writes during for BUSY with hwdata.
Read to enable with write enable to produce different, burst read the beginning, read when promptly new_read is effective to enable and should produce immediately, in reading the burst process, remain valid always.Whenever producing a new_read, the hreadyout signal will drag down a clock period, to guarantee the binary cycle response of static memorizer interface device.It should be noted that when read_during_wirte is effective, read/write conflict, it is invalid to read to enable imi_rden, wait until when read_after_write is effective, and reading to enable could be effectively.
5, responsive feedback module.
The responsive feedback module is fed back corresponding collision signal according to the conflict control signal that transmission type mistake discrimination module passes over to the bus of pipelined architecture, makes the bus of pipelined architecture not carry out the read operation of current period; According to the wrong control signal that transmission type mistake discrimination module passes over, feed back the corresponding error signal to the bus of pipelined architecture.
In above-mentioned static memorizer interface device shown in Figure 7, the concrete processing procedure of responsive feedback module is as follows:
The responsive feedback module mainly produces hresp and hreadyout signal, and this hresp and hreadyout signal should meet the AHB agreement, and this hresp and hreadyout signal are passed to the ahb bus interface.
Hreadyout is dragged down in the next clock period, to satisfy static memorizer interface device binary cycle response condition when reading the start signal generation.Therefore when new_read was set, hreadyout all was set, and in the zero clearing of following one-period.Simultaneously, for solving the conflict that read-after-write produces, whenever carrying out write operation is that imi_wren is when effective, if the cycle that be right after this moment is read operation, this moment, the hreadyout signal should be set so, show that module just is being busy with handling the write operation of one-period, the read operation of current period can not be carried out immediately, to guarantee that address wire is not conflicted.Can be by read_during_write and read_after_write control, when they were effective, hreadyout was all waiting status.
When producing mistake, the error sign is set, and produces a double-periodic hresp=ERROR response this moment.Error generation condition can change according to actual conditions for the also unsupported byte manipulation of static memorizer interface device takes place, as the operation of the operation of 8 bit data or 64 and above data bit width thereof.
6, data transmission module.
Data transmission module is mainly read enable signal according to what the read-write enable module passed over, from the static memory sense data and output to the bus of pipelined architecture; Write enable signal according to what the read-write enable module passed over, from the bus sense data of pipelined architecture and output to static memory.
The present invention also provides an embodiment who visits above-mentioned static memorizer interface device according to the Burst data mode.
Under the burst mode, write the sequential synoptic diagram as shown in figure 13 for one of static memorizer interface device inside.What AHB sent an INCR4 writes the HWORD signal, and steering logic has detected the burst write signal and produced, and produces a burst_wrproc at the clock edge, and this burst_wrproc shows that one of beginning writes the burst operation.Start address produces logic and has latched start address 4Ch, and keeps it constant when burst_wrproc is effective, makes imi_wren effective simultaneously, and beginning is to the static memorizer interface device write data.During Burst operation beginning, counter burst_cnt has been written into 00, increases progressively successively according to the HWORD rule later on.4C, 4E, 50,52 are exported in burst_cnt and start_addr addition successively.When counting up to 06, produce burst_end signal indication burst and finish, it is invalid therefore to be at burst_wrproc of following one-period and imi_wren.
As seen, the sequential of burst write operation is identical with continuous single write operation sequential, all AHB write datas all postpone a clock period and provide, unless bus has extra demand (to insert a latent period as clapping AHB the 3rd among Figure 13, after postponing a clock period, imi_wren is invalid, and counter stops counting).
Under the burst mode, read the sequential synoptic diagram as shown in figure 14 for one of static memorizer interface device inside.What AHB sent a WRAP4 reads the WORD signal.Steering logic has detected read signal and has produced, and putting burst_start is 1, and produces a burst_rdproc at the clock edge, and this burst_rdproc shows that beginning one reads the burst operation.Start address produces logic and has latched start address 44h, and it is constant when burst_rdproc is effective, makes imi_rden effective simultaneously, and beginning is to static memorizer interface device module read data.During first cycle of Burst operation beginning, read_start is effective, and therefore final defeated address imi_addr is 44 of straight-through haddr, and unison counter burst_cnt has been written into 04.After the second period of burst operation, burst_cnt and start_addr addition export 48,4C, 40 successively.When counting up to 0C, produce burst_end signal indication burst and finish, it is invalid therefore to be at burst_rdproc of following one-period and imi_rden.
As seen, under burst read operation mode, all read datas of static memorizer interface device all postpone two clock period and provide, unless bus has the requirement of wait (to clap AHB the 3rd among Figure 14 and inserted a latent period, this moment, imi_rden was invalid, and counter stops counting).After first clock period ran through, hreadyout put low, and AHB waits for a clock period, just no longer waited in the read procedure afterwards.
In such scheme, the data bit width of bus and static memory and address bit wide can or be deleted according to actual conditions expansions: data bit width can comprise 8 or 16 or 32 or 64 or 128 or the data bit width of non-2N arbitrarily, as 10,12 etc.; The address bit wide is decided according to the capacity of total system and static memory; Byte selects signal imi_hwls to decide according to bus data bit wide and static memory data bit width.
In such scheme, the described static memorizer interface device of this method is to be articulated on the ahb bus as an independent module, in actual applications, main modular in this static memorizer interface device or this static memorizer interface device (control logic module, address decoding module etc.) can be embedded in other modules.
In such scheme, adopted separation signal to finish the realization of whole static memorizer interface device, but in fact also can utilize state machine to realize the kernel control module of static memorizer interface device of the present invention.For example, steering logic submodule and responsive feedback submodule can form bus state machine, address decoding submodule and read-write enable submodule can form the address and the read-write control state machine.The central idea of state machine is to represent the operational process of system with a plurality of states, and main control state machine can comprise that byte is read, byte is write, burst mode is read, burst mode is write, idle, data transmit state such as make mistakes; Sub-states such as burst mode reads to be divided into first and read, non-ly read first, wait; Burst mode write can be divided into first write, non-ly write first, sub-state such as wait.Also can produce a desired effect with the state machine design steering logic.
In such scheme, described static memory can be inner static memory or external static storer, also can be meant device or module with the behavior of synchronous static memory interface, and their combination, as register file.And the kind of static memory comprises: all kinds such as various unidirectional single port, two-way single port, unidirectional dual-port and two-way dual-port.
The data transmission method of static memorizer interface device of the present invention mainly comprises:
The read-write state and the address state of the bus of static memorizer interface device monitoring pipelined architecture produce corresponding address signal; Bus according to the described pipelined architecture of described address signal is carried out data interaction according to setting data load mode and static memory.
Above-mentioned setting data load mode comprises: bursty data load mode or individual data load mode.
When ahb bus carries out data interaction with bursty data load mode and described static memory, the Data Receiving ratio of reading first address that ahb bus sends is read the address and is sent late two clock period, after, the read data that ahb bus sends receives than reading the address and sends a late clock period; The write data that ahb bus sends is than a late clock period of write address.
After sending a write operation on the ahb bus, when the back to back next clock period sends a read operation, ahb bus is set to busy state, the responsive feedback module is finished clock period of hreadyout home position signal to the task of ahb bus output, the read-write enable module produces in this clock period, and to read enable signal invalid, after this clock period finished, ahb bus and hreadyout signal were set to normal condition.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of claim.
Claims (12)
1. a static memorizer interface device is characterized in that, the bus of pipelined architecture is carried out data interaction by this static memorizer interface device and static memory, and described static memorizer interface device specifically comprises:
Control logic module: the read-write state of the bus of monitoring pipelined architecture also carries out judgment processing, the bus and the static memory that produce pipelined architecture carry out mutual needed read-write control signal, and the read-write control signal that produces is passed to the address decoding module;
Address decoding module:, produce the address signal that carries out mutual data stream with static memory according to the address state of the bus of pipelined architecture and the read-write control signal that control logic module passes over.
2. static memorizer interface device according to claim 1 is characterized in that, described static memorizer interface device also comprises:
Byte is selected module: the address signal that produces according to the address decoding module and carry out the total byte data bit width of mutual data stream with static memory, the output byte selection marker is given static memory.
3. static memorizer interface device according to claim 2 is characterized in that, the total byte data bit width of described data stream is: 8 or 16 or 32 or 64 or 128.
4. static memorizer interface device according to claim 1 is characterized in that, described static memorizer interface device also comprises read-write enable module and data transmission module,
Read-write enable module: the read-write control signal that passes over according to control logic module, the bus and the static memory that produce pipelined architecture carry out mutual reading enable signal or write enable signal, this are read enable signal or write enable signal to pass to static memory and data transmission module;
Data transmission module: read enable signal, bus from the static memory output data to pipelined architecture according to what the read-write enable module passed over; Perhaps, write enable signal according to what the read-write enable module passed over, from the bus output data of pipelined architecture to static memory.
5. static memorizer interface device according to claim 4 is characterized in that, described static memorizer interface device also comprises:
Responsive feedback module:, feed back corresponding collision signal to the bus of pipelined architecture according to the conflict control signal that control logic module produces and passes over; According to the wrong control signal that control logic module produces and passes over, feed back the corresponding error signal to the bus of pipelined architecture.
6. static memorizer interface device according to claim 5 is characterized in that, described control logic module comprises:
Transmission type mistake discrimination module: after the bus of pipelined architecture sends a write operation, when the back to back next clock period sends a read operation, send described conflict control signal to the responsive feedback module; And/or, when the bus generation error of transmission of pipelined architecture, send described wrong control signal to the responsive feedback module.
7. according to claim 1,2,3,4,5 or 6 described static memorizer interface devices, it is characterized in that described address decoding module comprises:
Computing module, the read-write control signal that first address that passes over according to the bus of pipelined architecture and control logic module pass over, utilize address counter, address adder, calculate with static memory and carry out the current address of mutual data stream and export to static memory; Perhaps
Delivery module, directly the first address that the pipelined architecture bus is passed over exports static memory to.
8. static memorizer interface device according to claim 7 is characterized in that, described static memorizer interface device is articulated on the bus of pipelined architecture or is embedded into static memory inside.
9. according to claim 5 or 6 described static memorizer interface devices, it is characterized in that, described control logic module and described responsive feedback module are formed bus state machine, and described address decoding module and described read-write enable module are formed address and read-write control state machine.
10. the data transmission method of a static memorizer interface device is characterized in that, comprising:
The read-write state and the address state of the bus of static memorizer interface device monitoring pipelined architecture produce corresponding address signal; According to described address signal, the bus of described pipelined architecture is carried out data interaction by static memorizer interface device according to setting data load mode and static memory.
11. method according to claim 10 is characterized in that, described method specifically comprises:
When advanced high performance bus ahb bus carries out data interaction as the bus of described pipelined architecture with bursty data load mode and described static memory, the Data Receiving ratio of reading first address that ahb bus sends is read the address and is sent late two clock period, after, the read data that ahb bus sends receives than reading the address and sends a late clock period; The write data that ahb bus sends is than a late clock period of write address.
12. method according to claim 11 is characterized in that, described method also comprises:
When after sending a write operation on the described ahb bus, when the back to back next clock period sends a read operation, ahb bus is set to busy state, with static memorizer interface device wait condition feedback signal hreadyout signal clock period of zero clearing to ahb bus output, static memorizer interface device produces in this clock period, and to read enable signal invalid, after this clock period finished, ahb bus and hreadyout signal were set to normal condition.
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| CN102508798B (en) * | 2011-10-18 | 2014-12-31 | 国电南京自动化股份有限公司 | CPU (Central Processing Unit) and FPGA (Field Programmable Gate Array) interface method based on BURST and flow line |
| CN103761208B (en) * | 2013-10-08 | 2017-01-18 | 苏州智汇谱电子科技有限公司 | Communication conversion bridge equipment between AHB bus and Crossbar bus |
| CN106030499B (en) * | 2014-05-28 | 2019-03-05 | 株式会社日立制作所 | Computer system and computer system control method |
| CN106372540B (en) * | 2016-08-29 | 2019-07-12 | 北京中电华大电子设计有限责任公司 | A kind of safe transmission method and circuit of chip secure information |
| CN108053856B (en) * | 2017-12-29 | 2020-04-28 | 西安智多晶微电子有限公司 | Circuit for reading and writing SRAM and SRAM data access method |
| CN108519947A (en) * | 2018-04-02 | 2018-09-11 | 郑州云海信息技术有限公司 | The method and tool of read-write register under a kind of Linux |
| CN109783933B (en) * | 2019-01-14 | 2020-07-28 | 浙江大学 | Bridging method for SRAM on AHB bus access chip |
| CN109800193B (en) * | 2019-01-14 | 2020-07-28 | 浙江大学 | Bridging device of SRAM on AHB bus access chip |
| CN110765043B (en) * | 2019-10-31 | 2023-03-21 | 山东华芯半导体有限公司 | RAID core computing device and method in SSD master control |
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