CN100394583C

CN100394583C - Integrated producing method for strain CMOS

Info

Publication number: CN100394583C
Application number: CNB2005100290946A
Authority: CN
Inventors: 宁先捷; 邵向峰
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2005-08-25
Filing date: 2005-08-25
Publication date: 2008-06-11
Anticipated expiration: 2025-08-25
Also published as: CN1921086A

Abstract

The invention relates to an integrated preparation of strain CMOS. Wherein, when forming the polycrystalline grid conductive structure and separated layer, it uses photo-etching adhesive to protect the polycrystalline grid and NMOS area of PMOS, to process silicon concave etching on the source and drain of PMOS, removes photo-etching adhesive layer, then uses electric medium layer to protect polycrystalline grid and NMOS area, at the same time, extends silicon germanium in the concave area, then removes electric medium layer and treats following process.

Description

The integrated manufacturing method of strain CMOS

Technical field

The present invention relates to CMOS (Complementary Metal Oxide Semiconductor) (Complementary Metal OxideSemiconductor; CMOS) manufacture method; what particularly relate to strain CMOS will protect polysilicon gate and N channel mos (N Channel Metal OxideSemiconductor; NMOS) zone; to P channel mos P Channel MetalOxide Semiconductor, PMOS) the integrated manufacture method of epitaxial growth SiGe is leaked in the source.

Background technology

Employing changes channel stress at source and drain areas selective epitaxial growth SiGe has become the effective ways that improve PMOS field effect transistor carrier animal migration.A committed step wherein is the selective epitaxial growth SiGe.In order to prevent that SiGe is grown on the polysilicon; usually adopt a hard mask; (Plasma Enhanced Chemical Vapor Deposition, the film that method PECVD) forms is protective layer used on the top of polysilicon as one as plasma-reinforced chemical vapor deposition.In order after the SiGe epitaxial growth, on polysilicon gate, to form metal silicide, need to remove this hard mask.And the SiGe epitaxial growth only need be grown in the PMOS zone, and the nmos area territory needs protection in order to avoid performance is affected.

Therefore, need in the source and drain areas epitaxial growth SiGe of PMOS, to protect polysilicon gate and the nmos area territory of PMOS, propose the present invention for this reason.

Summary of the invention

The integrated manufacturing method that the purpose of this invention is to provide a kind of strain CMOS, the epitaxial growth SiGe is leaked in the PMOS source in protection PMOS polysilicon gate and nmos area territory.

The integrated manufacturing method of strain CMOS of the present invention comprises:

A) deposit polysilicon and deposit hard mask material on the oxide skin(coating) on the substrate, photoetching, development, ion beam etching form the polysilicon gate pattern;

B) the hard mask on the removal polysilicon gate;

C) substrate injects through various ions and activation tempering doping, and the polysilicon gate both sides form the polysilicon gate wall by deposit first dielectric layer with eat-backing;

D) second dielectric layer is deposited on the substrate, and the photoresist mask covers the pattern in PMOS polysilicon gate and whole nmos area territory;

E) etching technics is removed second dielectric layer of the deposit of PMOS source and drain areas, and the silicon dent etching is to form PMOS source and drain areas depression;

F) remove photoresist;

G) PMOS source and drain areas depression goes up the epitaxial growth SiGe;

H) remove second dielectric layer of protecting PMOS polysilicon gate and nmos area territory;

I) carry out successive process.

According to the present invention, protection PMOS polysilicon gate and nmos area territory are in order to avoid second dielectric layer of SiGe growth is the nitrogen oxide of Si oxide, silicon nitride or silicon.Described second dielectric layer adopts plasma-reinforced chemical vapor deposition (PECVD) method, low-pressure chemical vapor phase deposition (LowerPress Chemical Vapor Deposition, LPCVD) method, (Atomic LayerDeposition, ALD) method forms atomic layer deposition.The second dielectric layer thickness scope is 10～80nm.

Second dielectric layer of PMOS source and drain areas adopts etching technics to remove.Adopt reactive ion beam etching (RIBE) technology to carry out the silicon dent etching to form PMOS source and drain areas depression.

Wet processing or reactive ion beam etching (RIBE) technology are removed second dielectric layer in protection polysilicon gate and nmos area territory.Wet processing adopts hydrofluoric acid base wet processing.

Advantage of the present invention,

The present invention adopts polysilicon gate and the nmos area territory of dielectric layer protection PMOS, the source of PMOS is leaked carry out the SiGe epitaxial growth simultaneously, makes the polysilicon gate of PMOS and the influence that SiGe is avoided in the nmos area territory.

Description of drawings

Fig. 1 is the schematic cross-section behind the formation poly-silicon pattern.

Fig. 2 is the schematic cross-section behind the hard mask of removal.

Fig. 3 is the schematic cross-section behind the various ions injections of substrate process and activation tempering doping and the formation inter polysilicon interlayer.

Fig. 4 is whole deposit one deck oxide skin(coating)s, then the schematic cross-section after forming the photoresist pattern on the polysilicon of nmos area territory and PMOS.

Fig. 5 is the polysilicon with photoresist protection nmos area territory and PMOS, removes the oxide of PMOS source leakage and the schematic cross-section after the etching that caves in.

Fig. 6 is the schematic cross-section behind the removal photoresist.

Fig. 7 is polysilicon and the nmos area territory with oxide skin(coating) protection PMOS, and the silicon dent etch areas of PMOS is carried out schematic cross-section after the SiGe epitaxial growth.

Fig. 8 is the schematic cross-section behind the removal oxide skin(coating).

Description of reference numerals

10 silicon substrates

The 11N well

12PMOS polysilicon gate oxide skin(coating)

The 13PMOS polysilicon gate

The hard mask of 14PMOS polysilicon

15PMOS polysilicon gate wall

Protective oxide film on the 16PMOS polysilicon gate

Photoresist layer on the 17PMOS polysilicon gate

The silicon dent etching is leaked in the 18PMOS source

The SiGe epitaxially grown layer is leaked in the 181PMOS source

20 shallow isolating trough

The 21P well

22NMOS polysilicon gate oxide skin(coating)

The 23NMOS polysilicon gate

The hard mask of 24NMOS polysilicon

25NMOS polysilicon gate wall

26NMOS zone protective oxide film

27NMOS zone photoresist layer

Embodiment

Describe the present invention in detail below in conjunction with accompanying drawing.

The integrated manufacturing method of strain CMOS of the present invention comprises the steps:

A) polysilicon is deposited on the monocrystalline silicon oxide layer, as by chemical gas-phase deposition method, and then deposit hard mask material, as in conjunction with PECVD silicon oxynitride and oxide, the main chemicals areSiH ₄And N ₂O, this stack layer photoetching, development, ion beam etching form the polysilicon gate pattern, as shown in Figure 1.

B) wet chemistry is removed method, adds water and phosphoric acid as hydrofluoric acid and removes hard mask 14 on the polysilicon gate, as shown in Figure 2.

C) substrate injects through ion and activation tempering doping, forms lightly doped source and leaks (LightDeposition Drain, LDD) shallow joint; By deposit first dielectric layer such as silica and silicon nitride, eat-back formation PMOS polysilicon gate wall 15 and NMOS polysilicon gate wall 25, as shown in Figure 3 in the polysilicon gate both sides.

D) one second dielectric layer 06 is deposited on substrate 10 and PMOS and the NMOS.This second dielectric layer 06 is selected from the nitrogen oxide of Si oxide, silicon nitride or silicon, adopts PECVD, LPCVD or the deposit of ALD method to form, with protection PMOS polysilicon gate and nmos area territory not by the SiGe epitaxial growth.The thickness range of this layer is 10～80nm.The photoresist mask is used to form the

pattern

17 and 27 that covers PMOS polysilicon gate and whole nmos area territory, as shown in Figure 4.

E) with photoresist 17 protection PMOS polysilicon gates with photoresist 27 protection nmos area territories; adopt etching technics to remove second dielectric layer of PMOS source and drain areas; second dielectric layer 16 on the reservation PMOS polysilicon gate and second dielectric layer 26 in nmos area territory; this removal technology can be hydrofluoric acid base wet processing or reactive ion beam etching (RIBE) technology; on substrate, adopt reactive ion beam etching (RIBE) technology to carry out the silicon dent etching then to form the silicon dent 18 that the PMOS area source leaks, as shown in Figure 5.

F) remove

photoresist layer

17 and 27, as adopting the plasma of oxygen, as shown in Figure 6.

G) with the polysilicon gate of second dielectric layer, 16 protection PMOS with second dielectric layer, 26 protection nmos area territories, silicon dent is leaked in the source of PMOS carry out the epitaxial growth of SiGe, as shown in Figure 7.

H) wet processing is removed second dielectric layer 16 of protection PMOS polysilicon and second dielectric layer 26 in nmos area territory; this wet processing is a hydrofluoric acid base wet processing; ratio as hydrofluoric acid and water is 1: 50-1: 200, and be preferably and contain 1% the dilute hydrofluoric acid aqueous solution, as shown in Figure 8.

Carry out follow-up common process processing procedure, comprising: ion implantation doping, grid, source are leaked and are formed metal silicide, the Metal Contact window, and the making of strain source leakage CMOS is finished in multiple layer metal interconnection and passivation etc.

Claims

1. the integrated manufacturing method of strain CMOS comprises the steps:

B) the hard mask on the removal polysilicon gate;

F) remove photoresist;

G) PMOS source and drain areas depression goes up the epitaxial growth SiGe;

I) carry out successive process.

2. the integrated manufacturing method of strain CMOS according to claim 1 is characterized in that, described second dielectric layer is the nitrogen oxide of Si oxide, silicon nitride or silicon.

3. the integrated manufacturing method of strain CMOS according to claim 1 is characterized in that, described second dielectric layer adopts plasma-reinforced chemical vapor deposition (PECVD) method to form.

4. the integrated manufacturing method of strain CMOS according to claim 1 is characterized in that, described second dielectric layer adopts low-pressure chemical vapor phase deposition (LPCVD) method to form.

5. the integrated manufacturing method of strain CMOS according to claim 1 is characterized in that, described second dielectric layer adopts atomic layer deposition (ALD) method to form.

6. the integrated manufacturing method of strain CMOS according to claim 1 is characterized in that, the described second dielectric layer thickness scope is 10～80nm.

7. the integrated manufacturing method of strain CMOS according to claim 1 is characterized in that, second dielectric layer of described PMOS source and drain areas adopts ion beam etching technology, and (ReactiveIon etch RIE) removes.

8. the integrated manufacturing method of strain CMOS according to claim 1 is characterized in that, adopts reactive ion beam etching (RIBE) technology to carry out the silicon dent etching to form PMOS source and drain areas depression.

9. the integrated manufacturing method of strain CMOS according to claim 1 is characterized in that, adopts wet processing to remove second dielectric layer in protection PMOS polysilicon gate and nmos area territory.

10. the integrated manufacturing method of strain CMOS according to claim 9 is characterized in that, described wet processing adopts hydrofluoric acid base wet processing.

11. the integrated manufacturing method of strain CMOS according to claim 1 is characterized in that, adopts reactive ion beam etching (RIBE) technology to remove second dielectric layer in protection PMOS polysilicon gate and nmos area territory.