CN100394406C - High speed buffer storage distribution - Google Patents
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- CN100394406C CN100394406C CNB200310125194XA CN200310125194A CN100394406C CN 100394406 C CN100394406 C CN 100394406C CN B200310125194X A CNB200310125194X A CN B200310125194XA CN 200310125194 A CN200310125194 A CN 200310125194A CN 100394406 C CN100394406 C CN 100394406C
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
- G06F12/0835—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means for main memory peripheral accesses (e.g. I/O or DMA)
Abstract
Cache allocation includes a cache memory and a cache management mechanism configured to allow an external agent to request data be placed into the cache memory and to allow a processor to cause data to be pulled into the cache memory.
Description
Technical field
The present invention relates generally to computer system, relate in particular to a kind of method and apparatus that is used for cache assignment.
Background technology
Processor in the computer system can send one to the request that is requested the data in the storage unit at storer.Processor can at first be attempted being accessed in and the storer of this processor close association, the data in for example cache memory, rather than by common, to the low access of primary memory.In general, cache memory comprise to more greatly, the selection area in the primary memory or the piece storer of simulating more slowly.Cache memory normally is filled based on request, physically more approaches processor, and has than primary memory access time faster.
If processor is not to be accessed in " " in the cache memory of storer, for example, in cache memory, do not find the copy of these data, then this cache memory is selected a storage unit in cache memory, be used for storing primary memory is requested the data that the data in the storage unit are simulated, send a request to primary memory, and the data of autonomous memory are inserted in the selected cache memories store unit in the future for the data that are requested the storage unit place.The data that are positioned at and are requested position approaching on the storage unit space can also be asked and be stored to cache memory, because the program of request msg usually proposes the time from the data of Memory Storage Unit approaching on identical or the space is gone up approaching request, therefore comprise that in cache memory data approaching on the space can increase efficient.By this way, processor can and/or be data in subsequently the request of data access cache for this request.
Summary of the invention
The present invention is directed to above problem and propose following technical scheme:
According to the present invention, a kind of equipment that is used for cache assignment is provided, comprising: cache; Cache management mechanism is configured to allow the external agent to ask data are put in the described cache, and allows processor that data are pressed in the described cache.According to the present invention, a kind of method that is used for cache assignment also is provided, comprising: allow the external agent to send being placed into the request of the data in the cache; And allow described external agent that the described data that will be placed in the cache are provided.
According to the present invention, a kind of equipment that is used for cache assignment also is provided, comprising: be used for allowing the external agent to send device the request of the data that will be placed into cache; And be used for allowing the external agent these data to be inserted the device of described cache.
According to the present invention, a kind of system that is used for cache assignment also is provided, comprising: cache; And memory management mechanism, be configured to allow the external agent to ask described cache: the delegation of selecting described cache is as the victim, described row comprises data, and uses from described external agent's new data and replace this data.
According to the present invention, a kind of system that is used for cache assignment also is provided, comprising: at least one Physical layer (PHY) equipment; At least one Ethernet medium access controller (MAC) equipment is used for the data that receive via PHY are carried out the link layer operation; Be used to ask logic via at least a portion of the data that received by at least one PHY of high-speed cache and at least one MAC; And high-speed cache, described high-speed cache comprises: cache; Cache management mechanism is configured in response to described request, and at least a portion of the data that will receive via at least one PHY and at least one MAC is placed in the described cache; And, allow processor that data are pressed in the described cache in response to not being stored in the request of the data in the described cache.
Description of drawings
Fig. 1 is the block scheme that comprises the system of cache memory.
Fig. 2 and 3 shows the process flow diagram of the processing of filling storage mechanism.
Fig. 4 shows the process flow diagram of the part in the processing of filling storage mechanism.
Fig. 5 is the block scheme that comprises the system of relevant lookaside buffer.
Embodiment
Referring to Fig. 1, exemplary systems 100 comprises external agent 102, and it can ask the row in the cache 104 (" high-speed cache 104 ") is distributed.Described external agent 102 can be pressed into data 106 li of the data-carrier stores that comprise in high-speed cache 104, and marker character is pressed into 108 li of the marker character arrays that comprise in high-speed cache 104.External agent 102 can also trigger row and distribute in additional this locality and/or remote cache, and/or relevant the renewal, and/or relevant invalid.Allow external agent 102 to trigger that row in the high-speed caches 104 distributes and request is sent to 104 li of high-speed caches with data, can reduce or eliminate the shortcoming that is associated in not with cache accessing first.For instance, processor 110 can with external agent 102 and one or more other external agents (for example, I/O (I/O) equipment and/or other processors) data in the shared storage 112, and cause in the high-speed cache so that the data that just write by another agency are carried out access.Cache management mechanism 114 (" manager 114 ") allows external agent 102 by triggering allocation of space and data being sent to 104 li of high-speed caches, come name imitation with processor 110 to looking ahead that data are carried out, thus help to reduce high-speed cache not in.The high-speed cache behavior is for processor 110, and is normally transparent.Manager such as manager 114 allows particular cache and storer transmitted and carries out managed together, so that strengthen the performance based on the message communication of storer between two agencies.Manager 114 can be used for receiving to the processor transmission of appointment from network interface the selected part of descriptor and reception buffer.Manager 114 can also be used for the cost minimization with the message between the processor or between the thread.Processor 110 can also comprise manager, for example cache management mechanism (manager) 116.
If the copy of the data in high-speed cache 104 comprises renewal or the modification that also is not reflected in the storer 112, then manager 114 can also allow external agent 102 to trigger high-speed cache 104, so that by be discarded in the selected memory cell content or by the content in the selected memory cell being write back to 112 li of storeies, sacrifice the current data in the storage unit in, the high-speed cache 104 104 that select by high-speed cache.High-speed cache 104 is carried out and is sacrificed and to the writing back of storer 112, but external agent 102 can trigger these incidents by transmit the request of storage data in high-speed cache 104 to high-speed cache 104.For example, external agent 102 can send a stacked order, this order comprises the address information that will be stored in the data in the high-speed cache 104 and be used for these data, is used for avoiding data storage was being read the potential of storer 112 before high-speed cache 104.If high-speed cache 104 has comprised the clauses and subclauses of the storage unit in the expression storer 106, described storage unit is in from stacked request of the external agent 102 shown in the indication, then high-speed cache 104 neither distributes new storage unit, does not also sacrifice any cache content.On the contrary, high-speed cache 104 uses the storage unit with matched indicia symbol, utilizes the data that are pressed into from external agent 102 that corresponding data is rewritten, and the capable state of corresponding cache is upgraded.In relevant multicomputer system, except that high-speed cache 104, have and the high-speed cache of the corresponding clauses and subclauses of storage unit of in stacked request, indicating, to or abandon those clauses and subclauses, perhaps use the data and the new state that are pressed into that they are upgraded, so that keep system's cache coherence.
Allowing processor 110 when requiring just high-speed cache 104 to be filled, allowing external agent 102 to trigger the row that is undertaken by high-speed cache 104 distributes, making can be with significant data, for example critical new data is placed on position in the high-speed cache 104, approaching with processor 110 selectively, thereby has improved processor performance.Row distributes, refer in general carry out in following the processing some or all: insert the row that selection is sacrificed in the operational processes carrying out high-speed cache; If revised content then the cache content of sacrificing be written to primary memory; Update mark symbol information is assigned with the new main memory address that the agency selects with reflection, upgrade as required the capable state of cache with the reflection status information, for example with the status information that writes back or cache coherence is relevant; And use the new data that sends by request broker to replace respective data blocks in high-speed cache.
Data can be used as " dirty " or " clean " is sent to the high-speed cache 104 from external agent 102.If data are transmitted as dirty, then when this row was finally sacrificed from high-speed cache 104, high-speed cache 104 usefulness were represented the currency updated stored device 112 of the cached data of this storage unit.After being pressed into high-speed cache 104, described data may or may not revised by processor 110.If data are as clean being transmitted, the mechanism except that high-speed cache 104 can use this Data Update storer 112 so, and in this example, described mechanism is external agent 102." dirty ", perhaps some equivalent states are indicated the current fresh copy with data in the storage unit of this high-speed cache, and are responsible for guaranteeing updated stored device 112 when data are evicted from from high-speed cache 104.In the multiprocessor coherent system, answer the request of high-speed cache, this responsibility can be transferred to different high-speed caches, for example when another processor is attempted this storage unit in the write store 112.
High-speed cache 104 can be to data storer 106 read and write data.High-speed cache 104 can also access flag accord with array 108, and produces and revise status information, produces marker character, and causes sacrifice.
further discuss use the external agent distribute cache capable before, with the unit that further specifies in the system 100.Unit in the system 100 can accomplished in various ways.
High-speed cache 104 can comprise can bridging memory memory access (for example, processor 110) and the storage mechanism of memory device or primary memory (for example storer 112).High-speed cache 104 had usually than primary memory access time faster.High-speed cache 104 can comprise many levels, and can comprise private cache, impact damper, memory bar, perhaps other similar storage mechanisms.High-speed cache 104 can comprise independently or be comprised in mechanism in the reserve part of primary memory.Instruction and data normally is delivered to high-speed cache 104 in the mode of piece, and send out from high-speed cache 104.Piece refers in general and transmits as a whole or the position of processing or the set of byte.A piece can comprise many words, and a word can comprise many positions or byte.
Data block can comprise the data in one or more network communication protocol data cells (PDU), described network communication protocol data cell for example be Ethernet or synchronous optical network (SONET) frame, transmission control protocol (TCP) section, Internet protocol (IP) bag, fragment, asynchronous transfer mode i (ATM) unit, etc., the perhaps part in them.Data block may further include descriptor.Descriptor is a kind of data structure in the storer normally, and the message such as external agent 102 or the transmitter of bag can use it to the information relevant with message or PDU of the receiver transmission such as processor 110.Descriptor content can include, but are not limited to: comprise the storage unit in the impact damper of message or bag, the byte number in the impact damper receives the identifier of the network port of this bag, and indication or the like makes mistakes.
Data-carrier store 106 can comprise the part of high-speed cache 104, and this part is configured to the data message that storage is located to read from primary memory (for example, storer 112).
High-speed cache 104 comprises manager 114, and can comprise single memory mechanism, and described single memory mechanism comprises data-carrier store 106 and marker character array 108, perhaps, and the storage mechanism that data-carrier store 106 and marker character array 108 can separate.If data-carrier store 106 and marker character array 108 are storage mechanisms separately, then " high-speed cache 104 " can be interpreted as suitable one or several in data-carrier store 106, marker character array 108 and the manager 114.
For ease of explanation, simplified illustrating to system 100.System 100 can comprise unit more or still less, for example one or more storing mechanism (high-speed cache, storeies, database, impact damper, or the like), bridge, chipset, network interface, pattern mechanism, display device, external agent, communication linkage (bus, radio link, or the like), memory controller, and can be included in the unit of other similar type in the system similar to system 100, described system for example is computer system or network system.
Referring to Fig. 2, show the exemplary process 200 of cache operations.Although handling 200 is to describe with reference to the unit that comprises in the exemplary systems 100 of Fig. 1, but can in system 100 or another similar system, carry out this processing or similar processing, comprise during these are handled identical, more or still less, transformed or not by transformed unit.
Agency in the system 100 sends (202) requests.This agency who is called as request broker can be external agent 102, processor 110 or another agency.In this example was discussed, external agent 102 was request brokers.
Requests for data can comprise that request high-speed cache 104 will be placed into the request of 104 li of high-speed caches from the data of request broker.This request can be the result of an operation, and the message between the network reception operation in this way of described operational example, I/O input, the processor transmits or other similar operation.
High-speed cache 104 determines via manager 114 whether (204) high-speed caches 104 comprise a storage unit usually, the storage unit in that this storage unit indicates in representing to ask, the storer 112.Can be by access cache 104, and finish for this memory of data address check marker character array 108 and a kind ofly like this to determine that described data are provided by request broker usually.
If handling 200 is used in one and comprises in a plurality of cache systems, this system perhaps supports the combination of multiprocessor or processor and IOS, then can use any agreement to check described a plurality of high-speed cache, and keep the relevant version of each storage address.Described high-speed cache 104 can be checked the address associated state with requested date in the marker character array of high-speed cache, checking whether the data at place, this address are included in another high-speed cache, and/or whether in another high-speed cache, be modified in the data at this place, address.For example, " exclusive " state can be indicated: the data at this place, address only are included in the described checked high-speed cache.For another example, " sharing " state can be indicated: these data can be included at least one other high-speed cache, and before request broker takes out requested date, may need to check other high-speed caches, to obtain data updated.Different processors and/or IOS can use same or different technology to check and upgrade cache marks and accord with.When the request of answering the external agent, when delivering to data in the high-speed cache, these data can be sent in one or more high-speed cache, and clearly the clauses and subclauses that must make coupling to its those high-speed caches that transmit data are invalid or to its renewal, so that keep system coherence.Can in request, indicate or otherwise select to be admitted to statically the high-speed cache of these data.
Effectively indicate if marker character array 108 comprises this address and this storage unit of expression, then identify cache hit.High-speed cache 104 comprises the clauses and subclauses of storage unit indicated in the request of being illustrated in, and external agent 102 is pressed into high-speed cache 104 with these data, legacy data to cache in capable is rewritten, and need not at first to distribute in high-speed cache 104 storage unit.External agent 102 can be pressed into 104 li of high-speed caches with some data or total data, and described data are the data that send processor 110 via shared storage to.For example, if request broker may not analyzed total data immediately or often, then only some data are pressed in the high-speed cache 104.For example, network interface can be pressed into descriptor and only direct packets content, for example the packet header information of receiving.If external agent 102 only is pressed into the data division of selection, does not have bulged-in other parts to change usually so and write 112 li of storeies by external agent 102.In addition, can use new data to be updated in any storage unit in high-speed cache 104 and other high-speed caches, that be illustrated in those storage unit that write by external agent 102 in the storer 112, perhaps make it invalid, so that keep system coherence.Data trnascription in other high-speed caches can be disabled, and the cache in the high-speed cache 104 is capable is marked as " exclusive ", and perhaps this copy is updated, and cache is capable is marked as " sharing ".
If marker character array 108 does not comprise requested address in effective storage unit, so this be high-speed cache not in, and high-speed cache 104 does not comprise the row that is requested storage unit in the expression storer 112.In this case, high-speed cache 104 selects (" distribution ") to put into the delegation that is pressed into data therein in high-speed cache 104 usually via the behavior of manager 114.Distribute cache to select a storage unit capable comprising, determine whether this storage unit comprises this high-speed cache 104 and be responsible for it is write back to piece in the storer 112, and if like this, the data that then will be replaced (perhaps " sacrifice ") are written in the storer 112, the address that use indicates in request, and use the capable state of suitable cache that the marker character of chosen storage unit is upgraded, will be written to from external agent 102 data in data array 106, in the storage unit corresponding to the symbol of the selection marquee in marker character array 108 storage unit.
High-speed cache 104 can by in high-speed cache 104 (for example, in data-carrier store 106 and in marker character storer 108) select (206) storage unit comprise the copy of data, external agent 102 request is responded.This selection can be known as distribution, and selecteed storage unit can be known as the storage unit that is assigned with.If the storage unit that is assigned with comprises the data of the different storage unit in effective marker character and the expression storer 112, then this content can be known as " victim ", and the behavior that it is removed from high-speed cache 104 can be known as " sacrifice ".The state of victim's row can be indicated: when this row was sacrificed, this high-speed cache 104 was responsible for using the data from this victim's row that the respective memory unit in the storer 112 is upgraded (208).
High-speed cache 104 or external agent 102 can be responsible for using the new data that is pressed into high-speed cache 104 from external agent 102 that storer 112 is upgraded.When new data being pressed into 104 li of high-speed caches, usually should be in this exemplary systems 100 coherence between the storage mechanism in the maintenance system, high-speed cache 104 and the storer 112.The coherence keeps like this: by any other copy of revising data resident in other storage mechanisms is upgraded, reflect this modification, for example by its state in other mechanisms being changed into engineering noise or other suitable state, use the data of revising that other mechanisms are upgraded, or the like.High-speed cache 104 can be marked as the owner of data, and becomes and be responsible for new data storer 112 being upgraded (212).High-speed cache 104 can externally act on behalf of 102 when data are pressed into high-speed cache 104 or after a while, and storer 112 is upgraded.Alternatively, data can be shared, and external agent 102 can upgrade the described mechanism that (214) are storeies 112 in this example, and with the new data updated stored device that is pressed into high-speed cache 104.Therefore, storer 112 can comprise the copy of latest edition data.
High-speed cache 104 is used in address that indicate in the request, in the storer 112, is that the storage unit of being sacrificed is upgraded (216) marker character in marker character array 108.
High-speed cache 104 can be used from external agent 102 data and replace (218) content in the quilt storage unit of sacrificing.If processor 110 is supported cache hierarchy, then external agent 102 can be pressed into data in the cache hierarchy one or more levels, usually from outermost layer.
Referring to Fig. 3, show another exemplary process 500 of cache operations.Described processing 500 has illustrated processor 110 accessing caches 104 and an example order being inserted high-speed cache 104.Although handling 500 is to describe with reference to the unit that comprises in the exemplary systems 100 of Fig. 1, but can in system 100 or other similar system, carry out this processing or similar processing, comprise during these are handled identical, more or still less, transformed or not by transformed unit.
When processor 110 sends a cacheable memory reference, to search for their relevant marker character array 108 with the high-speed cache 104 that the storage access of processor 110 is associated, in those high-speed caches, whether be expressed to determine that (502) requested storage unit is current.Whether the clauses and subclauses in the high-speed cache 104 that high-speed cache 104 is further determined (504) to be quoted have being requested the suitable permission of access, and for example whether row is in the correct coherency states that permission writes from processor.Be expressed in high-speed cache 104 if the storage unit in the storer 112 is current, and has the right permission, then detect " hitting ", and high-speed cache provides data or receives data from processor to processor by the name with the related memory cell in the storer 112, comes to be this request service (506).If the marker character in the marker character array 108 indication provide requested storage unit, but do not have suitable permission, then cache manger 114 obtains the permission of (508) right, for example realize, so that can be to wherein writing by the exclusive entitlement that obtains row.If high-speed cache 104 determines that requested storage unit is not in high-speed cache, then detect " not ", and cache manger 114 will distribute (510) storage unit in high-speed cache 104, be used for placing therein new row, to from storer 112, ask (512) data with suitable permission, in a single day and receive and just these data and relevant marker character are placed into (514) data in the storage unit of being distributed in high-speed cache 104.Supporting some high-speed caches and among them, keeping in coherence's the system that requested data may be actual in another high-speed cache, rather than from storer 112.May sacrifice current effective content of this row to the distribution of the row in the high-speed cache 104, and may be such as previously described, writing back of victim further caused.Therefore, handle 500 and determine whether (512) victim requires to write back, and, carry out row the writing back that (514) will be sacrificed to storer if like this.
Referring to Fig. 4, handle 300 to show throttle mechanism and how to help to determine (302) external agent 102 whether/when data may be pressed in the high-speed cache 104.Throttle mechanism can prevent be annihilated this high-speed cache 104 and cause too much sacrifice of external agent 102, and it can reduce the efficient of system.For example, if external agent 102 is pressed into data in the high-speed cache 104, the data that then are pressed into were sacrificed before this storage unit of processor 110 accesses, and after a while, processor 110 once just require with this error in data turn back in the high-speed cache 104, therefore during processor 110 can cause that potential high-speed cache is not, and cause unnecessary high-speed cache and memory traffic.
If external agent 102 is general data high-speed caches that are used for processor 110 to the high-speed cache 104 that wherein is pressed into data, then throttle mechanism use (304) trial method determine whether external agent 102 is pressed into more multidata in high-speed cache 104/when be acceptable.If acceptable time, then high-speed cache 104 can be selected a storage unit in 208 high-speed caches 104, in order to comprise this data.If current is not acceptable time, then throttle mechanism may keep (308) these data (perhaps to keep the request to these data, perhaps order external agent 102 in this request of retry after a while), till throttle mechanism uses trial method (resource contention when for example, asking based on capacity or based on reception) to determine to be an acceptable time.
If high-speed cache 104 is private caches, then throttle mechanism can comprise many determinacy mechanism rather than described trial method, and for example to the threshold test of formation, this mechanism is used to external agent 102 is carried out flow control (306).In general, formation comprises such data structure: therein, identical order is deleted element when entering with element.
Referring to Fig. 5, another exemplary systems 400 comprises a manager 416, this manager 416 can allow external agent 402 that data are pressed in relevant backup buffer (CLB) cache 404 (" CLB 404 "), should relevant backup buffer cache 404 be counterparts of primary memory 406 (" storer 406 "), it imitates storer 406 usually.Impact damper generally includes the temporary storage aera, and can carry out access to it than primary memory, for example storer 406 lower potentialities.CLB 404 is for providing the intermediate suspension zone from external agent 402, newly arrived or newly-generated data, and described external agent 402 provides access than storer 406 lower potentialities for processor.Have known access mode, for example when serve in the communication agency of buffer circle at processor 408, the use of CLB 404 can be by reducing because stopping of causing in not of the high-speed cache during the access new data, the performance CLB 404 that improves processor 408 can be shared by a plurality of agencies and/or processor and their respective caches.
The CLB marker character 412 that CLB 404 comprises respectively storage mark symbol and data and CLB data 414 (respectively to Fig. 1 in marker character array 108 similar with data-carrier store 106).For the clauses and subclauses sum that equals X * Y, for each the data clauses and subclauses in the formation 410, CLB marker character 412 and CLB data 414 include Y data block, and wherein Y equals positive integer.Marker character 412 can comprise an indicator signal, is used for each clauses and subclauses of the number of the continuous high speed cache blocks represented by this marker character, and perhaps this information can imply.Storer reads so that when several line data that will be pressed into CLB 404 by external agent 402 were inserted high-speed cache, CLB 404 can interfere these stacked data when processor 408 sends.CLB can transmit maximum Y blocks of data to processor 408 for each notice.Every is in response to the cache capable request of filling and is sent to processor 408 from CLB 404, described cache is capable fill the address of request and storage in CLB marker character 412 and be marked as one of effective address coupling.
CLB 404 has the strategy that reads once, in case so that processor high speed buffer memory from CLB data 414 reading of data clauses and subclauses the time, CLB 404 can be with these clauses and subclauses invalid (forgetting).If Y is greater than " 1 ", then CLB 404 makes each data block invalid separately when this storage unit is by access, and has had only when access when owning " Y " pieces, just makes the respective markers symbol invalid.Processor 408 is required all Y pieces that access is associated with notice.
Can to the unit that comprises in similar ground, the unit executive system 400 of the similar title that comprises in the system 100 of Fig. 1.System 400 comprises and compares unit more or still less with said system 100.In addition, system 400 in general with Fig. 2 and 3 in example work similarly, except external agent 402 is pressed into data in CLB 404 rather than the high-speed cache 104, and when requested date was present among the CLB 404, processor 408 required to insert high-speed cache from CLB 404.
Above-mentioned technology is not limited to any concrete hardware or software arrangements; Can in calculating miscellaneous or processing environment, use them.For example, the system that is used to handle network PDU can comprise one or more Physical layers (PHY) equipment (for example, wired, optics, perhaps wireless PHY) and one or more link layer device (for example, Ethernet medium access controller (MAC) or sonet frame regulator).Receive logic (for example, receiving hardware, processor, perhaps thread) can be placed on the descriptor of data that comprise or data in the high-speed cache of operation as mentioned above by request in PDU, the PDU that receives via PHY and link layer device is operated.Logic subsequently (for example, different threads or processor) can visit the relevant data of described PDU apace via high-speed cache, and in the middle of other operation, carry out bag and handle operation, for example bridge joint, route, determine service quality (QoS), determine flow process (for example, based on source and destination address and PDU port) or filtering.A kind of like this system can comprise network processing unit (NP), it is characterized in that it being the set that reduced instruction set computer calculates (RISC) processor.The thread of described NP processor can carry out aforesaid receive logic and bag is handled operation.
Described technology can realize with the form of hardware, software or both combinations.This technology can realize with the form of the program carried out on programmable machine, and described programmable machine for example is portable computer, static calculation machine, networked devices, personal digital assistant and the similar devices of the medium (comprising volatibility and nonvolatile memory and/or storage unit), at least one input equipment and the one or more output devices that include processor, can be read by this processor.Program code is applied to using the data of input equipment input, so that carry out above-mentioned functions and produce output information.Described output information is applied to one or more output devices.
Can realize each program with the form of advanced procedures or object oriented programming languages, so that communicate by letter with machine system.Yet, if desired, also can realize described program with the form of compilation or machine language.Under any circumstance, described language can be language compiling or that explain.
Can on storage medium or equipment, store each such program, described storage medium or equipment for example are compact disc read-only memory (CD), hard disk, floppy disk or the similar mediums or the equipment that can be read by general or special purpose programmable machine, described program is used for when described storage medium or equipment are read by computing machine, disposes and operates this machine and carry out illustrated in this article procedure.The form with the machinable medium that is configured to have a program that it is also conceivable that realizes this system, and the storage medium that is so disposed makes machine come work with specific and predetermined mode.
Other embodiment are also within the scope of following claims.
Claims (52)
1. equipment that is used for cache assignment comprises:
Cache;
Cache management mechanism is configured to allow the external agent to ask data are put in the described cache, and allows processor that data are pressed in the described cache.
2. equipment as claimed in claim 1 further comprises a throttle mechanism, can be by the visit of described cache management mechanism, and be configured to specified data and when can be placed in the described cache.
3. equipment as claimed in claim 1 is characterized in that: described cache management mechanism also is configured to maintain data that comprise in the described cache and the coherence between the copy that keeps data in primary memory.
4. equipment as claimed in claim 3 is characterized in that: described cache management mechanism also is configured to maintain data that comprise in the described cache and the coherence between the data that comprise in one or more other high-speed caches.
5. equipment as claimed in claim 4 is characterized in that: described cache management mechanism also is configured to make in described one or more other high-speed caches, invalid with the corresponding data of data that are sent to the described cache from described external agent.
6. equipment as claimed in claim 4 is characterized in that: described cache management mechanism also be configured to in described one or more other high-speed caches, upgrade with the corresponding data of data that are sent to the described cache from described external agent.
7. equipment as claimed in claim 1, it is characterized in that: described cache management mechanism also is configured to allow described external agent that primary memory is upgraded, and stores the copy of the data that kept in described cache in the described primary memory.
8. equipment as claimed in claim 1 is characterized in that: described cache management mechanism also is configured to allow described external agent's request to go distribution for these data in described cache.
9. equipment as claimed in claim 1 is characterized in that: the current data that this cache management mechanism also is configured to allow described external agent to make and comprises in described cache is rewritten.
10. equipment as claimed in claim 9 is characterized in that: the data that described cache management mechanism also is configured to be placed in the described cache are set to amended coherency states.
11. equipment as claimed in claim 10 is characterized in that: the data that described cache management mechanism also is configured to also be placed in the described cache are set to exclusive coherency states.
12. equipment as claimed in claim 10 is characterized in that: described cache management mechanism also is configured to also be placed into the coherency states that the data in the described cache are set to share.
13. equipment as claimed in claim 9 is characterized in that: the data that described cache management mechanism also is configured to be placed in the described cache are set to clean coherency states.
14. equipment as claimed in claim 13 is characterized in that: the data that described cache management mechanism also is configured to also be placed in the described cache are set to exclusive coherency states.
15. equipment as claimed in claim 13 is characterized in that: described cache management mechanism also is configured to also be placed into the coherency states that the data in the described cache are set to share.
16. equipment as claimed in claim 1, comprising further that at least one other cache store dashes deposits the germanium device, and described cache management mechanism also is configured to allow described external agent's request that data are put into described at least one other cache.
17. equipment as claimed in claim 16, it is characterized in that: described cache management mechanism also is configured to allow described external agent's request to go distribution at least one of described at least one other cache, so that data are put into wherein.
18. equipment as claimed in claim 16 is characterized in that: described cache management mechanism also is configured to allow described external agent's request to go distribution in a plurality of described other caches, so that data are put into wherein.
19. equipment as claimed in claim 16 is characterized in that: described cache management mechanism also is configured to, and the current data that allows described external agent that described other caches are comprised is rewritten.
20. equipment as claimed in claim 1 is characterized in that: described cache comprises a high-speed cache, this high-speed cache imitation primary memory, and other high-speed caches can be visited this high-speed cache when attempting to visit described primary memory.
21. equipment as claimed in claim 20 is characterized in that: after another high-speed cache carried out read operation, the row that comprises in described cache was disengaged distribution.
22. equipment as claimed in claim 20 is characterized in that: after another high-speed cache carried out read operation, row was converted to shared state.
23. equipment as claimed in claim 1 is characterized in that: described external agent comprises input-output apparatus.
24. equipment as claimed in claim 1 is characterized in that: described external agent comprises a different processor.
25. equipment as claimed in claim 1 is characterized in that: described data comprise at least a portion data at least one network communication protocol data cell.
26. a method that is used for cache assignment comprises:
Allow the external agent to send to being placed into the request of the data in the cache; And
Allow described external agent that the described data that will be placed in the cache are provided.
27. method as claimed in claim 26 further comprises allowing processor that data are pressed in the described cache.
28. method as claimed in claim 26, further comprise: allowing described cache is this data check cache, if and described cache do not comprise these data, then ask these data there from primary memory.
29. method as claimed in claim 26 further comprises: determine when described external agent can provide the data that will be placed in the described cache.
30. method as claimed in claim 26 further comprises: allowing described external agent to ask described cache is that described data in the cache are selected a storage unit.
31. method as claimed in claim 26 further comprises: upgrade described cache with the address of the described data in the primary memory.
32. method as claimed in claim 26 further comprises: the state with described data upgrades described cache.
33. method as claimed in claim 26 further comprises: with described data primary memory is upgraded from described external agent.
34. an equipment that is used for cache assignment comprises:
Be used for allowing the external agent to send device to the request of the data that will be placed into cache; And
Be used for allowing the external agent these data to be inserted the device of described cache.
35. equipment as claimed in claim 34 further comprises being used for allowing processor data to be pressed into the device of described cache.
36. equipment as claimed in claim 34, comprise that further being used to allow described cache is this data check cache, if and described cache do not comprise these data, then ask the device of these data there from primary memory.
37. equipment as claimed in claim 34 comprises that further being used for allowing described external agent to ask described cache is the device that the described data of cache are selected a storage unit.
38. a system that is used for cache assignment comprises:
Cache; And
Memory management mechanism is configured to allow the external agent to ask described cache:
The delegation of selecting described cache is as the victim, and described row comprises data, and
Use from described external agent's new data and replace this data.
39. system as claimed in claim 38 is characterized in that: described memory management mechanism also is configured to allow described external agent with the described cache of the position renewal of this new data in primary memory.
40. system as claimed in claim 39 is characterized in that: described memory management mechanism also is configured to allow described external agent to upgrade primary memory with new data.
41. system as claimed in claim 39 further comprises:
Processor; And
The cache management mechanism that comprises in described processor, it is configured to manage the access of described processor to described cache.
42. system as claimed in claim 39, further comprise the cache that at least one is extra, described memory management mechanism also is configured to allow described external agent to ask some in the described extra cache memory or is all distributing delegation in corresponding extra cache memory.
43. system as claimed in claim 42 is characterized in that: described memory management mechanism also be configured to in described extra cache, with upgrade from the corresponding data of described external agent's new data.
44. system as claimed in claim 39 further comprises primary memory, it is configured to store the master copy of the data that comprise in the described cache.
45. system as claimed in claim 39 further comprises the external agent that at least one is extra, described memory management mechanism is configured to allow each extra external agent to ask described cache:
The delegation of selecting described cache is as the victim, and described row comprises data, and
Use from the described extra external agent's who files a request new data and replace this data.
46. system as claimed in claim 39 is characterized in that: described external agent also is configured to only some new datas are pressed in the described cache.
47. system as claimed in claim 46 further comprises network interface, it is configured to be pressed into more described new datas.
48. system as claimed in claim 46 is characterized in that: the part new data that described external agent also is configured to not to be pressed in the described cache writes primary memory.
49. system as claimed in claim 39 is characterized in that: data comprise descriptor.
50. a system that is used for cache assignment comprises:
At least one Physical layer (PHY) equipment;
At least one Ethernet medium access controller (MAC) equipment is used for the data that receive via PHY are carried out the link layer operation;
Be used to ask logic via at least a portion of the data that received by at least one PHY of high-speed cache and at least one MAC; And
High-speed cache, described high-speed cache comprises:
Cache;
Cache management mechanism is configured to
In response to described request, at least a portion of the data that will receive via at least one PHY and at least one MAC is placed in the described cache; And
In response to not being stored in the request of the data in the described cache, allow processor that data are pressed in the described cache.
51. system as claimed in claim 50 is characterized in that: at least one thread in the sets of threads that is provided by network processing unit is provided described logic.
52. system as claimed in claim 50 further comprises being used for handling at least a logic operating to carry out following bag from described high-speed cache data retrieved: bridge joint, route, determine service quality, determine flow process and filtering.
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| US10/406,798 | 2003-04-02 |
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| WO2004095291A2 (en) | 2004-11-04 |
| EP1620804A2 (en) | 2006-02-01 |
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| TWI259976B (en) | 2006-08-11 |
| KR101038963B1 (en) | 2011-06-03 |
| KR20060006794A (en) | 2006-01-19 |
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| TW200426675A (en) | 2004-12-01 |
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