CN100394359C - Interface for intelligent card simulative debugging system - Google Patents
Interface for intelligent card simulative debugging system Download PDFInfo
- Publication number
- CN100394359C CN100394359C CNB2005100115186A CN200510011518A CN100394359C CN 100394359 C CN100394359 C CN 100394359C CN B2005100115186 A CNB2005100115186 A CN B2005100115186A CN 200510011518 A CN200510011518 A CN 200510011518A CN 100394359 C CN100394359 C CN 100394359C
- Authority
- CN
- China
- Prior art keywords
- simulation unit
- data
- control module
- register
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The present invention relates to an interface for a simulation debugging system of an intelligent card, which relates to the technical field of emulation debugging technique of the intelligent card. The present invention comprises an address line 1 coming from a control unit, an address line 2 coming from a simulation unit, a data line 1 communicated with the control unit in both way, a data line 2 communicated with the simulation unit in both way, a clock input line 1 coming from the control unit, a clock input line 2 coming from the simulation unit, a writing register group, a reading register group, a set of address decoding circuits 1 for address decoding to the writing register group and the reading register group relative to the control unit and a set of address decoding circuits 2 for address decoding to the writing register group and the reading register group relative to the control unit, wherein a clock of the writing register group is a system clock of the control unit, and a clock of the reading register group is the system clock of the simulation unit. The interface of the present invention can realize a plurality of different simulation units so as to simulate different intelligent cards, and can also ensure the reliable operation of an asynchronous clock system.
Description
Technical field
The present invention relates to intelligent card artificial debugging technique field, especially for the interface of intelligent card simulative debugging system.
Background technology
Generally comprise two parts of control module and simulation unit in the intelligent card simulative debugging system, wherein control module is used for being connected with computer interface, and simulation unit is used for the software and hardware function of smart card is simulated.In the prior art, control module is handled, the artificial debugging process is controlled the data of simulation unit by the interface of serial or parallel.Problem is that smart card product is of a great variety, and the hardware design of required simulation unit has nothing in common with each other, and causes the kind of control module and simulation unit interface also of all kinds.In addition, the system clock of most of smart card and the clock of control module have nothing in common with each other, and form the asynchronous clock system when making artificial debugging between control module and the simulation unit, at this moment can't guarantee both sides' reliable communicating with common serial line interface and parallel interface.
Summary of the invention
In order to solve above-mentioned problems of the prior art, the purpose of this invention is to provide a kind of interface that is used for intelligent card simulative debugging system.Use interface of the present invention can realize a plurality of different simulation unit, thereby the different smart card of emulation can also guarantee the reliably working of asynchronous clock system.
In order to reach above-mentioned goal of the invention, technical scheme of the present invention realizes as follows:
A kind of interface that is used for intelligent card simulative debugging system, it is used for being connected of intelligent card simulative debugging system control module and simulation unit, and realizes exchanges data and artificial debugging operation between control module and the simulation unit.Its design feature is that it comprises:
Address wire one from control module;
Address wire two from simulation unit;
With the data line one of control module both-way communication, data line one and control module carry out various data write;
With the data line two of simulation unit both-way communication, data line two and simulation unit are carried out various data write;
Clock incoming line one from control module;
Clock incoming line two from simulation unit;
Write registers group for one;
A read register group;
One cover is connected to the address decoding circuitry one of writing registers group with address wire one and reaches
One cover is connected to the address decoding circuitry two of writing registers group with address wire two;
Write registers group and be used for receiving various control signals and the data that control module sends, and control signal and data are sent to simulation unit;
The read register group is used for receiving data and the response signal that simulation unit is sent, and data are sent to control module;
The clock of writing registers group is the system clock of control module;
The clock of read register group is the system clock of simulation unit.
In above-mentioned interface, the described registers group of writing comprises:
Control register is used for the controlled variable that storage control unit writes;
Address register is used for the address of the simulation unit that storage control unit will visit;
Write data register is used for the data that storage control unit writes, and outputs to simulation unit then;
Write debug registers, be used for the debug signal that storage control unit writes, be loaded into simulation unit then;
Write handshake register, be used for the commencing signal of shaking hands that storage control unit writes, be loaded into simulation unit then.
In above-mentioned interface, described read register group comprises:
Read data register is used for the data that the storage emulation unit writes, and outputs to control module;
Read debug registers, be used for writing the debugging operations result of simulation unit, output to control module then;
Read handshake register, be used for writing the end signal of shaking hands that simulation unit transmits, finish debugging operations.
The present invention has been owing to adopted above-mentioned interface, uses it just can not do a plurality of different simulation unit of realization under the situation of any variation at user's computer program and control module, thus the different smart card of emulation.Simultaneously, by writing handshake register in the interface and reading the handshake that handshake register is transmitted, can realize the reliably working of asynchronous clock system in control module and the simulation unit.
The present invention will be further described below in conjunction with the drawings and specific embodiments.
Description of drawings
Fig. 1 is used for the connection diagram of intelligent card simulative debugging system for interface of the present invention;
Fig. 2 is the fundamental diagram of interface of the present invention;
Fig. 3 is for writing registers group, read register group respectively and the signal transitive relation figure between the control module, simulation unit in the interface of the present invention.
Embodiment
Apply the present invention in the intelligent card simulative debugging system, processing host links to each other with control module, control module is connected by interface of the present invention with simulation unit, and simulation unit is by its set contact card or non-contact card antenna and external read card device interaction data, as shown in Figure 1.
Referring to Fig. 2 and Fig. 3, interface of the present invention comprises address wire 1, address wire 22, data line 1, data line 24, clock incoming line 1, clock incoming line 26, adopts read register group 8, address decoding circuitry 1 and the address decoding circuitry 2 10 of writing registers group 7, employing simulation unit system clock of control module system clock.The function on partial line road is as shown in table 1 in the interface.
| Title | Direction (with respect to control module) | Functional definition |
| data[7:0] | Two-way | Data bus |
| rd_n | Output | Read signal is effectively low |
| wr_n | Output | Write signal is effectively low |
| addr[6:0] | Output | Address wire |
Table 1
Address wire 1 and clock incoming line 1 be from control module, and address wire 22 and clock incoming line 26 be from simulation unit, data line 1, data line 24 respectively with control module, simulation unit both-way communication.Address wire 1 is connected to by address decoding circuitry 1 and writes registers group 7, and address wire 22 is connected to by address decoding circuitry 2 10 and writes registers group 7.Write registers group 7 and receive various control signals and the data that control module sends, and control signal and data are sent to simulation unit.Read register group 8 receives data and the response signal that simulation unit is sent, and data are sent to control module.Writing registers group 7 comprises control register 71, address register 72, write data register 73, writes debug registers 74 and writes handshake register 75.The controlled variable that control register 71 storage control units write, the address of the simulation unit that address register 72 storage control units will be visited, is write debug registers 74 and is write handshake register 75 data, the debug signal that write of storage control unit and the commencing signal and output to simulation unit of shaking hands respectively write data register 73.Read register group 8 comprises read data register 81, reads debug registers 82 and reads handshake register 83.Read data register 81 and read debug registers 82 respectively the data that write of storage emulation unit and artificial debugging the result and output to control module, read handshake register 83 and write the end signal of shaking hands that simulation unit transmits.The function of above-mentioned register is as shown in table 2.
| Decoding address | Title | Registers group | Title | Function |
| 0 | W_ADDR | (7) | Address register | The address of the simulation unit that storage control unit will be visited |
| 1 | W_DAT | (7) | Write data register | The data that control module writes, simulation unit is read |
| 2 | CON | (7) | Control register | The controlled variable that control module writes |
| 3 | W_DEBUG | (7) | Write debug registers | The debug signal that control module writes |
| 4 | W_SHAKE | (7) | Write handshake register | The handshake that control module writes |
| 5 | R_DAT | (8) | Read data register | The data that control module is read, simulation unit writes |
| 6 | R_DEBUG | (8) | Read debug registers | The debug signal that control module is read |
| 7 | R_SHAKE | (8) | Read handshake register | The handshake that control module is read |
Table 2
Table 3 is the definition of control register CON in the table 2.
| R/W(D7) | Standby (D6-D3) | Se12(D2-D0) |
| Read-write is selected high low for writing for reading | Simulation unit processor address space is selected: 000 program address selects 001 internal data address selection, 010 external data address selection, 011 special function register to select 100 processor program counters (PC) to select 101 breakpoint address to select |
Table 3
Table 4 is definition of writing debug registers W_DEBUG in the table 2.
| D2 | D1 | D0 |
| Step_n | Stop_n | bpdis |
Table 4
Table 5 is function combinations of writing debug registers W_DEBUG in the table 4.
| step_n | stop_n | bpdis | Function |
| 0 | 0 | X | The program single step run |
| 0 | 0 | X | Out of service |
| X | 1 | 0 | Full speed running is met breakpoint and is stopped |
| X | 1 | 1 | Full speed running |
Table 5
Interface of the present invention comprises the operation of exchanges data and the operation of artificial debugging when using, and wherein the controlled step of exchanges data is:
1. control register 71 write control informations of control module in interface;
2. the write data register 73 of control module in interface writes data;
3. the write handshake register 75 of control module in interface writes the commencing signal of shaking hands, and passes to simulation unit;
4. after simulation unit is received the commencing signal of shaking hands, from control register 71 and write data register 73, read in corresponding control information and data respectively, carry out data exchange operation;
5. simulation unit read data register in interface 81 after exchanges data is finished writes the data after the exchange, and the handshake register 83 of reading in interface writes the end signal of shaking hands, and data exchange operation finishes.
Wherein the operation steps of artificial debugging is:
1. the write debug registers 74 of control module in interface writes debug signal, wherein single step is set, stops, breakpoint, the artificial debugging program such as forbids;
2. the write handshake register 75 of control module in interface writes the commencing signal of shaking hands, and passes to simulation unit;
3. after simulation unit is received the commencing signal of shaking hands, carry out corresponding artificial debugging operation;
4. simulation unit is read the result that debug registers 82 writes artificial debugging in interface after artificial debugging is finished, and the handshake register 83 of reading in interface writes the end signal of shaking hands, the artificial debugging EO.
Claims (3)
1. interface that is used for intelligent card simulative debugging system, it is used for being connected of intelligent card simulative debugging system control module and simulation unit, and realizes exchanges data and artificial debugging operation between control module and the simulation unit, it is characterized in that it comprises:
Address wire one (1) from control module;
Address wire two (2) from simulation unit;
Carry out various data write with the data line one (3) and the control module of control module both-way communication;
Carry out various data write with the data line two (4) and the simulation unit of simulation unit both-way communication;
Clock incoming line one (5) from control module;
Clock incoming line two (6) from simulation unit;
Write registers group (7) for one;
A read register group (8);
One cover is connected to the address decoding circuitry one (9) of writing registers group (7) with address wire one (1) and reaches
One cover is connected to the address decoding circuitry two (10) of writing registers group (7) with address wire two (2);
Write registers group (7) and be used for receiving various control signals and the data that control module sends, and control signal and data are sent to simulation unit;
Read register group (8) is used for receiving data and the response signal that simulation unit is sent, and data are sent to control module;
The clock of writing registers group (7) is the system clock of control module;
The clock of read register group (8) is the system clock of simulation unit.
2. the interface that is used for intelligent card simulative debugging system as claimed in claim 1 is characterized in that, the described registers group (7) of writing comprising:
Control register (71) is used for the controlled variable that storage control unit writes;
Address register (72) is used for the address of the simulation unit that storage control unit will visit;
Write data register (73) is used for the data that storage control unit writes, and outputs to simulation unit then;
Write debug registers (74), be used for the debug signal that storage control unit writes, be loaded into simulation unit then;
Write handshake register (75), be used for the commencing signal of shaking hands that storage control unit writes, be loaded into simulation unit then.
3. the interface that is used for intelligent card simulative debugging system as claimed in claim 1 is characterized in that, described read register group (8) comprising:
Read data register (81) is used for the data that the storage emulation unit writes, and outputs to control module;
Read debug registers (82), be used for writing the debugging operations result of simulation unit, output to control module then;
Read handshake register (83), be used for writing the end signal of shaking hands that simulation unit transmits, finish debugging operations.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100115186A CN100394359C (en) | 2005-04-01 | 2005-04-01 | Interface for intelligent card simulative debugging system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100115186A CN100394359C (en) | 2005-04-01 | 2005-04-01 | Interface for intelligent card simulative debugging system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1841270A CN1841270A (en) | 2006-10-04 |
| CN100394359C true CN100394359C (en) | 2008-06-11 |
Family
ID=37030326
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100115186A Active CN100394359C (en) | 2005-04-01 | 2005-04-01 | Interface for intelligent card simulative debugging system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100394359C (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102110047B (en) * | 2009-12-23 | 2013-12-11 | 北京中电华大电子设计有限责任公司 | Method for reading and writing RAM in development system |
| CN103885904B (en) * | 2014-04-16 | 2017-11-28 | 国网上海市电力公司 | A kind of data-storage system and method for portable main website |
| CN110489206B (en) * | 2019-07-05 | 2023-05-12 | 北京中电华大电子设计有限责任公司 | Emulator with program debugging prohibition function |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2572475Y (en) * | 2002-10-09 | 2003-09-10 | 中国印钞造币总公司 | Card terminal analog device |
| US6769622B1 (en) * | 2003-03-14 | 2004-08-03 | Stmicroelectronics, Inc. | System and method for simulating universal serial bus smart card device connected to USB host |
| CN2783404Y (en) * | 2005-04-01 | 2006-05-24 | 北京清华同方微电子有限公司 | Interface for emulation debugging system of intelligent card |
-
2005
- 2005-04-01 CN CNB2005100115186A patent/CN100394359C/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2572475Y (en) * | 2002-10-09 | 2003-09-10 | 中国印钞造币总公司 | Card terminal analog device |
| US6769622B1 (en) * | 2003-03-14 | 2004-08-03 | Stmicroelectronics, Inc. | System and method for simulating universal serial bus smart card device connected to USB host |
| JP2004280818A (en) * | 2003-03-14 | 2004-10-07 | Stmicroelectronics Inc | System and method for simulating universal serial bus smart card device connected to usb host |
| CN2783404Y (en) * | 2005-04-01 | 2006-05-24 | 北京清华同方微电子有限公司 | Interface for emulation debugging system of intelligent card |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1841270A (en) | 2006-10-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100565472C (en) | A kind of adjustment method that is applicable to multiprocessor karyonide system chip | |
| US6769622B1 (en) | System and method for simulating universal serial bus smart card device connected to USB host | |
| CN104484301B (en) | A kind of IO bus units based on FPGA with self-recognition function | |
| CN101198936A (en) | Method and apparatus for emulating a programmable unit | |
| CN101436171B (en) | Modular communication control system | |
| CN101118568A (en) | Device and method for outputting signal of emulation infrared detector | |
| CN101236774B (en) | Device and method for single-port memory to realize the multi-port storage function | |
| CN102999453A (en) | Universal nonvolatile memory control device for system on chip | |
| CN103389845A (en) | Capacitance touch screen burn test system | |
| CN104021101A (en) | USB interface system and implementation method based on LPC1768 platform | |
| CN100394359C (en) | Interface for intelligent card simulative debugging system | |
| CN103793263B (en) | DMA transaction-level modeling method based on Power PC processor | |
| CN204390227U (en) | Computing equipment expanding unit and extendible computing system | |
| CN104123246A (en) | Interface expansion device and serial attached SCSI expander | |
| CN101261611A (en) | Peripheral apparatus data-transmission apparatus and transmission method | |
| CN103377161A (en) | Main board and data processing method applied to same | |
| CN104572515B (en) | Tracking module, method, system and on-chip system chip | |
| CN101281507A (en) | USB interface type DSP real-time simulation development system | |
| CN103150262B (en) | Pipeline access means | |
| CN100511172C (en) | Inter-board transparent transmission bus test device and method thereof | |
| CN102880574A (en) | Method for simulating low speed parallel interface by using GPIO (general purpose input output) | |
| CN2783404Y (en) | Interface for emulation debugging system of intelligent card | |
| CN213601206U (en) | Structure for reducing computer memory occupation | |
| CN103049214B (en) | Magnetic disc array card and there is the disc array system of extended function | |
| CN102446132B (en) | Method and device for performing board-level management by simulating local bus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee | ||
| CP02 | Change in the address of a patent holder |
Address after: 100083 Beijing City, Haidian District Wudaokou Wangzhuang Road No. 1 Tongfang Technology Plaza D floor 18 West Patentee after: Beijing Tongfang Microelectronics Company Address before: 100083 A, block 2901, Tongfang science and Technology Plaza, Beijing Patentee before: Beijing Tongfang Microelectronics Company |