CN100388448C - Wafer-grade packing method - Google Patents
Wafer-grade packing method Download PDFInfo
- Publication number
- CN100388448C CN100388448C CNB2005100064502A CN200510006450A CN100388448C CN 100388448 C CN100388448 C CN 100388448C CN B2005100064502 A CNB2005100064502 A CN B2005100064502A CN 200510006450 A CN200510006450 A CN 200510006450A CN 100388448 C CN100388448 C CN 100388448C
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- Prior art keywords
- wafer
- those
- upper cover
- patterns
- cover wafer
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Links
- 238000000034 method Methods 0.000 title claims abstract description 28
- 238000012856 packing Methods 0.000 title abstract description 7
- 238000005538 encapsulation Methods 0.000 claims description 14
- 239000013078 crystal Substances 0.000 claims description 12
- 238000005520 cutting process Methods 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 8
- 238000004140 cleaning Methods 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 2
- 239000010453 quartz Substances 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims 1
- 229910052755 nonmetal Inorganic materials 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 64
- 238000012536 packaging technology Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000001771 impaired effect Effects 0.000 description 4
- 238000009940 knitting Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000003698 laser cutting Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000000007 visual effect Effects 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Images
Abstract
The present invention relates to a wafer-grade packing method. Firstly, an element wafer is offered, wherein the element wafer comprises a plurality of elements and a plurality of connection pads which are arranged on the upper surface of the element wafer and electrically connected with the elements. Subsequently, an upper cover wafer is offered, a plurality of jointing patterns and a plurality of groove patterns are formed at the lower surface of the upper cover wafer. Then, the upper surface of the element wafer is connected with the lower surface of the upper cover wafer by the jointing patterns; the positions of the groove patterns correspond to the positions of the connection pads.
Description
Technical field
The present invention relates to a kind of method of wafer-class encapsulation, particularly relate to a kind of method of wafer-class encapsulation of utilizing local engagement one an element wafer and a upper cover wafer.
Background technology
Packaging technology is a most important last part technology in the making of semiconductor element or microcomputer electric component.The rate of finished products of packaging technology not only influences the usefulness of semiconductor element or microcomputer electric component, and the while package dimensions is the key point of chip microminiaturization especially.Please refer to Fig. 1 to Fig. 4, Fig. 1 to Fig. 4 is the method schematic diagram of existing encapsulation.As shown in Figure 1, at first, provide an element wafer 10 to be packaged, wherein element wafer 10 comprises a plurality of elements 12, and a plurality of connection gasket 14 is located at the surface of element wafer 10.Then carry out a cutting technology, element wafer 10 is cut into a plurality of crystal grain 16 according to predefined Cutting Road (figure does not show).
As shown in Figure 2, also provide a upper cover wafer 18, and upper cover wafer 18 is cut into a plurality of over caps (cap) 20, wherein the shape of over cap 20 is corresponding to the shape of crystal grain 16, and its undersized is in the shape of crystal grain 16.As shown in Figure 3, then in surface coated one knitting layer 22 of crystal grain 16, and knitting layer 22 does not cover connection gasket 14.As shown in Figure 4, utilize knitting layer 22 to engage crystal grain 16 and over cap 20 at last.
Yet above-mentioned existing method for packing has following shortcoming.At first, existing method for packing cuts into element wafer after a plurality of crystal grain earlier, utilizes over cap to encapsulate again, therefore must utilize manual type production, causes the efficient of packaging technology low not good with rate of finished products.Moreover existing spent manpower of method for packing and money cost are too high, and under the trend of chip microminiaturization, existing method for packing can't be satisfied with the encapsulation requirement of micro element simultaneously.
In view of this, the applicant has proposed the present invention of improvement according to many years of experience, to overcome the shortcoming of existing method for packing, uses the rate of finished products and the production capacity of effective lifting packaging technology.
Summary of the invention
Therefore, main purpose of the present invention is to provide a kind of method of wafer-class encapsulation, to solve the difficult problem that prior art can't overcome.
According to claim of the present invention, provide a kind of method of wafer-class encapsulation.At first provide an element wafer, and this element wafer comprises a plurality of elements, and a plurality of connection gasket is located at a upper surface of this element wafer and is electrically connected with those elements.One upper cover wafer is provided subsequently, and forms a plurality of joint patterns and a plurality of groove pattern in a lower surface of this upper cover wafer.Subsequently, utilize those to engage pattern and engage this upper surface of this element wafer and this lower surface of this upper cover wafer, and the position of those groove patterns is corresponding to the position of those connection gaskets.
Method of wafer-class encapsulation of the present invention utilizes a upper cover wafer to be engaged on the element wafer in the local engagement mode; use and protect the element that is made on the element wafer; and by the connection pattern of upper cover wafer and the configuration of groove pattern; the upper cover wafer of external zones can be removed easily and not cause connection gasket impaired, therefore carries out further packaging technology after crystal grain forms easily.
In order further to understand feature of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing.Yet accompanying drawing only for reference with aid illustration usefulness, be not to be used for to the present invention's limitr in addition.
Description of drawings
Fig. 1 to Fig. 4 is the method schematic diagram of existing encapsulation.
Fig. 5 to Figure 10 is the method for wafer-class encapsulation schematic diagram of one embodiment of the present invention.
The simple symbol explanation
10 element wafers, 12 elements
14 connection gaskets, 16 crystal grain
18 upper cover wafer, 20 over caps
22 knitting layers, 50 element wafers
52 element regions, 54 external zoness
56 elements, 58 connection gaskets
60 upper cover wafer 62 engage pattern
64 groove patterns, 66 crystal grain
Embodiment
Please refer to Fig. 5 to Figure 10, Fig. 5 to Figure 10 is the method for wafer-class encapsulation schematic diagram of one embodiment of the present invention, wherein for highlight characteristics of the present invention and be convenient to the explanation for the purpose of, Fig. 5 to Figure 10 only demonstrates a single element region and a single external zones.As shown in Figure 5, one element wafer 50 at first is provided, element wafer 50 is divided into a plurality of element regions 52 and a plurality of external zoness 54, and element wafer 50 comprises that also a plurality of elements 56 are arranged at element region 52, and a plurality of connection gasket 58 is located at external zones 54 and is exposed to the upper surface of element wafer 50.Wherein element wafer 50 can be semiconductor wafer, as silicon wafer, or for other is applicable to the wafer of making various element, element 56 can be any semiconductor element, photo-sensitive cell or microcomputer electric component etc., and element 56 is electrically connected by a plurality of intraconnections (figure does not show) with connection gasket 58 and other.
As shown in Figure 6, provide a upper cover wafer 60, and form a plurality of joint patterns 62 and a plurality of groove patterns 64 in the lower surface of upper cover wafer 60.Engage pattern 62 and be formed at corresponding to the position around the element region 52, groove pattern 64 then is formed at the position corresponding to connection gasket 58.The visual demands of upper cover wafer 60 are different and select different materials for use, for example if element 56 be a photo-sensitive cell, then use chip glass or quartz wafer, are general semiconductor element or microcomputer electric component as if element 56, then use semiconductor wafer.The material that engages pattern 62 can be selected metal material for use, for example scolding tin or gold etc., or be nonmetallic materials, for example polyimides (polyimide) or epoxy resin (epoxy) etc., and the formation that engages pattern 62 also visual material characteristic or effect select different modes for use, for instance, select metal material for use if engage pattern 62, then can utilize evaporation, sputter, plating or wire mark mode to form, select nonmetallic materials for use, then can utilize wire mark or coating method to form if engage pattern 62.The formation of groove pattern 64 then can be according to the material difference of upper cover wafer 60, and utilizes modes such as laser cutting, machine cuts or etching to form.In addition, form joint pattern 62 and do not limit with the order that forms groove pattern 64, for example form joint pattern 62 earlier and form groove pattern 64 again, vice versa.In addition, before follow-up joint upper cover wafer 60 and element wafer 50, need to form contraposition key (figure does not show) prior to the surface of upper cover wafer 60, in the hope of accurate contraposition, and it should be noted that because formation contraposition key (figure does not show) easily produces particle contamination with the step that forms groove pattern 64, therefore can after forming, groove pattern 64 carry out a cleaning procedure, and impaired to avoid engaging pattern 62.
Please refer to Fig. 7, and in the lump with reference to figure 8.As shown in Figure 7, carry out a pair of position technology earlier, for example utilize the contraposition key (figure does not show) on the surface that is made in upper cover wafer 60 in advance, utilize the upper surface of joint pattern 62 joint element wafers 50 and the lower surface of upper cover wafer 60 again, by this upper cover wafer 60 with engage pattern 62 with element 56 airtight involutions, polluted in subsequent technique to avoid element 56.64 of groove patterns are positioned at connection gasket 58 tops, can avoid connection gasket 58 impaired when follow-up cutting upper cover wafer 60 by this.As shown in Figure 8; engaging pattern 62 is a closed pattern; and when upper cover wafer 60 with after element wafer 50 engages; engage pattern 62 be surrounded on element 56 around; and hermetic closed with upper cover wafer 60, therefore effective protection component 56, and groove pattern 64 is an annular patterns; and make connection gasket 58 tops have a cushion space, be beneficial to the cutting of follow-up upper cover wafer 60.
As shown in Figure 9, upper surface by upper cover wafer 60 covers wafer 60 corresponding to the position cutting upper cover wafer 60 of groove pattern 64 until cutting to put on, the particulate that is produced when then carrying out a cleaning procedure with removal cutting upper cover wafer 60 avoids connection gasket 58 to be polluted.Wherein the cutting of upper cover wafer 60 can utilize laser cutting, machine cuts or etching mode etc. to reach.At last as shown in figure 10, according to default in advance Cutting Road (figure does not show) cutting element wafer 50,, promptly finish the technology of wafer-class encapsulation of the present invention to form a plurality of crystal grain 66.Wherein the technology of cutting element wafer 50 can be utilized laser cutting, machine cuts or etching mode, and is undertaken by the upper surface or the lower surface of element wafer 50.
Method of wafer-class encapsulation of the present invention utilizes a upper cover wafer to be engaged on the element wafer in the local engagement mode; use and protect the element that is made on the element wafer; and by the connection pattern of upper cover wafer and the configuration of groove pattern; the upper cover wafer of external zones can be removed easily and not cause connection gasket impaired, therefore carries out further packaging technology after crystal grain forms easily.In addition, compared to prior art, therefore the present invention has high rate of finished products and lower cost owing to adopt batch production.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (9)
1. method of wafer-class encapsulation comprises:
One element wafer is provided, and this element wafer is divided into a plurality of element regions and a plurality of external zones, and this element wafer comprises that also a plurality of elements are arranged at those element regions, and a plurality of connection gasket is located at those external zoness and is exposed to a upper surface of this element wafer;
One upper cover wafer is provided;
A lower surface in this upper cover wafer forms a plurality of joint patterns and a plurality of groove pattern, and respectively this joint pattern is formed at corresponding to the position around this element region respectively, and respectively this groove pattern is formed at position corresponding to those connection gaskets;
Utilize those to engage pattern and engage this upper surface of this element wafer and this lower surface of this upper cover wafer, this upper cover wafer engages pattern with the airtight involution of those elements with those by this, and those groove patterns are positioned at those connection gasket tops simultaneously;
Cut this upper cover wafer by a upper surface of this upper cover wafer corresponding to the position of this groove pattern and wear this upper cover wafer until cutting;
Carry out cleaning procedure; And
Cut this element wafer, to form a plurality of crystal grain (die).
2. the method for claim 1, wherein those elements are photo-sensitive cell.
3. the method for claim 1, wherein those elements are semiconductor element.
4. the method for claim 1, wherein those elements are microcomputer electric component.
5. the method for claim 1, wherein this upper cover wafer is selected from semiconductor wafer, chip glass and quartz wafer.
6. the method for claim 1, wherein those materials that engage patterns are selected from metal.
7. the method for claim 1, wherein those materials that engage patterns are selected from nonmetal.
8. the method for claim 1, wherein those engage patterns are formed at this upper cover wafer prior to those groove patterns this lower surface.
9. the method for claim 1, wherein those groove patterns engage this lower surface that patterns are formed at this upper cover wafer prior to those.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100064502A CN100388448C (en) | 2005-02-01 | 2005-02-01 | Wafer-grade packing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100064502A CN100388448C (en) | 2005-02-01 | 2005-02-01 | Wafer-grade packing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1815704A CN1815704A (en) | 2006-08-09 |
| CN100388448C true CN100388448C (en) | 2008-05-14 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100064502A Expired - Fee Related CN100388448C (en) | 2005-02-01 | 2005-02-01 | Wafer-grade packing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100388448C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104944362B (en) * | 2014-03-26 | 2017-01-25 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing MEMS (Micro-Electro-Mechanical System) device structure |
| CN105984839B (en) * | 2015-02-27 | 2017-11-14 | 中芯国际集成电路制造(上海)有限公司 | A kind of MEMS and preparation method thereof, electronic installation |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5895233A (en) * | 1993-12-13 | 1999-04-20 | Honeywell Inc. | Integrated silicon vacuum micropackage for infrared devices |
| EP1199744A1 (en) * | 2000-10-19 | 2002-04-24 | Agilent Technologies, Inc. (a Delaware corporation) | Microcap wafer-level package |
| US20030075794A1 (en) * | 2001-10-23 | 2003-04-24 | Felton Lawrence E. | MEMS capping method and apparatus |
-
2005
- 2005-02-01 CN CNB2005100064502A patent/CN100388448C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5895233A (en) * | 1993-12-13 | 1999-04-20 | Honeywell Inc. | Integrated silicon vacuum micropackage for infrared devices |
| EP1199744A1 (en) * | 2000-10-19 | 2002-04-24 | Agilent Technologies, Inc. (a Delaware corporation) | Microcap wafer-level package |
| US20030075794A1 (en) * | 2001-10-23 | 2003-04-24 | Felton Lawrence E. | MEMS capping method and apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1815704A (en) | 2006-08-09 |
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