CN100380639C - Thin multiple semiconductor die package - Google Patents
Thin multiple semiconductor die package Download PDFInfo
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- CN100380639C CN100380639C CNB2004800034731A CN200480003473A CN100380639C CN 100380639 C CN100380639 C CN 100380639C CN B2004800034731 A CNB2004800034731 A CN B2004800034731A CN 200480003473 A CN200480003473 A CN 200480003473A CN 100380639 C CN100380639 C CN 100380639C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
Abstract
A method and apparatus for forming a multiple semiconductor die assembly (200, 300, 400) having a thin profile are presented. The semiconductor die assembly (200, 300, 400) comprises a plurality of die packages (100), with each die package (100) including a lead frame (10) having a plurality of leads (11) each having a down set portion (101) extending from a first surface (14). A semiconductor die (30) is disposed in a central region (12) of the lead frame (10) and is electrically connected to the leads (11). An encapsulant (50) is disposed in the central region (12) and covers to the semiconductor die (30) and a portion of the leads (11). The first surface (14) of the leads (11) and a first surface (34) of the semiconductor die (30) are substantially coplanar and are exposed from the encapsulant (50). The first surface (34) of the semiconductor die (30) and the down set portions (101) of the leads form a cavity (102). The semiconductor die packages (200, 300, 400) are stacked such that at least a portion of the encapsulant (50) is disposed in the cavity of a next higher semiconductor die package (200, 300, 400) in the stack.
Description
The related application reference
Present patent application requires to obtain U.S. Provisional Patent Application No.60/445,677 and U.S. Provisional Patent Application No.60/444,987 interests, they are respectively at filing an application on February 6th, 2003 and on February 4th, 2003, and the full content that this paper quotes them is as a reference.
Technical field
The present invention relates generally to the semiconductor manufacturing, more particularly, relates to the encapsulation of multiple semiconductor dice assembly.
Background technology
Portable electric appts, for example radio telephone, beep-pager and personal electric assistant (PDA) are just becoming and are becoming increasingly complex, and become more and more small and light simultaneously.Semiconductor chip or dice, for example microprocessor unit sheet and memory cell sheet are used for portable electric appts.Typically, dice is installed in pottery or the Plastic Package, and this encapsulation provides support, protection, dice heat radiation and being provided for is switched on and the lead system of signal allocation.
A kind of expectation is arranged in the semiconductor packages industry, make the profile (thickness) of semiconductor packages exactly thus minimize be convenient to move, the development in wireless and medical applications field.Current requirement for encapsulation is to have other profile of submillimeter level.Also produce another requirement for the demand that increases processing power and speed, increased number (just improving dice density) that can be coupled to the dice in the given area and the length that reduces circuit between the dice exactly.
For the requirement that increases dice density and reduction path, a kind of known solution is known as multi-chip module (MCM), and wherein a large amount of dice is stacked in the single molded package.In encapsulation, separate each dice by connecting isolation each layer/insert (interposer) with thread bonded connection and/or counter-rotating dice (flip die), this thread bonded and/or the connection of counter-rotating dice are used for dice is electrically connected on a common lead frame.Yet this solution has some shortcomings.For example, the encapsulation meeting with stacked die makes package assembling become complicated owing to increasing the number that is electrically connected and insulating barrier/insert need being set between dice at least in part.If produce any defective during component package, then whole encapsulation comprises chip, can not save.
An example of MCM encapsulation was a U.S. Patent No. 6,452,278, and it authorizes Vincent DiCaprio etc. on September 17th, 2002.DiCaprio etc. have described a kind of encapsulation, comprise the have center bore substrate of (central aperture).DiCaprio etc. further described be positioned at the chamber one or more semiconductor dice so that thin profile to be provided.
Can be appreciated that as those skilled in the art the cost ratio of the encapsulation defective goods with multiple unit sheet of doing over again the single die package defective goods of doing over again are higher.In order to make the cost minimum of doing over again, " known good dice (Known Good Die) " (KGD) rule is adopted in the semiconductor manufacturing.Generally speaking, thus the KGD rule is meant the higher dice grade product of price that makes each dice by other reliability guarantee of the certain level of can bringing of providing of semiconductor dice manufacturer.The rule of thumb (rule of thumb) during MCM makes is meant that if include 5 dice of any given type in the single encapsulation or the device that surpasses 200 bondings is arranged, then they should be KGD.This rule develops from following industry experience, promptly compares higher at the cost of doing over again on the dice rank with the cost of replacing inferior packed part on the circuit board rank.When the user runs into inferior MCM, compare with the cost of replacing independent packaged integrated circuits (IC), cost to influence meeting more serious.
Therefore, the inventor recognizes that people need semiconductor packages to have higher dice density (for example having more than a dice in an encapsulation), the profile that approaches and balance rework cost and the cost that obtains secure KGD.
Summary of the invention
Above-mentioned requirement with other is satisfied by a kind of semiconductor unit chip module, it comprises: a plurality of die package, each comprises: the lead frames with a plurality of lead-in wires around the center, each lead-in wire have first surface and divide into part from what first surface extended; A semiconductor dice that is positioned at center and electric connecting wire, first surface of the top formation of this semiconductor dice, the first surface that the first surface of this semiconductor dice and each lead-in wire upward form is coplane basically; With one be positioned at the center and cover semiconductor dice and the sealant (encapsulant) of a part of lead-in wire.The first surface of lead-in wire and the first surface of semiconductor dice expose the sealing agent, and the part of dividing into of the first surface of semiconductor dice and lead-in wire forms a cavity.A plurality of die package are stacked as at least a portion that makes sealant and are arranged in the cavity that piles up next higher die package.
In one embodiment, pile up in the lead-in wire of top die package divide into the lead-in wire that surpasses more following in a piling up die package.In another embodiment, pile up in the lead-in wire of die package isometric.
The lower surface of dividing into part of at least one die package can be welded on the encapsulation of adjacent dice in the encapsulation and divides on the upper surface of part in the encapsulation.In one embodiment, before stacked package, solder ball is sticked to dividing on the part of encapsulation.The encapsulation of piling up can adhere to each other before soldered.The side of sealant can be taper, and a plurality of lead-in wire can be positioned on two or more sides of center.
In another aspect of the present invention, a kind of method that is used to form the semiconductor unit chip module, comprise: form a plurality of independent semiconductor die package, comprise: provide to have a plurality of lead frames that center on the lead-in wire of center, each lead-in wire is included in the first surface that forms above, a semiconductor dice is set in the center, this semiconductor dice has the first surface that forms in the above, the first surface that the first surface of semiconductor dice and each lead-in wire upward form is coplane basically, semiconductor dice is electrically connected on lead-in wire, cover the part of semiconductor dice and the part of lead-in wire with sealant, with each lead-in wire is shaped is to comprise a first surface and the surface that divides into from the first surface extension, the first surface of lead-in wire and the first surface of semiconductor dice expose sealant, and the surface that divides into of the first surface of semiconductor dice and lead-in wire forms a cavity.This method further comprises piles up a plurality of independent semiconductor die package, thereby at least a portion of sealant is arranged in the cavity that piles up a following higher semiconductor die package; The lead-in wire of corresponding Stacket semiconductor die package with electrical interconnection.
The encapsulation of piling up can adhere to each other before soldered.This adhesion can be carried out with the glue of for example adhering, adhesive film or adhering liquid.The side of sealant can be taper, and a plurality of lead-in wire can be positioned on two or more sides of center.
In one embodiment, pile up in the lead-in wire of top semiconductor die package divide into the lead-in wire that surpasses more following in a piling up semiconductor die package.In another embodiment, pile up in the lead-in wire of die package isometric.
Electricity interconnecting line can comprise that the lower surface of dividing into part with at least one die package in the encapsulation is welded on the encapsulation of adjacent dice in the encapsulation and divides on the upper surface of part.Can before stacked package, solder ball be sticked to dividing on the part of encapsulation.Selectively, welding can be carried out by lead-in wire is immersed in the solder bath.The encapsulation that this method may further include in will piling up before dipping adheres to each other.
More particularly, the invention provides a kind of semiconductor unit chip module, comprise: a plurality of die package, each comprises: lead frame, it has a plurality of lead-in wires around the center, each lead-in wire has basal surface and divides into part from what basal surface extended, semiconductor dice, it is positioned at the center and is electrically connected on lead-in wire, this semiconductor dice has formation basal surface thereon, the basal surface of semiconductor dice and the basal surface coplane that on each lead-in wire, forms, and sealant, it is positioned at the center and covers semiconductor dice and part lead-in wire, and the basal surface of lead-in wire and the basal surface of semiconductor dice expose from sealant, and the part of dividing into of the basal surface of semiconductor dice and lead-in wire forms cavity; Wherein a plurality of die package are stacked at least a portion that makes sealant and are arranged in the cavity that piles up next higher semiconductor die package.
According to above-mentioned semiconductor unit chip module of the present invention, the lead-in wire of a more following die package was longer during the lead-in wire of top die package piled up than this during wherein this piled up.
According to above-mentioned semiconductor unit chip module of the present invention, the lead-in wire of each die package was isometric during wherein this piled up.
According to above-mentioned semiconductor unit chip module of the present invention, during wherein this piles up the lower surface of dividing into part of at least one die package be welded in this pile up in adjacent dice encapsulation divide into the upper surface of part.
According to above-mentioned semiconductor unit chip module of the present invention, wherein solder ball is adhered to the part of dividing into of this encapsulation.
According to above-mentioned semiconductor unit chip module of the present invention, the encapsulation during wherein this piles up adheres to each other.
According to above-mentioned semiconductor unit chip module of the present invention, wherein the side of sealant is taper.
According to above-mentioned semiconductor unit chip module of the present invention, wherein a plurality of lead-in wires are positioned on the both sides at least of center.
The present invention also provides a kind of method that is used to form the semiconductor unit chip module, this method comprises: form a plurality of independent semiconductor die package, it comprises: lead frame is provided, it has a plurality of lead-in wires around the center, each lead-in wire is included in the basal surface that forms above, semiconductor dice is arranged in the center, this semiconductor dice has the basal surface that forms in the above, the basal surface of this semiconductor dice and the basal surface coplane that on each lead-in wire, forms, semiconductor dice is electrically connected to lead-in wire, cover the part of semiconductor dice and the part of lead-in wire with sealant, and each lead-in wire that is shaped, to comprise basal surface and to divide into part from what basal surface extended, the basal surface and the semiconductor dice basal surface of lead-in wire expose from sealant, and the part of dividing into of semiconductor dice basal surface and lead-in wire forms a cavity; Thereby piling up a plurality of independent semiconductor die package makes at least a portion of sealant be arranged in the cavity that this piles up next higher semiconductor die package; And the respective lead of electrical interconnection institute Stacket semiconductor die package.
According to said method of the present invention, the lead-in wire of a more following die package was longer during the lead-in wire of top die package piled up than this during wherein this piled up.
According to said method of the present invention, the lead-in wire of each die package was isometric during wherein this piled up.
According to said method of the present invention, wherein electrical interconnection comprises: the upper surface of part was divided in the adjacent dice encapsulation during the lower surface of dividing into part of at least one die package was welded in and piles up in will piling up.
According to said method of the present invention, further comprise: before the Stacket semiconductor die package, solder ball is adhered to the part of dividing into of semiconductor die package.
According to said method of the present invention, further comprise: lead-in wire is immersed in the scolder bath.
According to said method of the present invention, further comprise: the semiconductor die package in will piling up before soldered adheres to each other.
According to said method of the present invention, wherein the side of sealant is taper.
According to said method of the present invention, wherein a plurality of lead-in wires are positioned on the both sides at least of center.
According to said method of the present invention, further comprise: the semiconductor die package in before electrical interconnection this being piled up adheres to each other.
Set forth one or more embodiments of the detail of the present invention below in conjunction with accompanying drawing and explanation.Other feature, target and advantage of the present invention will be apparent from specification, accompanying drawing and claim.
Description of drawings
When connection with figures is read the preferred embodiment detailed description, above-mentioned feature with other of the present invention will become apparent, wherein:
Figure 1A is the plane graph of supporting structure that comprises the semiconductor die package of lead frame and carrier (carrier);
Figure 1B is the side cutaway view of Figure 1A semiconductor die package supporting structure;
Fig. 2 A is the plane graph that has wherein adhered to Figure 1A supporting structure of semiconductor dice;
Fig. 2 B is the side cutaway view of Fig. 2 A semiconductor dice supporting structure;
Fig. 3 A is the plane graph of Fig. 2 A supporting structure of the molded operation of diagram;
Fig. 3 B is the side cutaway view of Fig. 3 A semiconductor die package;
Fig. 4 A is the plane graph that Fig. 3 A supporting structure of supporting structure carrier part is removed in diagram;
Fig. 4 B is the side cutaway view of Fig. 4 A semiconductor die package;
Fig. 5 A is that diagram forms the plane graph that lead frame refers to Fig. 4 A supporting structure of (finger);
Fig. 5 B is the side cutaway view of Fig. 5 A semiconductor die package;
Fig. 6 A and 6B illustrate the exemplary characteristics of an embodiment of semiconductor die package of the present invention;
Fig. 7 illustrates an example multiple semiconductor dice assembly that makes up according to one embodiment of the invention;
Fig. 8 illustrates an example multiple semiconductor dice assembly that makes up according to a further embodiment of the invention;
Fig. 9 illustrates an example multiple semiconductor dice assembly that makes up according to a further embodiment of the invention.
Similar identification element in the above-mentioned different accompanying drawing trends towards representing components identical, but does not mention whole accompanying drawings in specification.
Embodiment
Figure 1A and 1B illustrate and are positioned at carrier 20, for example strip or lamination, on a plurality of interconnecting line frames 10.In one embodiment, carrier 20 is strips that polyimides or other plastic material are made.According to an aspect of the present invention, each lead frame 10 is configured to 12 a plurality of lead-in wires 11 of arranging around the center.In the illustrated embodiment, each lead frame 10 comprises 5 lead-in wires 11 on each side that is arranged in center 12 4 sides.Yet should recognize that the number and the position of lead-in wire 11 can be according to concrete application corrects.For example, lead frame 10 can comprise two groups of lead-in wires that are positioned on 12 opposite sides of center.The lead frame 10 of interconnection can be formed with the thin slice of any suitable conductor, and preferably copper or acid bronze alloy.Acid bronze alloy is meant and contains the material that percentage by weight surpasses 50% copper.
Shown in Fig. 2 A and 2B, a plurality of semiconductor dice 30 are positioned at the center 12 of lead frame 10.Each dice 30 comprises a upper surface 32 and a lower surface 34.The lower surface 34 of carrier 20 supporter sheets 30.Should recognize that each of a plurality of semiconductor dice 30 all is positioned at center 12, thus lower surface 14 coplanes of lower surface of each dice 30 34 and lead frame 10.
Wiring 40 upper surfaces 32 from each dice 30 are bonded on the corresponding lead-in wire 11, thereby make dice 30 electricity be coupled lead frame 10.For example, the execution of thread bonded can utilize supersonic bonding, and wherein combination is exerted pressure and sonic oscillation pulse train (ultrasonicvibration burst) forms metallurgical cold weld and connects; Utilize the hot compression bonding, wherein the combination exert pressure and high temperature form welding; Perhaps utilize heat sound bonding (thermosonic bonding), wherein combination is exerted pressure, high temperature and supersonic oscillations pulse train form welding.The wire type of using in the bonding preferably is made of gold, gold-base alloy, aluminium or acieral.As substituting of thread bonded, can use band automated bonding (tape automated bonding) (TAB).
Shown in Fig. 3 A and 3B, by for example filling corresponding center 12 molded independently sealant (mold compound) 50 on each of dice 30, silk thread 40 and thread bonded site, thereby sealant 50 surrounds each dice 30 basically.Sealant 50 can apply with any traditional technology, for example shifts (transfer) or injection-molded and handles.Sealant 50 can also be a low temperature thermal glass composite.In one embodiment, the side of sealant 50 is tapers.
In case sealant 50 is applied to lead frame 10, just can remove carrier 20.Fig. 4 A and 4B illustrate this and remove operation.When finishing, each dice 30 is suspended in the center 12 of lead frame 10 by sealant 50.The upper surface 32 of each dice 30 and the part of each lead-in wire 11 are all encapsulated, the lower surface 34 of each dice 30 and the then exposure of lower surface 14 of each lead-in wire.
Remove carrier 20, thereby the interconnecting parts of lead frame 10 is cut and makes each semiconductor die package be cut list.Carry out encapsulation cut single can be by the dice punching press, cut saw, water spray, laser etc. with blade.Fig. 5 A and 5B illustrate and cut single semiconductor die package, generally show as 100.Shown in Fig. 5 A and 5B, lead-in wire 11 is configured as " class S shape " thereby comprises divides into part (down set portion) 101.For example, lead-in wire can be built into " class S shape " by bending or other form after cutting list.Lead-in wire 11 extends downwards from the surface that the lower surface 34 by dice 30 forms, thereby a cavity is provided below dice 30, generally shows as 102.In case cut list, can and wear out (burned-in) thereby encapsulation 100 assurance KGD reliabilities according to the industry standard processes test.Preferably, encapsulation 100 was tested before being stacked into the dice assembly as described below.Encapsulation 100 can be electrically connected an external circuit, for example printed circuit board (PCB) or another semiconductor packages on any exposed surface of contact 11.
Fig. 6 A and 6B illustrate an embodiment of the semiconductor die package 100 that makes up according to one embodiment of present invention.Three exemplary dimensions are marked as " A ", " B " and " C ", and illustration encapsulate 100 thickness.As shown in the figure, encapsulation 100 novel configuration be convenient to form have a thin profile pile up the multiple semiconductor die package.
For example, Fig. 7 illustrates five (5) semiconductor unit chip modules 200, has wherein assembled the die package 210,220,230,240 and 250 of layering respectively.Should recognize that each die package 210,220,230,240 is all identical with die package 100 with 250, be the size A difference of respective lead 11, thereby provide even lower level other encapsulation.As shown in Figure 7, encapsulate at 200 o'clock at the module units sheet, the encapsulated part of next unit sheet encapsulation is arranged in the cavity 102 that is formed by assembly 200 next higher stacked die package.For example, die package 210 is assembled into the cavity 102 that its dice of sealing 30 and wiring 40 (being instructed in 214 jointly) are positioned at die package 220, die package 220 is assembled into the cavity 102 that its dice of sealing and wiring 224 are positioned at die package 230, die package 230 is assembled into the cavity 102 that its dice of sealing and wiring 234 are positioned at die package 240, and die package 240 is assembled into its dice of sealing and connects up 244 cavitys 102 that are positioned at die package 250.After stacked die package 210,220,230,240 and 250, be electrically connected corresponding lead-in wire 11 by welding or similar method.The execution of welding can be used, and for example adheres to lead-in wire 11 solder ball, perhaps 11 is immersed in the scolder bath (solder bath) by going between.
Should recognize that A, B and the measurement of C or B and the C size of correlation unit sheet encapsulation 210-250 of the relative thickness of assembly 200 by continuous series calculated, and be as follows:
Ground floor-die package 210, thickness=A+B+C; Add
The second layer-die package 220, thickness=B+C (because size A is counted by following layer); Add
The 3rd layer-die package 230, thickness=B+C; Add
The 4th layer-die package 240, thickness=B+C; Add
Layer 5-die package 250, thickness=B+C.
Therefore, with respect to dice assembly 200, shown in the stacked die package of assembling, its profile is thinner than the stacked die package that each die package wherein is assembled in above the following primary unit sheet encapsulation simply.
Fig. 8 illustrates five (5) semiconductor unit chip modules 300, and it is assembled according to another embodiment of the invention, has the die package 310,320,330,340 and 350 of layering respectively.Die package 310,320,330,340 is identical with the die package of Fig. 5 A and 5B with 350.As shown in Figure 8, die package 310,320,330,340 has similar size with 350 lead-in wire 11, and for example the size A of each lead-in wire 11 (height of lead-in wire 11) is identical.In the embodiment of Fig. 8, and among any other the embodiment of this paper explanation, die package 310,320,330,340 can be bonded together according to layer mode before being connected lead-in wire 11 with 350, utilize adhesive, for example cyanoacrylate adhesive or analog perhaps do not have tenaculum adhesive (unsupported tape adhesive).Adhesive can be in the form of adhesive paste, binder film or adhesive liquid.
In the present embodiment, thereby adhesion die package 310,320,330,340 of bonding and 350 encapsulation 310,320,330,340 and 350 by the bonding of will adhere are immersed in and make lead-in wire 11 by the welding compound that keeps between them the in addition electrical interconnection that is bonded together, as 314 generally demonstrations in the high-temperature solder bath.As shown in Figure 8, welding compound 314 cavity 102 of closed cell sheet encapsulation 310,320,330,340 and 350 effectively.Should recognize that the relative thickness of dice assembly 300 can being calculated as explanation in the dice assembly 200.
Fig. 9 illustrates five (5) semiconductor unit chip modules 400, and it is assembled according to another embodiment of the invention, has the die package 410,420,430,440 and 450 of layering respectively.Identical with the assembly 300 of Fig. 8, die package 410,420,430,440 and 450 lead-in wire 11 have similar height, and for example size A, and die package 410,420,430,440 is identical with the die package of Fig. 5 A and 5B with 450.In the present embodiment, the die package 410,420,430,440 of layering and 450 is by the high-temperature solder ball between the lead-in wire 11 of melting unit sheet encapsulation 410,420,430,440 and 450 414 electrical interconnection in addition.After cutting single encapsulation, preferably before stacked package, solder ball 414 can adhere to dividing on the part 101 of each package lead 11.After stacked package, solder ball 414 can be melted and cool off with in conjunction with adjacent lead-in wire 11.As shown in Figure 9, solder ball 414 has sealed the cavity 102 of each die package 420,430,440 and 450 effectively.Should recognize that the relative thickness of dice assembly 400 can being calculated as explanation in the dice assembly 200.
Described with it is to be further appreciated that Figure 1A-5B example, each stage of assembling Stacket semiconductor encapsulation shown in Fig. 7,8 and 9.
In each embodiment described herein, thereby allowing to pile up a plurality of encapsulation, the configuration of lead-in wire 11 provides higher chip density, keep thin assembly profile simultaneously.Thereby compare with the conventional method that adopts stacked die to reduce in common molded package to pile up profile to increase chip density, the complexity that stacked package of the present invention has reduced assembled package provides simultaneously similarly piles up profile and chip density.The reduction of complexity has been at least in part owing to eliminated the separator/insert between the dice in the mutual encapsulation, and they are to use in the technical configuration formerly.Further, encapsulation of the present invention provides from ability upper and lower or that test in the side.Be packaged with defective if find any one, then abandon this independent encapsulation and chip thereof, thereby reduced the waste relevant with prior art, the prior art encapsulation need be removed a plurality of chips in the mutual encapsulation.The invention provides the encapsulation of littler profile, it can use separately or can be stacked use when needs increase chip density.
Although the present invention of explanation of contact preferred embodiment and illustration, those skilled in the art can carry out many changes and modification apparently, does not deviate from the spirit and scope of the present invention.For example and as mentioned above, technology of the present invention does not trend towards being limited to the stacked die package arrangement of any concrete number, 5 die package arrangement that for example describe in detail above.That is to say, should recognize that aspect of the present invention can be applied in other semiconductor arrangement that need thinner profile of equal valuely.
Therefore, the present invention who is proposed by accessory claim is not limited in the fine detail of above-mentioned explanation, and conspicuous for those skilled in the art change and modification trend towards being included in by in the spirit of the appended claims of the invention and the scope.
Claims (18)
1. a semiconductor unit chip module (200,300,400) comprising:
A plurality of die package (100), each comprises:
Lead frame (10), it has a plurality of lead-in wires (11) around center (12), and each lead-in wire (11) has basal surface (14) and divides into part (101) from what basal surface (14) extended,
Semiconductor dice (30), it is positioned at center (12) and is electrically connected on lead-in wire (11), this semiconductor dice (30) has formation basal surface (34) thereon, the basal surface (34) of semiconductor dice (30) and basal surface (14) coplane that upward forms at each lead-in wire (11), and
Sealant (50), it is positioned at center (12) and covers semiconductor dice (30) and part lead-in wire (11), the basal surface (14) of lead-in wire (11) and the basal surface (34) of semiconductor dice (30) expose from sealant (50), and the part (101) of dividing into of the basal surface (34) of semiconductor dice (30) and lead-in wire (11) forms cavity (102);
Wherein a plurality of die package (100) are stacked at least a portion that makes sealant (50) and are arranged in the cavity (102) that piles up next higher semiconductor die package (100).
2. according to the semiconductor unit chip module (200) of claim 1, the lead-in wire (11) of a more following die package (100) was longer during the lead-in wire (11) of top die package (100) piled up than this during wherein this piled up.
3. according to the semiconductor unit chip module (300,400) of claim 1, the lead-in wire (11) of each die package (100) was isometric during wherein this piled up.
4. according to the semiconductor unit chip module (300,400) of claim 1, during wherein this piles up the lower surface of dividing into part (101) of at least one die package (100) be welded in this pile up in adjacent dice encapsulation (100) divide into the upper surface of part.
5. according to the semiconductor unit chip module (400) of claim 4, wherein solder ball (414) is adhered to divide into partly (101) of this encapsulation (100).
6. according to the semiconductor unit chip module (300,400) of claim 4, the encapsulation (100) during wherein this piles up adheres to each other.
7. according to the semiconductor unit chip module (200,300,400) of claim 1, wherein the side of sealant (50) is taper.
8. according to the semiconductor unit chip module (200,300,400) of claim 1, wherein a plurality of lead-in wires (11) are positioned on the both sides at least of center (12).
9. method that is used to form semiconductor unit chip module (200,300,400), this method comprises:
Form a plurality of independent semiconductor die package (100), it comprises:
Lead frame (10) is provided, and it has a plurality of lead-in wires (11) around center (12), and each lead-in wire (11) is included in the basal surface (14) that forms above,
Semiconductor dice (30) is arranged in the center (12), and this semiconductor dice (30) has the basal surface (34) that forms in the above, basal surface (34) of this semiconductor dice (30) and basal surface (14) coplane that upward forms at each lead-in wire (11),
Semiconductor dice (30) is electrically connected to lead-in wire (11),
Cover the part of semiconductor dice (30) and the part of lead-in wire (11) with sealant (50), and
Each lead-in wire (11) is shaped, to comprise basal surface (14) and to divide into part (101) from what basal surface (14) extended, the basal surface (14) and semiconductor dice (30) basal surface (14) of lead-in wire expose from sealant (50), and the part (101) of dividing into of semiconductor dice (30) basal surface (34) and lead-in wire (11) forms a cavity (102);
Pile up a plurality of independent semiconductor die package (100) thus make at least a portion of sealant (50) be arranged in the cavity (102) that this piles up the higher semiconductor die package of the next one (100); And
The respective lead (11) of electrical interconnection institute Stacket semiconductor die package (100).
10. according to the method for claim 9, the lead-in wire (11) of a more following die package (100) was longer during the lead-in wire (11) of top die package (100) piled up than this during wherein this piled up.
11. according to the method for claim 9, the lead-in wire (11) of each die package (100) was isometric during wherein this piled up.
12. according to the method for claim 9, wherein electrical interconnection comprises:
The upper surface of part was divided in adjacent dice encapsulation (100) during the lower surface of dividing into part (101) of at least one die package (100) was welded in and piles up in will piling up.
13. the method according to claim 12 further comprises:
In Stacket semiconductor die package (100) before, solder ball (414) is adhered to divide into partly (101) of semiconductor die package (100).
14. the method according to claim 12 further comprises:
To go between (11) be immersed in the scolder bath.
15. the method according to claim 14 further comprises:
Semiconductor die package (100) in will piling up before soldered adheres to each other.
16. according to the method for claim 9, wherein the side of sealant (50) is taper.
17. according to the method for claim 9, wherein a plurality of lead-in wires (11) are positioned on the both sides at least of center (12).
18. the method according to claim 9 further comprises:
Semiconductor die package in before electrical interconnection this being piled up adheres to each other.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US44498703P | 2003-02-04 | 2003-02-04 | |
| US60/444,987 | 2003-02-04 | ||
| US60/445,677 | 2003-02-06 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1748304A CN1748304A (en) | 2006-03-15 |
| CN100380639C true CN100380639C (en) | 2008-04-09 |
Family
ID=36167010
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004800034731A Expired - Fee Related CN100380639C (en) | 2003-02-04 | 2004-02-03 | Thin multiple semiconductor die package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100380639C (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4982265A (en) * | 1987-06-24 | 1991-01-01 | Hitachi, Ltd. | Semiconductor integrated circuit device and method of manufacturing the same |
| US5138438A (en) * | 1987-06-24 | 1992-08-11 | Akita Electronics Co. Ltd. | Lead connections means for stacked tab packaged IC chips |
| CN2499978Y (en) * | 2001-10-26 | 2002-07-10 | 财团法人工业技术研究院 | Three dimension stacking package radiator module |
| US6452278B1 (en) * | 2000-06-30 | 2002-09-17 | Amkor Technology, Inc. | Low profile package for plural semiconductor dies |
-
2004
- 2004-02-03 CN CNB2004800034731A patent/CN100380639C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4982265A (en) * | 1987-06-24 | 1991-01-01 | Hitachi, Ltd. | Semiconductor integrated circuit device and method of manufacturing the same |
| US5138438A (en) * | 1987-06-24 | 1992-08-11 | Akita Electronics Co. Ltd. | Lead connections means for stacked tab packaged IC chips |
| US6452278B1 (en) * | 2000-06-30 | 2002-09-17 | Amkor Technology, Inc. | Low profile package for plural semiconductor dies |
| CN2499978Y (en) * | 2001-10-26 | 2002-07-10 | 财团法人工业技术研究院 | Three dimension stacking package radiator module |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1748304A (en) | 2006-03-15 |
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