CN100370759C - Thermo-back-up system and method - Google Patents
Thermo-back-up system and method Download PDFInfo
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- CN100370759C CN100370759C CNB2005101024184A CN200510102418A CN100370759C CN 100370759 C CN100370759 C CN 100370759C CN B2005101024184 A CNB2005101024184 A CN B2005101024184A CN 200510102418 A CN200510102418 A CN 200510102418A CN 100370759 C CN100370759 C CN 100370759C
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Abstract
The present invention discloses a warm backup system. A main plate and a standby plate respectively comprise a CPU, a memory, a memory controller and a transmission interface, wherein the CPU on the main plate executes read-write operation to the memory of the main plate through the memory controller of the main plate; the memory controller on the main plate records address space divided in advance and requiring backup in the memory; the CPU of the main plate is used for writing data into the memory address space requiring backup through the memory controller; the data is transmitted to a memory controller on a backup plate through the transmission interface on the main plate and the transmission interface on the standby plate; the memory controller of the standby plate receives the data and writes the data into the address space of the memory of the standby plate, which is identical to the address space of the data in the main plate; the transmission interfaces on the main plate and the standby plate are connected; the data is transmitted between the main plate and the standby plate. The present invention also discloses a warm backup method. The present invention reduces the occupation rates of the CPUs of the main and the standby plates and increases the backup efficiency.
Description
Technical field
The present invention relates to the data backup technical field, be meant a kind of hot backup system and method especially.
Background technology
Telecommunication apparatus need provide very high reliability, so adopted the mode of active and standby two-node cluster hot backup to improve the reliability of key component in many telecommunication apparatus.Active and standby two-node cluster hot backup is meant that the main board in the equipment moves identical key component simultaneously with standby plate, and after main board lost efficacy, standby plate was taken over the control of key component, and the assurance business is not interrupted.
In the prior art, by each is provided with the backup software that is exclusively used in backup on main board and standby plate, between the backup software of main board and standby plate, arrive the transmission of standby plate usually by the mutual realization main board data of application layer.Be specially: when certain task in the application program on the main board determines that certain data of its correspondence need back up, the backup software of application module on main board sends the backup indication, after backup software receives this backup indication, read data corresponding in this board memory according to the information in this indication by central processing unit (CPU), and send the data that read on the standby plate backup software by data/address bus with predefined transmission rate, after backup software on the standby plate receives above-mentioned data, data are stored in the corresponding standby plate memory address space by the CPU on the standby plate.
Because usually main board has only part to revise in the data of standby plate transmission, all the other and the former data consistent of having stored in the standby plate internal memory so can not will whole data are all write in the standby plate internal memory, get final product and only the part of changing need be write.Therefore a kind of method is provided in the prior art: the backup software on the standby plate is adjusted back the processing function at these data of main board after the data that receive the main board transmission, and according to this processing function the data in the standby plate internal memory is made amendment.Finish in transfer of data, and after the success of readjustment processing function, just finished modification, guaranteed the data consistency between the active and standby two-shipper the standby plate data in EMS memory.
Comprise a lot of tasks in the application module, and the corresponding a lot of data item of each task, in system's running, owing to undertaken alternately by application layer messages between the main standby plate in the Backup Data transmission course, the CPU usage height has reduced Hot Spare efficient; And because in the process that guarantees data consistency, readjustment is handled function and is very easy to make mistakes, and the call back function failure will influence the consistency of transfer of data, so cause the inconsistent of active and standby two-shipper data through regular meeting; In addition, owing to adopt data/address bus to carry out the transmission of Backup Data between the backup two-shipper, because data bus bandwidth is fixed, the Hot Spare data can not be transmitted in different ways according to quality scale; And because data bus bandwidth is fixed, cause a kind of Hot Spare mechanism can only be adapted to a kind of hardware configuration, after the message transmission rate in changing Hot Spare mechanism again, just need the change hardware configuration so that the data bus bandwidth after the change can satisfy the requirement of the transmission rate after the change, caused the Hot Spare mechanism can't shelfization.
Summary of the invention
In view of this, first main purpose of the present invention is to provide a kind of hot backup system, can reduce the CPU usage in the Hot Spare process.
Second main purpose of the present invention is to provide a kind of heat backup method, and this method can reduce the CPU usage in the Hot Spare process.
First aspect in order to achieve the above object the invention provides a kind of hot backup system, and this system comprises: comprise CPU, internal memory, Memory Controller Hub and coffret on main board and the standby plate respectively;
Wherein, the CPU on the main board carries out read-write operation by the Memory Controller Hub of this plate to the internal memory of this plate;
The address space of the needs backup of dividing in advance in the Memory Controller Hub record internal memory on the main board, and the data that write of the address space that main board CPU is needed to back up in the main board internal memory by the Memory Controller Hub on this main board, send to Memory Controller Hub on the standby plate through the coffret on the main board and the coffret on the standby plate;
The Memory Controller Hub of standby plate receives described data, and described data are write in the standby plate internal memory and described data identical address space in the main board internal memory;
Coffret on the primary, spare plate connects, and transmits data between main board and standby plate.
The Memory Controller Hub that described Memory Controller Hub can carry for CPU, coffret can be Ethernet interface, the Ethernet interface on the primary, spare plate connects by Ethernet.
Described Memory Controller Hub can also be the Memory Controller Hub in the FPGA module, described coffret can be the high-speed interface controller in the FPGA module, high-speed interface controller on the primary, spare plate connects by a plurality of high speed cables that use that maybe can walk abreast, or connects by a plurality of high speed optical cables that use that maybe can walk abreast.
Described standby plate can be for one or more; When described standby plate is a plurality of, Memory Controller Hub on the main board writes by this Memory Controller Hub main board CPU in the address space that the main board internal memory need back up data send to Memory Controller Hub each standby plate in the mode of broadcasting through the coffret on each standby plate by the coffret on the main board.
Preferably, CPU on the standby plate carries out read-write operation by the Memory Controller Hub of standby plate to the address space that does not need in the standby plate internal memory to back up, CPU on the standby plate only carries out read operation by the Memory Controller Hub of standby plate to the address space that needs in the standby plate internal memory to back up, thereby standby plate can utilize the memory headroom that does not need in the self EMS memory to back up to move and the irrelevant task of main board.
Second aspect in order to achieve the above object, the invention provides a kind of heat backup method, this method comprises: press the address space in the backup level division main board internal memory in advance, and on main board, need the backup level corresponding address space of backing up in the minute book board memory, this method also comprises:
Memory Controller Hub in A, the main board sends to the data in the address space of needs backup in this board memory according to the backup level corresponding address space of needs backup in this board memory that writes down on the main board Memory Controller Hub of standby plate;
After the Memory Controller Hub of B, standby plate receives described data, described data are write in this board memory and described data identical address space in the main board internal memory.
Described backup level can comprise: the needs backup is not backed up with not needing; Memory Controller Hub in the then described main board with the Memory Controller Hub that the data in the address space that needs in this board memory to back up send to standby plate is:
Memory Controller Hub in the main board sends to described data the Memory Controller Hub of standby plate when needing backup level corresponding address space to write data in this board memory;
And/or: the Memory Controller Hub in the main board regularly reads the data in the backup level corresponding address space that needs in this board memory to back up with the predefined cycle, and the described data that read is sent to the Memory Controller Hub of standby plate.
Described backup level can also comprise: important, generally and not need backup, the described backup level of backup that needs comprises important and general;
Memory Controller Hub in the described main board comprises the Memory Controller Hub that the data in the address space that needs in this board memory to back up send to standby plate:
Memory Controller Hub in A1, the main board sends to described data the Memory Controller Hub of standby plate when general backup level corresponding address space writes data in this board memory;
With,
Memory Controller Hub in A2, the main board regularly reads the data in the important backup level corresponding address space in this board memory with the predefined cycle, and the described data that read is sent to the Memory Controller Hub of standby plate.
Preferably, in the described steps A 2, the Memory Controller Hub that sends the data to standby plate further comprises before:
Whether judge has the consistent point identification of transmission, if having then wipe the consistent point identification of described transmission, carry out the described step that sends the data to the Memory Controller Hub of standby plate then in the standby plate; If do not have then the described step that sends the data to the Memory Controller Hub of standby plate of direct execution;
Further comprise after the described step B:
B1, main board write the consistent point identification of transmission to standby plate, indicating this time transmission success, and active and standbyly are in consistent state with the data in the important backup level corresponding address space in the board memory;
C, standby plate are after detecting main board and breaking down, and whether check has the consistent point identification of transmission, if having, then directly self is converted to main board in self.
Preferably, further comprise behind the described step B1: standby plate regularly is written to the data in this board memory in corresponding this plate file system;
Then among the step C, further comprise after whether the consistent point identification of transmission is arranged in the described inspection self: do not transmit consistent point identification in self if be checked through, then recover internal memory to the data in this plate file system of correspondence according to said write.
Preferably, the Memory Controller Hub that the described data that regularly read with the predefined cycle are sent in the standby plate is: the data that will regularly read with the predefined cycle send to Memory Controller Hub in the standby plate with the bandwidth that sets in advance;
The described bandwidth that sets in advance was provided with according to the described predefined cycle.
Preferably, this method further comprises: main board writes down in advance and relates to the operating system task of revising data in the backup level corresponding address space that needs to back up in the internal memory;
Memory Controller Hub in the then described main board with predefined cycle timing reading of data is:
Main board is regularly monitored operating system task movable in the operating system task of described record with the predefined cycle, after these movable operating system task finish, read described data by the Memory Controller Hub in the main board.
Preferably, this method further comprises: in advance by the file in the backup level division main board file system identical with internal memory;
Further comprise before the then described steps A and after the step B:
A01, system's primary, spare plate in service be with File mapping in internal memory the time, according to backup level will be separately File mapping to having in other address space of identical copy level with described file in the internal memory separately.
Further, can comprise before the described steps A 01: the initial data file backup procedure, be specially: after A00, main board and standby plate self check start, register address space in the internal memory separately and the file in the file system by backup level respectively, and main board directly copies the data in the backup level corresponding address space that needs in the self EMS memory to back up to address space identical in the standby plate internal memory.
Preferably, in this method, the modification situation of data in the minute book board memory address space on main board in advance;
Then the Memory Controller Hub in the main board described in the steps A with the Memory Controller Hub that the data in the address space that needs in this board memory to back up send to standby plate is:
Memory Controller Hub in the main board is according to the modification situation of the internal storage data in this board memory address space that writes down on the main board, read the data that have been modified in the backup level corresponding address space that needs in this board memory to back up, and the described data that have been modified are sent to the Memory Controller Hub of standby plate.
Preferably, need the method in the backup level corresponding address space of backing up to be in the described record internal memory:
Different backup level corresponding address space in the record internal memory on main board, and the registration RAM that writes down the address space backup instances in the internal memory is set on main board, whether the sector address space among this RAM in the corresponding main board internal memories of the different values of each needs backup;
The method of the data modification situation in the described minute book board memory address space is: the modification RAM of the data modification situation in the record memory address space is set on main board, and whether the sector address space among this RAM in corresponding this board memory of the different values of each is modified;
Then described modification situation according to the internal storage data in this board memory address space that writes down on the main board, reading the data that have been modified in the backup level corresponding address space that needs in this board memory to back up is: according to registration RAM and the value of revising the corresponding position of RAM determine the address space at data place from needs to being modified of writing of standby plate, read the data in the determined address space.
From above scheme as can be seen, in the hot backup system of the present invention, by Memory Controller Hub and coffret are set; CPU on the main board carries out read-write operation by the Memory Controller Hub of this plate to the internal memory of this plate; The address space of the needs backup of dividing in advance in the Memory Controller Hub record internal memory on the main board, and with main board CPU by its data that in the memory address space of needs backups, write, send to Memory Controller Hub on the standby plate by coffret on the main board and the coffret on the standby plate; The Memory Controller Hub of standby plate receives described data, and with described data write in the standby plate internal memory with described data in the main board internal memory in the identical address space; Coffret on the primary, spare plate connects, between main board and standby plate, transmit data, thereby when carrying out the transmission of Hot Spare data by this system, do not need upper layer software (applications) to participate in, just do not need the participation of CPU yet, thereby greatly reduce the occupancy of main board CPU, improved backup efficient.
In addition, comprise that by employing the FPGA module of Memory Controller Hub and high-speed interface controller realizes above-mentioned Memory Controller Hub and coffret in the hot backup system of the present invention, and the high speed optical cable or the high speed cable that use by walking abreast between the high-speed interface controller of primary, spare plate connect, thereby can be according to the demand of backup quality, transmission bandwidth is set, make a kind of hot backup system can adapt to the multiple hardwares environment, realized the shelfization of hot backup system.
In the heat backup method of the present invention, press the address space in the backup level division main board internal memory in advance, and on main board, need the address space that backs up in the minute book board memory, the Memory Controller Hub of main board by wherein directly reads the Memory Controller Hub that data in the address space that needs in the internal memory to back up are sent to standby plate, by the Memory Controller Hub of standby plate with these data write with these data in the main board internal memory in the identical address space, thereby need not upper layer software (applications) in backup procedure participates in, also need not main, CPU on the standby plate participates in, and has reduced in the Hot Spare process main, the occupancy of standby plate CPU.
And, in heat backup method of the present invention, by a plurality of backup levels that need backup are set, and realize Hot Spare, thereby realized the hierarchical transmission of Hot Spare data for the different backup method of The data in the backup level corresponding memory address space of different needs backups.
In addition, in the heat backup method of the present invention, carry out record, in backup procedure, only the data that have been modified are backed up, further improved backup efficient by in main board, whether the data in the memory address space being modified.
Description of drawings
Fig. 1 is the system construction drawing of the specific embodiment of the invention;
Fig. 2 is the Hot Spare flow chart of the specific embodiment of the invention;
Fig. 3 is the software architecture figure of the specific embodiment of the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.
Main thought of the present invention is to press the address space in the backup level division main board internal memory in advance, and in main board and standby plate Memory Controller Hub is set, the address space of the needs backup of dividing in advance in the record internal memory in main board; In that system is in service when backing up, the Memory Controller Hub of main board reads the data in the backup level corresponding address space that needs in this board memory to back up, and described data is sent to the Memory Controller Hub of standby plate; After the Memory Controller Hub of standby plate receives described data, described data are write in this board memory and described data identical address space in the main board internal memory, finish Hot Spare.
Above-mentioned backup level can include only to be needed backup and not to need to back up two backup levels, can also comprise important, generally and not need to back up three backup levels, even more backup level, wherein important and general all is the backup level that need back up.Press the address space in the backup level division main board internal memory, can adopt the method for static division, promptly the address space in the internal memory is divided just no longer change of back; Also can adopt the method for dynamic division, promptly can be according to the address space in the corresponding internal memory of the different needs adjustment of each backup level.
Transmit data by the coffret on each plate between the Memory Controller Hub on the above-mentioned primary, spare plate.Memory Controller Hub on every plate and coffret can realize that Memory Controller Hub and Ethernet interface as CPU carries also can comprise that the FPGA module of Memory Controller Hub and high-speed interface controller realizes by increasing by existing unit in system.For the former, the address space of the needs backup of in Memory Controller Hub, dividing in advance in the record internal memory, the coffret between the main standby plate connects by Ethernet; For the latter, the address space of the needs backup of in the FPGA module, dividing in advance in the record internal memory, and the coffret between the main standby plate connects by high speed optical cable or high speed cable.
The initiation of Hot Spare can be real-time triggering, also can be regularly to trigger, in Hot Spare timing triggering mode, for fear of in the process of reading of data, CPU makes amendment to these data, can also need the operating system task of the address space that backs up to monitor in the internal memory to relating to revising by software, after these task terminations, reading of data.
In addition, can also in main board, whether carry out modification among the present invention and carry out record the data in the main board memory address space, after Hot Spare was initiated, the data that have been modified in the memory address space that the Memory Controller Hub of main board only will need to back up sent to standby plate and back up.
Standby plate among the present invention can be one, also can be a plurality of, if standby plate is greater than one, then the backup module of main board sends to the Memory Controller Hub of each standby plate in the mode of broadcasting with the data in the address space that needs in the internal memory to back up, and by the Memory Controller Hub of each standby plate with storage in the standby plate internal memory with described data identical address space in the main board internal memory.
Below the present invention is described in detail by specific embodiment.
In the present embodiment, when memory address space being divided by backup level, adopted the dividing mode of three backup levels, soon memory address space will be divided into does not need backup, general and important, and, for two backup levels of needs backups, the address space in promptly general and important the corresponding internal memory has adopted different backup modes, is described below.
In advance the address space in the internal memory is divided by backup level in the present embodiment, comprised three class address spaces after the division: the I class, do not need the memory address space that backs up, as this board status etc., backup level is for needing backup; The II class, the memory address space that need back up, as call distribution record etc., backup level is general; The III class, important internal storage data and the core image that needs to guarantee the internal consistency file, as resource allocation situation, device hardware state etc., backup level is important.
Correspondingly,, also divide in the present embodiment, comprise three class files after the division by backup level for file system: category-A, the file that does not need to carry out active and standby exchange, as the running log of this plate etc., backup level is not for needing backup; Category-B need carry out active and standby exchange, but but non-critical file or the seldom very big file of operation do not need to guarantee the consistency of main standby plate data, as User operation log or board software bag etc., backup level is general; The C class, the critical file that need carry out active and standby exchange need to guarantee the consistency of main standby plate data, as the data configuration file etc., backup level is important.
After internal memory and file system carried out above-mentioned division, system was when carrying out File mapping, and in every plate, the category-A File mapping is in I class address space, and the category-B File mapping is in II class address space, and the C class file is mapped in the III class address space.
In specific embodiments of the invention, (Field ProgrammableGate Array, FPGA) module comprises Memory Controller Hub and high-speed interface controller as backup module in the FPGA module to adopt field programmable gate array.Wherein, all open and standardization, no longer explanation here of Memory Controller Hub that is adopted in the FPGA module and high-speed interface controller; The high-speed interface controller that is adopted in the FPGA module can carry out automatically and go here and there, go here and there and change, when transmitting, according to the difference of transmission circuit property, can adopt a plurality of high speed cable or high speed optical cables that use that can walk abreast to connect between the high-speed interface controller of main board and standby plate.The use because high speed optical cable or high speed cable can walk abreast, so can be according to the quality requirement of backup, promptly according to the minimum interval of needs data sync time between active and standby, it is the timing cycle of following timed backup, register by in the configuration FPGA module is arranged on the high speed optical cable of parallel use in the backup procedure or the quantity of cable.For example, in the FPGA module, be provided with the high speed optical cable of 8 2.5Gbps, then the backup quality rank that can provide for from 2.5Gbps, 5.0Gbps up to eight ranks of 20Gbps.
In the present embodiment, the FPGA module on every plate is carried out record to the dividing condition of address space in the internal memory, promptly writes down I class, II class and III class address in the internal memory respectively.
And, also the RAM by wherein is to the backup instances in this board memory for FPGA module on the main board, and promptly which address space needs backup in this board memory, and which address space does not need backup to carry out record, for convenience of description, claim this to be recorded as registration RAM in the present invention.Owing to whether need backup to carry out record to each address in the memory address, need expend RAM with the identical size of internal memory, and because the internal memory bit wide is 8nbit, it is m that the internal memory numbers of particles of independent addressing system is arranged, when backing up, the least unit of backup is 1024 * n * m byte, whether each address needs backup in the internal memory so also there is no need to write down, whether only need the sector address space in the record internal memory to need backup to get final product, above-mentioned least unit can be selected in this sector address space.Therefore, in registration RAM, can be to the address space of internal memory with 1024 * n * laggard line item of m byte delivery, promptly register the address space of the 1024 * n * m byte in (bit) corresponding internal memory among the RAM, the value of for example registering a certain position among the RAM is 1, has just represented the 1024 * n * m byte address space requirement backup of this correspondence; If value is 0, then represent the address space of the 1024 * n * m byte of this correspondence not need backup.internally deposit into gone as present embodiment in after the aforesaid division, here among the said registration RAM, place value corresponding to the registration RAM of II class in the internal memory and III class address space is 1, identifying these address spaces need back up, and be 0 corresponding to the place value of the registration RAM of I class address space, identifying these address spaces does not need backup.
In addition, the FPGA module is also carried out record by RAM to the modification situation of internal memory, for convenience of description, the RAM that claims this record internal memory to revise situation in the present invention is modification RAM, identical with the method for record Memory Backup situation, whether corresponding 1024 * n * m byte address space is modified in one the value representation internal memory to revise among the RAM in the present embodiment, the value of for example revising among the RAM certain is 1 o'clock, represent the address space of the 1024 * n * m byte of this correspondence to be modified, be 0 o'clock, represent the address space of the 1024 * n * m byte of this correspondence not to be modified.
In addition, in the hot backup system of present embodiment, the hardware cell on main board and the standby plate also comprises CPU element, internal storage location respectively except that the FPGA module, and as shown in Figure 1, wherein veneer 1 is a main board, and veneer 2 is a standby plate.In each veneer shown in Figure 1, CPU reads data in this board memory by the Memory Controller Hub in the FPGA module.And when writing data in internal memory, main board CPU is by the Memory Controller Hub handwritten copy board memory in the main board FPGA module; After Memory Controller Hub among the main board FPGA sends to standby plate FPGA module with Backup Data by high speed optical cable between primary, spare plate or high speed cable, the Memory Controller Hub of standby plate FPGA module by wherein with Backup Data be written on the standby plate with main board in the internal memory in the identical address space in Backup Data address.Standby plate CPU does not need the address space that backs up, i.e. I class address space in can only the handwritten copy board memory.In addition, for file system too, standby plate needs the file that backs up in can not the handwritten copy plate.Be that II class, III class address space and category-B, C class file system in the standby onboard memory only allows standby plate to write when backing up associative operation, and do not allow standby plate writing according to self-operating with the irrelevant task of backup.Like this, both guarantee the data that standby plate self can not changed to be needed in the internal memory in the address space that backs up, can utilize the operation of I class address space and other irrelevant tasks of backup in this board memory on the standby plate again.
In the present embodiment, when CPU carries out read-write to internal memory by the Memory Controller Hub in the FPGA module, Memory Controller Hub is resolved the read/write memory instruction that CPU sends to it, instruction and the internal memory that can discern with internal memory is mutual then, even change so the model of internal memory has been carried out the type of change or internal memory, after process FPGA module is changed instruction,, still needn't change command system for upper layer software (applications).For example, in the command system that upper layer software (applications) is supported, the memory address instruction is: READ Address, and the memory address that internal memory can be discerned instruction is: READ rowcolumn, then the Memory Controller Hub of FPGA module is after the READ Address instruction that receives the CPU transmission, this instruction is converted into corresponding READ row column instruction, reads corresponding internal storage data by this instruction then.
As shown in Figure 2, be the flow chart of Hot Spare in the present embodiment, wherein the left side is the backup flow process of main board, and the right side is the backup flow process of standby plate, and concrete steps are as follows:
After step 201a, main board self check start, to the registration of classifying of file system and internal memory, promptly register category-A file, category-B file and C class file in the main board file system, and the I class in the main board internal memory, II class and III class address, and with the registration the C class file be mapped in the III class address space of main board internal memory.
After step 201b, standby plate self check start, to the registration of classifying of file system and internal memory, promptly register category-A file, category-B file and C class file in the standby plate file system, and the I class in the standby plate internal memory, II class and III class address, and with the registration the C class file be mapped in the III class address space of standby plate internal memory.
Step 202b, standby plate detect the state of main board, are normal operating condition if detect main board, execution in step 203b; Otherwise self is started as main board.
Because II, III class memory address space backup level difference, so the backup mode of correspondence is also inequality in system's running.
The map in II class memory address space for internal storage data in the II class memory address space and category-B file, owing to do not need to guarantee consistency, so adopt the mode of backing up in realtime, promptly at main board CPU when II class address space carries out write operation in the internal memory on to main board by the Memory Controller Hub in the main board FPGA module, the FPGA module is changed to 1 with the value of address space corresponding position in revising RAM of being modified.In addition, main board FPGA module is carried out and operation the registration RAM and the modification RAM of II class address space correspondence in the main board internal memory in real time, and will be that data in 1 the RAM corresponding memory address space are by the high-speed interface controller in the main board FPGA module with operation back result, high speed optical cable or high speed cable, and the high-speed interface controller of standby plate sends to the Memory Controller Hub in the standby plate FPGA module, Memory Controller Hub in the standby plate FPGA module is written to the data that receive in the standby plate internal memory and described data identical address space in the main board internal memory, after data are successfully write address space identical in the standby plate internal memory, return the backup successful information to main board FPGA module, the main board FPGA module value of wherein revising among the RAM corresponding position is set to 0 then.In addition, for the category-B file, high layer software is being revised each category-B end of file, as after calling the Close file, calculate the CRC check position of this document, and this CRC check position is sent in the standby plate internal memory in the corresponding address space, in standby plate, finished the modification of this document with sign, then when standby plate is converted to main board, can activate this document.
And for HI class address space, because wherein the map of C class file in internal memory need guarantee consistency, so adopt the mode of timed backup to carry out.Software in the present embodiment on the main board can be according to the cycle of user's appointment, regularly the operating system task of revising the archive memory district that relates to of activity is monitored, after these movable tasks all discharge CPU, FPGA module on main board sends backup command, the FPGA module that triggers on the main board is carried out the timed backup operation, again the main board internal memory is carried out the problem that write operation caused with regard to having avoided in backup like this.Main board CPU is when writing in the main board internal memory III class address space by the Memory Controller Hub in the FPGA module, the value of the III class address space that main board FPGA module is modified corresponding position in revising RAM is set to 1.Main board FPGA module is after receiving backup command, registration RAM and modification RAM to III class address space correspondence carry out and operation, read then carry out with all results of operation back be data in 1 the corresponding memory address space, position, and with these data by the high-speed interface controller in the main board FPGA module, high-speed interface controller in high speed optical cable or high speed cable and the standby plate FPGA module sends to the Memory Controller Hub in the standby plate FPGA module, by the Memory Controller Hub in the standby plate FPGA module with these data be written in the standby plate internal memory with these data in the main board internal memory in the identical III class address space, and after finishing backup, return the backup successful information to main board FPGA module, the value of the position of modification RAM correspondence corresponding in the main board FPGA module is changed to 0.In addition, owing to need to keep the consistency of C class file III class address space map in main board and standby plate internal memory, the FPGA module is after receiving backup command, before backing up, at first judge the consistent point identification of the transmission that whether has flag data to be in consistent state in the standby plate III class internal memory, transmit consistent point identification if having then wipe this, and after this backup is finished, write the consistent point identification of transmission again.
Can not lose in order to guarantee the Backup Data in the standby plate internal memory because of outage or other modes, FPGA module on the standby plate regularly is written to the data in II class on the standby plate and the III class internal memory in the file system in the present embodiment, these data that will be written in this specification in the file system are called standby plate savepoint file, and these files are used to recover internal storage data.
Whether step 205, standby plate break down to main board is detected, after detecting main board and breaking down, and execution in step 206.
Whether data consistency in this step: checking has the consistent point identification of transmission in the III class internal memory if being recovered specifically to comprise, if having then directly self is converted to main board; Otherwise, with the standby savepoint File mapping in the file system in internal memory.And utilize the CRC check position in the II class internal memory to judge whether this document is complete, if then activate this document; Otherwise do not activate this document.The file that is activated promptly is in the main state of using, and any subsequent file operation all can be carried out this document.Because need to preserve the resource status table that comprises each single board information on the main board, and only need to preserve in other veneers to relate to its other resources state table, auditing is exactly that the resource status table of main board and the resource status table of other veneers are consistent.Standby plate is initiated audit after being converted to main board, and the information of this plate record that promptly aligns and the information of other veneers record make whole telecommunication apparatus get back to consistent state.
For present embodiment more clearly is described, the software architecture to present embodiment is described below.As shown in Figure 3, in the present embodiment, software function is divided into following protocol stack: top is service application layer, and next coming in order are Hot Spare management level, operating system layer and file/internal memory Drive Layer, and the final physical layer is the FPGA module.Wherein, each upper-layer subsystem all is carried on lower floor's subsystem, and semantically more senior function is provided.Below every layer of performed operation is elaborated:
Service application layer is each concrete business function module, as Operation and Maintenance, accounting module etc.Wherein, each business function module is determined the backup level of the file that self relates to, and which is the category-A file promptly to determine the involved file of each business function module, and which is the category-B file, and which is the C class file.And when being file application internal memory, in the I of internal memory class address space, apply for internal memory for the category-A file, and in the II of internal memory class address space, apply for internal memory for the category-B file, in the III of internal memory class address space, apply for internal memory for the C class file.In addition, main board all is to be realized by the fault detect task of moving in the fault detection module in main board and the standby plate service application layer standby plate state and standby plate to the main board status detection among above-mentioned steps 202a, the 202b; Equally, the detection that whether standby plate breaks down to main board among the step 205a also is that the fault detect task of moving in the fault detection module by the standby plate service application layer realizes.
The Hot Spare management level, the system call relevant to Hot Spare shields, and carries out the grasp on Hot Spare opportunity and the management of Hot Spare quality scale.Work among above-mentioned steps 201a and the step 201b is carried out by the Hot Spare management level of main board and standby plate.In addition, above-mentionedly send backup command to the FPGA module and also carry out by the Hot Spare management level, be the Hot Spare management level of main board according to the user by coding or by the internal memory of script configuration and the classification of file, registration relates to revises the operating system task that need in the address space that backs up and/or the file system to need the file that backs up in the internal memory, these operating system task are called the backup inter-related task in this manual, but inter-related task does not comprise the task of operating system itself, and after System self-test starts, according to the cycle of user's appointment, regularly the backup inter-related task of activity is monitored, after the backup inter-related task of these activities all discharges CPU, FPGA module on main board sends backup command, and the FPGA module that triggers on the main board is carried out the timed backup operation.
Operating system layer adopts the general-purpose operating system or embedded OS with priority scheduling mechanism.The task of an operating system scheduling is called affairs from obtaining CPU to the process that discharges CPU, after affairs are finished, the internal memory and the file that need in the system to back up are in consistent state, and active and standby transmission with the timed backup data between the board memory only takes place at this moment.
File/internal memory Drive Layer is responsible for providing hardware driving, and all open and standardization of the Memory Controller Hub in the FPGA module no longer is described here.
Physical layer, i.e. FPGA module, the internal memory controlled function of taking over CPU, and under the configuration of upper layer software (applications) with File mapping in internal memory, and the operating backup operation of executive system.In description, described the how operating backup operation of executive system of FPGA module in detail to step 204a and step 204b.
Having under the situation of a plurality of standby plates, the mode of describing backup mode from main board to all standby plates and the foregoing description is basic identical, difference is that main board is carrying out the initial data file backup, system is operating to back up in realtime and during timed backup, all be data to be sent on all standby plates in the mode of broadcasting, each standby plate is all identical with the performed work of standby plate in the foregoing description, just after the main board fault, each standby plate through consultation or the mode of competition is definite is converted to main board by which standby plate, to guarantee having and a have only standby plate to convert main board to.
More than be explanation, press three address spaces in the backup levels division internal memory in this embodiment, and press the specific implementation after more or less backup level is divided memory address space, get final product with reference to above-mentioned specific embodiment to the specific embodiment of the invention.For example, memory address space is being divided into when not needing backup and needing two backup levels of backup, the operating backup of system so can adopt the mode of backing up in realtime, also can be adopted the mode of timed backup owing to only need carry out a backup level corresponding memory address space.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being made, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (16)
1. a hot backup system in this system, comprises CPU and internal memory respectively on main board and the standby plate; It is characterized in that, also comprise respectively on the main board of this hot backup system He on the standby plate: Memory Controller Hub and coffret;
Wherein, the CPU on the main board carries out read-write operation by the Memory Controller Hub of this plate to the internal memory of this plate;
The address space of the needs backup of dividing in advance in the Memory Controller Hub record internal memory on the main board, and the data that write of the address space that main board CPU is needed to back up in the main board internal memory by the Memory Controller Hub on this main board, send to Memory Controller Hub on the standby plate through the coffret on the main board and the coffret on the standby plate;
The Memory Controller Hub of standby plate receives described data, and described data are write in the standby plate internal memory and described data identical address space in the main board internal memory;
Coffret on the primary, spare plate connects, and transmits data between main board and standby plate.
2. system according to claim 1 is characterized in that, described Memory Controller Hub is the Memory Controller Hub that CPU carries, and described coffret is an Ethernet interface, and the Ethernet interface on the primary, spare plate connects by Ethernet.
3. system according to claim 1, it is characterized in that, described Memory Controller Hub is the Memory Controller Hub in the FPGA module, described coffret is that high-speed interface controller, the high-speed interface controller on the primary, spare plate in the FPGA module connects by a plurality of high speed cables that use that maybe can walk abreast, or connects by a plurality of high speed optical cables that use that maybe can walk abreast.
4. system according to claim 1 is characterized in that, described standby plate is one or more; When described standby plate is a plurality of, Memory Controller Hub on the main board writes by this Memory Controller Hub main board CPU in the address space that the main board internal memory need back up data send to Memory Controller Hub each standby plate in the mode of broadcasting through the coffret on each standby plate by the coffret on the main board.
5. according to arbitrary described system in the claim 1 to 4, it is characterized in that, CPU on the standby plate carries out read-write operation by the Memory Controller Hub of standby plate to the address space that does not need in the standby plate internal memory to back up, CPU on the standby plate only carries out read operation by the Memory Controller Hub of standby plate to the address space that needs in the standby plate internal memory to back up, thereby standby plate can utilize the memory headroom that does not need in the self EMS memory to back up to move and the irrelevant task of main board.
6. a heat backup method is characterized in that, presses backup level in advance and divides address space in the main board internal memory, and need the backup level corresponding address space of backing up in the minute book board memory on main board, and this method also comprises:
Memory Controller Hub in A, the main board sends to the data in the address space of needs backup in this board memory according to the backup level corresponding address space of needs backup in this board memory that writes down on the main board Memory Controller Hub of standby plate;
After the Memory Controller Hub of B, standby plate receives described data, described data are write in this board memory and described data identical address space in the main board internal memory.
7. method according to claim 6 is characterized in that, described backup level comprises: the needs backup is not backed up with not needing; Memory Controller Hub in the then described main board with the Memory Controller Hub that the data in the address space that needs in this board memory to back up send to standby plate is:
Memory Controller Hub in the main board sends to described data the Memory Controller Hub of standby plate when needing backup level corresponding address space to write data in this board memory;
And/or: the Memory Controller Hub in the main board regularly reads the data in the backup level corresponding address space that needs in this board memory to back up with the predefined cycle, and the described data that read is sent to the Memory Controller Hub of standby plate.
8. method according to claim 6 is characterized in that, described backup level comprises: important, generally and not need backup, the described backup level of backup that needs comprises important and general;
Memory Controller Hub in the described main board comprises the Memory Controller Hub that the data in the address space that needs in this board memory to back up send to standby plate:
Memory Controller Hub in A1, the main board sends to described data the Memory Controller Hub of standby plate when general backup level corresponding address space writes data in this board memory;
With,
Memory Controller Hub in A2, the main board regularly reads the data in the important backup level corresponding address space in this board memory with the predefined cycle, and the described data that read is sent to the Memory Controller Hub of standby plate.
9. method according to claim 8 is characterized in that, in the described steps A 2, the Memory Controller Hub that sends the data to standby plate further comprises before:
Whether judge has the consistent point identification of transmission, if having then wipe the consistent point identification of described transmission, carry out the described step that sends the data to the Memory Controller Hub of standby plate then in the standby plate; If do not have then the described step that sends the data to the Memory Controller Hub of standby plate of direct execution;
Further comprise after the described step B:
B1, main board write the consistent point identification of transmission to standby plate, and indicating this time transmission success, and the data in the important backup level corresponding address space are in consistent state in the primary, spare board memory;
C, standby plate are after detecting main board and breaking down, and whether check has the consistent point identification of transmission, if having, then directly self is converted to main board in self.
10. method according to claim 9 is characterized in that, further comprises behind the described step B1: standby plate regularly is written to the data in this board memory in corresponding this plate file system;
Then among the step C, further comprise after whether the consistent point identification of transmission is arranged in the described inspection self: do not transmit consistent point identification in self if be checked through, then recover internal memory to the data in this plate file system of correspondence according to said write.
11. according to arbitrary described method in the claim 7 to 10, it is characterized in that the Memory Controller Hub that the described data that regularly read with the predefined cycle are sent in the standby plate is: the data that will regularly read with the predefined cycle send to Memory Controller Hub in the standby plate with the bandwidth that sets in advance;
The described bandwidth that sets in advance was provided with according to the described predefined cycle.
12. according to arbitrary described method in the claim 7 to 10, it is characterized in that this method further comprises: main board writes down in advance and relates to the operating system task of revising data in the backup level corresponding address space that needs to back up in the internal memory;
Memory Controller Hub in the then described main board with predefined cycle timing reading of data is:
Main board is regularly monitored operating system task movable in the operating system task of described record with the predefined cycle, after these movable operating system task finish, read described data by the Memory Controller Hub in the main board.
13., it is characterized in that this method further comprises: in advance by the file in the backup level division main board file system identical with internal memory according to arbitrary described method in the claim 6 to 10;
Further comprise before the then described steps A and after the step B:
A01, system's primary, spare plate in service be with File mapping in internal memory the time, according to backup level will be separately File mapping to having in other address space of identical copy level with described file in the internal memory separately.
14. method according to claim 13 is characterized in that, further comprise before the described steps A 01: the initial data file backup procedure is specially:
After A00, main board and standby plate self check start, register address space in the internal memory separately and the file in the file system by backup level respectively, and main board directly copies the data in the backup level corresponding address space that needs in the self EMS memory to back up to address space identical in the standby plate internal memory.
15. method according to claim 6 is characterized in that, in advance the modification situation of data in the minute book board memory address space on main board;
Then the Memory Controller Hub in the main board described in the steps A with the Memory Controller Hub that the data in the address space that needs in this board memory to back up send to standby plate is:
Memory Controller Hub in the main board is according to the modification situation of the internal storage data in this board memory address space that writes down on the main board, read the data that have been modified in the backup level corresponding address space that needs in this board memory to back up, and the described data that have been modified are sent to the Memory Controller Hub of standby plate.
16. method according to claim 15 is characterized in that, needs the method in the backup level corresponding address space of backing up to be in the described record internal memory:
Different backup level corresponding address space in the record internal memory on main board, and the registration RAM that writes down the address space backup instances in the internal memory is set on main board, whether the sector address space among this RAM in the corresponding main board internal memories of the different values of each needs backup;
The method of the data modification situation in the described minute book board memory address space is: the modification RAM of the data modification situation in the record memory address space is set on main board, and whether the sector address space among this RAM in corresponding this board memory of the different values of each is modified;
Then described modification situation according to the internal storage data in this board memory address space that writes down on the main board, reading the data that have been modified in the backup level corresponding address space that needs in this board memory to back up is: according to registration RAM and the value of revising the corresponding position of RAM determine the address space at data place from needs to being modified of writing of standby plate, read the data in the determined address space.
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| CNB2005101024184A CN100370759C (en) | 2005-09-06 | 2005-09-06 | Thermo-back-up system and method |
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| CNB2005101024184A CN100370759C (en) | 2005-09-06 | 2005-09-06 | Thermo-back-up system and method |
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| CN101072088A (en) * | 2007-07-10 | 2007-11-14 | 华为技术有限公司 | Data backup system, main board and data backup method |
| CN101583144B (en) * | 2009-07-07 | 2011-11-16 | 杭州华三通信技术有限公司 | Wireless controller service information backup method and equipment |
| CN101980476B (en) * | 2010-11-16 | 2012-12-12 | 北京星网锐捷网络技术有限公司 | Warm backup method and network equipment |
| CN102118309B (en) * | 2010-12-31 | 2013-08-21 | 中国科学院计算技术研究所 | Method and system for double-machine hot backup |
| CN103731402B (en) * | 2012-10-12 | 2018-07-24 | 腾讯科技（深圳）有限公司 | The access method and device of flag bit |
| CN103959710B (en) * | 2012-11-22 | 2018-01-23 | 华为技术有限公司 | A kind of method of facility information backup, equipment and system |
| CN103455372B (en) | 2013-08-31 | 2017-05-10 | 华为技术有限公司 | Data migration method for memory modules in server and server |
| EP2913754B1 (en) | 2013-11-22 | 2016-11-09 | Huawei Technologies Co., Ltd. | Memory data migration computer and method |
| CN113110880A (en) * | 2020-01-10 | 2021-07-13 | 中移物联网有限公司 | System starting method and electronic equipment |
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