CN100365932C

CN100365932C - Apparatus, methods and articles of manufacture for a multiband switch

Info

Publication number: CN100365932C
Application number: CNB2003801093408A
Authority: CN
Inventors: 马克·F·凯尔库斯; 克里斯托弗·N·布林德尔
Original assignee: Pine Valley Investments Inc
Current assignee: MA Com Inc
Priority date: 2002-12-17
Filing date: 2003-12-17
Publication date: 2008-01-30
Anticipated expiration: 2023-12-17
Also published as: CN1745517A

Abstract

The invention is directed to a multi-band switch having a transmitter switching section with a plurality of transmission ports, and a receiver switching section with a plurality of receiver ports, each having associated switching topologies to switch one of the ports to an antenna port. The switching topologies may use a plurality of series-connected FETs, such as insulated gate n-channel FETs, where the transmitter port switching elements may have larger switching transistors than the receiver port switching elements. The main signal path transistors of the transmitter and receiver switching elements be interdigitated FETs, in which source region fingers and drain region fingers alternate within the transistor area. These interdigitated source and drain regions may be spaced apart from each other by a sinuous channel region, over which is a gate metallization.

Description

Be used for device, the method for multiband switch and manufacture a product

Technical field

The present invention relates to a kind of switch, concrete is a kind of multiband (multi-band) switch that is used for wireless transmission and reception, on single semiconductor chip, makes.

Background technology

The conventional switch device is operated the path of advancing with control signal.Normally used switching device has two kinds of fundamental types: dynamo-electric with solid-state.Solid-state switch uses certain semiconductor device that carries out switch process, and this semiconductor device can be diode, field-effect transistor or bipolar transistor.Usually, diode switch has low insertion loss, and the switching speed that transistor is formed is very fast.In switching, the high-frequency signal of switch such as radio frequency (RF) makes field-effect transistors (FET).

The FET switch is in OFF (ending) state (high impedance) till the control voltage (saturation voltage) with predetermined amplitude puts on its grid.When saturation voltage is put on grid, FET switches to ON (conducting) state that current path between its source electrode and drain electrode shows low-down resistance states.

Though the FET switch does not provide output (Yu Ding output meeting at this moment provides in drain electrode) till saturation voltage is put on grid in theory, in fact before applying saturation voltage, FET can leakage current.And, reaching after control gate pole tension and switch be in the work, harmonic wave appears in output voltage.Circuit designers is attempted sharpening (sharpen) FET firing point and is attempted to minimize harmonic wave of output voltage.Simultaneously, integrated circuit (IC) design person attempts to minimize as much as possible the size (realestate) of (on-chip) on the chip and pursues lower control voltage simultaneously.Loss is inserted in the impedance that designers of signal switches also attempts to be minimized in the signal path.

In conventional wireless switch practice (as WLAN, bluetooth, CDMA, TDMA, GSM, W-CDMA etc.), produced with wireless mode and not only sending out line data on the antenna but also on antenna, receiving the demand of line data.Used different transmitters and receiver chip to carry out these tasks so far.As long as single-chip (single-die) integrated circuit is not subjected to the adverse effect of the improper load of the electric capacity that the coexistence owing to sender-switch circuit on the chip produces to its receiver port (vice versa), merge on the circuit of single-chip integrated these functions highly beneficial from technical elements.

Summary of the invention

The invention discloses device, the method that is used for multiband switch and manufacture a product.Embodiments of the invention comprise circuit of single-chip integrated, the receiver switch sections of realizing having the sender-switch part of a plurality of transmit ports thereon and having a plurality of receiver ports.Each transmitter and receiver port all are associated with switch topology, can be with its operation so that a selected port be switched to antenna port, and the transmission of signal or the reception of the signal of entering a profession are used to go on a journey.

With at least one of switch topology be arranged at different levels in, wherein the first order is near in antenna port and last the most approaching a plurality of transmitters of level or the receiver port each.In order to transmit signal from selected port by last level, with a transistor or comprise that the transistorized transistor switch element of several serials encourages, and this switch element comprises that the first order is to be connected to antenna port with selected port.With the remainder of last level and remaining switch topology deexcitation (deactivate) thus isolate those ports from antenna port.In a preferred embodiment, when being switched to antenna port, uses a selected receiver port level of these cascades.

According to a preferred embodiment of the invention, make field-effect transistors realize switch topology, and preferably use insulated-gate type n slot field-effect transistor (though can use other semiconductor device) for identical purpose.Because the intensity of trip sender signal will be basically greater than by the signal that antenna received that is connected to antenna port, so the transmitter port switch element has than the big switching transistor of receiver port switch element.In the embodiment shown, each transmitter port switch element comprises a plurality of FET connected in series, need be applied in grid grid is placed the saturation voltage of " ON " state thereby reduced.And preferably the main signal path transistor of transmitter and receiver switch element is interdigitated FET, and wherein source area finger-type thing (finger) and drain region finger-type thing are staggered in transistor area.Separate each other by the channel region that wriggles of gate metalized thereon source electrode and drain region these interdigital.

According to a preferred aspect of the present invention, place bypassed resistor across each signal transfer switch element transistors, thus these transistor turns of sharpening and the voltage when turn-offing.Preferably the transistor switch topology also comprises preceding feedback condenser, is used for the power control and the unwanted harmonic wave of decaying.The grid that can use shunting transistor will be in those switching transistors of OFF state is connected to ground, thereby strengthens the isolation between unselected port and antenna port.

The major technique advantage of various embodiment of the present invention comprises provides circuit of single-chip integrated, and it is used for the transmission of wireless signal and reception and minimizes switch element simultaneously and insert loss, and reduces the capacitive load on the port that is switched of such chip.

Particularly, according to an aspect of the present invention, a kind of circuit of single-chip integrated is provided, be used among a plurality of transmit ports and a plurality of receiver port, switching, this circuit of single-chip integrated comprises: have the sender-switch part of a plurality of transmit ports, can operate the transmitter control circuit one of selected a plurality of transmit ports are switched to transmission node; With receiver switch sections with a plurality of receiver ports, can operate the receiver control circuit one of selected a plurality of receiver ports are switched to transmission node, wherein, for each transmit port, sender-switch partly comprises the series field effect transistor FET switch topology that can be operated to last described transmit port is coupled to transmission node, wherein at least one FET switch topology comprises at least one FET, and this FET has the source region and a plurality of drain region interdigitate that are connected of a plurality of connections, formation is to be wrapped in the grid that wriggles between source region and the drain region.

According to a further aspect of the invention, provide a kind of single-chip multiband switch that is used for radio communication, comprising: antenna port; A plurality of transmitter port can the console switch topology switch to antenna port with last described transmitter port for each transmitter port; With a plurality of receiver ports, can the console switch topology last described receiver port be switched to antenna port for each receiver port, wherein at least one switch topology comprises at least one interdigitated field-effect transistor, and this interdigitated field-effect transistor has the drain region of the connection of a plurality of elongations, the source region that is connected with a plurality of elongations of drain region interdigitate, the sinuous channel region of the elongation that the drain region is separated from the source region, thereby and the interdigitated field-effect transistor of switch between ON and OFF state of the grid on channel region.

According to a further aspect of the invention, provide a kind of one of a plurality of receivers and a plurality of transmitters are switched to the method for receiver/transmitter antenna, the method comprising the steps of: each transmitter is connected to corresponding of a plurality of transmitter port of being formed on the single integrated circuit chip; Each receiver is connected to corresponding of a plurality of receiver ports of being formed on the chip; Control each with transmitter and receiver port in corresponding related a plurality of switch topologies selected one so that of the corresponding selection of transmitter and receiver port is connected to the antenna port that is formed on the chip; With other switch topologies of control with transmitter and the isolation of receiver port and antenna port with other, wherein said method also comprises step: at least some switch topologies are arranged in the level of cascade, and the level of described cascade comprises the first order that is coupled to antenna port and is coupled to the last level of a plurality of transmitters or receiver port; By the conducting first order one of the selection of last described transmitter or receiver port is connected to antenna port, and a related switch of conducting and the described selection of last described transmitter and receiver, wherein last described switch is the part of last level; With other switches and the remaining switch topology that turn-off in the level in the end.

Description of drawings

Also with reference to following detailed explanation, various aspects of the present invention will further become clear in conjunction with the drawings, and identical in the accompanying drawings label is represented identical parts, wherein:

Fig. 1 shows and is in the set of circuits schematic diagram that modeling is carried out in the impedance of the conventional switch of " ON " state to have two branch roads, each branch road dual serial switch, one of them branch road according to prior art;

Fig. 2 show to according to the embodiment of the invention, have a set of circuits schematic diagram that modeling is carried out in impedance that a selected branch road is in switch electronic switch, cascade of " ON " state;

Fig. 3 shows the set of circuits schematic diagram that modeling is carried out in impedance that two branch roads shown in Fig. 1 all are in the circuit of " OFF " state;

Fig. 4 shows the set of circuits schematic diagram that circuit that two branch roads shown in Figure 2 all are in " OFF " state carries out modeling;

Fig. 5 shows according to an embodiment of the invention, be used for the circuit diagram with the circuit of single-chip integrated that switches a plurality of transmitters and receiver port from antenna port;

Fig. 6 (a)-(d) is the circuit diagram of the embodiment of integrated circuit shown in Figure 5; With

Fig. 7 is the plane graph of the representative topological layout of circuit shown in Fig. 3 and 4.

Embodiment

Fig. 1 and 2 is many group circuit diagrams, and they are to carrying out modeling according to the impedance (Fig. 1) of theoretical two branch switch paths of conventional practice with according to the impedance (Fig. 2) of theoretical two branch switch paths of the employed Cascading Methods of the embodiment of the invention.In Fig. 1 and 2, shown in a branch road 11 of switch be in the ON state, be sent to output 14 to allow signal from input 12.Another branch road 15 guiding outputs 16.Two kinds of topologys are all constructed by insulated-gate type field effect transistor (IGFET).In Fig. 1, generally the two branch switchs by 10 indications have first branch road 11, and it is included in and is modeled as two

FET switches

13 and 20 that resistance is the resistance of R here.Another branch road 15 has two FET17 and 22, and they are in the OFF state with advantage junction capacitance C.As described in first kind of simplification, branch road 11 has equivalent resistance 2R and branch road 15 has equivalent junction capacitance C/2.By again one the step simplify, it can be approximated to be the total insertion loss 21 of 2R.

Fig. 2 shows the switching mode with identical purpose, wherein signal through as the transistor or the switch of the similar number that in the circuit of Fig. 1, occurs propagate.But the switch of cascade 23 has big capacity FET19, its gate perimeter double (as) FET20, therefore produce the ON resistance of R/2.This FET19 replaces the branch road of FET13 among Fig. 1 and 17.The FET20 of conducting presents resistance R, and the FET22 that ends presents junction capacitance C.The electric capacity of FET22 is ignored in first simplification of this circuit, keeps the R/2 and the R of series connection, and it inserts loss less than the 2R that Fig. 1 circuit is presented.

Fig. 3 illustrates the traditional circuit of Fig. 1, but two branch roads are in the OFF state.FET13 in the branch road 11 and each of 20 all have junction capacitance C, and it is reduced to C/2.Similarly, FET17 in

branch road

15 and 22 each junction capacitance C merge into equivalent capacity C/2.As shown in the last level of simplifying, the impedance of seeing on the input 12 of OFF circuit is C.In Fig. 4 (it is a circuit shown in Figure 2, but has two OFF branch roads), be 2C by big public (common) junction capacitance that switch P ET19 produced.Branch road FET20 and 22 each all present junction capacitance C.As in the diagrammatic sketch of centre shown in 24, it is reduced to each and has value 2C, serial, two electric capacity.28 show it and are reduced to from port one 2 and see input impedance C in the past in the diagrammatic sketch of simplifying.Therefore in the OFF state, tradition produces identical impedance results with Cascading Methods.

Fig. 5 is the schematic layout pattern of cascade branch road integrated circuit according to an embodiment of the invention.Can on single integrated circuit chip or tube core 100, make this embodiment.Chip 100 has a plurality of signals and control port/pad at its peripheral edge.

In an illustrated embodiment, arrange transmitter port along a side of chip, and arrange the receiver port along an other side of chip.Transmitter port comprises port Tx2 and Tx1.With the load modeling that is connected to these ports is the capacitor of 100 pico farads.Sender-switch holding wire V_Tx1 is related with transmitter port Tx2 and Tx1 respectively with V_Tx2.The left side of chip in this example also has antenna port ANT, and a transmitter port or a receiver port are connected to this antenna port ANT.

In an illustrated embodiment, integrated circuit 100 comprises SP3T (SP3T) switch sections 102, and its border illustrates with pecked line.Signal path illustrates and switch controlling signal path shown in broken lines with solid line.Switch sections 102 comprises switch 104, and it can be by control line V_Tx1 operation to be connected to antenna port ANT with transmitter port Tx1.By switch 106 like the switching signal V_Tx2 class of operation so that transmitter port Tx2 is connected to antenna port ANT.Switch 108 is the first order in the cascaded switch system, and can be by receiver switching signal V_RxC operation so that receiver signal node 110 is connected to antenna port ANT.Though in the embodiment shown, integrated circuit 100 selectively switches one of two transmitter port, and the present invention also can be used to have the embodiment of or three or more transmitter port.

Embodiment shown in Fig. 5 has four receiver port Rx1, Rx2, Rx3 and Rx4, pad by along the chip right side (as shown in this figure), place with respect to transmitter port and antenna port.Throw (SP4T) switch sections 112 by hilted broadsword four and switch among these receiver ports Rx1-Rx4 selected one.Console switch part 112 is switching to node 110 one of among four receiver port Rx1-Rx4.Particularly, receiver switch sections 112 comprises: switch 114, and it is operated so that receiver port Rx4 is switched to node 110 by control voltage V_Rx4; Switch 116, it is operated so that receiver port Rx3 is switched to node 110 by control voltage V_Rx3; Switch 118, it is operated so that receiver port Rx2 is switched to node 110 by control voltage V_Rx2; And switch 120, it is operated so that receiver port Rx1 is switched to node 110 by control voltage V_Rx1.Thereby with one of switch 108 console switch 114-120 with in the receiver port selecteed one be connected to antenna port ANT.As in transmit port, receiver port Rx1-Rx4 is modeled as comprises 100 pico farad external loadings.Use Cascading Methods to come switched antenna ANT to reduce the influence of the insertion loss that received signal is subjected to by two-stage 108,112.In the embodiment shown in fig. 5, circuit 100 is in two transmitter port one, and perhaps in four receiver ports switches to antenna port, and isolates remaining port simultaneously.The number of transmitter/receiver and kind can with shown in different.In with three or more transmitter port selected one when switching to antenna port, should arrange one group of switch of cascade, as the situation of four receiver ports in the embodiment shown in this for this reason.The switch topology of cascade can be used similarly with a receiver end that switches to antenna port in the three or more receiver ports.

Fig. 6 (a)-(d) is the circuit diagram of the possible embodiment of integrated circuit shown in Fig. 5.Fig. 6 (a) is a general synoptic diagram, shows the use that single FET grid is used for each receiving port (Rx1-Rx4).Fig. 6 (b) is a general synoptic diagram, shows the use that two grids are used for each receiving port.Fig. 6 (c) is a detailed maps more, shows the use of bypassed resistor and preceding feedback condenser.Fig. 6 (d) is a detailed maps more, shows the use into the integrated series/shunt of preceding feedback condenser.

As discussed above, can comprise three signal path field effect transistor groups connected in series 104,106 and 108 at the SP3T shown in Fig. 5 (SP3T) switch sections 102, be responsible for switching transmitter port Tx1, Tx2 and receiver node 110 respectively.In the embodiment shown in Fig. 6 (a)-(d),

switch topology

104 and 106 is mutually the same basically, and switch 104 will describe in detail as an example.Switch 104 in the embodiment shown can comprise three field-effect transistors connected in series to 140,142 and 144, and its each all is that transistor connected in series is to (though the invention is not restricted to this).Send line or signal path 146 and transmitter bond pad Tx1 can be connected to first end of field-effect transistor 140 current path.The grid of each FET to 140 can be connected to voltage control line 154 by

resistance

150 and 152, and voltage control line 154 extends to the VTX1 pad subsequently.Before feedback condenser 156 can be connected with grid an end of 140 across FET.

FET was to an end of 142 current path in the middle of second end of the current path of two FET140 (being assigned therein as source electrode or drain electrode is arbitrarily) can be connected to.Similarly, FET can be connected to the end of last FET to 144 current path to 142 second end.FET can be connected to node 166 to second end of 144 current path, and node 166 can be connected to antenna bond pad subsequently.The voltage control line 154 of signal VTX1 can be connected to control electrode or the grid of two FET 142 via resistors in parallel 168 and 170, and is connected to the grid of last two FET 144 by resistor 172 and 174.Preceding feedback condenser 176 can be connected to second end of its current path from the grid of two FET 144.Finish the topology of this switch element, shown in the embodiment as shown in Fig. 6 (c)-(d), bypassed resistor 180 can be from connecting 140-144 across FET, thereby the current path connected in series of FET 140,142 and 144 is created IEEE Std parallel highway.

In the embodiment shown, signaling switch FET 140-144 can be a n channel enhancement isolated-gate field effect transistor (IGFET).Can use the transistor of other kinds or conduction type in these positions, as bipolar transistor or junction field effect transistor.Transistorized conduction type can not be n raceway groove but p raceway groove, and the present invention and unrestricted.Transistor in the embodiment shown can form on the semiconductor aspect such as silicon or best GaAs.

Switch element 104 can be from the strong relatively sender-switch signal of line 146 carryings.In the embodiment shown, Tx1 switch element 104 can be built in around six FET connected in series of paired arrangement, though the number of FET connected in series can increase or reduce in other embodiment.Can use a plurality of FET connected in series to form in the embodiment shown switch element 104,106 and 108, operate and do not need to increase peripheral components or chip size at low control voltage (being the low pressure of VTX1) to allow switch.

In theory, desirable switch does not provide output up to till obtaining saturation voltage on the grid.But the switch element such as switch 104 does not have ON time accurately in practice, but just begins conducting before saturation voltage is applied in.Use Fig. 6 (c) and (d) shown in, the timing accuracy that increases switch activator such as the bypass resistance topology of the single resistor 180 of all three two FET connected in series 140,142,144 of leap.Bypassed resistor 180 provides known resistive path.Select resistance than the FET 140-144 in the OFF state little, but than the big bypass resistance of resistance of the FET 140-144 in the ON state.The resistance of the resistor of selecting in this resistance value scope 180 allows bypassed resistor 180 control flows to cross the electric current of switch element 104.

When switch 104 is in the OFF state, the known electric current (being actually known leakage current) that bypassed resistor 180 produces by that path.Along with control voltage increases to saturation voltage, the resistance of FET 140-144 begins to reduce.The resistance of FET 140-144 reduces to cause usually the leakage current that increases or arrives saturation voltage part switch activator state before.But bypassed resistor 180 restriction and prevent that preferably electric current from flowing through FET 140-144 is till the resistance of the such FET point during less than the resistance of bypassed resistor 180.In fact, bypassed resistor 180 restriction electric currents flow through FET up to FET approaching reach capacity voltage and then conducting.Like this, bypassed resistor 180 increases switch activator accuracy regularly by sharpening control voltage.

Because the linearity is not a problem, so use bypassed resistor 180 to focus on that increase is to the accuracy of whole switch element 104 increase activation timings rather than at the single FET 140,142 and 144 that forms switch.In example embodiment, device 140-144 does not need high linearity.As the situation that in a single day switch activator will be exported big relatively electric current here, also the most handy single bypassed resistor 180.In the embodiment that substitutes, can replace resistor 180 with each a plurality of resistor of crossing over each field-effect transistor 140-144.For FET 140-44 substitutes the activation timing accuracy that individual resistors can focus on to be increased into each independent FET 140-144.The performance characteristics that causes them when the aborning technique change of FET 140-144 not simultaneously, this may be extremely important.Use individual resistors can allow resistance change in the position of resistor 180, thereby but the technique change transistor 140-144 of even now still can be in approximately identical time conducting or shutoff.

Not as saving in the important alternate embodiment of chip size, can omit bypassed resistor 180 (shown in Fig. 6 (a)-(b)) at conducting/stopcock exactly.

Preferably switch element 104,106 and 108 each all comprise one or more before feedback condensers, such as

capacitor

156 and 176, shown in Fig. 6 (c)-(d).The harmonic noise that uses these preceding feedback condensers to reduce distorted signals and improve their associated FET 140-144 reduces the feature and the linearity.In other embodiments, can omit one or two of preceding

feedback condenser

156 or 176, shown in Fig. 6 (a)-(b).

Can form preceding feedback condenser by the known method in the known technology.Particularly, with dielectric substance suitable between them, the metallising of using can be expanded to an electrode of formations (for example) capacitor 156 in the grid that forms FET 140-144, and the metallising that will form signal transmission line 146 expands to its other electrodes of formation.

And in other embodiments, based on the switch element 106 of FET can FET number connected in series, whether have aspect the electrical value of bypassed resistor or preceding feedback condenser or any of these device different with switch element 104, in the embodiment shown, the switch element 106 of switching signal path Tx2 is identical with switch element 104 under the influence of control voltage VTX2.Therefore will no longer describe in detail.

Switch element 108 is similar to

switch element

104 and 106 aspect most of with regard to configuration.In the embodiment shown, switch element 108 comprises two transistors that are connected in series to 184 and 186, and it is the n channel insulated gate field preferably.First end of the current path of two FET 186 (as drain electrode) is connected to antenna node 166.The current path of two FET 184 or the other end of passage can be connected to receiver switching node 110.

In an illustrated embodiment, use resistors in parallel 192 and 194 that VRXC voltage control line 196 is connected to transistor to 186 control electrode or grid.Similarly, resistors in parallel 198 and 200 is connected to FET to 184 grid with voltage control line 196.In the embodiment shown in Fig. 6 (c), can connect bypassed resistor 204 across the current path of the FET 184-186 that is connected in series.Perhaps, as shown in Fig. 6 (d), can use bypassed

resistor

204 and 205.

As mentioned above, switch sections 108 is first order of receiver switching circuit, the second level comprises a plurality of (for example four) receiver signaling switch transistor 114,116,118 and 120.These transistors can comprise that (for example) single FET or FET are right, as shown in an embodiment.Each of first end of these transistorized current paths (in the embodiment shown, being drain electrode) can be connected to intermediate node 110.Along any one receiver signal/antenna signal paths, two FET 184,186 can with switching transistor 120,118,116 and 114 in one of in pairs, thereby six transistors are arranged in signal path.Then this will be matched with six transistors in each sender signal path at the transistor in the received signal path.In the embodiment shown in Fig. 6 (a), can in switch sections 108, comprise extra FET.

Second end of the current path of FET 114 can be connected to the pad that is used for receiver signal Rx4.Second end of the current path of FET 116 can be connected to the pad of receiver signal Rx3.Second end of the current path of FET 118 can be connected to the pad of receiver signal Rx2.Second end of the current path of FET120 can be connected to the pad of receiver signal Rx1.

In the embodiment shown, each receiver switching transistor 114-120 is associated with it one group of assembly that comprises grid resistor, preceding feedback condenser and shunting transistor.Because any one these assemblies to other from series connection receiver switching transistor 114-120 are all identical in the embodiment shown, so their one group here only is described.Should be appreciated that according to technology and design and consider that one from receiver switching transistor 114-120 to another, the present invention thinks over the variation when being with or without these elements and the variation of their values.

Grid resistor 228,229 can be connected to the grid of each FET of transistor 114 pad of receiver control signal VRX4 via gate node 226.By the current path of shunting transistor 230 and bridging condenser 232, gate node 226 can also be connected to pad 234, and pad 234 is connected to ground subsequently.The grid of shunting transistor 230 can be connected to pad 234 via resistor 238.It is much smaller that shunting transistor 230 cans be compared to its associated signaling switch transistor 114 most, and be depletion device.Thereby can connect the timing of bypassed resistor 240 sharpening shunting transistors 230 across the current path of shunting transistor 230.

Use a main cause of shunting transistor 230 and associated component to be: when receiver signaling switch 114 is in the OFF state, to increase isolation from receiver signal node Rx4 to node 110.Because identical signal VRX4 is fed into the drain electrode of the grid and the shunting transistor 230 of transistor 114, so this phenomenon takes place.Any value of control signal VRX4 all has opposite effects to the operation of transistor 114 and shunting transistor 230.Such as, deducting in pinch-off voltage (pinchoff voltage) Vp (on the magnitude at the 0.7V) situation with the desired signal voltage that surpasses Rx4 in the value of selecting VRX4, VRX4 turn-offs shunting transistor 230 simultaneously with actuating switch transistor 114.If the value of VRX4 arrives deliberately the value less than Rx4-Vp repeatedly, then VRX4 is with stopcock transistor 114 and the shunting transistor of conducting simultaneously 230.The isolation that this exhausts the voltage on gate node 226 and increases node 110 and Rx4 port/pad.The shunt transistor current path ground connection that bridging condenser 232 has prevented to be coupled resistance.

Though in an illustrated embodiment, provide single integrated circuit that one of one of four receiver ports or two transmitter port are switched to antenna port, but can change the number of receiver port and/or the number of transmitter port as required because and the switching circuit that provides together of each such port be that big pattern is determined.And expectation provides the

FET switch element

104 and 106 of a plurality of series connection, and they can switch to the signal of high relatively electric current the antenna node of trip, preferably wireless transmission.On the other hand, thus the signal that on antenna, detects will more weak switch 114-120 each all have single FET.The signal of attempting to switch according to them consider intensity, the number of switching transistor and size can change.

Fig. 7 show with in the layout and the topology of the similar integrated switching circuit of integrated switching circuit shown in Fig. 5 and Fig. 6 (a)-(d).Show the FET that is used to switch sender signal Tx1 and Tx2 102, and show the receiver switch sections 112.Each of tandem tap FET all is the interdigitated switching transistor of high power, and wherein each of source electrode and drain electrode all has a plurality of finger pieces it is interlaced with each other.By the suitable dopants of first conduction type being mixed source electrode and the drain electrode that the Semiconductor substrate with films of opposite conductivity can produce interdigital shape, and alloy can be self-aligned to grid, and described grid is placed between them.In an illustrated embodiment, grid is carried out metallising sinuously, but can alternatively grid be carried out branch in a further embodiment.Certainly, the shape of raceway groove is corresponding with grid.

In view of the second level receiver transistor in 112 parts must switch the signal of smaller power, so they are less.This transistor less relatively and in the embodiment shown each transistor have only one, non-interdigitated source electrode and drain region.Thereby the raceway groove of doped crystal pipe becomes depletion device.Can be with the traditional approach device that has a resistance, such as polysilicon lines, and can adjust their value by the length of adjusting line.

In operation, can be with any integrated circuit of operating in the embodiment shown in two transmitter mode or four receiver modes.If (for example) will send signal from pad Tx1, then VTx1 will be high, and VTx2, VRxC, VRx2, VRx1, VRx3 and VRx4 will be low.This conducting serial transistor topology 104, and turn-off every other switching transistor.In this case, serial transistor topology 104 will produce low relatively resistance and give other junction capacitance and insert loss, and the OFF branch road of circuit is very little to the induced impedance influence.

If will receive specific signal (as, with a signal that appears on the Rx3), then control signal VTx1, VTx2, VRx1, VRx2 and VRx4 will be low.Control signal VRx3 and VRxC will be high, turn-on transistor topology 108 and transistor 116.The transistor 108,116 of conducting will produce relatively little resistance and insert loss to resultant signal; Ignore the high relatively junction capacitance that is produced by the OFF branch road.Therefore, the circuit topology of cascade shows that the signal lower than traditional non-cascaded topology inserts loss.

In a word, illustrated and illustrated can be used for to the circuit of single-chip integrated that switches a plurality of wireless signals from antenna.Thereby illustrated IC arranges its switch FET to reduce insertion loss in the intensity of the signal that is switched with cascaded topology.Integrated circuit according to the embodiment of the invention is very useful for the switching signal in CDMA, w-CDMA, IEEE 802.11, bluetooth and similar wireless protocols, and compares the saving space with the chip that receives with the individual processing transmission.

Though had been illustrated in the accompanying drawings the preferred embodiments of the present invention and have been described in detail in the above, the present invention only is subject to the scope of appended claims and main idea and is not limited to foregoing.

Claims

1. a circuit of single-chip integrated is used for switching among a plurality of transmit ports and a plurality of receiver port, and this circuit of single-chip integrated comprises:

Sender-switch part with a plurality of transmit ports can be operated the transmitter control circuit one of selected a plurality of transmit ports are switched to transmission node; With

Receiver switch sections with a plurality of receiver ports can be operated the receiver control circuit one of selected a plurality of receiver ports are switched to transmission node,

Wherein, for each transmit port, sender-switch partly comprises the series field effect transistor FET switch topology that can be operated to last described transmit port is coupled to transmission node,

Wherein at least one FET switch topology comprises at least one FET, the source region that this FET has a plurality of connections with a plurality of drain region interdigitate that are connected, form to be wrapped in the grid that wriggles between source region and the drain region.

2. integrated circuit according to claim 1, wherein the receiver switch sections comprises the level of at least two cascades, the level that can control first cascade switches to receiver node with transmission node, and the level that can control second cascade switches in a plurality of receiver ports selected one with receiver node.

3. integrated circuit according to claim 1 also comprises the antenna port that is coupled to transmission node.

4. integrated circuit according to claim 1, wherein each series connection FET switch topology comprises a plurality of FET, it has the current path of coupled in series each other.

5. integrated circuit according to claim 4, wherein each series connection FET switch topology comprises: first FET among the FET, approach corresponding transmit port, a FET has the current path that has first end that is coupled to a transmit port and a grid, be coupling in described first end and the grid that is coupled between a preceding feedback condenser and a grid.

6. integrated circuit according to claim 4, wherein each FET switch topology comprises: have current path and grid last FET, be coupled to the preceding feedback condenser of first end of the current path of transmission node, first end from gate coupled to described current path.

7. integrated circuit according to claim 4 wherein, at least one of FET switch topology, is coupled bypassed resistor across two current paths of a plurality of FET at least.

8. single-chip multiband switch that is used for radio communication comprises:

Antenna port;

A plurality of transmitter port can the console switch topology switch to antenna port with last described transmitter port for each transmitter port; With

A plurality of receiver ports can the console switch topology switch to antenna port with last described receiver port for each receiver port,

Wherein at least one switch topology comprises at least one interdigitated field-effect transistor, thereby this interdigitated field-effect transistor has the drain region of the connection of a plurality of elongations, the sinuous channel region and the interdigitated field-effect transistor of switch between ON and OFF state of the grid on channel region of the elongation that separates from the source region with the source region that is connected of a plurality of elongations of drain region interdigitate, with the drain region.

9. switch according to claim 8, wherein at least one switch topology comprises the field-effect transistor of a plurality of series connection, and described at least one switch topology of control signal control of described at least one switch topology is selectively to connect or to isolate each transmitter or receiver port from antenna port.

10. switch according to claim 8, wherein said chip has a zone, and the transmitter port switch topology occupies one than the big chip area of receiver port switch topology.

11. switch according to claim 8, also comprise at least one multiple-pole switch topology, the first order of this multiple-pole switch topology selectively connects or the isolated antennas port from this multiple-pole switch topology, and the last level of this multiple-pole switch topology selectively connects or isolate a plurality of other ports from this multiple-pole switch topology.

12. switch according to claim 11, wherein said other ports are receiver ports.

13. switch according to claim 11, wherein for each receiver port, described last level comprises signal path FET, and it has can be controlled to the current path that the receiver port is connected to intermediate node, can operate the described first order so that intermediate node is connected to antenna port.

14. switch according to claim 13, wherein each described signal path FET has grid, the shunting FET of the control signal of being applied in, described shunting FET has the drain electrode of being coupled to described grid, is coupled to the one source pole on ground, and can be operated to strengthen when signal path FET is in the OFF state isolation of receiver port centering intermediate node.

15. one kind switches to the method for receiver/transmitter antenna with one of a plurality of receivers and a plurality of transmitters, the method comprising the steps of:

Each transmitter is connected to corresponding of a plurality of transmitter port of being formed on the single integrated circuit chip;

Each receiver is connected to corresponding of a plurality of receiver ports of being formed on the chip;

Control each with transmitter and receiver port in corresponding related a plurality of switch topologies selected one so that of the corresponding selection of transmitter and receiver port is connected to the antenna port that is formed on the chip; With

Control other switch topologies with transmitter and receiver port and antenna port isolation with other,

Wherein said method also comprises step:

At least some switch topologies are arranged in the level of cascade, and the level of described cascade comprises the first order that is coupled to antenna port and is coupled to the last level of a plurality of transmitters or receiver port;

By the conducting first order one of the selection of last described transmitter or receiver port is connected to antenna port, and a related switch of conducting and the described selection of last described transmitter and receiver, wherein last described switch is the part of last level; With

Turn-off other switches and remaining switch topology in the level in the end.

16. method according to claim 15, wherein selected one the described step of control switch topology comprises the step that a plurality of tandem tap transistors is switched to the ON state.

17. method according to claim 15 also comprises step:

At least one signal path transistor is switched to the ON state to transmit signal by the transistorized current path of signal path from one of the receiver of association or transmitter port;

The shunting transistor that will have the drain electrode that is connected with the transistorized grid of signal path turn-offs so that described grid is isolated with ground;

For at least one non-selected receiver or transmitter port, the signal path transistor of association is switched to the OFF state; With

For described at least one non-selected receiver or transmitter port, shunting transistor conducting with association, this related shunting transistor has the drain electrode that connects with the transistorized grid of described related signal path, thereby last described gate coupled is to ground and strengthen the isolation of non-selected receiver or transmitter port.