CN100361111C - Bus integrating system - Google Patents
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- CN100361111C CN100361111C CNB2004100462416A CN200410046241A CN100361111C CN 100361111 C CN100361111 C CN 100361111C CN B2004100462416 A CNB2004100462416 A CN B2004100462416A CN 200410046241 A CN200410046241 A CN 200410046241A CN 100361111 C CN100361111 C CN 100361111C
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Abstract
The present invention relates to a bus integration system applied in a data processing system, which comprises a bus control module and a bus integration processor, wherein the bus control module is lapped with at least one peripheral device so as to drive a device corresponding to the peripheral device to access data according to the data access information transmitted by the peripheral device; the bus integration processor comprises at least one first bus data access information pin and at least one second bus data access information pin so that the bus control module controls a peripheral device of a first data transmission specification bus and a second data transmission specification bus and the other peripheral device with the same or different data transmission specifications as the peripheral device to access the data by the single bus. The bus integration system can control the data transmission of the buses of different data transmission specifications by the single bus and the integrated bus control system so as to achieve the purposes of reducing the hardware occupation space and the manufacture cost.
Description
Technical field
The invention relates to a kind of bus integration system, particularly about a kind of bus integration system that the bus of different pieces of information transmission standard is integrated.
Background technology
Bus (BUS) is that an establishment stands in many computer components and interelement electronic circuit (electrical circuits), is used for transmitting data at the interelement of computer system.In fact bus can be understood as is a sharable highway of user (shared highway), the various different pieces that connecting computer system are as central processing unit, internal memory, disc driver, printer, image system or input/output port etc.Bus not only electrically connects different elements and device, and has the function of transmission information.And bus is to be managed by central processing unit., the bus data volume that can transmit simultaneously is that the quantity by mobile scale-of-two electronic information number decides.A PC the inside four following buses are arranged all generally: processor bus (processorbus), rambus (memory bus), address bus (address bus) and input/output bus (I/O bus).
With above-mentioned input/output bus is example, it is also referred to as expansion bus (expansion bus), can allow the user of personal computer adopt standardized connector, install additional voluntarily such as peripheral devices such as display card, printer, CD-ROM drives, so input/output bus is to use the highest bus of frequency.Bus structure commonly used at present can be divided into following five kinds: industrial standard architecture bus (ISA-Industry Standard Architecture bus), Micro Channel Architecture bus (MCA-MicroChannel Architecture bus), EISA bus (EISA-ExtendedIndustry Standard Architecture bus), VESA's local bus (VESAlocal-Video Electronics Standard Association Local BUS), interconnected local bus of external unit (PCI local-Peripheral Component Interconnect Local BUS) and AGP bus (AGP-Accelerated Graphics Port) etc.
Said external devices interconnect local bus (PCI Local BUS) is the specification by INTEL Corp. exploitation, the definition of this specification allow the compatible expansion boards of a plurality of and peripheral element interconnection (PCI) to be installed on the local bus system in the computing machine.Pci controller and central processing unit can once exchange 32 or 64 s' data according to the situation decision of carrying out, and the compatible expansion board of a plurality of PCI that allows to have intelligence, can be by the technology of using bus master (bus mastering) and central processing unit execution work simultaneously, and the PCI specification allows to have the multi-tasking that surpasses more than one PCI compatible apparatus simultaneously on bus, so also can be referred to as shared bus (share bus).
Except above-mentioned at the designed bus of personal computer, being mainly in addition provides notebook computer, laptop computer, palmtop computer and other portable computer and the design of intelligent electronic device, be used to install the common standard of PC card (pC Card) Card BUS slot, it is by PCMCIA (personal computer memory card international association) (Personal Computer MemoryCard International Association; PCMCIA) interfacing equipment of being formulated connects standard.PC card wherein is to be portable device, as size as the credit card, is designed to insert use in the Card BUS slot (PCMCIA Slot) of PCMCIA specification.Wherein the pcmcia bus standard of 32 PC card is called card bus (Card BUS).Be different from above-mentioned PCILocal BUS, can provide permission on bus, to have the multi-tasking that surpasses more than one PCI compatible apparatus simultaneously with sharing mode, single main bridge (Host Bridge) only can provide the device of single Card BUS to be connected with it, so also can be referred to as point-to-point bus (pointto point bus).
Brought forward is described, though PCI Local BUS and Card BUS on unified bus, whether can provide surpass aspect the more than one electronic installation different, yet both are very identical on system's operation and establishing method.But, both are still respectively and are linked up by different controllers and central processing unit so far, if the bus structure of these two kinds of different sizes can be integrated, just can reduce shared space of hardware and manufacturing cost, are problems suddenly to be solved at present how therefore with both integration.
Summary of the invention
For overcoming the shortcoming of above-mentioned prior art, fundamental purpose of the present invention is to provide a kind of bus integration system, so as to the data transmission standard difference is provided but the similar bus structure of host-host protocol are carried out the control of peripheral device data access by the bus control module of unified bus and integration.
Another object of the present invention is to provide a kind of bus integration system, the original bus structure that must carry out data transmission in point-to-point mode are provided, share the control of formula peripheral device data access by the bus control module of unified bus and integration.
For reaching above-mentioned and other purpose, bus integration system of the present invention comprises: bus control module, overlap joint be at least one peripheral device, the document access information that sends according to this peripheral device, driving is carried out data access to device that should the peripheral device document access information; And bus integration processor, it comprise at least one first bus data access information pin be connected with first peripheral device in this peripheral device and at least one second bus data access information pin to be connected with second peripheral device in this peripheral device, this first peripheral device is compatible with the shared formula structure of first data transmission standard, and second peripheral device is compatible with the point-to-point formula structure of second data transmission standard, this bus integration processor is connected with this first peripheral device and second peripheral device by single shared bus, and this first peripheral device and second peripheral device connect by this shared bus, and this bus integration processor is controlled the bus processor of this first peripheral device and second peripheral device respectively to carry out the access of data by activating this first and second bus data access signal pin under the different time under different cycles by this shared bus.
With existing bus control system texture ratio, bus integration system of the present invention is except providing the bus structure of different pieces of information transmission standard, bus control module by single integration carries out outside the control of peripheral device data access, the original bus structure that must carry out data transmission in point-to-point mode can also be provided, share the control of formula peripheral device data access by the bus control module of single integration, reach and reduce the shared space of hardware and the purpose of manufacturing cost.
Description of drawings
Fig. 1 is the system architecture block schematic diagram, shows the system architecture that bus of the present invention is integrated;
Fig. 2 is the waveform synoptic diagram of bus integration system when data transmission.
Embodiment
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention.
In following examples, bus integration system of the present invention is applied among the personal computer system, and this personal computer system has an interconnected local bus of external unit (PCI LocalBUS) system at least, and a card bus (Card BUS) system.Wherein, the expansion board that meets this pci data transmission standard by such as peripheral element interconnection slot (PCI Slot), is installed, for example network card and/or display card etc. for the user by this PCI Local BUS system; This Card BUS system then for the Card BUS slot (PCMCIA Slot) of user by the PCMCIA specification, the PC card (PC Card) that meets this PCMCIA specification is installed, and in the present embodiment, this PC card is 32 a specification.Because the bus structure of this PCI and this Card BUS are prior aries, so, below only describe at the part relevant with bus integration system of the present invention.
Fig. 1 is the system architecture synoptic diagram of bus integration system 100 of the present invention, and this bus integration system comprises: bus control module 110 and pci bus integration processor 120.
This bus control module 110, overlap respectively to CPU (central processing unit) 130, storage unit 140 and pci bus 150, according to the document access information that CPU (central processing unit) 130 is sent, drive this CPU (central processing unit) 130, this storage unit 140 or peripheral device and carry out data access each other.In the present embodiment, this bus control module 110 is except that comprising that this is used to handle the pci bus integration processor 120 of pci bus, the CPU (central processing unit) bus processor (figure is mark) that also comprises processing and 130 buses of this CPU (central processing unit), and the storage unit bus processor of processing and 140 buses of this storage unit (figure marks).
This pci bus integration processor 120, build and put in this bus control module 110, at least comprise PCI BUS data transmission start signal pin (frame) 111 and at least one CardBUS data transmission start signal pin (cframe) 112, the peripheral device of controlling PCI and/or Card BUS for this bus control module carries out data access.Wherein this PCI BUS data transmission start signal pin (frame) 111 is activated, and is to send data access request signal or other device sends data access request signal to this PCI device from the PCI device; This Card BUS data transmission start signal pin (cframe) 112 is activated, and is to send data access request signal or other device sends data access request signal to this Card BUS device from Card BUS device.By activating different start signal pins, carry out data access between corresponding peripheral device.
Wherein, this CPU (central processing unit) 130 is used to provide this personal computer system to extract, decipher and the function of execution command, and can as above give an account of in the CPU (central processing unit) bus processor of 110 of this bus control modules etc. by data transfer path, transmit and receive data etc. from other Energy Resources Service.
This storage unit 140 provides this personal computer system's other module or random access memory (the Random Access Memory of unit quick access desired data; RAM), dynamic RAM (Dynamic Random Access Memory for example; DRAM), synchronous DRAM (Synchronous Dynamic Random Access Memory; SDRAM) or double-speed Synchronous Dynamic Random Access Memory (Double Data Rate Synchronous DynamicRandom Access Memory; DDRSDRAM) etc.And it also can be as this CPU (central processing unit) 130, by and the storage unit bus processor of 110 of this bus control modules etc. transmit and receive data from other Energy Resources Service.
This pci bus 150 is PCI Local BUS structure in the present embodiment, and overlaps respectively to PCI slot 151 and PCI slot152, and the Card BUS slot 153 of PCMCIA specification; Wherein, this PCI slot 151 and 152 is respectively applied for the network card 154 and display card 155 that provides the user to install to meet this pci data transmission standard; 153 of the Card BUS slots of this PCMCIA specification are used to provide the user to install and meet the wireless network card 156 of this PCMCIA specification.What need special instruction is, in the present embodiment for ease of outstanding technical characterictic of the present invention, this pci bus 150 is meant the data line except that this PCI BUS data transmission start signal pin (frame) 111 and 112 two pins of this Card BUS data transmission start signal pin (cframe), comprises that with existing the PCI BUS of all data lines is different.
Brought forward is described, 150 of this bus control module 110 and this pci buss are provided with following signal output and input pins at least: this PCI BUS data transmission start signal pin (frame) 111 is activated, be to send data access request signal or other device sends data access request signal to this PCI device at the PCI device, and this Card BUS data transmission start signal pin (cframe) 112 is activated, and is to send data access request signal or other device sends data access request signal to this Card BUS device at Card BUS device.In addition, 150 of this bus control module 110 and this pci buss also comprise following signal output and input pins:
(1) pulse signal pin (CLK) supplies the respectively pin of this peripheral equipment receiver sequential (Timing) signal input.
(2) the ready pin of starter (Initiator Ready; IRDY), send for this main device and inform that destination apparatus prepared to receive the signal of transmission data.
(3) the ready pin of target (Target Ready; TRDY), send for this destination apparatus (Target) and inform that this main device prepared to transmit the signal of data.
(4) device is selected pin (Device Select; DEVSEL), supply this destination apparatus to send and inform the signal of having been selected by main device.
(5) stop pin (Stop), send the signal that stops data transmission for this destination apparatus.
(6) address date pin (Address and Data; AD), the signal of transport address and data.
(7) bus line command/byte activates pin (Bus Command and Byte Enable; C/BE), send the signal of transfer bus control command for this main device.
Brought forward is described, what need special instruction is, in the present embodiment, except that this Card BUS data transmission start signal pin (cframe) 112, respectively this pin all with the pin function compatibility of existing PCI Local BUS, and only show and the relevant pin of bus integration system of the present invention that herein remaining pin all is compatible with the specification of this PCI Local BUS, so no longer illustrate at this.
The waveform synoptic diagram that Fig. 2 is this bus control module 110 when carrying out data transmission between peripheral device.
Brought forward is described, in the present embodiment, when this wireless network card 156 will be from these storage unit 140 reading of data, this wireless network card 156 is set at main device, 120 of this pci bus integration processor are made as destination apparatus, make this pci bus integration processor 120 can be according to the reading of data request of this wireless network card 156, by between the storage unit bus processor of 140 of this storage unit to these storage unit 140 reading of data.In addition, send the bus data access information by this wireless network card 156, this bus data access information is meant that Card BUS data transmission start signal pin (cframe) 112 sends low-potential signal in this embodiment, be used to represent that this wireless network card 156 that meets the card bus data transmission standard is carrying out data read, and transmit the signal to this pci bus integration processor 120.
Secondly, make this wireless network card 156 send the ready signal of starter, be used to represent that this wireless network card 156 carried out the preparation of data read to this pci bus integration processor 120.
Then, make these pci bus integration processor 120 issue devices select signal, be used to represent that this pci bus integration processor 120 is selected, afterwards, obtain the data of this storage unit 140 by this storage unit bus processor, make this pci bus integration processor 120 send the target ready signal, be used to represent that this pci bus integration processor 120 carried out the preparation that is read data.
Simultaneously, this wireless network card 156 activates the command context that sets according to this bus line command/byte, carries out reading of data by the pci bus integration processor 120 of this bus control module 110.
Brought forward is described, if another network card 154 is arranged will be from these storage unit 140 reading of data the time, this network card 154 is set to main device, this pci bus integration processor 120 then is made as destination apparatus, so as to making this pci bus integration processor 120 can be according to the reading of data request of this network card 154, by between the storage unit bus processor of 140 of this storage unit to these storage unit 140 reading of data.Send another bus data access information by this network card 154, be meant that at this another bus data access information of this embodiment PCI BUS data transmission start signal pin (frame) 111 sends low-potential signal, be used to represent that this network card 154 of accord with PCI data transmission standard will carry out data read, and transmit the signal to this pci bus integration processor 120.
Secondly, make this network card 154 send the ready signal of starter, be used to represent that this network card 154 carried out the preparation of data read to this pci bus integration processor 120.
Then, make these pci bus integration processor 120 issue devices select signal to be used to represent that this pci bus integration processor 120 is selected, obtain the data of this storage unit 140 afterwards by this storage unit bus processor, make this pci bus integration processor 120 send the target ready signal, be used to represent that this pci bus integration processor 120 carried out by the preparation of data read.
Simultaneously, this network card 154 activates the command context that sets according to this bus line command/byte, carries out reading of data by the pci bus integration processor 120 of this bus control module 110.
Brought forward is described, the pci bus integration processor 120 of this bus control module 110 is by receiving the data access request that peripheral device sent of different bus data transmission standard, so as to judging this peripheral device data transmission standard, and carry out data access for this peripheral device according to this perimeter data transmission standard.
In addition, the transmission status of these pci bus integration processor 120 these pci buss of monitoring in addition carries out data transmission for peripheral device meeting, so as to the situation of bus contention takes place between the bus of avoiding the different pieces of information transmission under this bus specification.
Bus integration system of the present invention only needs to increase Card BUS data transmission start signal pin (cframe) on this pci bus integration processor 120, the peripheral device that can connect the card bus specification that is same as this CardBUS data transmission start signal pin (cframe), in other words, a plurality of card bus specification peripheral devices are by this pci bus integration processor 120, only need to carry out the transmission of data by bus interface, reach as the peripheral device bus, allow on bus, to exist simultaneously the multi-tasking that surpasses more than one electronic signal.
In sum, bus integration system of the present invention removes the bus structure that the different pieces of information transmission standard can be provided, bus control module by unified bus and integration carries out outside the control of peripheral device data access, can also provide original must be with point-to-point bus structure of carrying out data transmission, share the control of formula peripheral device data access by the bus control module of unified bus and integration, reach and reduce the shared space of hardware and the purpose of manufacturing cost.
In addition, when bus integration system of the present invention is applied in the peripheral device of Card BUS specification, the quantity of this Card BUS data transmission start signal pin (cframe) can increase and decrease according to the quantity of this CardBUS peripheral device, and then the quantity of this Card BUS peripheral device can increase and decrease according to user's needs.On the other hand, principle according to above-mentioned bus integration system, this bus integration system also can be applicable on the personal computer system who only has a plurality of Card BUS peripheral devices, a plurality of Card BUS data transmission start signal pins (cframe) by corresponding these Card BUS peripheral device quantity provide these Card BUS peripheral devices to carry out the access work of data at other peripheral device.
In addition, bus integration system of the present invention also can be incorporated in the integrated circuit (IC) chip (IC Chip), is used to provide the various electronic installations solution that efficient bus is integrated.
Claims (17)
1. bus integration system, be applied in the data handling system, the peripheral device with the interconnective different pieces of information transmission standard of this data handling system is provided, carry out data transmission by unified bus integration processing mechanism, it is characterized in that this bus integration system comprises:
Bus control module, overlap to affiliated peripheral device at least one bus processor, be used for the document access information that sends according to this peripheral device, driving is to bus processor that should the peripheral device document access information, carry out data access, and then reach the exchanges data between each bus processor; And
The bus integration processor, it comprise at least one first bus data access information pin be connected with first peripheral device in this peripheral device and at least one second bus data access information pin to be connected with second peripheral device in this peripheral device, this first peripheral device is compatible with the shared formula structure of first data transmission standard, and second peripheral device is compatible with the point-to-point formula structure of second data transmission standard, this bus integration processor is connected with this first peripheral device and second peripheral device by single shared bus, and this first peripheral device and second peripheral device connect by this shared bus, and this bus integration processor is controlled the bus processor of this first peripheral device and second peripheral device respectively to carry out the access of data by activating this first and second bus data access signal pin under the different time under different cycles by this shared bus.
2. the system as claimed in claim 1 is characterized in that, this first data transmission standard is the interconnected local bus of external unit, and this first bus data access information pin is the data transmission start signal pin of the interconnected local bus specification of this external unit.
3. the system as claimed in claim 1 is characterized in that, this first data transmission standard is a card bus, and this first bus data access information pin is the data transmission start signal pin of this card bus specification.
4. the system as claimed in claim 1 is characterized in that, this second data transmission standard is a card bus; This second bus data access information pin is the data transmission start signal pin of this card bus specification.
5. the system as claimed in claim 1 is characterized in that, this shared bus can be a kind of in the interconnected local bus of external unit of definition complete function in the specification or the interconnected local bus of external unit of supporting partial function.
6. the system as claimed in claim 1 is characterized in that, this shared bus can be a kind of in the card bus of the card bus of the complete function that defines in the specification or support partial function.
7. the system as claimed in claim 1 is characterized in that, this first data transmission standard can be a bus specification of sharing the formula structure.
8. the system as claimed in claim 1 is characterized in that, this first data transmission standard can be the bus specification of point-to-point formula structure.
9. the system as claimed in claim 1 is characterized in that, this bus integration processor can be to support a kind of in the bus processor of the first data transmission standard repertoire or partial function.
10. the system as claimed in claim 1 is characterized in that, this bus integration processor can be to support a kind of in the bus processor of the second data transmission standard repertoire or partial function.
11. the system as claimed in claim 1, it is characterized in that, when this bus integration processor comprises a plurality of this second bus data access information pin, a peripheral device that respectively is compatible with second data transmission standard in this second bus data access information pin and this peripheral device is connected, by the corresponding second bus data access information pin, send data access request signal or other device sends data access request signal to this peripheral device for each peripheral device.
12. the system as claimed in claim 1 is characterized in that, this system can be applicable in the electronic product.
13. system as claimed in claim 12, it is characterized in that this electronic product can be a kind of in personal computer, notebook computer, palmtop computer, personal digital assistant, Tablet PC, server system, workstation, digital household appliances, mobile device, communication facilities, multimedia equipment, medical equipment, the automation control appliance.
14. the system as claimed in claim 1 is characterized in that, this bus control module is incorporated in the integrated circuit (IC) chip.
15. the system as claimed in claim 1 is characterized in that, this bus integration processor is incorporated in the integrated circuit (IC) chip.
16. the system as claimed in claim 1 is characterized in that, this bus integration processor is incorporated in this bus control module.
17. the system as claimed in claim 1 is characterized in that, this bus control module and this bus integration processor are integrated circuit (IC) chip independently.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2004100462416A CN100361111C (en) | 2004-06-04 | 2004-06-04 | Bus integrating system |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2004100462416A CN100361111C (en) | 2004-06-04 | 2004-06-04 | Bus integrating system |
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| CN1707458A CN1707458A (en) | 2005-12-14 |
| CN100361111C true CN100361111C (en) | 2008-01-09 |
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| CNB2004100462416A Active CN100361111C (en) | 2004-06-04 | 2004-06-04 | Bus integrating system |
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| CN111708313B (en) * | 2020-04-28 | 2021-11-09 | 北京骥远自动化技术有限公司 | PLC system capable of realizing efficient transmission and data transmission method thereof |
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| CN1326573A (en) * | 1998-03-26 | 2001-12-12 | 格姆普拉斯公司 | Versatile interface smart card |
| CN1104688C (en) * | 1994-06-28 | 2003-04-02 | 英特尔公司 | PCI to ISA interrupt protocol converter and selection mechanism |
| US20030081391A1 (en) * | 2001-10-30 | 2003-05-01 | Mowery Keith R. | Simplifying integrated circuits with a common communications bus |
| US20030229748A1 (en) * | 2002-06-06 | 2003-12-11 | James Brewer | Method and system for supporting multiple bus protocols on a set of wirelines |
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2004
- 2004-06-04 CN CNB2004100462416A patent/CN100361111C/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1104688C (en) * | 1994-06-28 | 2003-04-02 | 英特尔公司 | PCI to ISA interrupt protocol converter and selection mechanism |
| CN1326573A (en) * | 1998-03-26 | 2001-12-12 | 格姆普拉斯公司 | Versatile interface smart card |
| US20030081391A1 (en) * | 2001-10-30 | 2003-05-01 | Mowery Keith R. | Simplifying integrated circuits with a common communications bus |
| US20030229748A1 (en) * | 2002-06-06 | 2003-12-11 | James Brewer | Method and system for supporting multiple bus protocols on a set of wirelines |
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