CN100346470C - Nonvolatile internal memory and its manufacturing method - Google Patents
Nonvolatile internal memory and its manufacturing method Download PDFInfo
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- CN100346470C CN100346470C CNB2004101012055A CN200410101205A CN100346470C CN 100346470 C CN100346470 C CN 100346470C CN B2004101012055 A CNB2004101012055 A CN B2004101012055A CN 200410101205 A CN200410101205 A CN 200410101205A CN 100346470 C CN100346470 C CN 100346470C
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Abstract
The present invention relates to a nonvolatile memory, which comprises a substrate, a dielectric layer, a conductor layer, an isolating layer, an embedded type bit line, a tunneling dielectric layer, a charge trapping layer, a blocking dielectric layer and a word line, wherein the conductor layer is arranged on the dielectric layer which is arranged on the substrate, and the isolating layer which is arranged on the substrate is adjacent to the conductor layer and the dielectric layer. In addition, the embedded type bit line which is arranged in the substrate is positioned below the isolating layer; the charge trapping layer is arranged on the tunneling dielectric layer which is arranged on the substrate and the side walls of the conductor layer and the isolating layer, and the blocking dielectric layer is arranged on the charge trapping layer. In addition, the word line which is arranged on the substrate is staggered with the embedded type bit line.
Description
Technical field
The present invention relates to a kind of memory cell, and particularly relevant for a kind of non-volatile memory cells and manufacture method thereof.
Background technology
The advantage that the data that non-volatile memory cells owing to have deposits in also can not disappear after outage, therefore must possess this type of memory cell in many electric equipment products, keeping the electric equipment products normal running in when start, and become extensively a kind of memory unit package of employing of personal computer and electronic equipment institute.
Known a kind of non-volatile memory cells is to be provided with silica-silicon-nitride and silicon oxide (oxide-nitride-oxide between grid and substrate, abbreviation ONO layer) structure that lamination constituted, silicon nitride layer wherein is promptly as the rete that electric charge is absorbed in, be also referred to as electric charge capture layer (charge trapping layer), and utilize this kind material to be called nitride ROM (nitride readonly memory) as the memory cell of electric charge capture layer.
Fig. 1 illustrate is the generalized section according to known a kind of nitride ROM.Please refer to Fig. 1, nitride ROM comprises substrate 100, source electrode 102, drain electrode 104, following silicon oxide layer 106, silicon nitride layer 108, goes up silica 110 and grid 112.Wherein, following silicon oxide layer 106, the silicon nitride layer 108 that is disposed in the substrate 100 is silica-silicon-nitride and silicon oxide lamination, promptly so-called ONO layer 114 with last silica 110.In addition, the big dotted line scope shown in the figure is a memory cell 116, and is respectively first 118 and second 120 shown in the less dotted line scope.For memory cell 116, a memory cell can respectively store a position (bit) (first 118 and second 120) near silicon nitride layer 108 both sides in the ONO layer 114 of drain electrode 104 and source electrode 102 basically, and forms the non-volatile memory cells of two (2bits/cell) storages of a kind of single memory cell.
Yet known two bit non-volatile memory cell are when carrying out sequencing, and two positions of same memory cell can interact each other and have problems.Briefly, if stored one (second 120) near drain electrode 104 parts, then can when carrying out reverse reading (reverse read), produce second and answer (2nd-bit effect), make originally to have the situation that electric current descends for the part of high electric current.That is to say that when memory cell read, the position that has originally existed can impact memory cell, and potential barrier (barrier) is improved, and the start voltage (threshold voltage is called for short Vt) that causes reading improves.In addition, above-mentioned two positions because of single memory cell influence the problem of deriving each other can cause difficulty on the assembly operation, even can cause the reliability (reliability) of assembly to reduce.
And known two bit non-volatile memory cell are when carrying out sequencing, and the hot electron that injects the electronics immersed layer can form electron distribution curve according to injecting energy.Yet the problem of second above-mentioned effect can make charge-distribution curve become wide and links together.Therefore, memory cell can't coincide together with electron distribution curve at the formed distribution curve of electric charge capture layer injected hole when removing, and cause the long removal time of needs, and or even the problem that can't remove fully.
Summary of the invention
In view of this, purpose of the present invention is exactly that a kind of manufacture method of non-volatile memory cells is being provided, can avoid two because of the single memory cell in the non-volatile memory cells to influence the problem that produces each other, to promote the reliability of memory unit package.
Another object of the present invention provides a kind of non-volatile memory cells, can store two bit data in single memory cell, and can not produce second effect with and the problem of deriving.
The present invention proposes a kind of manufacture method of non-volatile memory cells, and the method is that a substrate is provided earlier, and in substrate, form dielectric layer in regular turn, conductor layer and mask layer.Then, patterned mask layer, conductor layer and dielectric layer expose most first openings of substrate with formation.Then, in the substrate of first open bottom, form embedded type bit line, in substrate, form separator again in first opening.Afterwards, remove the part separator, and be mask, to form most second openings with remaining separator.Then, remove mask layer and the separator that covers this mask layer, and form tunneling dielectric layer, electric charge capture layer in regular turn and stop dielectric layer in substrate, conformal covering second opening, separator and conductor layer are inserted material layer again in second opening.Then, removal is not by part tunneling dielectric layer, the electric charge capture layer of layer of material covers and stop dielectric layer, and removes material layer, forms word line again in substrate.
According to the manufacture method of the described non-volatile memory cells of preferred embodiment of the present invention, the formation method of wherein above-mentioned separator comprises carries out a high density plasma CVD technology.
According to the manufacture method of the described non-volatile memory cells of preferred embodiment of the present invention, the material of wherein above-mentioned separator comprises silica, silicon nitride or silicon oxynitride.
According to the manufacture method of the described non-volatile memory cells of preferred embodiment of the present invention, wherein remove the part separator after, also be included on the mask layer and keep most angles type separators.Above-mentioned angle type separator bottom width is less than the width of the mask layer that is positioned at its below.
According to the manufacture method of the described non-volatile memory cells of preferred embodiment of the present invention, the method for wherein above-mentioned formation second opening comprises carries out an etch process.
According to the manufacture method of the described non-volatile memory cells of preferred embodiment of the present invention, the material of wherein above-mentioned mask layer comprises silicon nitride.
According to the manufacture method of the described non-volatile memory cells of preferred embodiment of the present invention, the material of wherein above-mentioned dielectric layer comprises silica.
According to the manufacture method of the described non-volatile memory cells of preferred embodiment of the present invention, the formation method of wherein above-mentioned conductor layer and mask layer comprises chemical vapour deposition technique.
According to the manufacture method of the described non-volatile memory cells of preferred embodiment of the present invention, the method that wherein forms embedded type bit line in the substrate of first open bottom comprises carries out an ion implantation step.
According to the manufacture method of the described non-volatile memory cells of preferred embodiment of the present invention, wherein above-mentioned removal mask layer comprises that with the method for the separator that covers this mask layer carrying out an etch process or peels off (lift off) technology.
According to the manufacture method of the described non-volatile memory cells of preferred embodiment of the present invention, the method for wherein inserting material layer in second opening comprises utilizes a method of spin coating.
According to the manufacture method of the described non-volatile memory cells of preferred embodiment of the present invention, the material of wherein above-mentioned material layer comprises macromolecular material or photo anti-corrosion agent material.
According to the manufacture method of the described non-volatile memory cells of preferred embodiment of the present invention, wherein remove not and to be comprised by part tunneling dielectric layer, the electric charge capture layer of layer of material covers and the method that stops dielectric layer and to carry out an etch process.
According to the manufacture method of the described non-volatile memory cells of preferred embodiment of the present invention, the method for wherein above-mentioned removal material layer comprises carries out an etch process.
According to the manufacture method of the described non-volatile memory cells of preferred embodiment of the present invention, wherein above-mentioned word line comprises doped polysilicon layer.
According to the manufacture method of the described non-volatile memory cells of preferred embodiment of the present invention, the wherein above-mentioned method that forms word line in substrate comprises carries out a chemical vapor deposition method.
The present invention proposes a kind of non-volatile memory cells in addition, comprises substrate, dielectric layer, conductor layer, separator, embedded type bit line, tunneling dielectric layer, electric charge capture layer, stops dielectric layer and word line.Wherein, dielectric layer is disposed in the substrate, and conductor layer is disposed on the dielectric layer.In addition, separator is disposed in the substrate, and separator and conductor layer and dielectric layer are adjacent, and embedded type bit line is arranged in substrate, and is disposed at the separator below.Wherein, tunneling dielectric layer is disposed in the substrate and the sidewall of conductor layer and separator, and electric charge capture layer is disposed on the tunneling dielectric layer, stops that dielectric layer is disposed on the electric charge capture layer.In addition, word line is disposed in the substrate, and word line and embedded type bit line are interlaced with each other.
From the above, the present invention forms earlier dielectric layer in substrate, and this dielectric layer can separate electric charge capture layer, just on the memory cell everybody can be separated from each other, so can avoid producing two problems that the position influences each other of single memory cell, the problem that does not just have so-called second effect produces.In addition, the present invention also is not easy to produce the situation of voltage or current anomaly when memory cell writes and removes, and causes component failures, and then has influence on the reliability of assembly.
And, the bottom width of the angle type separator that forms in the technology of the present invention is less than the bottom width of the rete of below, and can utilize this angle type separator as etching mask, to remove unwanted rete in the technology, and it can be considered a kind of self-registered technology (self-aligned process), above-mentioned self-registered technology need not form mask layer in addition again with the rete that covers desire and remove or carry out other technology, can obtain accurate patterns.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 is the generalized section that illustrates to known non-volatile memory cells.
Fig. 2 A to Fig. 2 I illustrate is the flow process profile according to the manufacture method of the non-volatile memory cells of preferred embodiment of the present invention.
Symbol description
100,200: substrate 102: source electrode
104: drain electrode 106: following silicon oxide layer
108: silicon nitride layer 110: go up silica
112: grid 114: silica-silicon-nitride and silicon oxide layer (ONO layer)
116,222: memory cell 118,224: the first
120,226: the second 202: dielectric layer
204: conductor layer 206: mask layer
208,214: opening 210: embedded type bit line
212: separator 212a: angle type separator
215: tunneling dielectric layer 216: electric charge capture layer
217: stop dielectric layer 218: material layer
220: word line
Embodiment
Fig. 2 A to Fig. 2 I illustrate is the flow process profile according to the manufacture method of the non-volatile memory cells of preferred embodiment of the present invention.
At first please refer to Fig. 2 A, a substrate 200 is provided, this substrate 200 for example is a silicon base.Then, form dielectric layer 202 in substrate 200, wherein, the material of dielectric layer 202 for example is a silica, and its formation method for example is thermal oxidation method (thermal oxidation).And this dielectric layer 202 is as the lock oxide layer.
Then, on dielectric layer 202, form conductor layer 204.Afterwards, form mask layer 206 on conductor layer 204, wherein the material of mask layer 206 for example is a silicon nitride, the formation method for example be chemical vapour deposition technique (chemical vapor deposition, CVD).
Then, patterned mask layer 206, conductor layer 204 and dielectric layer 202 expose most openings 208 of substrate 200 with formation.Wherein, the method that above-mentioned formation exposes most openings 208 of substrate 200 for example is prior to after covering a photoresist layer (not illustrating) in the substrate 200, to this photoresist layer expose, developing process, to form a patterning photoresist layer.Then, be mask with this patterning photoresist layer, carry out an etch process, to remove part mask layer 206, conductor layer 204 and dielectric layer 202, till exposing substrate 200, expose most openings 208 of substrate 200 with formation, remove patterning photoresist layer afterwards again.
Then, please refer to Fig. 2 B, in the substrate 200 of each opening 208 bottom, form embedded type bit line 210.Wherein, the above-mentioned method that forms embedded type bit line 210 in the substrate 200 of each opening 208 bottom for example is to carry out an ion implantation step.
Afterwards, please refer to Fig. 2 C, in substrate 200, form separator 212 in opening 208.Wherein, the material of separator 212 for example is silica, silicon nitride or silicon oxynitride, and the formation method for example is to carry out a high density plasma enhanced chemical vapor deposition technology (HDP-CVD).
Then, please refer to Fig. 2 D, remove part separator 212, and on mask layer 206, form most angle type separator 212a.Wherein, behind the above-mentioned removal part separator 212, the surface of the separator 212 in the opening 208 is the surfaces that are lower than mask layer 206, and exposes the top margin of mask layer 206.And the width of angle type separator 212a bottom is less than the width of the mask layer 206 that is positioned at its below.
Continue it, please refer to Fig. 2 E, remove not by the conductor layer 204 and dielectric layer 202 of the mask layer 206 of angle type separator 212a covering and below thereof, to form most openings 214.Wherein, the formation method of above-mentioned opening 214 for example is to be that mask carries out an etch process with angle type separator 212a, and the conductor layer 204 of removing not the mask layer 206 that covered by angle type separator 212a and below thereof and dielectric layer 202 are to form.
Particularly, in the present invention, because the width of above-mentioned angle type separator 212a bottom is less than the width of the mask layer 206 that is positioned at its below.Therefore, in above-mentioned step, can utilize angle type separator 212a to be etching mask, to remove not by part dielectric layer, conductor layer and the mask layer of separator 212 with angle type separator 212a covering, and the method can be considered an automatic Alignment Process, and it can utilize the method to obtain accurate patterns in technology.In addition, above-mentioned automatic Alignment Process except can be applicable to present embodiment, also applicable in other suitable technology, the technology that for example can be applicable to make PACAND.
Then, please refer to Fig. 2 F, remove mask layer 206 and angle type separator 212a.Wherein, removal mask layer 206 for example is to carry out etch process or peel off (lift off) technology with the method for angle type separator 212a.
Afterwards, please refer to Fig. 2 G, in substrate 200, form tunneling dielectric layer 215, electric charge capture layer 216 in regular turn, stop dielectric layer 217.Then, in opening 214, insert material layer 218 again.Wherein, above-mentioned tunneling dielectric layer 215 with stop that the material of dielectric layer 217 for example is a silica, the material of electric charge capture layer 216 retainings for example is a silicon nitride.Certainly, the material of electric charge capture layer 216 is not limited to silicon nitride, and it also can be that any electric charge that can make is absorbed in material wherein.In addition, the material of above-mentioned material layer 218 for example is macromolecular material or photo anti-corrosion agent material, and its formation method for example is to utilize method of spin coating.
Then, please refer to Fig. 2 H, utilize an etch process, remove part tunneling dielectric layer 215, the electric charge capture layer 216 do not covered, stop dielectric layer 217, then remove material layer 218 again by material layer 218.In addition, material layer 218 can for example be a conductor layer also, and can utilize etch-back (Etch Back) mode to eat-back.
Then, please refer to Fig. 2 I, in substrate 200, form word line 220.Wherein, the formation method of word line 220 for example is earlier to form conductor layer (not illustrating) in substrate, then defines this conductor layer, and forming the conductor layer of patterning in substrate, and this patterning conductor layer is to be perpendicular to one another with embedded type bit line.Wherein, the material of above-mentioned conductor layer (word line 220) for example is a doped polycrystalline silicon, and the formation method for example is a chemical vapour deposition technique.
It below is the structure that explanation utilizes the resulting non-volatile memory cells of manufacture method of above-mentioned non-volatile memory cells.
Please refer to Fig. 2 I, the big dotted line scope among Fig. 2 I is the memory cell 222 of non-volatile memory cells of the present invention, and is respectively first 224 and second 226 shown in the less dotted line scope.The structure of above-mentioned non-volatile memory cells comprises substrate 200, dielectric layer 202, conductor layer 204, separator 212, embedded type bit line 210, tunneling dielectric layer 215, electric charge capture layer 216, stops dielectric layer 217 and word line 220.
Wherein, dielectric layer 202 is disposed in the substrate 200, and conductor layer 204 is disposed on the dielectric layer 202.In addition, separator 212 is disposed in the substrate 200, and adjacent with conductor layer 204 and dielectric layer 202, and embedded type bit line 210 is arranged in substrate 200, and is disposed at separator 212 belows.Wherein, tunneling dielectric layer 215 is disposed in the substrate 200 and the sidewall of conductor layer 204 and separator 212, and electric charge capture layer 216 is disposed on the tunneling dielectric layer 215, stops that dielectric layer 217 is disposed on the electric charge capture layer 216.In addition, word line 220 is disposed in the substrate 200, and word line 220 is interlaced with each other with embedded type bit line 210.
From the above, the present invention forms earlier dielectric layer 202 in substrate 200, just with tunneling dielectric layer 215, the electric charge capture layer 216 of dielectric layer 202 instead of part and stop dielectric layer 217.In other words, the present invention is at tunneling dielectric layer 215, electric charge capture layer 216 and stops between the dielectric layer 217 and to form dielectric layer 202, so that first 224 and second 226 of memory cell 222 are separated.Therefore, the present invention can avoid memory cell to produce the problem of second effect when operating.
In addition, the present invention also is not easy to produce the situation of voltage or current anomaly when memory cell writes and removes, and causes component failures, and then has influence on the reliability of assembly.
In sum, the present invention has following advantage at least:
1. the present invention can form dielectric layer and is separated from each other with each position with memory cell in memory cell, produces with the problem of avoiding second effect.And this dielectric layer and as the usefulness of gate dielectric layer, therefore also can reduce writing/voltage/current when removing above the local channel district between the two adjacent embedded type bit line.
2. self-registered technology of the present invention except can be applicable to present embodiment, also applicable in other suitable technology, the technology that for example can be applicable to make PACAND.
3. the present invention be except can avoiding interdigit interacts, and also can avoid producing the situation of voltage or current anomaly when causing writing and removing because of second effect, and have influence on the problem of the reliability of assembly.
Though the present invention with preferred embodiment openly as above; right its is not in order to limiting the present invention, anyly has the knack of this operator, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when according to being as the criterion of being defined in the claim.
Claims (17)
1. the manufacture method of a non-volatile memory cells is characterized in that: comprising:
One substrate is provided, in this substrate, forms a dielectric layer, a conductor layer and a mask layer in regular turn;
This mask layer of patterning, this conductor layer and dielectric layer expose most first openings of this substrate with formation;
In the substrate of each these first open bottom, form an embedded type bit line;
In this substrate, form a separator in these first openings;
Remove the part separator, and be that mask is to form most second openings with remaining separator;
Remove the separator of mask layer and coverage mask layer;
In this substrate, form a tunneling dielectric layer in regular turn, an electric charge capture layer and stops dielectric layer, these second openings of conformal covering, separator and conductor layer;
In these second openings, insert a material layer;
Removal is not by part tunneling dielectric layer, the electric charge capture layer of this layer of material covers and stop dielectric layer;
Remove material layer; And
In this substrate, form a word line.
2. the manufacture method of non-volatile memory cells as claimed in claim 1, it is characterized in that: the formation method of this separator comprises carries out a high density plasma CVD technology.
3. the manufacture method of non-volatile memory cells as claimed in claim 1, it is characterized in that: the material of this separator comprises silica, silicon nitride or silicon oxynitride.
4. the manufacture method of non-volatile memory cells as claimed in claim 1 is characterized in that: after removing the part separator, also be included in most angles type separators of reservation on this mask layer.
5. the manufacture method of non-volatile memory cells as claimed in claim 4 is characterized in that: each angle type separator bottom width is less than the width of the mask layer that is positioned at its below.
6. the manufacture method of non-volatile memory cells as claimed in claim 1, it is characterized in that: the method that forms these second openings comprises carries out an etch process.
7. the manufacture method of non-volatile memory cells as claimed in claim 1, it is characterized in that: the material of this mask layer comprises silicon nitride.
8. the manufacture method of non-volatile memory cells as claimed in claim 1, it is characterized in that: the material of this dielectric layer comprises silica.
9. the manufacture method of non-volatile memory cells as claimed in claim 1, it is characterized in that: the formation method of this conductor layer and mask layer comprises chemical vapour deposition technique.
10. the manufacture method of non-volatile memory cells as claimed in claim 1 is characterized in that: the method that forms embedded type bit line in the substrate of each first open bottom comprises carries out an ion implantation step.
11. the manufacture method of non-volatile memory cells as claimed in claim 1 is characterized in that: the method for removing the separator of mask layer and coverage mask layer comprises carries out an etch process or a stripping technology.
12. the manufacture method of non-volatile memory cells as claimed in claim 1 is characterized in that: the method for inserting material layer in these second openings comprises utilizes a method of spin coating.
13. the manufacture method of non-volatile memory cells as claimed in claim 1 is characterized in that: the material of this material layer comprises macromolecular material or photo anti-corrosion agent material.
14. the manufacture method of non-volatile memory cells as claimed in claim 1 is characterized in that: remove not and to be stopped by this tunneling dielectric layer of the part of this layer of material covers, this electric charge capture layer and this that method of dielectric layer comprises and carry out an etch process.
15. the manufacture method of non-volatile memory cells as claimed in claim 1 is characterized in that: comprise in the method for removing this material layer and to carry out an etch process.
16. the manufacture method of non-volatile memory cells as claimed in claim 1 is characterized in that: this word line comprises doped polysilicon layer.
17. the manufacture method of non-volatile memory cells as claimed in claim 1 is characterized in that: the method that forms word line in this substrate comprises carries out a chemical vapor deposition method.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6642586B2 (en) * | 2001-02-07 | 2003-11-04 | Fujitsu Limited | Semiconductor memory capable of being driven at low voltage and its manufacture method |
| CN1462478A (en) * | 2000-09-22 | 2003-12-17 | 三因迪斯克公司 | Non-volatile memory cell array and method of forming |
| US6670240B2 (en) * | 2001-08-13 | 2003-12-30 | Halo Lsi, Inc. | Twin NAND device structure, array operations and fabrication method |
| CN1501455A (en) * | 2002-10-31 | 2004-06-02 | ��ʽ���������Ƽ� | Method of fabricating semiconductor device |
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- 2004-12-15 CN CNB2004101012055A patent/CN100346470C/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1462478A (en) * | 2000-09-22 | 2003-12-17 | 三因迪斯克公司 | Non-volatile memory cell array and method of forming |
| US6642586B2 (en) * | 2001-02-07 | 2003-11-04 | Fujitsu Limited | Semiconductor memory capable of being driven at low voltage and its manufacture method |
| US6670240B2 (en) * | 2001-08-13 | 2003-12-30 | Halo Lsi, Inc. | Twin NAND device structure, array operations and fabrication method |
| CN1501455A (en) * | 2002-10-31 | 2004-06-02 | ��ʽ���������Ƽ� | Method of fabricating semiconductor device |
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