CN100345128C - Bus arbiter based on dynamic priority and method for dynamic changing priority - Google Patents
Bus arbiter based on dynamic priority and method for dynamic changing priority Download PDFInfo
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- CN100345128C CN100345128C CNB2004100034165A CN200410003416A CN100345128C CN 100345128 C CN100345128 C CN 100345128C CN B2004100034165 A CNB2004100034165 A CN B2004100034165A CN 200410003416 A CN200410003416 A CN 200410003416A CN 100345128 C CN100345128 C CN 100345128C
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Abstract
The present invention discloses a bus arbitrator based on dynamic priority and a method for dynamically changing priority. The bus arbitrator comprises a bus arbitration circuit and priority registers, wherein the bus arbitration circuit is connected with a plurality of primary devices, and the priority registers are used for storing the priority of the primary devices which are represented by a binary system. The priority registers can receive external instructions so as to update the priority of the internally stored primary devices, and a decoder is respectively connected with the bus arbitration circuit and the priority registers and is used for decoding the priority stored in the priority registers. When the priority is dynamically changed, the priority registers receive the instructions from programs or upgrade request signals from the primary devices, and the priority registers update the priority of the primary devices in the priority registers. With the present invention, users can dynamically adjust the priority distribution of devices, and devices can actively apply to priority adjustment when loading happens so as to obtain a better bus arbitration mechanism.
Description
Technical field
The present invention relates to the SOC chip design, particularly the bus arbiter of the real-time of chip response processing and management and running.
Background technology
In many host processing systems, bus arbiter plays a part the comparison key, and good moderator improves the transfer efficiency of bus direct relation, has the bus scheduling policing issue equally at the SOC design field.
Yet the application of SOC is diversified, has different scheduling strategies at different disposal, needs dynamic-configuration priority, can do dynamic disposal according to task, improves real-time responsiveness.
Conventional way is to distribute priority in advance, and the often difficult arbitration effect that changes of user developer is unfavorable for that the user does further exploitation flexibly.In the SOC chip design, certainly will be by the decision of hardware line, in case after the flow, just can not change priority.
In order to change this situation, need to introduce the mechanism that dynamically changes priority, in addition, avoid unbalance problem, each main equipment can make the system dynamics equilibrium according to self response time lifting priority.
Summary of the invention
But the object of the present invention is to provide a kind of bus arbiter of dynamically-changing priority; Another object of the present invention provides a kind of bus arbiter by the programmed instruction dynamically-changing priority; A further object of the present invention provides a kind of bus arbiter, the request of this moderator Facility Accepted and promote the priority of this equipment.
To achieve these goals, the invention provides a kind of bus arbiter based on dynamic priority, comprise the bus arbitration arbiter, this bus arbitration arbiter is connected with a plurality of main equipments, reception comes from the bus request signal of described main equipment, and according to the priority of main equipment the main equipment of initiating bus request is carried out prioritization; Also comprise:
Priority register is used to store the priority of each main equipment of binary representation, and described priority register can receive the priority that external command upgrades each main equipment of its stored; Described priority register also is connected with described a plurality of main equipments, to accept the priority upgrade request signal from described main equipment;
Code translator is connected with described priority register with described bus arbitration arbiter respectively, is used for the priority that priority register is stored is deciphered.
The present invention also provides a kind of method for dynamically-changing priority, is used for dynamically changing the priority of a plurality of main device bus requests, comprising:
Step 1), main equipment send the priority upgrade request to bus arbiter;
Step 2), bus arbiter can carry out the priority adjustment by the programmed instruction modification or according to the priority upgrade request of main equipment automatically to the priority facility of being stored in the priority register;
Bus arbitration arbiter in step 3), the bus arbiter carries out prioritization according to the priority facility of storing in the priority register to the main equipment of initiating bus request;
Step 4), main equipment send bus to bus arbiter and occupy request signal;
Step 5), bus arbiter switch bus to corresponding master device according to the result of step 3) medium priority ordering.
After adopting the present invention, the user can dynamically adjust the priority of equipment, prevent on the bus main equipment some " make " (must arrive service) extremely full, some " dies of hunger " (can not get service always) phenomenon, and equipment itself can initiatively apply for adjusting priority when load changes, and obtains bus arbitration mechanism preferably.
Description of drawings
Fig. 1 is the synoptic diagram of the bus arbiter based on dynamic priority of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments the present invention is described in further detail.
In Fig. 1, priority register 11 stores the priority of each main equipment, and in one embodiment, this register allows each equipment that four kinds of priority are arranged, represent that with the binary number 00,01,10 and 11 that is stored in the register 11 its priority orders is 11>10>01>00 respectively.In one embodiment, the priority of register 11 storages is as shown in table 1.
Table 1
Main equipment 1 | Main equipment 2 | Main equipment 3 | … | Main equipment n-1 | Main equipment n |
00 | 11 | 01 | … | 11 | 10 |
Wherein, second of table 1 row is exactly the priority of priority register 11 storages.Priority in the register 11 can be provided with by the instruction of BIOS or system scheduler.For example in Fig. 1, register 11 receives the instruction that comes from program, write device priority in register 11.When system moved, the data in the register 11 were upgraded in the instruction that can receive program, and dynamically changed the priority of equipment, then by the code translator 12 bus arbitration arbiter 13 that direct transfers, with asking bus next time effectively.
A code translator 12 is set between priority register 11 and bus arbitration arbiter 13, and this code translator will change into bus arbitration arbiter 13 spendable hardware signals in the priority of the binary representation in the register 11.For example,, can use a 2-4 code translator to realize decoding, so that judge by bus arbitration arbiter 13 which priority this main equipment is grouped on for the priority of a main equipment of describing with two bits in the table 1.
Though technique scheme can dynamically change the priority of each main equipment in the register 11 by programmed instruction, but when practical application, each main equipment often changes to the demand that takies of bus, therefore, just needs to promote the priority of this equipment when main equipment has hunger.
As an improvement of the present invention, as shown in Figure 1, each main equipment 1~n also respectively with priority register 11 so that send priority upgrade request signals to priority register 11.When a main equipment has hunger, can send the priority upgrade request to moderator 10, the priority of this equipment of priority register 11 stored is done corresponding modify thereupon, and directly influences bus arbitration arbiter 13 by code translator 12, obtains the bus service.For example in one embodiment, each main equipment 1~n is as shown in table 1 in the priority of priority register 11, when 3 pairs of buses of main equipment need hunger the time, it sends a upgrade request signal to priority register 11, the priority of storage changes thereupon in the priority register 11, and is as shown in table 2.
Table 2
Main equipment 1 | Main equipment 2 | Main equipment 3 | … | Main equipment n-1 | Main equipment n |
00 | 11 | 10 | … | 11 | 10 |
After the priority update of priority register 11, by the code translator 12 bus arbitration arbiter 13 that direct transfers, effectively with asking bus next time.
Claims (2)
1, a kind of bus arbiter based on dynamic priority, comprise the bus arbitration arbiter, this bus arbitration arbiter is connected with a plurality of main equipments, reception comes from the bus request signal of described main equipment, and according to the priority of main equipment the main equipment of initiating bus request is carried out prioritization; It is characterized in that, also comprise:
Priority register, be used to store the priority of each main equipment of binary representation, described priority register can receive the priority that external command upgrades each main equipment of its stored, described priority register also is connected with described a plurality of main equipments, to accept the priority upgrade request signal from described main equipment;
Code translator is connected with described priority register with described bus arbitration arbiter respectively, is used for the priority that priority register is stored is deciphered.
2, a kind of method for dynamically-changing priority is used for dynamically changing the priority of a plurality of main device bus requests, comprising:
Step 1), main equipment send the priority upgrade request to bus arbiter;
Step 2), bus arbiter is revised by programmed instruction the priority facility of being stored in the priority register or is carried out the priority adjustment automatically according to the priority upgrade request of main equipment;
Bus arbitration arbiter in step 3), the bus arbiter carries out prioritization according to the priority facility of storing in the priority register to the main equipment of initiating bus request;
Step 4), main equipment send bus to bus arbiter and occupy request signal;
Step 5), bus arbiter switch bus to corresponding master device according to the result of step 3) medium priority ordering.
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CNB2004100034165A CN100345128C (en) | 2004-02-25 | 2004-02-25 | Bus arbiter based on dynamic priority and method for dynamic changing priority |
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CNB2004100034165A CN100345128C (en) | 2004-02-25 | 2004-02-25 | Bus arbiter based on dynamic priority and method for dynamic changing priority |
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CN100345128C true CN100345128C (en) | 2007-10-24 |
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Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
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CN100444143C (en) * | 2006-11-28 | 2008-12-17 | 北京中星微电子有限公司 | An arbitration device and method for accessing internal storage |
CN101026556B (en) * | 2007-01-10 | 2010-04-21 | 华为技术有限公司 | Arbitrating method and device for supporting service quality |
CN103218331B (en) * | 2012-12-07 | 2015-11-11 | 浙江大学 | Synchronous mode is adopted to switch and the self-adjusting bus unit of frame priority and method |
CN103136142A (en) * | 2013-03-05 | 2013-06-05 | 浪潮齐鲁软件产业有限公司 | Bus arbitration method |
CN103257942B (en) * | 2013-03-27 | 2015-12-02 | 青岛中星微电子有限公司 | A kind of method of SOC (system on a chip) shared bus request process and device |
CN107634889B (en) * | 2017-10-17 | 2019-12-03 | 珠海格力电器股份有限公司 | A kind of device intelligence Synergistic method and device |
CN109101443B (en) * | 2018-07-27 | 2021-09-28 | 天津国芯科技有限公司 | Weight time-sharing arbitration device and method |
CN112949247B (en) * | 2021-02-01 | 2022-05-20 | 上海天数智芯半导体有限公司 | Phase-based on-chip bus scheduling device and method |
CN116028398B (en) * | 2022-11-01 | 2023-10-31 | 中科计算技术西部研究院 | Interconnection network arbitration system, device, method and storage medium |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1282924A (en) * | 1999-07-29 | 2001-02-07 | 国际商业机器公司 | Enhanced bus orbitrator using variable priority and reasonableness |
CN1335562A (en) * | 2000-07-27 | 2002-02-13 | 三星电子株式会社 | Arbiter and its bus system |
TW569098B (en) * | 2002-09-24 | 2004-01-01 | Ind Tech Res Inst | An exchanging bus apparatus with recombination and its arbitrating method |
JP2004038767A (en) * | 2002-07-05 | 2004-02-05 | Matsushita Electric Ind Co Ltd | Bus arbitration device |
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1282924A (en) * | 1999-07-29 | 2001-02-07 | 国际商业机器公司 | Enhanced bus orbitrator using variable priority and reasonableness |
CN1335562A (en) * | 2000-07-27 | 2002-02-13 | 三星电子株式会社 | Arbiter and its bus system |
JP2004038767A (en) * | 2002-07-05 | 2004-02-05 | Matsushita Electric Ind Co Ltd | Bus arbitration device |
TW569098B (en) * | 2002-09-24 | 2004-01-01 | Ind Tech Res Inst | An exchanging bus apparatus with recombination and its arbitrating method |
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