CH631018A5 - Data processing installation - Google Patents

Description

The present invention relates to a data processing installation. It is therefore located in the field of digital computers, that is to say the field of processes and apparatuses by which the states of various circuits of latch, flip-flop, etc. ..., in a data processing set, 50 are explored for the purpose of maintenance and error analysis.

In large-scale, high-speed data processing facilities, the ability to detect the state of any latch or flip-flop or other circuit in the data processing system is desirable, particularly for analysis and detection. fault conditions. Prior art installations have frequently included key points that are directly wired in the data processing system to a control panel or console to illuminate the console lights thereby providing an indication of the state of the memo circuits -60 risation in the system. However, the attempt at direct wiring becomes impossible to master for large data processing systems because the number of lamps to be illuminated on the system console becomes too large for a useful or interesting analysis on the part of the operator.

65 Other prior art installations have used the computational capacity of the system to record data using conventional data paths of the processing system to store circuit states at locations

3

631,018

system memory requirements. The use of normal data paths in the storage system offers the problem that if the data path or the control circuit associated with it is defective, the information recorded is erroneous, which makes the location of the fault and its difficult isolation while taking a long time.

Because of these problems with prior art data processing facilities, there is a need for improved access to storage circuits in the data processing system in order to facilitate the analysis of information. maintenance and other purposes. The object of the invention consists in particular in obtaining such performances.

According to the invention, this object is achieved by the presence of the characters set out in claim 1.

The dependent claims define particularly advantageous embodiments, in particular as regards their reliability, the efficiency of their structures, their economy, and the quality of their construction.

It is noted that, as long as the addressing and the access are done under the control of a secondary program in a digital computer, the sequence according to which the various circuits are addressed and put in access can be easily modified. This therefore offers the advantage of great flexibility in the way in which information is accessed, for fault location or for any other purpose.

The invention therefore offers numerous improvements over what the prior art knew.

Details and particularities of the subject of the invention will emerge from the description below, given by way of example and with reference to the accompanying drawings, in which:

fig. 1 is a block diagram of an embodiment of a data processing installation, in accordance with the particular design proposed,

fig. 2 is a schematic representation of the desk unit of the installation of FIG. 1,

fig. 3 is a schematic representation of the interface control device and of the desk control interface in the desk unit of FIG. 2,

FIG. 4 is a schematic representation of the way in which the data processing installation of FIG. 1 is assembled with multi-plate supports which are addressed and which are accessible by means of the console control interface of FIG. 3 .

Figure 5 is a schematic representation of the physical grouping of a typical multiple chip carrier.

Figure 6 is a schematic representation of how the chips on a typical support are grouped logically.

FIG. 7 is a schematic representation of the several data paths in the execution unit of the installation of FIG. 1.

FIG. 8 is a schematic representation of the arrangement of chips of the register 1H which is part of the data path in the apparatus of FIG. 7.

FIG. 9 is a schematic representation of the chip associated with a bit in the circuit of FIG. 8.

FIG. 10 is a schematic representation of the recording microchip associated with the support for multiple wafers containing the circuit of FIG. 8.

Figure 11 is a schematic representation of an alternative embodiment of the chip selection circuit.

In FIG. 1, the data processing installation according to the invention is represented as comprising a main memory 2, a storage control unit 4, an instruction unit 8, an execution unit 10, a data unit channel or channel 6 with an associated input / output and a unit

of console 12. The installation of figure 1 works under the command of instructions of principal installation of which an organized group forms a program of installation. The system instructions and the data on which the instructions 5 work are introduced from the input / output equipment via the channel or channel unit 6 and the storage control unit 4, in the main memory 2. From the latter, the instructions for installing the data are sought by the instruction unit 8 through the intermediary of the memory command 4 and are processed so as to command the execution in execution unit 10.

With reference to FIG. 4, the logic circuits and others constituting the whole or the major part of the installation of FIG. 1 are produced on multi-plate supports (MCC) 15 602 each of which comprises a multiplicity of micro-plates of integrated circuit as shown generally in FIG. 5. For example, up to 64 multi-plate supports 602 designated by MCC (0,0), ..., (MCC (7,7) can be provided. of these supports typically comprises up to 20 42 microchips in a rectangular grouping of 6 × 7, as indicated in FIG. 5.

There is shown in more detail in Figure 2 the desk unit 12 of Figure 1. The desk 12 includes a digital computer 501 which is interconnected with a 32 kilobit memory 502, in a conventional manner. The digital computer 501 is connected to a multiplicity of control devices such as a disc control device 516, a channel or channel control device 411, a switchboard control device 513 and a control device interface 511. Additional control devices can be connected to the indicated computer 501 in a similar manner.

The disk controller 516 interfaces the computer 501 with a 256 kilobit disk classification system 528. The channel controller 411 is one of the channel or channel controllers 6 of Figure 1. The panel controller 513 provides the interface between the digital computer 501 and the control panel 524. The interface controller 511 provides the interface between the console control interface 525 and I'or-40 digital computer 501.

The computer 501 is, typically, a Nova 1200 computer manufactured by the firm "Data General Corporation". The details of operation of such a computer and the manner in which the control units such as the units 45 411, 511, 513 and 516 of Figure 2 interface with the computer 501 are described in a publication entitled "How to use the Nova Computers ", DG NM-5, Data General Corporation, April 1971.

The interface control device 511, connected to the digital computer 501 by 48-bit wiring 535, ensures the connection with the desk control interface by wiring 533. The desk control interface (CCI ) 525 is connected by output exploration wiring 436 to circuits throughout the data processing system of Figure 55 1. Unit I, Unit C and Unit S interconnections from l The console control interface 525 will be described in more detail below.

In FIG. 3, the console control interface 525 and the interface control device 511 as well as their inter-60 connections are shown in more detail. The desk control interface (CCI) 525 includes a 16-bit order register (CR) 551 having a 16-bit order wiring output 540 which is connected as an input to unit I and unit C, as described below. Interface 525 65 further includes 16-bit address registers 552 and 553 which form the 32-bit output address wiring 542 which interconnects with address paths in unit I and l 'S unit of the data processing installation.

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4

The interface 525 further includes 16-bit data registers 554 and 555 having outputs forming the 32-bit desk data wiring 543 which acts as a desk data input to the data paths in the unit C, unit S and unit I of the data processing system of FIG. 1.

The desk registers 551 to 556 and doors 561 to 565 are addressed by the decoded outputs from a decoder 567 which decodes and selects one of these 11 entities in response to the address in a storage address register 4-bit 574 in the interface controller 511.

Interface 525 further includes a 9-bit output exploration address register 556 which specifies, through 9-bit exploration address wiring 590, circuits in the installation. processing data that should be explored.

Interface 525 further includes 64-bit output scan data wiring 591 which is connected to 16-bit scanning doors 561 to 564. Likewise, 16-bit triggered state wiring 592 is connected to status doors 572 to the console computer 501 and via a selection circuit 576 and wiring 535. The decoder 567 receives the 4-bit input from the storage address register 574 and decodes this 4-bit address into one of the 11 lines 621-1 to 621-11. The selection lines 621-7 to 621-11 act so as to select the exploration doors 561 to 564 and the status door 565, respectively. The gates 561 to 565 are each 16-bit and receive the cables 634-1 to 634-4 which form the wiring of 64-bit exploration data 591. The triggered state wiring 592 derives status information from the unit I in the data processing installation of FIG. 1.

The interface 525 further includes the desk interface control (CIC) 570 which includes logic circuits establishing outputs in response to inputs collectively identified as lines 541. More specifically, a start line acts to initiate clock signals in the unit I in order to establish time adjustment signals throughout the installation of FIG. 1. Lines S, I and C valid 545, one for each of the units S, I and C , respectively, act to signal one or more of the respective selected units which must be activated to receive orders from the desk unit. When the respective units S, I and C have received a "valid" signal, they indicate the reception of this signal via order lines S, I and C 544, one for each of the units S, I and C, respectively . An active unit status line 1595 signals the stop, wait for PSW, check and measurement status conditions when they occur in the system of FIG. 1. A fine line OP detects the associated time setting pulses at the installation of FIG. 1 and if the delay between the pulses exceeds a fixed duration, an error condition exists in the installation of FIG. 1. The fine line OP constitutes an input of a carry-over detection circuit 581 which detects the length of time between the time setting pulses and produces an output to signal an excessive delay.

The command 570, the hold detection circuit 581 and the stop line indicate via the active state doors (AS) 582 the state of the system of FIG. 1, by means of the lines 584 connected to the circuits of selection 576. Doors 583 detect the 8-bit interrupt mask register (IMR) 579. The doors 582 and the register 579 have a correlation of one bit for one bit which constitutes for the bits 0.1, ..., 7, the orders order S, order C, stop, wait PSW, stop verification, detector retained and measure, respectively.

Interrupt mask register 579 controls the settings of the "executed" line from gate 583. Since there is a one-to-one correspondence between the bits in the IMR register 579 and the bits in the gates active status 582, activating a bit in the active status gate sets the line executed if the corresponding bit in register 579 is not set. If the bit in register 579 is set, the line output executed from gate 583 is not set.

A validation register 578 stores 3 bits of information which define which or which lines among the valid lines S, I and C 545 must be put into action. A bit 0 means the selection of the unit S, a bit 1 the selection of the unit I and a bit 2 the selection of the unit C. The remaining decoded conditions of the 3 10 bits in register 578 are conditions " unimportant ”.

The CIC 570 responds to a start input line which also triggers the start output line. In addition, the CIC start-up input line initiates the operation of the control circuit 570. An input line emptying CIC acts so as to empty the logic circuits CIC 570 in anticipation of a new order intended for the system of Figure 1 from computer 501.

Referring now to FIG. 4, the exploration address wiring 590 starting from the output 2o exploration data register 556 of FIG. 3 is connected in parallel to several multi-plate supports 602 in order to address a particular microchip on each support and to further address a particular lock or toggle on the address microchip for each multiply support. The state of the addressed worm-25 appears as an output on a respective line among the output exploration lines 603. For example, the latch addressed on the support (0,0) presents its output on a line of exploration 603 (0.0). Similarly, each of the 64 multiple wafer carriers of Figure 4 has a corresponding output line 603 thus producing 64-bit wiring 591. This wiring 591 is the exploration output data wiring 591 which is connected as an input to exploration doors 561 to 564 in Figure 3.

Referring now to Figure 5, there is shown a typical multiple pad holder 602 consisting of 42 chips 606. These chips are grouped, for convenience, into 7 rows numbered 1 to 7 and 6 columns listed A to F. Each of the logic chips 606 comprises a multiplicity of circuits intended to carry out the logic and memory functions executed in the system of FIG. 1. In addition, at least one of the chips, for example the chip 1F to FIG. 5 is an exploration or recording microchip which receives the 9-bit exploration address wiring 590 and offers the 1-bit exploration exploration line 453 which, together with the others 1-bit exploration lines from other multiple wafer carriers, forms the output exploration data wiring. Although location 1F has been selected for the recording microchip in Figure 5, any of the em-50 microchip placements may actually contain this recording microchip, since the physical situation in the array is not critical. In Figure 5, each multiple wafer carrier is shown as typically comprising up to 42 microchips, each of which has a specific physical location on its carrier.

In FIG. 6, the physical multiple platelet support of FIG. 5 is redefined as a function of its logical accessibility by the exploration apparatus. The multiple logic pad holder 60 of Figure 6 is defined as comprising 32 logic chips addressable with each logic chip 608 of Figure 6 having at least one physical chip 606 of Figure 5. Since there are only 32 addressable microchips in Figure 6, each logic chip-65 te 608 may include a non-addressable physical microchip 608 or any part of a physical microchip 606 for ease. The recording chip 611 in FIG. 6 corresponds to the chip 1F at

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631018

Figure 5. The logic chips C (0,0), C (0,1), .. C (0,7) of figure 6 are organized in a first row among four rows. The chips 608 in FIG. 6 can correspond to any combination of the chips 606 in FIG. 5. The recording chip 611 in FIG. 6 receives as input the 9-bit exploration address wiring 590 and provides 1 bit on an output line 603 of the output exploration data wiring 591 of Figures 3 and 4. In addition, the recording chip 611 provides 8 output column selection lines 614-1 to 614-8 and 4 microchip selection lines 613. The recording microchip 611 also receives the 4-bit wiring 612 which consists of 4 exploration lines of rows 612-1 to 612-4. Each row line 612-1 to 612-4 receives the output exploration data from a row of 8 logic chips 608, all grouped together according to OR logic to form a common line.

The recording microchip 611 in FIG. 6 acts in such a way as to receive the 9-bit address on the 590 wiring. The 3 bits of higher rank of this 590 wiring are decoded to select one of the 8 lines 614. The line 614 selected, for example line 614-1, selects the corresponding column, for example column C (0.0), C (1.0), C (2.0) or C (3.0). The 4 lower rank bits of the 9-bit address on line 590 are transmitted via the wiring 613 to each of the chips 608 for the selection of a circuit from up to 64 circuits on each chip 608. L the state of the circuit selected on each chip is then transferred by door to the corresponding row line 612-1 to 612-4. The 2 remaining address bits (center) on wiring 590 are used in the recording chip 611 to select one of the 4 row scanning lines 612 for transmission as output on the wiring line Exploration 603. Other details of the output exploration arrangement will now be described with reference to a typical example. The example described is the register 1H in the execution unit 10 of the system of FIG. 1, as illustrated in FIG. 7.

In FIG. 7, the register 1H 24 is represented between the LUCK unit 20 and the byte adder 32, which are all part of the execution unit 10 of the system of FIG. 1.

In general, the register 1H 24 is a 32-bit register which receives input data from the LUCK unit 20 and connects its output, inter alia, to the byte adder 32. The information is locked in register 24 by a clock pulse on a line 631 coming from a clock 102. It is considered that a typical bit, identified as bit location 124, comprises a latch or flip-flop circuit. The latch circuit 124 of the register 24 in FIG. 7 is shown in more detail with reference to FIGS. 8 and 9.

In FIG. 8, bit 124 representing the bit position 24 of the 32 bits from 0 to 31, is located on the chip 606-1. In addition to bit 24 of register 24 in Figure 7, bits 25 to 31 are also shown as located on chips 606-2,606-3, ..., 606-8 which are designated as bit 25, bit 26,. .., bit 31, respectively. Bit 24, designated by 606-1, is one of the chips 606 similar to that described above with respect to FIG. 5. Likewise, each of the other chips 606-2 to 606-8 is also identical in a way typical for 606 chips in Figure 5. The eight chips 606-1 to 608-8 are part of the eight chips that form a row such as row 0 in Figure 6 having a common output combined according to an OR logic, 612-1 .

In addition to chips 606-1 through 606-8, the logic chips of Figure 6 in a row include other logic that is not located on the same physical chips. For example, a logic chip C (0,0) comprises the physical chip 606-1 and a logic gate 623-1. Likewise, the logic chip of Figure 6, C (0,1) includes the physical chip 606-2 of Figure 8 and the column selection gate 623-2. Column selection doors 623-1 and 623-2, in a preferred embodiment, are located on different physical chips. Similarly, the chips 606-3,606-4 and 606-5 in Figure 8 are three different physical chips, each of which is associated with column selection doors 623-3,623 ^ 4 and 623-5, respectively Column selection doors 623-3 to 623-5 are produced, in a preferred form, on a single physical chip. Likewise, the microchips 606-6,606-7 and 606-8 each consist of three different physical microchips while the corresponding selection doors 623-6, 623-7 and 623-8 are located on a different physical microchip. As described, circuits 617-1 grouped on physical chips as shown, form a row from C (0.0) to C (0.7) of logic chips 608.

In the same way that circuits 617-1 re-20 present a row of eight logic chips for a multiple type 601 chip holder, similar additional circuits 617-2,617-3 and 617-4 represent rows of logic chips which each offer an output line 612—2,612—3 and 612-4, respectively. The four lines 612-1 through 612-4 form the 4-bit wiring 612. Each of the row circuits 617-1 through 617-4 receives the eight column selection lines 614 and the four microchip address lines 613 derived from the recording microchip 611 in Figure 6.

Other details of the bit chip 24,606-1, which represents bit 24 in the register 1H 24 of Figure 7, are illustrated in Figure 9. In the latter, the chip 606-1 includes a latch circuit or flip-flop 124-1 which constitutes bit 24 among the bits 0 to 31 of the register 1H 24 of FIG. 7. Lock 124-1 receives its input from the LUCK unit 20, via lines 652 whose one is a data line and the other is a command line. Likewise, latch 124—1 receives inputs from the shift register via lines 653, one of which is a command line and another 40 a data line, and from the adder through l line 654, one of which is a data line and the other a command line. The lock 124-1 also has a synchronous reset input via a line 651 to return the lock to the initial state at appropriate times during the operation of the data processing system . In addition, lock 124-1 receives input on lines 631 and 632 to control synchronization of the lock. Line 631 is a clock input 102, while line 632 is an inhibit command 50 intended to prevent the clock command from latch 124-1. The lock 124-1 has an output on a line 656 which is connected to a phase separator 637 which constitutes the first level, I, of the logic associated with the byte adder. In addition to the connection with the phase separator 55 55 which constitutes the normal data path of the system of FIG. 1, the lock 124-1 has an output to an additional phase separator 638 which constitutes the start of the data paths d exploration of the installation in Figure 1.

60 In addition to latch 124-1, the chip 606-1 in a preferred embodiment of the invention includes a latch or toggle 124-2 which is associated with bit 24 in the register 2H 25 of the circuits of FIG. 7 Likewise, the chip 606-1 comprises latch circuits 124-3 and 124-4 corre-65 sponding to bits 24 of the register IL and of the register 2L which are additional registers associated with the execution unit 10 but which are not shown more particularly in this patent. The output of lock 124—2 on line 657 is

631,018

6

even connected to phase separator 637 and to phase separator 638 as is the case for the outputs of locks 124-3 and 124-4.

The phase separator 638 includes a door 639 which transmits the state of the latch 124-1 as indicated on line 656 to the selection door 641. The latter is one of the four doors in the selector circuit 640 intended for suitably select the one of the four locks 124-1 to 124-1 which must be connected to an output on line 643. The selection of the door concerned in the selector 641 is done under the control of the decoder 642 which comprises two bipolar doors 645 and 646 responding to 2 bits on lines 613-1 and 613-2 of 4-bit wiring 613. The 2 bits on line 613-1 and 613-2 are decoded so as to select in a particular way one of the four doors in the selector circuit 640. When the lines + LA and + LB of doors 645 and 646 are energized, door 641 is selected by offering the output of line 643 as input to a door 644 which provides the outputs on a line 619. Referring again to FIG. 8, the output on the line e 619 is the bit output 24 of the selected chip. In circuits 601-1 of Figure 9, only two of the four wiring chip address lines 613 are used, namely lines 613-1, 613-2. The two binary addresses specified by these two lines define in a very particular way one of the four locks 124-1 to 124-4. Additional lines 613-3 and 613-4 can be used so that a total of up to 16 latch or other types of circuits per chip can be used in a preferred embodiment of the invention. The output on line 619 according to FIG. 9 represents one of four locks on the chip 606-1. When more locks are used, up to 16, the output on line 619 will represent one of the 16 lock states as addressed by the address occurring on wiring 613.

Other details of the recording chip of Figure 8 are shown in Figure 10. The recording chip 611 receives the 9 input address bits on the input wiring 590. The 3 row bits higher on lines 590-1,590—2 and 590—3 are applied to the column selection decoding circuits 626 or, in a conventional manner, they are decoded to select eight output lines 614. The eight lines 614—1 to 614—8 form the wiring 614 which is connected as an input to each of the row selection circuits 617-1 to 617-4 of Figure 8. In the latter, the column selection lines act so as to select one door at a time, according to the 3 input address bits, among doors 623-1 to 623-8, respectively.

The 2 row bits immediately following address wiring 590 appear on lines 590-4 and 590-5 where they serve as inputs for the decoding and row selection circuits 627. In the latter, the 2 bits on lines 590-4 and 590-5 are decoded to select one of the four doors 661—1 to 661-4 which receive the row status lines 612-1 to 612—4, respectively, on the outgoing 612 wiring of the multiple wafer holder of Figure 8. The line selected from the four lines 612 in response to the information encoded in the input bits 590-4 and 590-5 appears as output on line 603 which constitutes the one of the 16 bits in the 634-1 wiring which is one of the 64 bits in the 64 bit 591 wiring shown in Figure 4.

Likewise, the 4 bits of lower rank on lines 590-6 to 590-9 are fed into the power excitation circuit 628 and retransmitted via the wiring 613 to each of the microchips on the support 601 of FIG. 6 and in particular to the row chips 617-1 of FIG. 8. The signals on lines 590-6 to 590-9 appear as identical signals on lines 613-1 to 613-4, respectively.

The main apparatus of FIG. 1, under the control of the main instructions processed by the instruction unit 8, collects or searches for information from the storage control 4 and from the main memory 2. The control unit exé-5 cution 10 executes the main instructions under the control of information from the instruction unit 8. For example, some main instructions in the main unit use an adder in the execution unit 10 which is shown in more detail in FIG. 7. To execute a main instruction, information is applied to the adder 32 of FIG. 7, via the LUCK unit 20, where it is stored in the register 1H 24 and register 2H 25. The information locked in registers 24 and 25 is added by the adder 32 so as to form results 15 which appear in register 38.

Locking of data in register 24 occurs more precisely at a time controlled by the clock signal on line 631, a line which acts, as illustrated in FIG. 9, so as to adjust each of the bit positions of 0 to 20 32 of register 24 and more precisely bit 24 of register 1H designated by 124—1. The setting of the latch or flip-flop 124-1 and the other bit positions in register 24 is generally done under the control of the main apparatus for the execution of the instructions of a main instruction stream. The desk computer 501 of Figure 2 acts to provide access to information from address locations in the main apparatus of Figure 1 in accordance with a secondary instruction program. The operation of the secondary apparatus and the program of secondary instructions 30 in the computer 501 is independent of the operation of the main apparatus for the execution of the main instructions.

In a preferred embodiment, address locations in the main apparatus of Figure 1 are specified in accordance with a 16-bit binary address produced by the computer 501. This address has the following meaning.

Bits 0 and 1 specify one of four groups of 16 multiple wafer holders and in particular their output lines 603. Bits 0 and 1 are decoded to select one of four exploration doors 561 to 564 to Figure 3, thus selecting one of four groups of 16 lines.

Bits 2 to 5 specify one of the 16 bits of information appearing on this particular group of 16 lines selected by bits 0 and 1.

45 Bit 6 specifies whether or not the selected information bit of the 64 multiple wafer carriers of Figure 4 must be inverted to have the correct polarity. Bit 6 is useful in a preferred embodiment of the invention, since a preferred technology uses inversion logic. In an inversion logic, the existence of an odd number or an even number of logic levels in the transmission of information to the exploration doors determines whether the information has a correct or reversed polarity. By using bit 6 in this addressing format, the information 55 addressed can be arbitrarily returned to the scanning gates without the need to require the use of an odd or even number of logical levels. By setting bit 6 appropriately, the correct polarity is established for each bit of information to which one has access.

60 Bits 7 to 9 select one of the eight columns of the plates 608 in FIG. 6. Bits 7 to 9 are three of the nine address bits in the output on the exploration address wiring 590 in FIG. 3.

Bits 10 and 11 select one of the four rows of the 65 chips 608 in Figure 6. Bits 10 and 11 are two of the nine address bits on the exploration address wiring 590.

Bits 12 to 15 are four bits that select a circuit from up to sixteen circuits on each of the 608 chips

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631,018

in Figure 6. Bits 12 through 15 are the remaining four bits of the nine address bits on the wiring 590 in Figure 3.

Although any circuit location in the main unit can be made addressable for access by the console computer 501, a particular example selected by way of explanation is the register 1H 24 and more precisely the location of the bit 24 in it, as shown in Figure 7.

Bit 24 of register 1H 24 has the following 16-bit binary address:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 010 100 000 0 0 0 0 0 0

In the binary address of bit 24, bits 0 and 1 represent a binary 3 which means that the exploration gate 563 2 will be the one put into action. Gate 563 receives the information addressed from the main device and more precisely the 16 lines 603 from the multiple platelet supports MCC (0.4), MCC (1.4), ..., MCC (7.4) and MCC (0.5), MCC (1.5), ..., MCC (7.5).

Bits 2 to 5 of the address of bit 24 represent a binary 0 which signifies that the desired information bit will appear on the tenth multiple wafer medium, MCC (1,5), in the media group specified by the bits 0 and 1.

The 0 in bit 6 of the above binary address indicates that no inversion is required in the information returned for bit 24 of register 1H.

All 0s for column selection bits 7 to 9 and for row selection bits 10 and 11 mean that bit 24 of register 1H is on the chip located in column 0 and row 0 of the chips. More specifically, with reference to FIG. 6, the column 0 and the row 0 have for intersection the microchip C (0,0).

Referring to FIG. 10, bits 7, 8 and 9 are applied to lines 590-1,590-2 and 590-3 to select the column output line 0 614-1 from among the eight lines 614. This line 614- 1 in FIG. 8 acts so as to select the gate 0 623-1 which receives as other input, the output on line 619 of bit location 24 601-1 in column 0 of row 0 617-1. Simultaneously, rows 617-2,617-3 and 617-4 also select an output from column 0 on their rows 612-2,612-3 and 612-4.

In FIG. 10, bits 10 and 11 for the row selection are applied to lines 590-4 and 590-5 and are decoded in order to select the gate 661-1 which thus functions so as to select from the four row lines 612, the row line 0 612-1 which is derived from FIG. 8.

In Figure 10, bits 12,13,14 and 15 are applied to lines 590-6 to 590-9 which appear in the output wiring 613 which is in turn applied to the chips of Figure 6, including the chip C (0,0) which is the chip 606-1 of FIGS. 8 and 9. In FIG. 9, two of these 4 bits are actually used in a preferred embodiment, namely the 2 bits on lines 613-1 and 613-2. Since bits 12 to 15 are 0, they condition gates 645 and 646 with + LA and + LB at state 0. State 0 of these two outputs is applied as input to decoder 640 and acts in such a way as to condition gate 641 with 0s at the inputs + LA and + LB. With the door 641 thus conditioned, its output is controlled by the state of the line 656 'of the door 639. The door 639 is connected from the reversing output of the flip-flop 124-1 on the line 656. The reverse output on line 656 is obviously the reverse of bit 24 addressed from register 1H.

The output on line 656 is reversed in gate 639, in gate 641, in gate 644, in gate 623-1 in Figure 8 and in gate 661-1 in Figure 10, providing input addressed among the 64 inputs on line 603 to 64-bit wiring 591. The number of inversions from line 656 to line 603 in Figure 6 is five, which in combination with the output inverted by itself on line 656 offers the correct polarity to the scanning gate 563 in Figure 3.

The desk computer 501 of Figure 2 works through the interface controller 511 and the desk control interface 525 to perform the addressing and access required for information in the main unit of Figure 1 in accordance with a secondary instruction program as indicated by Table I below.

Table I ■>

S 1

XLOGB:

STA

3.2

S 2

NORM:

LDA

1, LGAMK

S 3

AND

0.1

S 4

SUB

1.0

S 5

MOVS

1.1

S 6

MOVR

1.3

S 7

MOVR

1.1

S 8

COM

1.1

S 9

.PTY

S10

100

Sil

DOB

1, CCI1

S12

LDA

3, SADR

S13

DOAP

3, CCI1

S14

MOVZL

0.0

S15

MOVL

0.0

S16

MOVL

0.0

S17

LDA

1, RMSK

S18

AND

0.1

S19

MOVR

0.0

S20

LDA

3, GRPT

S21

ADD

1.3

S22

LDA

1.0.3

S23

DOA

1, CCI1

S24

DIA

1, CCI1

S25

.PTY

S26

200

S27

BITSL:

MOVZL

0.0, SZC

S28

MOVS

1.1

S29

MOVL

0.0, SZC

S30

ADDL

1.1, SKP

S31

MOV

0.0, SKP

S32

ADDL

1.1

S33

MOVL

0.0, SZC

S34

ADDL

1.1

S35

MOVL

0.0, SZC

S36

MOVL

1.1

S37

SUBZR

3.3

S38

MOVZL

1.1

S39

AND

3.0, SNR

S40

MOVC

0.0

S41

MOVL

0.0

S42

JMP

0.2

S43

SADR:

120,000

S44

GRPT:

. +1

S45

000000

S46

010000

S47

130,000

S48

040000

S49

LGAMK:

000777

S50

RMSK:

000003

The processing of the aforementioned secondary instruction program is described with respect to bit 24 in the register 1H 24. In a preferred embodiment, the computer 501 is a Nova computer using the standardized Nova instructions. A jump subroutine (JSR) is used to enter the program from Table I. The computer jumps to the address XLOGB as

5

10

15

20

25

30

35

40

45

50

55

60

65

631,018

8

indicated in the SI instruction of table I. In the SI instruction, a return address in the accumulator 3 is stored in the accumulator 2.

Prior to instruction S2, the 16-bit address of bit 24 in the IH register was stored in accumulator 0.

In S2, the accumulator 1 is charged with the content of a fixed address, “LGAMK”, in S49. As indicated in S49, the value is 000777 in octal code.

In S3, the content of accumulator 0 is combined according to an AND logic with the content of accumulator 1, so that the address bits 7 to 15 are stored in the locations 7 to 15 of accumulator 1 .

In S4, address bits 7 to 15 in accumulator 1 are subtracted from the contents of bits 0 to 15 of accumulator 0, so that bits 0 to 6 are left in accumulator 0 at locations 0 to 6, while bits 7 to 15 of accumulator 0 are now equal to 0.

In S5, S6 and S7, bits 7 to 15 at locations 7 to 15 of accumulator 1 are shifted to locations 0 to 8 of accumulator 1.

In S8, the content of the accumulator 1 is put in the form of a complement to bring the information to the desired form during the transfer to the system by the output data register (ODR) 575 of FIG. 3.

In S9 and S10, an installation call prevents an interruption of the instruction flow up to S25 and S26.

In SI 1, the address bits 7 to 15 at locations 0 to 8 of the accumulator 1 are transmitted to the output data register (ODA) 575 in the interface control device 511.

In S12, the accumulator 3 is charged with the content of a fixed address "SADR", in S43. As indicated in S43, the content of the SADR address is 1200000 in octal code.

In S13, the content of the accumulator 3 is transmitted to the interface control device 511 and locked in the SAR 574. The decoder 567 acts so as to decode the octal code 1200000 to condition, via the line 621 -6, the entrance door 548 to the SADR register 556. Also in S13, a signal is produced on line 549, which excites gates 548, which, together with the signal on line 621-6, locks the 9-bit address from the ODR register 575 in the SADR register 556. In S13, the secondary device in response to the secondary program of table I, addresses the primary device in accordance with the 9-bit address in the register 556.

In S14, S15 and S16, the address bits 0 and 1 are moved in the accumulator 0 from locations 0 and 1 to locations 14 and 15. This operation leaves bits 2 to 6 in carry locations up to 4.

In S17, the accumulator 1 is charged with the content of a fixed address, "RMSK", in S50. As indicated in S50, the value is 000003 in octal code.

In SI 8, the content of accumulator 0 is combined according to an AND logic with accumulator 1, so that the latter, because of the mask, presents the address bits 0 and 1 at locations 14 and 15.

In S19, the address bits 2 to 6 are moved from the transfer locations up to 4 of the accumulator 0 to the locations 0 to 5 of the accumulator 0.

In S20, the accumulator 3 is loaded with the content of the fixed address GRPT, which is the address of S44 plus one.

In S21, the content of accumulator 1, bits 0 and 1, which constitutes the binary 2 for bit 24 of register 1H, is added to the address of accumulator 3 to specify the door addressed among the four doors exploration 561, 562, 563 and 564 in Figure 3.

In S22, the accumulator 1 is loaded with the exploration door address from the contents of the location whose address is in the accumulator 3.

In S23, the exploration gate address of the accumulator 1 is applied to the SAR register 574 and decoded by the decoder 567 in order to select the gate 563.

In S24, entry doors 572 are conditioned to lock the 16 bits of exploration information coming from doors 563 in the accumulator 1. In S24, obtaining access to information from the the primary unit is finished. The information to which we had access in S24 is that which was addressed in SI 3.

In S25 and S26, the inhibition of interruptions established in S9 and S10 is suppressed.

In S27 to S38, using standardized programming techniques, the address bits 2 to 6 located in the accumulator 0 are analyzed to determine which of the 16 bits of exploration training in the accumulator 1 which constitutes the desired bit corresponding to the state of bits 24 of register 1H. The program determines that this is the tenth bit. In S38, this bit is moved to the carry locations.

In S39, the address bit 6 is queried, which causes a bypass to S40 if the tenth exploration bit is to be set as a complement.

In S40, take the complement if necessary as determined in S39.

In S41, the tenth exploration bit at the location of 25 carryovers is placed at location 15 of the accumulator 0.

In S42, the program is terminated and the secondary data processing installation returns to the return address specified in SI.

FIG. 11 shows an alternative embodiment 30 for the decoding and selection circuits with the four bits used for addressing on the chips. More specifically, the 9-bit 590 cabling has the four bits on chip 590-6,590-7,590-8 and 590-9 which are applied as input to a 4 to 7,586 recoder. The 596,35 recoder in a preferred embodiment, recodes the four input bits 590-6 to 590-9 in accordance with table II below. In the latter, the four address lines 590-6 to 590—9 are identified in the columns lines 590- The recoded output appears in table II in the columns lines 597-,

40

Table II

Lines 590-

Lines 597-

OCTAL

6

7

8

9

AT

B

vs

D

E

F

G

45 0

0

0

0

0

0

0

1

1

1

1

1

1

0

0

0

1

0

1

1

0

1

1

1

2

0

0

1

0

1

0

0

1

1

1

1

3

0

0

1

1

1

1

0

0

1

1

1

4

0

1

0

0

0

1

0

1

1

1

1

50 5

0

1

1

0

0

1

1

1

1

0

1

6

0

1

1

0

1

1

0

1

0

1

1

7

0

1

1

1

1

1

0

1

1

0

1

10

1

0

0

0

1

0

1

1

0

1

1

11

1

0

0

1

1

1

1

0

0

1

1

55 12

1

0

1

0

1

0

1

0

1

1

1

13

1

0

1

1

1

1

1

0

1

0

1

14

1

1

0

0

0

1

1

1

0

1

1

15

1

1

0

1

1

1

1

1

0

0

1

16

1

1

1

0

1

0

1

1

1

1

0

60 17

1

1

1

1

1

0

1

1

1

0

1

Still referring to FIG. 11, the 7-bit wiring 597 of the recoder 586 is connected to the decoders 581—1,587—2, ..., 587-8. The decoders 587 each include a multi-65 plicity of three input doors 598. The door 598-0 receives two of the seven outputs on the wiring 597 and receives an input 473 which is connected to the same circuit in the processing installation. data of figure 1 which must present information

9

631018

exit by exploration when gate 598-0 is conditioned by inputs 0 on two of lines 597. Gate 598-0 typically receives inputs 597-A and 597-B among the seven lines 597. These lines correspond to an octal code of 0 and select gate 598-0 exclusively.

Similarly, gate 598-1 has inputs 597-A and 597-D which represent an octal 1 in Table II. The outputs of doors 598-0 to 598-7 are connected in common to the first door 599-1 of the eight column doors 599-1 to 599-8. The outputs of decoders 587-2 to 587-8 are likewise connected to the column doors 599-2 to 599-8, respectively.

The eight column doors 599-1 to 599-8 are in turn connected in common to form the output line 612'-1 which is analogous to line 612-1 in Figure 8. Similarly, the four lines 612 '-1 to 612'-4 are analogous to the four lines in wiring 612 in Figure 10.

The two decoding schemes of Figures 9 and 11 are used in a preferred embodiment of the invention. In a preferred embodiment, the typical circuit connected to line 473 is derived from the desk unit. This line 5,473 detects the active state of the circuit when it is not a latch or toggle circuit. Bit 24 of register 1H as defined with reference to FIG. 9 is, for comparison, a latch or flip-flop circuit. Consequently, the described arrangement can be used either to read the state of locks or other storage elements in the data processing installation, or to read the state of particular lines which can change dynamically independently of the locking of data. . Although the circuits explored are mainly latch or toggle circuits, it will be obvious to the person skilled in the art that the state of any circuit can be explored.

10

15

VS

8 sheets of drawings

Claims (8)

631,018 1. Data processing installation, characterized in that it comprises: - a main data processing device, formed of a plurality of units (2,4,6,8,10) at least one of which comprises main circuits (20,24,25,32,38) interconnected by main channels and operating to process data, each said main circuit being established in a logic state in response to a main instruction program executed by said main apparatus, - And a secondary device (12) for processing a secondary instruction program independently of the data processing by said main device, this secondary device (12) comprising addressing means (552-553), connected by independent channels, foreign to said main channels, and operating in response to an address from said secondary program to address said main circuits without disturbing their logic states, said secondary device further comprising an access device (561-565) for accessing selectively to certain selected ones of said main circuits, under the control of said secondary program and independently of said main channels, so that said secondary device (12) receives the logic states of these selected main circuits. 2. Installation according to claim 1, characterized in that the secondary device (12) comprises: - a programmable digital computer (501) for communicating with peripheral devices via a plurality of control devices (411,513,516) in response to the secondary program, - an interface control device (511) intended to communicate with the digital computer (501), this interface control device comprising an output data register (575) for supplying addresses of the main circuits; - And a control interface device (525) comprising an output exploration address register (556) and connected between the interface control device (511) and the main appliance, this interface device control (525) comprising said addressing means (552,553) and said access device (561-565), said addressing means (552, 553) being connected so as to be conditioned by the register of output data (575) in response to the secondary program for addressing and providing access to the main circuits. 3. Installation according to claim 2, characterized in that said output exploration address register (556) is connected to the output data register (575) and has an output forming an exploration address wiring. (590) connected in parallel with a plurality of said main circuits (20,24,25,32,38), said access device (561—565) consisting of exploration doors connected to a plurality of said circuits main by cabling of output exploration data (591), and in that the control interface device (525) comprises a device (567) responding to the addresses produced by the secondary program in order to condition the register of exit exploration address and exploration doors, so that information is addressed and access is obtained to it in the main unit. 4. Installation according to claim 3, characterized in that it comprises: - a plurality of integrated circuit chips (608) each containing a plurality of said main circuits, - a plurality of microchip holders (601,602), each containing an associated plurality of these microchips (608), and each connected so as to receive the exploration address wiring (590) and to provide an input to the wiring of output exploration data (591), a device (611) associated with each chip holder for addressing one of the chips in the associated plurality in response to information on the cabling of the exploration address (590), - And, on each of the microchips, a device (623) 5 responding to the exploration address wiring for addressing a main circuit specified on the microchip and for connecting each main circuit addressed to the exploration exploration data wiring (591 ). 5. Installation according to claim 1, comprising a plu-lorality of integrated circuit microchips (608) to form said main circuits (20,24,25,32,38), characterized in that it comprises a device output exploration (640, 642) on each chip to address certain selected ones of these main circuits, under the command of said secondary instruction program, as well as to give access to the logic states of these main circuits thus selected, independently of said main tracks and under the control of said secondary instruction program. 6. Installation according to claim 5, characterized in that the secondary apparatus further comprises a digital computer, an interface control device (511) responding to the operation of the digital computer and a control interface device console (525) connecting the interface control device to the chips. 7. Installation according to claim 6, characterized in that the desk control interface device (525) comprises an output exploration address register (556) for memorizing the addresses of the main circuits to which one must have access and provide these addresses, and output discovery data wiring (591) connected to a plurality of said main circuits for receiving the state of the circuit specified by the output discovery address register (556) . 8. Installation according to claim 7, characterized in that it comprises a plurality of microchip supports 35 (601,602), each medium providing a line (603) for wiring output exploration data. 9. Installation according to claim 8, characterized in that each chip holder (601, 602) comprises an element (611) for the reception of a wiring of address of explo- 40 ration (590) to select a main circuit to be linked to the associated exploration data line.