CA2387110A1 - Packet video signal inverse transport processor memory address circuitry - Google Patents
Packet video signal inverse transport processor memory address circuitry Download PDFInfo
- Publication number
- CA2387110A1 CA2387110A1 CA002387110A CA2387110A CA2387110A1 CA 2387110 A1 CA2387110 A1 CA 2387110A1 CA 002387110 A CA002387110 A CA 002387110A CA 2387110 A CA2387110 A CA 2387110A CA 2387110 A1 CA2387110 A1 CA 2387110A1
- Authority
- CA
- Canada
- Prior art keywords
- data
- payloads
- memory
- common buffer
- buffer memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
An inverse transport processor system for a TDM packet signal TV receiver includes apparatus for selectively extracting desired payloads of program component data and coupling this data to a common buffer memory data input port. A microprocessor associated with the system also couples data to the common buffer memory data input port. The respective component payloads and data generated by the microprocessor are stored in respective blocks of the common buffer memory in response to associated memory address which are applied to a memory address input port by an address multiplexer. A decryption device is included to decrypt payload data according to packet specific decryption keys. In addition a detector is included to detect payloads including entitlement data. Payloads containing entitlement data are directed via the common buffer memory to a smart card which generates the packet specific decryption keys. A memory data output port is coupled to a bus interconnected with the respective program component processors. Responsive to data requests from the respective program component processors, and data write requests from the component payload source, memory access for read and write functions is arbitrated so that no incoming program data is lost, and all component processors are serviced.
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/232,787 US5475754A (en) | 1994-04-22 | 1994-04-22 | Packet video signal inverse transport processor memory address circuitry |
US232,789 | 1994-04-22 | ||
US08/232,789 US5521979A (en) | 1994-04-22 | 1994-04-22 | Packet video signal inverse transport system |
US232,787 | 1994-04-22 | ||
CA002146472A CA2146472C (en) | 1994-04-22 | 1995-04-06 | Packet video signal inverse transport processor with memory address circuitry |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA002146472A Division CA2146472C (en) | 1994-04-22 | 1995-04-06 | Packet video signal inverse transport processor with memory address circuitry |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2387110A1 true CA2387110A1 (en) | 1995-10-23 |
CA2387110C CA2387110C (en) | 2008-02-19 |
Family
ID=27169989
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA002387110A Expired - Lifetime CA2387110C (en) | 1994-04-22 | 1995-04-06 | Packet video signal inverse transport processor memory address circuitry |
Country Status (1)
Country | Link |
---|---|
CA (1) | CA2387110C (en) |
-
1995
- 1995-04-06 CA CA002387110A patent/CA2387110C/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
CA2387110C (en) | 2008-02-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EEER | Examination request | ||
MKEX | Expiry |
Effective date: 20150407 |