CA2385145A1

CA2385145A1 - Non-saturating magnetic element(s) power converters and surge protection

Info

Publication number: CA2385145A1
Application number: CA002385145A
Authority: CA
Inventors: Christopher Allen Riggio; Garth Blair Woodland
Original assignee: Online Power Supply, Inc.; Christopher Allen Riggio; Garth Blair Woodland
Current assignee: Online Power Supply Inc
Priority date: 1999-10-01
Filing date: 2000-09-26
Publication date: 2001-04-12
Also published as: WO2001026207A2; JP2003511999A; WO2001026207A3; KR20020038789A; CN1391719A; EP1222732A2; AU7715000A; IL148862A0

Abstract

Single, multistage, and distributed magnetic switched and tank resonant powe r conversion systems utilizing NSME. The NSME provide, superior protection to conducted lightning transients, superior thermal operating bandwidth, higher magnetizing efficiency, greater flux/power density potential and form factor flexibility when implemented with the disclosed circuit strategies. Output voltage is maintained substantially constant and ripple free in the presence of line and load variations by the action of various feedback strategies. These mechanisms combine to produce compensations by controlling the duratio n and/or frequency of a switch or switches. A novel function generator implementation supplies a signal, which is a function of magnetic flux tracking, AC line phasing, and output voltage feedback to provide output regulation, active ripple rejection, and power factor correction to the AC line. Efficient energy storage and transfer is achieved by the optimized application of NSME. The use of efficient rectifying flyback management techniques protects switches and provides additional output. A second novel generator implementation supplies a two-phase signal, which is a function of switching frequency/duty cycle, and output voltage, provides regulation. Further efficiencies are realized by the inclusion of switching buffers that substantially reduce switching losses by presenting a high slew rate, low source impedance critically damped drive current to the main switch or switches.

Description

2

3 Non-Saturating Magnetic Elements) Power Converters

4 and Surge Protection 7 This application is a continuation in part of 8 application 09/410/849, filed on 10/1/99.

FIELD OF INVENTION

12 The present invention relates to converters, power 13 supplies, more particularly, to single, or multi stage, 14 AC/DC or DC/DC isolated and non-isolated push-pull converters including but not limited to, forward, 16 flyback, buck, boost, push pull, and resonant mode 17 converters, and power supplies, having individual or 18 distributed NSME with high speed FET switching and 19 efficient flyback management and or having input PFC
(power factor correction) and input protection from 21 lightning transients. The invention also allows the 22 magnetic elements) be distributed to accommodate 23 packaging restrictions, multiple secondary windings, or 24 operation at very high winding voltages.

28 There are several basic topologies commonly used to 29 implement switching converters.
A DC-DC converter is a device that converts a DC
31 voltage at one level to a DC voltage at another level.
32 The converter typically includes a magnetic element 1 having primary and secondary windings wound around it to 2 form a transformer. By opening and closing the primary 3 circuit at appropriate intervals control over the energy 4 transfer between the windings occurs. The magnetic element provides an alternating voltage and current whose 6 amplitude can be adjusted by changing the number and 7 ratio of turns in each set of the windings. The magnetic 8 element provides galvanic isolation between the input and 9 the output of the converter.
One of the topologies is the push-pull converter.
11 The output signal is the output of an IC network that 12 switches the transistors alternately "on" and "off". High 13 frequency square waves on the transistor output drive the 14 magnetic element into AC (alternating current) bias. The isolated secondary outputs a wave that is rectified to 16 produce DC (direct current). The push-pull converters 17 generally have more components as compared to other 18 topologies. The push-pull approach makes efficient use of 19 the magnetic element by producing AC bias, but suffers from high parts count, thermal derating, oversized 21 magnetics, and elaborate core reset schemes. The 22 destructive fly-back voltages occurring across the 23 switches are controlled through the use of dissipative 24 snubber networks positioned across the primary switches.
Another of the topologies is the forward converter. 4~Ihen 26 the primary of the forward converter is energized, energy 27 is immediately transferred to the secondary winding. In 28 addition to the aforementioned issues the forward 29 converter suffers from inefficient (dc bias) use of the magnetic element. The prior art power supplies use high 31 permeability gapped ferrite magnetic elements. These are 32 well known in the art and are widely used. The magnetics 1 of the prior art power supplies are generally designed 2 for twice the required power rating and require complex 3 methods to reset and cool the magnetic elements resulting 4 in increased costs and limited operating temperatures.
This is because high permeability magnetic elements 6 saturate during operation producing heat in the core, 7 which increases permeability and lowers the saturation 8 threshold. This produces runaway heating, current spikes 9 and/or large leakage currents in the air gap, reduced efficiency, and ultimately less power at higher 11 temperatures and/or high load. The overall effects are, 12 lower efficiency, lower power density, and forced 13 air/heatsink dependant supplies that require over-rated 14 ferrite magnetic elements for a given output over time, temperature, and loading.

19 The combined improvements of the invention translate to higher system efficiencies, higher power densities, 21 lower operating temperatures, and, improved thermal 22 tolerance thereby reducing or eliminating the need for 23 forced air cooling per unit output. The non-saturating 24 magnetic properties are relatively insensitive to temperature (see FIG. 17), thus allowing the converter to 26 operate over a greater temperature range. In practice, 27 the operating temperature for the NSME is limited to 200C
28 by wire/core insulation; the non-saturating magnetic 29 material remains operable to near its Curie temperature of 500C.
31 What are needed are converters having circuit 32 strategies that make advantageous use of individual and 1 distributed NSME.
2 What are needed are converters having buffer 3 circuits that provide fast, low impedance critically 4 damped switching of the main FETs.
What are needed are converters that incorporate 6 efficient multiple "stress-less" flyback management 7 techniques to rectify and critically damp excessive node 8 voltages across converter switches.
9 What are needed are converters having flux feedback frequency modulation.
11 What are needed are converters that correct AC power 12 factor.
13 What is needed are converters that meet or exceed 14 class B conducted EMI requirements.
What are needed are converters tolerant of lightning 16 and harsh thermal environments. The present invention 17 addresses these and more.

SUMMARY OF THE INVENTION

22 The main aspect of the present invention is to 23 implement converters having circuit strategies that make 24 advantageous use of individual and distributed NSME for the achievement of the key performance enhancements 26 disclosed herein.
27 Another aspect of the present invention is to 28 provide unique resonant tank circuit converter strategies 29 with individual and distributed NSME that make use of higher primary circuit voltage excursions in the 31 production of high frequency / high density magnetic 32 flux.

1 Another aspect of the present invention is a high 2 energy density single stage frequency controlled resonant 3 tank converter topology enabled by the use of individual 4 and distributed NSME. Another aspect of the present

5 invention is to provide a converter design that utilizes

6 a FET drive technique consisting of an ultra fast, low

7 RDS on N-channel FET for charging the main FET gate and

8 an ultra fast P-channel transistor for discharging the

9 main FET gate.
Another aspect of the present invention is to 11 provide converters that incorporate efficient multiple 12 "stress-less" flyback management techniques to rectify 13 and critically damp excessive node voltages across 14 converter switches.
Another aspect of the present invention is to 16 provide a converter having core (flux) synchronized zero 17 crossing frequency modulation.
18 Another aspect of the present invention is to 19 present a high power factor to the AC line.
Another aspect of the present invention is to 21 provide protection from high voltage (input line) 22 transients.
23 Another aspect of the' present invention is to 24 combine distributed magnetics advantageously with the other converter aspects.
26 Another aspect of the present invention is active 27 ripple rejection provided by several high-gain high-speed 28 isolated control and feedback systems.
29 Other aspects of this invention will appear from the following description and appended claims, reference 31 being made to the accompanying drawings forming a part of 32 this specification wherein like reference characters 1 designate corresponding parts in the several views.

4 FIG. 1 and 1A is a schematic diagram of a two-stage power factor corrected AC to DC isolated output converter 6 embodiment of the invention.
7 FIG. 2 is a schematic diagram of a single stage DC to AC
8 converter embodiment with isolated output sub-9 circuit DCAC1.
FIG. 3 and 3A is a schematic diagram of a three stage AC
11 to DC isolated output converter embodiment of the 12 invention.
13 FIG. 4 is a schematic diagram of a power factor corrected 14 single stage AC to DC converter sub-circuit ACDFPF.
FIG. 4A is a schematic diagram of an alternate power 16 factor controller with load sharing converter sub-17 circuit ACDFPF1.
18 FIG. 5 is a graph comparing typical winding currents in 19 saturating and non-saturating magnetics of equal inductance.
21 FIG. 6 is a schematic for a non-isolated low side switch 22 buck converter sub-circuit NILBK.
23 FIG. 7 is the preferred embodiment schematic for a tank 24 coupled single stage converter sub-circuit TCSSC.
FIG. 8 is a schematic for a tank coupled totem pole 26 converter sub-circuit TCTP.

1 FIG. 9 is a block diagram for a single stage non-isolated 2 DC to DC boost converter NILSBST.
3 FIG. 10 is a schematic for a two stage isolated DC to DC
4 boost controlled push-pull converter BSTPP.
FIG. 11 is a graph of permeability as a function of 6 temperature for typical prior art magnetic element 7 material.
8 FIG. 12 is a graph of flux density as a function of 9 temperature for typical prior art magnetic element material.' 11 FIG. 12A is a graph of magnetic element losses for 12 various flux densities and operating frequencies 13 typical of prior art magnetic element material.
14 FIG. 13 is a graph showing standard switching losses.
FIG. 14 is a graph showing lower switching losses of the 16 invention.
17 FIG. 15 is a graph showing the magnetizing curve (BH) for 18 the NSME material.
19 FIG. 15A is a graph of the magnetization curves for H
Material.
21 FIG. 16 is a graph of magnetic element losses for various 22 flux densities and operating frequencies of the NSME
23 material.
24 FIG. 17 is a graph of permeability as a function of temperature for the NSME.

1 FIG. 18 is a schematic representation of the boost NSME
2 sub-circuit PFTl.
3 FIG. 18A is a schematic representation of the NSME sub-4 circuit PFT1A.
FIG. 18B is a schematic representation of the non-6 saturating two terminal NSME sub-circuit BL1.
7 FIG. 18C is a schematic diagram of the NSME implemented 8 as distributed magnetic assembly PFT1D.
9 FIG. 19 is a schematic representation of the push-pull NSME sub-circuit PPT1.
11 FIG. 19A is a schematic representation of the alternate 12 push-pull NSME sub-circuit PPT1A.
13 FIG. 20' is a schematic diagram of the NSME input 14 transient protection and line filter sub-circuit LL.
FIG. 20A is a schematic showing an alternate line filter 16 LF .
17 FIG. 21 is a schematic diagram of the alternate NSME
18 input transient protection and line filter sub-19 circuit LLA.
FIG. 22 is a schematic diagram of the AC line rectifier 21 sub-circuit BR.
22 FIG. 23 is a schematic diagram of the power factor 23 controller sub-circuit PFA.
24 FIG. 24 is a schematic diagram of the alternate power factor correcting boost control element sub-circuit 1 PFB.
2 FIG. 25 is a schematic diagram of the output rectifier 3 and filter sub-circuit OUTA.
4 FIG. 25A is a schematic diagram of an alternate rectifier sub-circuit OUTB.
6 FIG. 25B is a schematic diagram of an alternate final 7 output rectifier and filter sub-circuit OUTBB.
8 FIG. 26 is a schematic diagram of the floating 18 Volt DC
9 control power sub-circuit CP.
l0 FIG. 26A is a schematic diagram of and alternate 18 Volt 11 DC control power sub-circuit CP1.
12 FIG. 26B is a plot of VCC control voltage as a function 13 of output power in watts during operation of sub-14 circuit ACDCPF1 (FIG. 4A).
FIG. 27 is a schematic diagram of the alternate floating 16 18 Volt DC push-pull control power sub-circuit CPA.
17 FIG. 28 is a schematic diagram of the over temperature 18 protection sub-circuit OTP.
19 FIG. 29 is a schematic diagram of the high-speed low impedance buffer sub-circuit AMP, AMP1, AMP2 and 21 AMP3 .
22 FIG. 30 is a schematic diagram of the main switch snubber 23 sub-circuit SN.
24 FIG. 30A is a schematic diagram of the main switch rectifying diode snubber sub-circuit DSN.

1 FIG. 30B is a schematic diagram of the main switch 2 snubber sub-circuit SNBB.
3 FIG. 31 is a schematic diagram of the alternate snubber 4 sub-circuit SNA.
5 FIG. 32 is a schematic diagram of the mirror snubber sub-6 circuit SNB.
7 FIG. 33 is a schematic diagram of the pulse-8 width/Frequency modulator sub-circuit PWFM.
9 FIG. 34 is an oscillograph of node voltages measured

10 during operation of sub-circuit PWFM (FIG. 33).

11 FIG. 35 is an oscillograph of the primary tank voltage

12 measured during operation of sub-circuit TCTP (FIG.

13 8) .

14 FIG. 36 is a schematic diagram of the non-isolated 18-Volt DC control power sub-circuit REG.
16 FIG. 37 is a schematic for a non-isolated high-side 17 switch buck converter sub-circuit HSBK.
18 FIG. 38 is a schematic for the low-side buck regulated 19 two-stage converter embodiment with isolated push-pull output sub-circuit LSBKPP.
21 FIG. 39 is a schematic for an alternate isolated two-22 stage low-side switch buck converter sub-circuit 23 LSBKPPHR.
24 FIG. 40 is a schematic diagram of the over voltage feed back sub-circuit IPFFB.

1 FIG. 40A is a schematic diagram of the non-isolated boost 2 output voltage feedback sub-circuit FBA.
3 FIG. 40B is a schematic diagram of the isolated output 4 voltage feedback sub-circuit IFB.
FIG. 40C is a schematic diagram of..the alternate isolated 6 over voltage feedback sub-circuit IOVFB.
7 FIG. 40D is a schematic diagram of and alternate the non-8 isolated boost output voltage feed back sub-circuit 9 FBD.
FIG. 41 is a schematic diagram of the non-isolated output 1l voltage feedback sub-circuit FBI.
12 FIG. 41A is a schematic diagram of an alternate non-13 isolated feedback sub-circuit FB2.
14 FIG. 42 is a schematic diagram of an over voltage protection sub-circuit OVP.
16 FIG. 42A is a schematic diagram of the isolated over 17 voltage feedback sub-circuit OVP1.
18 FIG. 42B is a schematic diagram of the over voltage 19 protection sub-circuit OVP2.
FIG. 42C is a schematic diagram of the isolated over 21 voltage feedback sub-circuit OVP3.
22 FIG. 43 is a schematic diagram of the Push-pull 23 oscillator sub-circuit PPG.
24 FIG. 44 is a schematic diagram of the soft start/inrush current limit sub-circuit SS1.

1 FIG. 44A is an oscillograph of line current and output 2 voltage during operation of sub-circuit SS1 (FIG.
3 44 ) .
4 FIG. 45 is a schematic diagram of the fast start sub-s circuit FS1.
6 FIG. 45A is an oscillograph of sub-circuit FS1 during 7 operation of sub-circuit SSl (FIG. 44).

9 FIG. 46 is a schematic diagram of an alternate transient protection sub-circuit TRN.

12 FIG. 46A is a schematic diagram of an alternate transient 13 protection sub-circuit for external application 14 TRNX .
16 FIG. 46B is an oscillograph of the converter operation 17 during a high voltage transient event.

19 FIG. 47 is a signal flow diagram teaching the load sharing system.

22 FIG. 47A is an alternate signal flow diagram teaching the 23 load sharing system.

Before explaining the disclosed embodiments of the 26 present invention in detail, it is to be understood that:
27 The invention is not limited in its application to the 28 details of the particular arrangements shown or 29 described, since the invention is capable of other embodiments.
31 The expression "distributed magnetic(s)" refers to 1 the configuration of multiple magnetic elements that 2 share a single series coupled primary winding to induce 3 isolated output currents from multiple series or parallel 4 secondary windings.
Also, the terminology used herein is for the purpose 6 of description not limitation.

In this and other descriptions contained herein, the 11 following symbols shall have the meanings attributed to 12 them: "+" shall indicate a series connection, such as 13 resistor A in series with resistor B shown as "A+B". "~I"
14 Shall indicate a parallel connection, such as resistor A
in parallel with resistor B shown as "A~~B".

17 Referring first to FIG. 7, a schematic diagram of 18 the preferred embodiment of the invention.
19 FIG. 7 is a schematic of the preferred embodiment of a tank coupled single stage converter sub-circuit TCSSC.
21 Sub-circuit TCSSC consists of resistor R20 and RLOAD, 22 capacitor C10, transistors Q21 and Q11, sub-circuit CP
23 (FIG. 26), sub-circuit PFT1 (FIG. 18), sub-circuit OUTA
24 (FIG. 25), sub-circuit AMP (FIG. 29), sub-circuit IFB
(FIG. 40B) and sub-circuit PWFM (FIG. 33).
Figure Table Element Value/part number R20 1k ohms R61 2k ohms C10 l.8uf 1 TCSSC can be configured to operate as an AC-DC
2 converter, a DC-DC converter, a DC-AC converter, and an 3 AC-AC converter. Sub-circuit TCSSC consists of resistor 4 R20 and RLOAD, capacitor C10, switches Q11 and Q21, opto-isolator U12, sub-circuit PFT1 (FIG. 18), sub-circuit 6 OUTA (FIG. 25), sub-circuit CP (FIG. 26), sub-circuit AMP
7 (FIG. 29), sub-circuit IFB (FIG. 40B) and sub-circuit 8 PWFM (FIG. 33). External power source VBAT connects to 9 pins DCIN+ and DCIN-. Source power may also be derived from rectified AC line voltage such as FIG. 20 or FIG. 21 11 to form a single stage power factor corrected AC to DC
12 converter with isolated output. From DCIN+ resistor R20 13 connects to sub-circuit CP pin CP+, sub-circuit AMP pin 14 GA+, U12 LED anode and to sub-circuit PWFM pin PWFM+.
Resistor R20 provides startup power to the converter 16 until the control supply regulator sub-circuit CP reaches 17 the desired 18-volt output. VBAT negative is the ground 18 return node connects to sub-circuit PWFM pin PWFMB, Q11 19 source, sub-circuit AMP pin GAO, sub-circuit CP pin CTO, pin DCIN- and sub-circuit PFT1 pin S1CT. Magnetic element 21 winding node S1H of sub-circuit PFT1 is connected to CP
22 pin CTlA. Magnetic element winding node S1L of sub-23 circuit PFT1 is connected to CP pin CT2A. Sub-circuit 24 PWFM is designed as a constant 50o duty-cycle variable frequency generator. Sub-circuit PWFM Clock output pin 26 CLK is connected to input of buffer sub-circuit AMP pin 27 GA1. The output of buffer sub-circuit AMP pin GA2 is 1 connected to the gate of Q11 and R21. Resistor R21 is 2 connected to the cathode of U12 LED. The emitter of Q21 3 and drain of Q11 is connected to sub-circuit PFT1 pin 4 PlA. Pin P1B of sub-circuit PFT1 is connected through 5 tank capacitor C10 to node DCIN+, Q21 collector and 6 through resistor R61 to U12 phototransistor collector.
7 The emitter of U12 phototransistor is connected to the 8 base of Q21. With PWFM pin CLK high transistor Q11 9 conducts charging capacitor C10 through NSME PFT1 from 10 VBAT storing energy in PFT1. Sub-circuit PWFM switches 11 CLK low, Q11 turns "off". With CLK low LED of U12 is 12 turned "on" injecting base current into Q21. With 13 transistor Q21 "on" the tank circuit is completed, 14 allowing capacitor C10 to discharge into NSME PFT1 IS winding 100 (FIG. 18). Now the energy not transferred 16 into the load is released from NSME PFT1 into the now 17 forward biased NPN switch Q21 back into capacitor C10.
18 Thus any energy not used by the secondary load remains in 19 the tank coupled primary circuit (winding 100) . When the switching occurs at the resonant frequency, high voltages 21 oscillate between C10 and winding 100 creating high flux 22 density AC excursions in PFT1. C10 and PFT1 exchange 23 variable AC currents whose magnitude is controlled by 24 frequency modulation scheme IFB and PWFM. The large primary voltage generates large, high frequency biases in 26 the NSME PFT1 thereby producing high flux density AC
27 excursions to be harvested by secondary windings 102 and 28 103 (FIG. 18) to support a load or rectifier sub-circuit 29 OUTA. Magnetic element winding node S2H of sub-circuit 30PFT1 is connected to OUTA pin C7B. Magnetic element 31winding node S2L of sub-circuit PFT1 is connected to OUTA

32pin CBB. Magnetic element winding node S2CT of sub-1 circuit PFT1 is connected to OUTA pin OUT-. Node OUT- is 2 connected to RLOAD, pin B- and to sub-circuit IFB pin 3 OUT-. Rectified power is delivered to pin OUT+ of OUTA
4 and is connected to RLOAD, pin B+ and to sub-circuit IFB
pin OUT+. Sub-circuit IFB provides the isolated feedback 6 signal to the sub-circuit PWFM. Frequency control pin FM1 7 of sub-circuit PWFM is connected to sub-circuit IFB pin 8 FBE. Internal reference pin REF of sub-circuit PWFM is 9 connected to sub-circuit IFB pin FBC. PWFM is designed to operate at the resonate frequency of the tank 11 (2*pi*(square root (C10 * inductance of 100 (FIG. 18)).
12 When sub-circuit IFB senses the converter output is at 13 the target voltage, current from PWFM pin REF is injected 14 into FM1. Injecting current into FM1 commands the PWFM to a lower clock frequency pin CLK. Driving the tank out of 16 resonance reduces the amount of energy added to the tank 17 thus reducing the .converter output voltage. In the event 18 the feedback signal from IFB commands the PWFM off or 19 OHz, i.e.: at no load, all primary activity stops. The input current from VBAT may be steady state or variable 21 DC. When TCSSC is operated from rectified AC (sub-circuit 22 LL FIG. 20), high input (line) power factor and input 23 transient protection is achieved. The primary and 24 secondary currents of PFT1 are sinusoidal and free of edge transitions ,making the converter very quiet. In 26 addition the switches Q11 and Q21 are never exposed to 27 the large circulating voltage induced in the tank (See 28 FIG. 35). This allows the use of lower voltage switches 29 in the design thereby reducing losses and increasing the MTBF. Sub-circuit TCSSC takes advantage of the desirable 31 properties of the NSME in this converter topology. TCSSC
32 is well suited for implementation with distributed NSME

1 PFT1D (FIG. 18C). This combination exemplifies how 2 distributed magnetics enable advantageous high voltage 3 converter design variations that support form factor 4 flexibility and multiple parallel secondary outputs from series coupled voltage divided primary windings across 6 multiple NSME. This magnetic strategy is useful in 7 addressing wire/core insulation, form factor and 8 packaging limitations, circuit complexity and 9 manufacturability. These converter strategies are very useful for obtaining isolated high current density output 11 from a high voltage low current series coupled primary.
12 Adjusting the secondary turn's ratio allows TCSSC to 13 generate very large AC or DC output voltages as well as 14 low-voltage high current outputs.

18 FIG. 1 and 1A is a schematic diagram of a two stage 19 power factor corrected AC to DC converter. The invention is comprised of line protection filter sub-circuit LL
21 (FIG. 20) and full-wave rectifier sub-circuit BR (FIG.
22 22) . A power factor corrected regulated boost stage with 23 sub-circuits PFA2 (FIG. 23), snubber sub-circuit SN (FIG.
24 30),. magnetic element sub-circuit PFT1 (FIG. 18), sub-circuit CP (FIG. 26), buffer sub-circuit AMP (FIG. 29), 26 over temperature sub-circuit OTP (FIG. 28), over voltage 27 feedback sub-circuit IPFFB (FIG. 40) and voltage feedback 28 sub-circuit IFB (FIG. 40B). Start up resistor R2, filter 29 capacitor C1, PFC capacitor C2, flyback diode D4, switch transistor Q1, hold up capacitors C17 and C16, and 31 resistor R17. An efficient push-pull isolation stage with 32 sub-circuits CPA (FIG. 27), PPG (FIG. 43), AMP1 (FIG.

1 29), AMP2 (FIG. 29), snubber sub-circuits SNB (FIG. 32) 2 and SNA (FIG. 31), resistor Rload, transistors Q6 and Q9, 3 magnetic element PPT1 (FIG. 19), and OUTA (FIG. 25).
Figure Table Element Value/part number C1 O.Oluf C2 l.8uf R2 100k ohms D4 8A,600V

C17 100uf C16 100uf R17 375k ohms 4 In the two-stage converter the primary side voltage to the second push-pull output stage is modulated by the 6 power factor corrected input (boost) stage. Each stage 7 can comprise of individual and distributed NSME. A graph 8 of B-H hysteresis for the non-saturating magnetics is set 9 forth in FIG. 15. Although the following description is in terms of particular converter topologies, i.e., 11 flyback controlled primary and constant duty cycle push 12 pull secondary, number of outputs, the style, and 13 arrangement of the several topologies are offered by way 14 of example, not limitation. In addition non-saturating magnetics BL1, PFT1, and PPT1 may be implemented as 16 distributed NSME. As an example PFT1 is shown as a 17 distributed magnetic PFT1A (FIG. 18C). Distributed 18 magnetics enable advantageous high voltage converter 1 design variations that support form factor flexibility 2 and multiple parallel secondary outputs from series 3 coupled voltage divided primary windings across multiple 4 NSME. The negative of the hold-up capacitors) [C17I~C16]
is connected to bridge positive. This allows the 6 rectified line voltage to be excluded from the boost 7 voltage in the hold-up capacitor(s). This, in turn, 8 allows direct regulation of the push-pull stage from the 9 boost (PFC) stage. This eliminates the typical PWM
control of the oversized thermally derated transformer 11 and many sub-circuit components from the known art. AC
12 line is connected to sub-circuit LL (FIG. 20) between 13 pins LL1 and LL2. AC/earth ground is connected to node 14 LLO. The filtered and voltage limited AC line appears on node/pin LL5 of sub-circuit LL and connected to node BR1 16 of bridge rectifier sub-circuit BR (FIG. 22). The 17 neutral/AC return leg of the filtered and voltage limited 18 AC appears on pin LL6 of sub-circuit LL is connected to 19 input pin BR2 of BR. The line voltage is full-wave rectified and is converted to a positive haversine 21 appearing on node BR+ of sub-circuit BR (FIG. 22 ) . Start 22 up resistor R2 connects BR+ to sub-circuit CP pin CP+.
23 Node CP+ connects to pins PFA+ of control element sub-24~ circuit PFA (FIG. 23) and over temperature switch sub-circuit OTP (FIG. 28) pin GAP: Resistor R2 provides start 26 up power to the control element until the 27 rectifier/regulator CP is at full output. Node S1H from 28 PFT1 is connected to node PFVC of sub-circuit PFA. The 29 zero crossings of the core are sensed when the voltage at S1H is at zero. The core zero crossings are used to reset 31 the PFC and start a new cycle. The positive node of the 32 DC side of bridge BR+ is connected through capacitor C2 1 to BR-. C2 is selected for various line and load 2 conditions to de-couple switching current from the line 3 improving power factor while reducing line harmonics and 4 EMI. Primary of NSME sub-circuit PFT1 (FIG. 18) pins P1B
5 and S2CT connects to pin SNL1 of snubber sub-circuit SN
6 (FIG. 30) , to sub-circuit BR pin BR+ and connects to pin 7 BR+ (FIG 1A). The return line for the rectified AC power 8 BR- is connected to the following pins: BR- of sub-9 circuit BR, PFA pin BR-, sub-circuit AMP pin GAO, output 10 switch Q1 source, capacitor C2, sub-circuit CP pin CTO
11 sub-circuit PFT1 pin S1CT and CT20 through EMI filter 12 capacitor C1 to earth ground node LLO. Pin BR+ from FIG.
13 1 is connected to FIG. 1A sub-circuits CPA pin SN pin 14 SNL1, sub-circuit PFT1 pin P1B, and sub-circuit PFT1 pin

15 S2CT. Pin BR+ continues to FIG. 1A connecting to sub-

16 circuit CPA pin CT20, PPG (FIG. 43) pin PPGO, sub-circuit

17 AMP1 pin GAO, sub-circuit AMP2 pin GAO, sub-circuit IPFFB

18 pin PF-, Capacitor [C16~~C17~~resistor R17], transistor

19 Q6 source, transistor Q9 source, sub-circuit SNA pin SNA2

20 and sub-circuit SNB pin SNB2. The drain of output switch

21 Ql is connected to diode D4 anode, sub-circuit SNB pin

22 SNL2, and sub-circuit PFT1 pin P1A and sub-circuit SN pin

23 SNL2. Snubber network SN reduces the high voltage stress

24 to Q1 until flyback diode D4 begins conduction. Line coupled, power factor corrected boost regulated output 26 voltage of the AC to DC converter stage (FIG. 1) appears 27 on node PF+. Addition efficiency may be realized by 28 connecting sub-circuit DSN (FIG. 30A) in parallel with 29 D4. The regulated boost output PF+ connects to the following: sub-circuit SN pin SNOUT, sub-circuit DSN pin 31 SNOUT and diode D4 cathode. Node PF+ also connects on 32 FIG. 1A to capacitors [C16~IC17IIR17], sub-circuit IPFFB

1 (FIG. 40) pin PF+, sub-circuit PPT1 (FIG. 19) pin P2CT, 2 snubber sub-circuit SNA (FIG. 31) pin SNA3, and snubber 3 SNB (FIG. 32) pin SNB3. Magnetic element winding pin S1H
4 of sub-circuit PFT1 is connected to CP pin CT1A and pin PFVC of sub-circuit PFA. Magnetic element winding node 6 S1L of sub-circuit PFT1 is connected to CP pin CT2A.
7 Magnetic element winding node S2H of sub-circuit PFT1 is 8 connected to pin 10 FIG. 1A then to CPA pin CT1B.
9 Magnetic element winding node S2L of sub-circuit PFT1 is connected to pin 12 FIG. 1A then to CPA pin CT2B. Sub-11 circuit PFA using the AC line phase, load voltage, and 12 magnetic element feedback, generates a command pulse 13 PFCLK. Pin PFCLK of sub-circuit PFA (FIG. 23) is 14 connected to the input of buffer amplifier pin GAl of sub-circuit AMP1 (FIG. 29). Buffered high-speed gate 16 drive output pin GA2 of sub-circuit AMP is connected to 17 gate of switch FET Q1. The buffering provided by AMP
18 shortens switch Ql ON and OFF times greatly reducing 19 switch losses (see FIG. 13 & 14). The source of Q1 with pin GAO is connected to return node BR-. Power to sub-21 circuit AMP is connected to pin GA+ from sub-circuit OTP
22 pin TS+. Thermal switch THS1 is connected to Q1. In the 23 event the case of Q1 reaches approximately 105C THS1 24 opens removing power to sub-circuit AMP, safely shutting down the first (input) stage. Normal operation resumes 26 after the switch temperature drops 20-30 deg. C closing 27 THSl. Drain of output switch Q1 is connected to primary 28 winding pin P1A of non-saturating magnetic sub-circuit 29 PFT1 (FIG. 18) and to pin SNL2 of snubber sub-circuit SN
(FIG. 30). Reference voltage from PFC sub-circuit PFA pin 31 PFA2 is connected to feedback networks sub-circuit IPFFB
32 pin FBC and to sub-circuit IFB pin FBC. Control current 1 feedback networks is summed at node PF1 of sub-circuit 2 PFA. Pin PF1 is connected to feed back networks sub-3 circuit IPFFB pin FBE and to sub-circuit IFB pin FBE.
4 Constant frequency/duty-cycle non-overlapping two-phase generator sub-circuit PPG (FIG. 43 1A) generates the 6 drive for the push-pull output stage. Phase one output 7 pin PH1 is connected to sub-circuit AMPl pin GA1, second 8 phase output pin PH2 is connected to sub-circuit AMP2 pin 9 GA1. Output of amplifier buffer sub-circuit AMP1 pin GAP2 connects to gate of push-pull output switch Q6. Output of 11 amplifier buffer sub-circuit AMP2 pin GAP2 connects to 12 gate of push-pull output switch Q9. The buffering 13 currents from AMP1 and AMP2 provide fast, low impedance 14 critically damped switching to Q6 and Q9 greatly reducing ON-OFF transition time and switching losses. Regulated 16 18-volt power from sub-circuit CPA (FIG. 1A) pin CP2+ is 17 connected to amplifier buffer sub-circuit AMP1 pin GA+, 18 amplifier buffer sub-circuit AMP2 pin GA+ and sub-circuit 19 PPG pin PPG+. Drain of transistor Q6 is connected to snubber network sub-circuit SNB pin SNB1 and to non-21 saturating center tapped primary magnetic element sub-22 circuit PPTl pin P2H. Drain of transistor Q9 is connected 23 to snubber network sub-circuit SNA (FIG. 31) pin SNAl and 24 sub-circuit PPT1 pin P2L. Source of transistor Q6 is connected to snubber network sub-circuit SNB pin SNB2, 26 transistor Q9 source, sub-circuit SNA pin SNA2 and to 27 return node BR+. Isolated output of NSME sub-circuit PPT1 28 pin SH connects to Pin C7B of rectifier sub-circuit OUTA
29 (FIG. 25A), pin SL connects to sub-circuit OUTA CBB.
Center tap of PPT1 pin SCT is the output return or 31 negative node OUT- it connects to sub-circuit OUTA pin 32 OUT- and sub-circuit IFB (FIG. 40B) pin OUT- and RLOAD.

1 Converter positive output from sub-circuit OUTA pin OUT+
2 is connected to RLOAD and sub-circuit IFB pin OUT+.
3 Figure 1 elements LL1, BR, PFA, AMP, Q1, IPFFB, IFB and 4 PFT1 (input stage) perform power factor corrected AC to DC conversion. The regulated high voltage output of this 6 converter supplies the efficient fixed frequency/duty-7 cycle push-pull stage comprising PPG, AMP1, AMP2, Q6, Q9, 8 PPT1 and OUTA (FIG. 1A). Magnetic element sub-circuit 9 PPT1 provides galvanic isolation and minimal voltage overshoot and ripple in the secondary thus minimizing 11 filtering requirements of the rectifier sub-circuit OUTA.
12 Five volt reference output from sub-circuit PFA pin PFA2 13 connects to pin 15 then to FIG. 1A sub-circuit IPFFB pin 14 FBC and to sub-circuit IFB pin FBC. Pulse width control input from sub-circuit PFA pin PF1 connects to pin 14 16 then to FIG. 1A sub-circuit IPFFB pin FBE and to sub-17 circuit IFB pin FBE. Sub-circuit IFB provides high-speed 18 feedback to the AC DC converter, the speed of the boost 19 stage provides precise output voltage regulation and active ripple rejection. In the event of sudden line or 21 load changes, sub-circuit IPFFB corrects the internal 22 boost to maintain regulation at the isolated output.
23 Remote load sensing and other feedback schemes known in 24 the art may be implemented with sub-circuit IPFFB. This configuration provides power factor corrected input 26 transient protection, rapid line-load response, excellent 27 regulation, isolated output and quiet efficient operation 28 at high temperatures.
29 FIG. 2 is a schematic diagram of an embodiment of a DC to AC converter. The invention DCACl is an efficient 31 push-pull converter. Comprised of sub-circuits PPG (FIG.
32 43), AMP1 (FIG. 29), AMP2 (FIG. 29), SNB (FIG. 32), SNA

1 (FIG. 31), PPT1 (FIG. 19) and OUTA (FIG. 25), switches Q6 2 and Q9.
Figure Table Element Value/part number 3 Converter ACDC1 accepts variable DC voltage and 4 efficiently converts it to a variable AC voltage output at a fixed frequency. Variable frequency operation may be 6 achieved by simple changes to PPG. In this embodiment 7 fixed frequency operation is required. The magnetic 8 element comprises non-saturating magnetics. A graph of B-9 H hysteresis for the nori-saturating magnetics is set forth in FIG. 15. Variable DC voltage is applied to pin 11 DC+. The pin DC+ connects to the following, sub-circuit 12 PPT1 (FIG. 19) pin P2CT, snubber sub-circuit SNA (FIG.
13 31) pin SNA3, and snubber SNB (FIG. 32) pin SNB3.
14 Constant frequency non-overlapping two-phase generator sub-circuit PPG (FIG. 43) generates the drive for the 16 push-pull output switches. Phase one output pin PH1 is 17 connected to sub-circuit AMP1 pin GA1, the second phase 18 output pin PH2 is connected to sub-circuit AMP2 pin GA1.
19 Output of amplifier buffer sub-circuit AMP1 pin GAP2 connects to gate of push-pull output switch Q6. Output of 21 amplifier buffer sub-circuit AMP2 pin GAP2 connects to 22 gate of push-pull output switch Q9. The buffering 23 provided by AMP1 and AMP2 shortens switch Q1 ON and OFF
24 times greatly reducing switching losses (See FIG. 13 and 14). External regulated 18-volt power from pin P18V
26 connected to amplifier buffer sub-circuit AMP1 pin GA+, 27 amplifier buffer sub-circuit AMP2 pin GA+ and sub-circuit 1 PPG pin PPG+. Drain of transistor Q6 is connected to 2 snubber network sub-circuit SNB pin SNB1 and to non-3 saturating center tapped primary magnetic element sub-4 circuit PPT1 pin P2H. Drain of transistor Q9 is connected 5 to snubber network sub-circuit SNA (FIG. 31)' pin SNA1 and 6 sub-circuit PPT1 pin P2L. Source of transistor Q6 is 7 connected to snubber network sub-circuit SNB pin SNB2, 8 transistor Q9 source, sub-circuit SNA pin SNA2, sub-9 circuit AMP1 pin GAO, sub-circuit AMP2 pin GAO, sub-10 circuit PPG pin PPGO, and to return pin DC-. AC output of 11 NSME sub-circuit PPT1 pin SH connects to Pin ACH, pin SL
12 connects to pin ACL. Center tap of PPT1 pin SCT is 13 connected to pin ACO. Magnetic element sub-circuit PPT1 14 provides galvanic isolation and minimal voltage overshoot 15 in the secondary thus minimizing filtering requirements 16 if a rectifier assembly is attached. Sub-circuit DCAC1 17 may be used as a stand-alone converter or as a fast quiet 18 efficient stage in a multi stage converter system. Sub-19 circuit DCAC1 achieves isolated output, quiet operation, 20 efficient conversion, and operation at high and low 21 temperatures.
22 FIG. 3 and 3A is a three-stage version of the 23 present invention. The arrangement is comprised of an AC-24 DC or DC-DC boost converter stage, DC-DC forward

25 converter stage, and a push-pull stage. This system

26 reduces losses by combining low current buck regulation,

27 buffered switching, rectified snubbering, and NSME in

28 each stage . A power factor corrected boost stage is used

29 to assure that any load connected to the converter looks like a resistive load to the AC line, eliminating 31 undesirable harmonic and displacement currents in the AC
32 power line. NSME having a lower permeability compared to 1 the prior art are used to minimize magnetizing losses, 2 improve coupling e fficiency, minimize magnetic element 3 heating, eliminate saturated core current spikes/gap 4 leakage, reduce parts count, reduce thermal deterioration, and increase MTBF (mean time before 6 failure). The invention an emitter follower also uses 7 circuit with a high speed switching FET to slew the main 8 FET gate rapidly. The use of non- saturating magnetics 9 allows operation at higher voltages, which proportionally 10lowers current further reducing switch, magnetic element, 11 and conductor losses due to I2R heating. High voltage FET
12 switches have the added benefit of lower gate 13 capacitance, which translates to faster switching. At 14 turn on, the n-channel gate drive FET quickly charges the main FET gate. At turn off, a PNP Darlington transistor 16 switch quickly discharges the main FET gate. The flyback 17 effect in the PFC stage is managed by use of rectifying 18 RC networks positioned across the output diode with an 19 additional capacitor coupled diode across the switched magnetic element to decouple and further dampen the 21 inductive flyback. The invention is comprised of a power 22 factor corrected regulating boost stage with line 23 protection filter sub-circuit LL1 (FIG. 21) and full-wave 24 rectifier sub-circuit BR (FIG. 22) and capacitors C1 and C2. Sub-circuits PFB (FIG. 24), resistor R2, rectifier CP
26 (FIG. 26), magnetic element PFT1 (FIG. 18), over 27 temperature protection OTP (FIG. 28) snubber SN (FIG. 30) 28 gate buffer AMP (FIG. 29), switch transistors Q1, flyback 29 diode D4, holdup capacitors C17 and C16, bleed resistor R17, and voltage feedback sub-circuit FBA (FIG. 40A). An 31 efficient second pre-regulating buck stage with sub-1 circuits PWFM (FIG. 33), current sense resistor R26, 2 rectifier CPA (FIG. 27), magnetic element BL1 (FIG. 18B), 3 over voltage protection OVP (FIG. 42), IPFFB (FIG. 40) 4 gate buffer AMP3 (FIG. 29), switch transistor Q2, flyback diode D70, storage capacitor C4, and voltage feedback 6 sub-circuit IFB (FIG. 40B). An efficient third push-pull 7 isolation stage with sub-circuits CPA (FIG. 27), two-8 phase generator PPG (FIG. 43), gate buffers AMP1 (FIG.
9 29) and AMP2 (FIG. 29), switch transistors Q6, and Q9, snubbers SNA (FIG. 31) and SNB (FIG. 32), magnetic 11 element PPT1 (FIG. 19) and rectifier OUTA (FIG. 25).

Figure 3, 3a Table Element Value/part number C1 .Oluf C2 l.8uf R2 100k ohms D4 STA1206 Diode R17 375 k ohms C16 100uf C17 100uf R26 .05 ohms C4 l0uf Q6 FSl4Sm-18A

Q9 FSl4Sm-18A

14 AC line is connected to sub-circuit LLA (FIG. 21) between pins LLl and LL2. AC/earth ground is connected to 1 node LLO. The filtered and voltage limited AC line 2 appears on node/pin LL5 of sub-circuit LLA and connected 3 to node B R1 of bridge rectifier sub-circuit BR. The 4 neutral/AC return leg the filtered and voltage limited of AC appears on pin LL6 sub-circuit LL is connected to of 6 input pin BR2 of BR. The line voltage is full-wave 7 rectified and is converted to a positive haversine 8 appearing on node BR+ of sub-circuit BR. Start up 9 resistor R2 connects BR+ to sub-circuit CP pin CP+. Node CP+ connects to pins PFA+ of control element sub-circuit 11 PFB and over temperature switch sub-circuit OTP pin GAP.
12 Resistor R2 provides start up power to the control 13 element until the regulator CP is at full output. Node 14 S1H from PFT1 is connected to pin 31 (FIG. 3) then to pin CT1A of sub-circuit CP and pin PFVC of sub-circuit PFB.
16 The zero crossing of the core bias are sensed when the 17 voltage at S1H is at zero .relative to BR- . The core zero 18 crossings are used to reset the PFC and start a new 19 cycle. The positive node of the DC side of bridge BR+ is connected through capacitor C2 to BR-. Capacitor C2 is 21 selected for various line and load conditions to de-22 couple switching current from the line improving power 23 factor. Sub-circuit BR pin BR+ connects to pin SNL1 of 24 snubber sub-circuit SN, sub-circuit PFB pin BR+ and pin BR+ (FIG. 3A) then to primary of NSME sub-circuit PFT1 26 pin P1B and to sub-circuit OVP pin BR+. The return line 27 for the rectified AC power is connected to the following 28 pins; BR- of sub-circuit BR, sub-circuit PFT1 pin S1CT, 29 PFC sub-circuit PFB pin BR-, sub-circuit FBA pin BR-, capacitor C2, sub-circuit CP pin CTO, sub-circuit IPFFB
31 pin FBE, and through EMI filter capacitor C1 to earth 32 ground node LLO. Node BR- continues to FIG. 3A connecting 1 to R26, capacitors [C16~~C17~~R17], sub-circuit OVP pin 2 BR-, sub-circuit PWFM pin PWFMO, sub-circuit AMP3 pin 3 GAO, switch Q2 source. Floating ground node PF- is 4 connected to magnetic element sub-circuit PFT1 pin S2CT, rectifier sub-circuit CPA pin CT20, generator sub-circuit 6 PPG (FIG. 43) pin PPGO, sub-circuit AMP1 pin GAO, sub-? circuit AMP2 pin GAO, capacitor C4, magnetic element BL1 8 pin, transistor Q6 source, transistor Q9 source, sub-9 circuit SNA pin SNA2 sub-circuit SNB pin SNB2, pin PF-FIG. 3 then to sub-circuit IPFFB pin PF-. Drain of output 11 switch Q1 is connected to diode D4 anode, sub-circuit SN
12 pin SNL2, then to pin 34 of FIG. 3A then to sub-circuit 13 PFTl pin P1A. Snubber SN reduces the high voltage stress 14 to Q1 until flyback diode D4 begins conduction.
Additional rectification efficiency and protection is 16 achieved by adding sub-circuit DSN (FIG. 30A) across 17 flyback diode D4. Feedback corrected boost output voltage 18 of the power factor corrected AC to. DC converter stage 19 appears across nodes PF+ and PF-. The regulated 385-volt boost output node PF+ connects to the following; sub-21 circuit SN pin SNOUT, diode D4 cathode, sub-circuit IPFFB
22 (FIG. 40) pin PF+, sub-circuit FBA pin PF+, then to pin 23 PF+ of FIG. 3A, capacitors [C16~IC17IIR17], magnetic 24 element sub-circuit PTT1 (FIG. 19) pin P2CT, snubber sub-circuit SNA (FIG. 31) pin SNA3, and snubber SNB (FIG. 32) 26 pin SNB3, sub-circuit OVP pin PF+, capacitor C4 and diode 27 D70 cathode. Magnetic element winding node S1H of sub-28 circuit PFT1 is connected to pin 31 FIG. 3 then to sub-29 circuit CP pin CT1A and pin PFVC of sub-circuit PFB.
Magnetic element winding node S1L of sub-circuit PFT1 is 31 connected to pin 33 FIG. 3 then to sub-circuit CP pin 32 CT2A. Magnetic element winding node S2H of sub-circuit 1 PFT1 is connected to CPA pin CT1B. Magnetic element 2 winding node S2L of sub-circuit PFT1 is connected to CP
3 pin CT2B. Sub-circuit PFB using feedback from the phase 4 of the AC line, Q1 switch current, magnetic bias first 5 stage and output voltage feedback generates a command 6 pulse on pin PFCLK. Pin PFCLK of sub-circuit PFB (FIG.
7 24) is connected to the input of buffer AMP amplifier pin 8 GA1 of sub-circuit AMP1. Buffered high-speed low 9 impedance gate drive output pin GA2 of sub-circuit AMP is '10 connected to gate of switch FET Q1. The buffering 11 provided by AMP shortens switch Q1 "ON" and "OFF" times 12 greatly reducing switch losses (See Figures 13 and 14).
13 The source of Q1 is connected to sub-circuit AMP pin GAO, 14 pin 35 of FIG. 3A then to current sense resistor R26 15 connected to return node BR-. The voltage developed 16 across R26 is fed back to PFB pin PFSC. This signal is 17 used to protect the switch by reducing the pulse width in 18 response to a low line or high load induced over current 19 fault. The return line of sub-circuit FBA pin BR- is 20 connected to node BR- and to pin BR- of sub-circuit PFB.
21 This feedback is non-isolated; network values are 22 selected for the first stage to develop a 385-Volt output 23 at PF+.' Sub-circuit feedback network FBA (FIG. 40A) pin 24 PF1 is connected to sub-circuit PFB pin PF1. Controller 25 PFB modulates PFCLK signal to maintain a substantially 26 constant 385-voltage at PF+ independent of line and load 27 conditions. In the event of a component failure in sub-28 circuit FBA the PBF may command the converter to very 29 high voltages. Sub-circuit OVP monitors the first stage

30 boost in the event it exceeds 405-volts OVP will clamp

31 the output of sub-circuit BR causing fuse Fl in sub-

32 circuit LLA to open. An alternate over voltage network 1 OVP1 (FIG. 42A) may replace OVP clamping the 18-volt 2 control power stopping the boost action of the converter 3 without opening the fuse. Sampled converter output at 4 node from sub-circuit FBA pin PF1 is connected to sub-s circuit PFB pin PF1. The haversine on BR+ is used with an 6 internal multiplier by PFB to generate variable width 7 control pulses on pin PFCLK. The high frequency 8 modulation of switch Q1 makes the load/converter appear 9 resistive to the AC line. Over temperature protection sub-circuit OTP pin TS+ is connected to sub-circuit AMP
11~ pin GA+. Thermal switch THS1 is connected to Q1. In the 12 event Q1 reaches approximately 105C THSl opens removing 13 power to sub-circuit AMP, safely shutting down the first 14 stage. Normal operation resumes after the temperature decreases 20-30C closing THS1. The second stage is 16 configured as a buck stage. It accepts the 385-Volt 17 output of the first stage. By employing a second floating 18 reference node PF- energy storage element capacitor C4 19 the voltage to the final push-pull stage may be regulated with minimal loss. Power from sub-circuit CP pin CP18V+
21 is connected to pin 30 of FIG. 3A then to sub-circuit 22 PWFM (FIG. 33) pin PWM+ and AMP3 pin GA+. Feedback 23 current from sub-circuit IPFFB pin FBC is connected to 24 pin 36 FIG. 3A then to sub-circuit IFB pin FBC and sub-circuit PWFM pin PF1. Sub-circuit IPFFB only shunts 26 current from this node if the output of the second stage 27 is greater than 200-volts. when the converter reaches its 28 designed output voltage, IFB shunts current from PWFM pin 29 PF1 signaling PWFM to reduce the pulse width on pin PWMCLK. Sub-circuit AMP3 input pin is connected to sub-31 circuit PWFM pin PWMCLK. Output of AMP3 buffer pin GA2 is 32 connected to gate of switch Q2. Drain of Q2 is connected 1 to anode of D70 and non-saturating magnetic sub-circuit 2 BL1 pin P2B (FIG. 18B). Turning on switch Q2 charges C4 3 also storing energy in magnetic element BL1. Releasing 4 switch Q2 allows energy stored in magnetic element BL1 to charge C4 through flyback diode D70. Larger pulse widths 6 charge C4 to larger voltages thus efficiently blocking 7 part of the first stage voltage to the final push-pull 8 stage. This action provides regulated voltage to the 9 final converter stage. The third and final push-pull l0 (transformer) converter stage provides the galvanic 11 isolation, filtering and typically converts the internal 12 high voltage bus to a lower regulated output voltage. The 13 efficient push-pull stage produces alternating 14 magnetizing currents in the NSME for maximum load over core mass. Constant frequency non-overlapping two-phase 16 generator sub-circuit PPG (FIG. 43) generates the drive 17 for the push-pull output stage . Phase one output pin PH1 18 is connected to sub-circuit AMP1 pin GAl, output pin PH2 19 is connected to sub-circuit AMP2 pin GA1. Output of amplifier buffer sub-circuit AMP1 pin GAP2 connects to 21 gate of push-pull output switch Q6. Output of amplifier 22 buffer sub-circuit AMP2 pin GAP2 connects to gate of 23 push-pull output switch Q9. The buffering provided by 24 AMP1 and AMP2 shortens switch Q1 ON and OFF times greatly reducing switching losses. (See FIG. 13 and 14) Regulated 26 18-volt power from sub-circuit CPA pin CP18+ is connected 27 to amplifier buffer sub-circuit AMP1 pin GA+, amplifier 28 buffer sub-circuit AMP2 pin GA+ and sub-circuit PPG pin 29 PPG+. Drain of transistor Q6 is connected to snubber network sub-circuit SNB pin SNB1 and to non-saturating 31 center tapped primary magnetic element sub-circuit PPT1 32 pin P2H. Drain of transistor Q9 is connected to snubber

33 1 network sub-circuit SNA (FIG. 31) pin SNA1 and sub-2 circuit PPT1 pin P2L. Return node PF- connects source of 3 transistor Q6 to snubber network sub-circuit SNB pin 4 SNB3, transistor Q9 source, sub-circuit SNA pin SNA3 and to return node GND2. Output of NSME sub-circuit PPT1 pin 6 SH connects to pin C7B of rectifier sub-circuit OUTA
7 (FIG. 25), pin SL connects to CBB. Center tap of PPT1 pin 8 SCT is the output return or negative node OUT- it 9 connects to sub-circuit pin OUT- and sub-circuit IFB pin OUT- and RLOAD. Supply positive output from sub-circuit 11 OUTA pin OUT+ is connected to RLOAD and sub-circuit IFB
12 pin OUT+. Elements LL1, BR, PFA, AMP, Ql, IPFFB, IFB and 13 PFT1 provide power factor corrected AC to DC conversion 14 and DC output regulation. The regulated high voltage output of this converter is used to power the efficient 16 fixed frequency push-pull stages PPG, AMP1, AMP2, Q6, Q9, 17 PPT1 and OUTA. Magnetic element sub-circuit PPT1 provides 18 galvanic isolation and minimal voltage overshoot in the 19 secondary thus minimizing filtering requirements of the rectifier sub-circuit OUTA. Sub-circuit IFB provides 21 high-speed feedback to the AC DC converter, the speed of 22 the boost stage provides precise output voltage 23 regulation and active ripple rejection. In the event of a 24 sudden line or load changes sub-circuit IPFFB compensates the internal boost. This system reduces losses by 26 focusing output control in the middle (low current) stage 27 of the converter and by using non-saturating magnetics, 28 buffered switching, and. rectifying snubbers throughout 29 each stage. The combined improvements translate to higher system efficiencies, higher power densities, lower 31 operating temperatures, and, improved thermal tolerance 32 thereby reducing or eliminating the need for forced air-

34 1 cooling per unit output. The non-saturating magnetic 2 properties are relatively insensitive to temperature (see 3 FIG. 17), thus allowing the converter to operate over a 4 greater temperature range. In practice, the operating temperature for the Kool Mu NSME is limited to 200C by 6 wire/core insulation; the non-saturating magnetic 7 material remains operable to near its Curie temperature 8 of 500C. This configuration provides power factor 9 corrected input transient protection, rapid line-load and ripple compensation, excellent output regulation, output 11 isolation and quiet efficient operation at high 12 temperatures.
13 FIG. 4 is a schematic diagram of a power factor 14 corrected single stage AC to DC converter sub-circuit ACDCPF. The invention is comprised of line protection 16 filter sub-circuit LL (FIG. 20) and full-wave rectifier 17 sub-circuit BR (FIG. 22). A power factor corrected 18 regulated boost stage with sub-circuits PFB (FIG. 24), 19 snubber sub-circuit SN (FIG. 30), magnetic element sub-circuit PFT1A (FIG. 18A), sub-circuit CP (FIG. 26), 21 buffer sub-circuit AMP (FIG. 29), over temperature sub-22 circuit OTP (FIG. 28), and voltage feedback sub-circuit 23 FBA (FIG. 40A). Start up resistor R2, filter capacitor 24 C1, PFC capacitor C2, flyback diode D4, switch transistor Q1, hold up capacitors C17 and C16, and resistor R17.

Figure Table Element Value/part number C1 .Oluf C2 l.8uf R2 100k ohms R26 0.05 ohms DI

C17 100uf C16 100uf R17 375k ohms 1 AC line is connected to sub-circuit LL (FIG. 20) 2 between pins LL1 and LL2. AC/earth ground is connected to 3 node LLO. The filtered and voltage limited AC line 4 appears on node/pin LL5 of sub-circuit LL1 and connected 5 to node BRl of bridge rectifier sub-circuit BR (FIG. 22).
6 The neutral/AC return leg of the filtered and voltage 7 limited AC appears on pin LL6 of sub-circuit LL is 8 connected to input pin BR2 of BR. The line voltage is 9 full-wave rectified and is converted to a positive 10 haversine appearing on node BR+ of sub-circuit BR (FIG.
11 22). Start up resistor R2 connects BR+ to sub-circuit CP
12 pin CP+. Node CP+ connects to pins PFA+ of power factor 13 controller sub-circuit PFA (FIG. 24) and over temperature 14 switch sub-circuit OTP (FIG. 28) pin GAP., Resistor R2 15 provides start up power to the control element until the 16 rectifier and regulator CP is at full output. Node S1H
17 from PFT1A is connected to node PFVC sub-circuit PFB. The 18 zero crossing of the core bias are sensed when the 19 voltage at S1H is at zero. The core zero crossings are 20 used to reset the PFC and start a new cycle. The positive 21 node of the DC side of bridge BR+ is connected through 22 capacitor C2 to BR- . C2 is selected for various line and 23 load conditions to de-couple switching current from the 24 line improving power factor. Primary of NSME sub-circuit 1 PFT1A (FIG. 18A) pin P1B connects to pin SNL1 of snubber 2 sub-circuit SN (FIG. 30), sub-circuit PFB pin BR+ and 3 connects to node BR+. The return line for the rectified 4 AC power BR- is connected to the following pins; BR- of sub-circuit BR, sub-circuit PFB pin BR-, sub-circuit AMP
6 pin GAO, sense resistor R26, capacitor [C16~~C17 7 Ilresistor R17], capacitor C2, sub-circuit CP pin CTO, 8 sub-circuit PFT1A pin S1CT and through EMI filter 9 capacitor C1 to earth ground node LLO. Drain of output switch Q1 is connected to diode D4 anode, sub-circuit 11 PFT1A pin P1A and snubber sub-circuit SN pin SNL2.
12 Additional rectification efficiency and protection is 13 achieved by adding sub-circuit DSN (FIG. 30A) in parallel 14 flyback diode D4. Sub-circuit provides reduces the high voltage stress to Q1 until flyback diode D4 begins 16 conduction. Line coupled, power factor corrected boost 17 regulated output voltage of the AC to DC converter stage 18 (FIG. 1) appears on node PF+. The regulated boost output 19 PF+ connects to the following; sub-circuit SN pin SNOUT, diode D4 cathode, capacitor [C16~~C17~~R17], and snubber 21 DSN (FIG. 30A) pin SNOUT. Magnetic element winding node 22 S1H of sub-circuit PFT1A is connected to CP pin CT1A and 23 pin PFVC of sub-circuit PFB. Magnetic element winding 24 node S1L of sub-circuit PFT1A is connected to CP pin CT2A. Sub-circuit PFB using the phase of the AC line, and 26 load voltage generates a command pulse PFCLK. Pin PFCLK
27 of sub-circuit PFB (FIG. 24) is connected to the input of 28 buffer amplifier pin GA1 of sub-circuit AMP1 (FIG. 29).
29 Buffered high-speed gate drive output pin GA2 of sub-circuit AMP is connected to gate of switch FET Q1. The 31 buffering provided by AMP shortens switch Q1 ON and OFF
32 times greatly reducing switch losses. The source of Q1 is 1 connected to current sense resistor R26, pin PFSC of sub-2 circuit PFB, connected then to return node BR-. The 3 voltage developed across R26 is feedback to PFB pin PFSC.
4 This signal is used to protect the switch in the event of an over current fault. Thermal switch THS1 is connected 6 to Q1. In the event Ql reaches approximately 105C THS1 7 opens removing power to sub-circuit AMP, safely shutting 8 down the first stage. Normal operation resumes after the 9 switch temperature drops 20-30C closing THS1. Sub-circuit feedback network FBA (FIG. 40A) pin PF1 is connected to 11 sub-circuit PFB pin PF1. Converter output at node PF+
12 (the junction of [C17 ~ ~ C16] and D4) is connected to sub-13 circuit FBA pin PF+. The return line of sub-circuit FBA
14 pin BR- is connected to pin BR- of sub-circuit PFB. This feed back is non-isolated; network values are selected 16 for a substantially constant 385-Volt output at PF+
17 relative to BR-. The high-voltage haversine from the 18 rectifier section BR pin BR+ is connected to sub-circuit 19 PFB pin BR+. The haversine is used with an internal multiplier by PFB to make the converter ACDCPF appear 21 resistive to the AC line. Sub-circuits LL1, BR, PFB, AMP, 22 Q1, OTP, FBA, IFB and PFT1A perform power factor 23 corrected AC to DC conversion. The regulated high voltage 24 output of this converter may be used use to power one or more external converters connected to the PF+ and BR-26 nodes. The NSME sub-circuit PPTlA provides efficient 27 boost action at high power levels in a very small form 28 factor. Sub-circuit FBA provides high-speed feedback to 29 the converter the speed of the boost stage provides precise output voltage regulation and active ripple 31 rejection. This configuration provides power factor 32 corrected input transient protection, rapid line-load 1 response, excellent regulation, and quiet efficient 2 operation at high temperatures.
3 FIG. 4A is a schematic diagram of a power factor 4 corrected converter with auto load leveling sub-circuit ACDCPF1. The invention is comprised of line filter sub-6 circuit LF (FIG. 20A), fast start sub-circuit FS1 (FIG.
7 45), transient diodes D460, D461, and D462 (FIG. 46) and 8 inrush limiter sub-circuit SS1 (FIG. 44). A power factor 9 corrected regulated boost stage with sub-circuits PFB
(FIG. 24), snubber sub-circuit SNBB (FIG. 30B), magnetic 11 element sub-circuit PFT1A (FIG. 18A), sub-circuit CP1 12 (FIG. 26A), buffer sub-circuit AMP (FIG. 29), over 13 temperature sub-circuit OTP (FIG. 28), over voltage sub-14 circuit FB2 (FIG. 41A), and voltage feedback sub-circuit FBD (FIG. 40D). Auto load-leveling resistor 8345, filter 16 capacitor C1, PFC capacitor C2, flyback diode D4, switch 17 transistor Q1, hold up capacitors C442 and C417.
Figure Table Element Value/part number C1 .Oluf C2 l.8uf R26 0.05 ohms C442 330 of C417 0.58 of 8345 1 MEG ohms 18 AC line is connected to sub-circuit LF (FIG. 20A) 19 between nodes LL1 and LL2. AC/earth ground is connected to node LLO. The filtered and rectified AC line appears 1 on pin BR+ of sub-circuit LF connects to anode of 2 transient diodes D460-462. Cathode of diodes D460-462 3 connects to node PF+ and main storage capacitor C442.
4 The line voltage is full-wave rectified converted to a positive haversine appearing on node B+ of sub-circuit LF
6 (FIG. 20A). Node B+ of filter sub-circuit LF is 7 connected to input pin BR2 of PFB (FIG. 24) , positive of 8 C2, pin PB1 of PFT1A, pin B+ of SS1. Capacitor C2 is 9 selected for various line and load conditions to de-couple switching current from the line improving power 11 factor. Fast start sub-circuit FS1 node TP17 connects to 12 sub=circuit CP1 pin TP17. Node VCC of CP1 connects to 13 pin PFA+ of power factor controller sub-circuit PFA (FIG.
14 24), auto load leveling resistor 8345 connects to pin PF1 of PFB and PF1 of FBD. VCC of FS1 connects to over 16 temperature switch sub-circuit OTP (FIG. 28) pin GAP.
17 Fast start FS1 provides start up power until the 18 converter is at full power. It also provides control 19 power in the event of an extended loss of boost. Node S1H from PFT1A is connected to node PFVC sub-circuit PFB.
21 The zero crossing of the core bias are sensed when the 22 voltage at SH1 is at zero. The core zero crossings are 23 used to reset U1B and start a new cycle . Primary of NSME
24 sub-circuit PFT1A (FIG. 18A) pin P1B connects to pin SNL2 of snubber sub-circuit SNBB (FIG. 30B), sub-circuit PFB
26 pin BR+ and connects to node B+. Return line for the 27 rectified AC power BR- is connected to the following 28 pins; BR- of sub-circuit LF, sub-circuit PFB pin BR-, 29 sub-circuit AMP pin GAO, sub-circuit SS1 pin BR-, sense resistor R26, sub-circuit SS1 pin BR-, capacitors C417 31 and C2, sub-circuit CP1 pin CTO, sub-circuit FB2 pin BR-, 32 sub-circuit FBD pin BR-, sub-circuit FS1 pin BR-, sub-1 circuit PFTlA pin S1CT and through EMI filter capacitor 2 C1 to earth ground node LLO. Drain of output switch Q1 is 3 connected to diode D4 anode, sub-circuit PFT1A pin P1A
4 and snubber sub-circuit SNBB pin SNL2. Switch protection 5 is achieved by adding sub-circuit SNBB (FIG. 30B) in 6 parallel flyback diode D4. Sub-circuit SNBB provides 7 reduces the high voltage stresses to Q1 until flyback 8 diode D4 begins conduction. Regulated output voltage of 9 the converter appears on node PF+. The regulated boost 10 output PF+ connects to the following; sub-circuit SNBB
11 pin SNOUT, diode D4 cathode, capacitor C417, sub-circuit 12 FS1 pin PF+, sub-circuit SS1 pin PF+, and diode D460-462 13~ cathodes. Magnetic element winding node S1H of sub 14 circuit PFT1A is connected to CP1 pin CT1A and pin PFVC
15 of sub-circuit PFB. Magnetic element winding node S1L of 16 sub-circuit PFT1A is connected to CP1 pin CT2A. Sub 17 circuit PFB using the phase of the AC line, and load 18 voltage generates a command pulse PFCLK. Pin PFCLK of 19 sub-circuit PFB (FIG. 24) is connected to the input of 20 buffer amplifier pin GA1 of sub-circuit AMP1 (FIG. 29).
21 Buffered high-speed gate drive output pin GA2 of sub 22 circuit AMP is connected to gate of main switch Q1. The 23 buffering provided by AMP shortens switch Q1 "ON" and 24 "OFF" times greatly reducing switch losses. The source of 25 Q1 is connected to current sense resistor R26, pin PFSC
26 of sub-circuit PFB, connected then to return node BR-.
27The voltage developed across R26 is feedback to PFB pin 28PFSC. This signal is used to protect the switch in the 29event of an over current Thermal switch THS1 is fault.

30thermally connected to Q1. In the event Q1 reaches 31approximately 105C THS1 removing power to sub-opens 32circuit AMP, safely shutting down boost operation.

1 Normal operation resumes after the switch temperature 2 drops 20-30C closing THS1. Sub-circuit feedback network 3 FBD (FIG. 40D) pin PF1 is connected to sub-circuit PFB
4 pin PF1. Sub-circuit feedback network FB2 (FIG. 41A) pin PF2 is connected to sub-circuit PFB pin PF2. This feed 6 back is non-isolated; network values are selected for a 7 substantially constant 385-Volt output at PF+ relative to 8 BR-. The high-voltage haversine from the rectifier 9 section pin B+ is connected to sub-circuit PFB pin HR+.
The haversine is used with an internal multiplier by PFB
11 to make the converter ACDCPF1 appear resistive to the AC
12 line. The regulated high voltage output of this 13 converter may be used use with one or more external 14 converters connected in parallel. A unique feature of the converter ACDCPF1 is the automatic load-sharing feature.
16 Where the signal VCC varies as a function of load as 17 shown in FIG. 26B. Load leveling resistor connected 18 between nodes VCC and PF1 regulates the output voltage 19 lower as the load/boost increases. This unique action allows units to be operated in parallel with out the 21 typical master slave connections. In this way the 22 lightly loaded converter will increase it's output 23 voltage thus accepting more load. Like wise the heavy 24 loaded converter will reduce voltage, automatically shedding load to parallel converters. In this way any 26 number of converters may be connected in parallel for 27 high power or redundant applications. In the prior art 28 master/slave configuration, loss of the master unit is 29 catastrophic. In the instant invention failure or removal of a unit causes the remaining unit/units to 31 assume the additional load. The NSME sub-circuit PPTlAl 32 provides efficient boost action at high power levels in a 1 very small form factor. Inrush limiter sub-circuit SS1 2 allows "hot swapping" with minimal system disturbance.
3 The unique magnetic features allow full power operation 4 at temperature ranges were common art converters can not.
Providing high power factor, transient protection, low 6 inrush currents, excellent regulation, automatic recovery 7 from fault conditions and quiet efficient operation at 8 temperature extremes.
9 FIG. 5 is a graph comparing typical currents in saturating and non-saturating magnetic elements. As the 11 inductance does not radically change at high temperatures 12 and currents in the NSME, the large current spikes due to 13 the rapid reduction of inductance common in saturating 14 magnetics is not seen. As a result, destructive current levels, excessive gap leakage, magnetizing losses, and 16 magnetic element heating are avoided in NSME.
17 FIG. 6 is a schematic for non-isolated low side 18 switch buck converter sub-circuit NILBK. Sub-circuit 19 NILBK consists of resistor R20, diode D6, capacitor C6, FET transistor Q111, sub-circuit CP (FIG. 26), sub-21 circuit PFT1A (FIG. 18A), sub-circuit IFB (FIG. 408), 22 sub-circuit AMP (FIG. 29) and sub-circuit PWFM (FIG. 33).

Figure 6 Table Element Value/part number R20 100k ohms C6 l0uf 24 External power source VBAT connects to pins DCIN+
and DCIN-. From DCIN+ through resistor R20 connects to 1 sub-circuit CP pin CP+, sub-circuit AMP pin GA+ and to 2 sub-circuit PWFM pin PWFM+. Resistor R20 provides startup 3 power to the converter before regulator sub-circuit CP
4 reaches it full 18-volt output. VBAT negative is connected to pin DCIN- connects to sub-circuit PWFM pin 6 PWFMO, sub-circuit AMP pin GAO, Q111 source, sub-circuit 7 IFB pin FBE, sub-circuit CP pin CTO, and sub-circuit PFT1 8 pin S1CT. Magnetic element winding node S1H of sub-9 circuit PFT1A is connected to CP pin CT1A. Magnetic element winding node S1CT of sub-circuit PFT1 is 11 connected to CP pin CTO. Magnetic element winding node 12 S1H of sub-circuit PFT1A is connected to CP pin CT2A. The 13 regulated 18 volts from sub-circuit CP+ is connected to 14 R20, sub-circuit AMP pin GA+ and to sub-circuit PWFM pin PWFM+. Sub-circuit PWFM is designed for variable pulse 16 width operation. PWFM is configured for maximum pulse 17 width 90-95% with no feedback current from sub-circuit 18 IFB pin FBC. Increasing the feedback current reduces the 19 pulse-width and output voltage from converter NILBK. Sub-circuit PWFM clock/PWM output pin CLK is connected to the 21 input pin GA1 of buffer sub-circuit AMP. The output of 22 sub-circuit AMP pin GA2 is connected to the gate of Q111.
23 Input node DCIN+ connects to the cathode of flyback diode 24 D6, sub-circuit IFB pin OUT+, resistor RLOAD, capacitor C6 and pin B+. The drain of Q111 is connected to sub-26 circuit PFT1 pin P1B and the anode of D6. Pin P1A of sub-27 circuit PFT1A is connected to capacitor C6, RLOAD, sub-28 circuit IFB pin OUT- and to node B-. With sub-circuit 29 PWFM pin CLK high buffer AMP output pin GA2 charges the gate of transistor switch Q111. Switch Q111 conducts 31 charging capacitor C10 through NSME PFT1A from source 32 VBAT and storing energy in PFT1A. Feedback output pin FBC

1 from sub-circuit IFB is connected to sub-circuit PWFM
2 pulse-width adjustment pin PW1. Sub-circuit IFB removes 3 current from PW1 commanding PWFM to reduce the pulse-4 width or on time of signal CLK. After sub-circuit PWFM
reaches the commanded pulse-width PWFM switches output 6 pin CLK low turning "off" Q111 stopping the current into 7 PFT1A. The energy not transferred into regulator sub-8 circuit CP load is released from NSME PFTlA into the now 9 forward biased diode D6 charging capacitor C6. By modulating the "on" time of switch Q111 the converter 11 buck voltage is regulated. Regulated voltage is developed 12 across Nodes B- and B+. Sub-circuit IFB provides the 13 isolated feedback voltage to the sub-circuit PWFM. When 14 sub-circuit IFB senses the converter output (nodes B+ and B-) is at the designed voltage, current from REF is 16 removed from PM1. Sinking current from PM1 commands the 17 PWFM to a shorter pulse-width thus reducing the converter 18 output voltage. In the event the feedback signal from IFB
19 commands the PWFM to minimum output. Gate drive to switch Q111 is removed stopping all buck activity capacitor C6 21 discharges through RLOAD. Input current from VBAT is 22 sinusoidal making-the converter very quiet. In addition 23 the switch Q111 is not exposed to large flyback voltage.
24 Placing less stress on the switches thereby increasing the MTBF. Sub-circuit NILBK takes advantage of the 26 desirable properties of the NSME in this converter 27 topology. Adjusting the NSME 100 (FIG. 18A) primary 28 inductance and component values in sub-circuit IFB
29 determines the output buck voltage.
FIG. 8 is a schematic for a tank coupled single 31 stage converter sub-circuit TCTP. Sub-circuit TCTP
32 consists of resistor R20 and RLOAD, capacitor C10, 1 Darlington transistors Q10 and Q20, sub-circuit CP (FIG.
2 26), sub-circuit PFT1 (FIG. 18), sub-circuit OUTB (FIG.
3 25A), sub-circuit IFB (FIG. 40B) and sub-circuit PWFM
4 (FIG. 33).
S
Figure 8 Table Element Value/part number R20 5k ohms C10 l.8uf 7 External power source VBAT connects to pins DCIN+
8 and DCIN-. From DCIN+ connects to Q10 collector then 9 through resistor R20 connects to sub-circuit CP pin CP+
10 and to sub-circuit PWFM pin PWFM+. Resistor R20 provides 11 startup power to the converter before regulator sub-12 circuit CP reaches it full 18-volt output. VBAT negative 13 is connected to pin DCIN- ground/return node GND. Node 14 GND connects to sub-circuit PWFMO pin PWFMO, Q20 15 collector, C10, sub-circuit CP pin CTO and sub-circuit 16 PFT1 pin S1CT. Magnetic element winding node S1H of sub-17 circuit PFTl is connected to CP CT1A. Magnetic element 18 winding node S1L of sub-circuit PFT1 is connected to CP
19 CT2A. Magnetic element winding node S1CT of sub-circuit 20 PFT1 is connected to CP pin CTO. Magnetic element winding 21 node S2H of sub-circuit PFT1 is connected to CP pin CT2A.
22 The regulated 18-volts from sub-circuit CP+ is connected 23 to R20 and to sub-circuit PWFM pin PWFM+. Sub-circuit 24 PWFM is designed for a constant 50% duty cycle variable 25 frequency generator. Sub-circuit PWFM clock output pin 1 CLK is connected to. the base of Q10 and Q20. The emitters 2 of Q10 and Q20 are connected to sub-circuit PFT1 pin P1B.
3 This forms an emitter follower configuration. Pin P1A of 4 sub-circuit PFT1 is connected through tank capacitor C10 to node GND. With PWFM CLK pin high forward biased 6 transistor Q10 supplies current to the tank from HAT1 7 charging capacitor C10 through NSME PFT1 and transferring 8 energy into PFT1. Sub-circuit PWFM switches CLK low 9 turning "off" Q10 stopping the current into PFT1. Energy not transferred into the load is released from NSME PFTl 11 into the now forward biased PNP transistor Q20 back into 12 capacitor C10. Thus any energy not used by the secondary 13 loads is transferred back to the primary tank to be used 14 next cycle. When the switching occurs at the resonant frequency large circulating currents develop in the tank.
16 Also C10 is charged and discharged to very large 17 voltages. Oscillograph in FIG. 35 is the actual voltage 18 developed across capacitor C10 with VBAT equal to 18 19 volts . A very large 229-Volts peak to peak was developed across the nodes P1A and P1A of NSME PFT1. The large 21 primary voltage generates large biases in the NSME PFT1 22 to be flux harvested by the windings 102 and 103 (FIG.
23 18) and transferred to a load or rectifier sub-circuit 24 OUTB. Magnetic element winding node S2L of sub-circuit PFT1 is connected to OUTB CBb. Magnetic element winding 26 node S2H of sub-circuit PFT1 is connected to C7B of sub-27 circuit OUTB node OUT-. Node OUT- is connected to RLOAD, 28 pin B- and to sub-circuit IFB pin OUT-. Rectified power 29 is delivered to pin OUT+ of OUTB and is connected to RLOAD, pin B+ and to sub-circuit IFB pin OUT+. Sub-31 circuit IFB provides the isolated feedback signal to the 32 sub-circuit PWFM. Frequency control pin FM1 of sub-1 circuit PWFM is connected to sub-circuit IFB pin FBE.
2 Internal reference pin REF of sub-circuit PWFM is 3 connected to sub-circuit IFB pin FBC. PWFM is designed to 4 operate at the resonate frequency of the tank. When sub-s circuit IFB senses the converter output is at the 6 designed voltage, current from REF is injected into FMl.
7 Injecting current into FM1 commands PWFM to a lower 8 frequency. Operating below resonance reduces the amount 9 of energy added to the primary tank thus reducing the converter output voltage. In the event the feedback 11 signal from IFB commands the PWFM to 0-Hz all primary 12 activity stops. Input current from VBAT is sinusoidal 13 making the converter very quiet. In addition the switches 14 Q10 and Q20 are never exposed to the large circulating voltage (FIG. 35). Placing less stress on the switches 16 thereby increasing the MTBF. Sub-circuit TCTP takes 17 advantage of the desirable properties of the NSME in this 18 converter topology. Adjusting secondary turns allows TCTP
19 to generate very large AC or DC output voltages as well as low-voltage high current outputs.
21 FIG. 9 is a schematic for non-isolated low side 22 switch boost converter sub-circuit NILSBST. Sub-circuit 23 NILSBST consists of resistor R20 and RLOAD, diode D6, 24 capacitor C6, FET transistor Q111, sub-circuit CP (FIG.
26), sub-circuit PFT1A (FIG. 18A), sub-circuit FBI (FIG.
26 41), sub-circuit AMP (FIG. 29) and sub-circuit PWFM (FIG.
27 3 3 ) .
Figure 9 Table Element Value/part number R20 100k ohms C6 200uf 1 External power source VBAT connects to pins DCIN+
2 and DCIN-. From DCIN+ Resistor R20 connects to sub-3 circuit CP pin CP+, sub-circuit AMP pin GA+ and to sub-4 circuit PWFM pin PWFM+. Resistor R20 provides startup power to the converter before regulator sub-circuit CP
6 reaches it full 18-volt output. VBAT negative is 7 connected to pin DCIN- and ground return node GND. Node 8 GND connects to sub-circuit PWFM pin PWFMO, sub-circuit 9 AMP pin GAO, Q111 source, sub-circuit FBA pin BR-, sub-circuit FBA pin FBA, sub-circuit CP pin CTO, capacitor 11 C6, resistor RLOAD, transistor Q111 source, and sub-12 circuit PFT1 pin S1CT. Magnetic element winding node S1H
13 of sub-circuit PFT1A is connected to CP pin CT1A.
14 Magnetic element winding node S1CT of sub-circuit PFT1 is connected to CP pin CTO. Magnetic element winding node 16 S2H of sub-circuit PFT1A is connected to CP pin CT2A. The 17 regulated 18 volts from sub-circuit CP+ is connected to 18 R20, sub-circuit AMP pin GA+. and to sub-circuit PWFM pin 19 PWFM+. Sub-circuit PWFM is designed for variable pulse width operation. PWFM is configured for maximum pulse 21 width 90-95% (maximum boost voltage) with no feedback 22 current from sub-circuit FBI. Increasing the feedback 23 current reduces the pulse-width' reducing the boost 24 voltage and reducing the output from converter NILSBST.
Sub-circuit PWFM clock/PWM output pin CLK is connected to 26 the input pin GA1 of buffer sub-circuit AMP. The output 27 of sub-circuit AMP pin GA2 is connected to the gate of 28 Q111. Input node DCIN+ connects to the NSME PFT1A pin 29 P1A. The drain of Q11 is connected to sub-circuit PFT1A

1 pin P1B and the anode of D6. Cathode of diode D6 is 2 connected to sub-circuit FBA pin PF+, resistor RLOAD, C6 3 and pin BK+. With sub-circuit PWFM pin CLK high ,buffer 4 AMP output pin GA2 charges the gate of transistor switch Q111. Switch Q111 conducts reverse biasing diode D6 6 capacitor C10 stops charging through NSME PFT1A from 7 source VBAT. During the time Q111 is conducting, energy 8 is stored in NSME sub-circuit PFT1A. Feedback output pin 9 FBC from sub-circuit FBI is connected to sub-circuit PWFM
pulse-width adjustment pin PW1. Sub-circuit FBI removes 11 current from PW1 commanding PWFM to reduce the pulse-12 width or on time of signal CLK. After sub-circuit PWFM
13 reaches the commanded pulse-width PFFM switches CLK low 14 turning "off" Q111 stopping the current into PFTlA. The energy not transferred into regulator sub-circuit CP load 16 is released from NSME PFT1A into the now forward biased 17 diode D6 charging capacitor C6. By modulating the "on"
18 time of switch Q111 the converter boost voltage is 19 regulated. Regulated voltage is developed across Nodes B-and B+. Sub-circuit IFB provides the feedback current to 21 the sub-circuit PWFM. When sub-circuit IFB senses the 22 converter output (nodes B+ and B-) is at or greater than 23 the designed voltage, current is removed from PMl.
24 Sinking current from PM1 commands the PWFM to a shorter pulse-width thus reducing the converter output voltage.
26 In the event the feedback signal from IFB commands the 27 PWFM to minimum output. Gate drive to switch Q111 is 28 removed stopping all boost activity capacitor C6 charges 29 to VBAT. Input current from VBAT is sinusoidal making the converter very quiet . In addition the switch Q111 is not 31 exposed to large flyback voltage. Placing less stress on 32 the switches thereby increasing the MTBF. Sub-circuit 1 NILBK takes advantage of the desirable properties of the 2 NSME in this converter topology. Adjusting the NSME 100 3 (FIG. 18A) primary inductance and component values in 4 sub-circuit IFB determines the output boost voltage.
5 FIG. 10 is a schematic for a two stage isolated DC
6 to DC boost controlled push-pull converter BSTPP. Sub-7 circuit BSTPP consists of diode D14, capacitor C14, FET
8 transistor Q14, sub-circuit REG (FIG. 36), sub-circuit 9 BL1 (FIG. 18B), sub-circuit IFB (FIG. 40B), sub-circuit 10 AMP (FIG. 29), sub-circuit DCAC1, and sub-circuit PWFM
11 (FIG. 33). External power source VBAT connects to pins 12 DCIN+ and DCIN-.
Figure 10 Table Element Value/part number C14 l0uf 13 From pin DCIN+ connects to sub-circuit REG pin RIN+
14 andsub-circuitBLl pin PlA. Voltage regulator sub-circuit 15 output pin +18V connects to sub-circuit AMP pin GA+ and-16 to sub-circuit PWFM pin PWFM+. Sub-circuit REG provides 17 regulated low voltage power to the controller and to the 18 main switch buffers. VBAT negative is connected to pin 19 DCIN- and ground return node GND. Node GND connects to 20 sub-circuit PWFM pin PWFMO, sub-circuit AMP pin GAO, Q14 21 source, capacitor C14, sub-circuit IFB pin FBE, sub-22 circuit REG pin REGO, sub-circuit DCAC1 pin DC-. Sub-23 circuit PWFM (FIG. 33) is designed for variable pulse 24 width operation. The nominal frequency is between 20-25 600Khz PWFM is configured for maximum pulse width 90%
26 (maximum boost voltage) with no feedback current from 1 sub-circuit FBI. Increasing the feedback current reduces 2 the pulse-width reducing the boost voltage and reducing 3 the output from converter BSTPP. Sub-circuit PWFM
4 clock/PWM output pin CLK is connected to the input pin GA1 of buffer sub-circuit AMP (FIG. 29). The output of 6 switch speed up buffer sub-circuit AMP pin GA2 is 7 connected to the gate of Q14. Input node DCIN+ connects 8 to the NSME BL1 pin P1A. The drain of Q14 is connected to 9 sub-circuit BL1 pin P1B and the anode of D14. Cathode of flyback diode D14 is connected to sub-circuit DCAC1 pin 11 DC+ and C14. With sub-circuit PWFM pin CLK high buffer 12 AMP output pin GA2 charges the gate of transistor switch 13 Q14. Switch Q14 conducts reverse biasing diode D14 14 capacitor C14 stops charging through NSME BL1 from source VBAT. During the time Q14 is conducting, energy is stored 16 in NSME sub-circuit BL1. Feedback output pin FBC from 17 sub-circuit IFB is connected to sub-circuit PWFM pulse-18 width adjustment pin PW1. Sub-circuit IFB removes current 19 from PW1 commanding PWFM to reduce the pulse-width or "on" time of signal CLK. After sub-circuit PWFM reaches 21 the commanded pulse-width PFFM switches CLK low turning 22 "off" Q14 stopping the current into BL1. The energy is 23 released from NSME BL1 into the now forward biased 24 flyback diode D14 charging capacitor C14. By modulating the "on" time of switch Q14 the converter boost voltage 26 is regulated. Regulated voltage is developed across C14 27 Nodes DC+ and GND is provided to the isolated constant 28 frequency push-pull DC to AC converter sub-circuit DCAC1 29 (FIG. 2). Sub-circuit DCACl provides efficient conversion of the regulated boost voltage to a higher or lower 31 voltage set by the magnetic element-winding ratio. The 32 center tap of the push-pull output magnetic is connected 1 to, sub-circuit OUTB pin OUT-, RLOAD, sub-circuit IFB pin 2 OUT- and the pin OUT- forming the return line for the 3 load and feedback network. Output of sub-circuit DCAC1 4 pin ACH is connected to sub-circuit OUTB pin C7b. Output of sub-circuit DCAC1 pin ACL is connected to sub-circuit 6 OUTB pin CBb. Sub-circuit OUTB provides rectification of 7 the AC power generated by sub-circuit DCAC1. Since the 8 non-saturating magnetic converter has low output ripple, 9 minimal filtering is required by OUTB. This further reduces cost and improves efficiency as losses to filter 11 components are minimized. Sub-circuit IFB provides the 12 isolated feedback current to the sub-circuit PWFM. When 13 sub-circuit IFB senses the converter output (nodes OUT+
14 and OUT-) is greater than the designed/desired voltage, current is removed from node PM1. Sinking current from 16 PM1 commands the PWFM to a shorter pulse-width thus 17 reducing the converter output voltage. In the event the 18 feedback signal from IFB commands the PWFM to minimum 19 output. Gate drive to switch Q14 is removed stopping all boost activity capacitor C14 charges to VBAT. As the non-21 saturating does not saturate the destructive noisy 22 current "spikes" common to prior art are absent. Input 23 current from VBAT to charge C14 is sinusoidal making the 24 converter very quiet. In addition the switch Q14 is not exposed a potentially destructive current spike. Placing 26 less stress on the switches thereby increasing the MTBF.
27 Sub-circuit BSTPP takes advantage of the desirable 28 properties of the NSME. Adjusting the NSME BL1 (FIG. 18B) 29 sets the amount of boost voltage available to the final push-pull isolation stage. Greater efficiencies are 31 achieved at higher voltages. The final output voltage is 32 set by the feedback set point and the turns ratio of the 1 push-pull element PPT1 (FIG. 19).
2 FIG. 11 is a graph of permeability as a function of 3 temperature for typical prior art magnetic element 4 material. The high permeability material in FIG. 11 exhibits large changes in permeability of almost 100%
6 over a 1000 range as compared to the less than 5% change 7 for the material in FIG. 17. The increase in permeability 8 at high temperatures of the prior art material increases 9 the flux density resulting in core saturation for a constant power level. (See FIG. 12) Thus the prior art 11 core must be derated at least 1000 to operate over 12 extended temperatures. The instant invention takes 13 advantage of the desirable properties of the NSME.
14 Eliminating the need to derate the magnetic element. As the magnetic element performs better at high 16 temperatures, currently limited by melting wire 17 insulation.
18 FIG. 12 is a graph of flux density as a function of 19 temperature for typical prior art magnetic element material. The reduction of maximum flux density with 21 temperature is typical of the saturating magnetic element 22 prior art material. Thus the prior art core is commonly 23 derated at least 1000 to operate over extended 24 temperatures. Resulting in a larger more expensive design, and or the requirement to cool the core.
26 FIG. 12A is a graph of magnetic element losses for 27 various flux densities and operating frequencies typical 28 of prior art magnetic element material.
29 FIG. 13 is a graph showing standard switching losses. The hashed area represents the time when the 31 switch is in a resistive state. The hashed area is 32 proportional to the amount of energy lost each time the 1 output switch operates. Total power lost is the product 2 of the loss per switch times the switching frequency.
3 FIG. 14 is a graph showing the inventions switching 4 losses. The hashed area represents the time when the switch is in a resistive state. The smaller hashed area 6 is due to the action of the buffer in FIG. 29 and the 7 snubber isolation diode D805 in FIG. 30. Generally the 8 NSME has a wider usable frequency band and can be 9 magnetized from higher primary voltages. Higher operating voltages have proportionally smaller currents for a given 11 power level thus proportionally lower losses. Switching z 12' losses more closely resemble I R losses. Most switching 13 loss occurs during turn "on" and turn "off" transitions;
14 total switching losses are reduced proportionally by the lower switching frequencies and faster transition times 16 characteristic of the disclosed NSME converters. In 17 addition the properties of the NSME allow operation at 18 temperature extremes beyond the tolerance of standard 19 prior art magnetics and their geometry's. The combined contributions of the above yields a converter that 21 requires little or no forced air-cooling. (See FIG. 15, 22 16, and 17) 23 FIG. 15 is a graph of the NSME magnetization curves 24 for Kool Mu material. The invention makes advantageous use of the available saturation range of the NSME.
26 FIG. 15A is a graph of the magnetization curves for 27 H Material.
28 FIG. 16 is a graph of the Kool Mu NSME losses for 29 various flux densities and operating frequencies. It can be seen from the data that much higher flux densities are 31 available per unit losses over the prior art.

1 FIG. 17 is a plot of permeability vs. temperature 2 for several Kool Mu materials. This data demonstrates the 3 usefulness and stability of the magnetic properties over 4 temperature.
5 FIG. 18 is a schematic representation of the non-6 saturating magnetic boost element PFT1. Sub-circuit PFTl 7 consists of a primary winding 100 around a NSME 101 with 8 two center-tapped windings 102 and 103.
Figure 18 Table Element Value/part number 100 55 turns 203uh 101 2 x 77932-A7 102 14 turns 102 14 turns 9 The primary winding 100 has nodes P1B and PlA for 10 connections to external AC source. Secondary 102 winding 11 has center-tapped node S1CT and node S1H and S1L
12 connections to the upper and lower halves respectively.
13 Secondary 103 winding has center-tapped node S2CT and 14 node S2H and S2L connections to the upper and lower 15 halves respectively. Both 102 and 103 are connected to 16 external full-wave rectifier assemblies. Magnetic element 17. magnetic element 101 comprises a non-saturating, low 18 permeability magnetic material. The permeability is on 19 the order of 26u with a range of 1u to 550u, as compared 20 to the prior art, which ranges from 1500 to 5000u.
21 Flyback management is of concern when using NSME in a 22 boost converter because the magnetic element generates 23 high drain source voltages across the primary switch 24 during the reverse recovery time of the flyback (output) 25 diode. The magnitude per cycle of flyback current from 1 NSME is greater for a given input magnetizing force 2 relative to the prior art. (See FIG. 5) For example, Kool 3 Mu torroids (Materials from Magnetics) are suitable for 4 this application. This material is not identified by way of limitation. The material comprises, by weight, 85%
6 iron, 6% aluminum, and 9% silicon. Further, the magnetic 7 element may be air, (permeability=1); a molypermalloy 8 powder, (MPP) a high flux MPP, a powder, a gapped 9 ferrite, a tape wound, a cut magnetic element, a laminated, or an amorphous magnetic element. Unlike the 11 prior art, the NSME is temperature tolerant in that the 12 critical parameters of permeability and saturability 13 remain substantially unaffected during extreme thermal 14 operation over time. Some materials such as air also exhibit little or no change in permeability or saturation 16 levels over time, temperature, and conditions. The prior 17 art uses high permeability saturable materials often 18 greater than 2000u permeability. These magnetics exhibit 19 undesirable changes in permeability and saturation during operation at or near rated output making operation at 21 high power levels and temperature difficult. See the 22 permeability vs. temperature FIG. 11. This deficiency is 23 overcome by the use of expensive oversized magnetic 24 elements or output current sharing with multiple supplies. (See the graph brat vs. temperature FIG. 12) 26 This invention takes advantage of the desirable 27 properties of NSME. See the permeability vs. temperature 28 FIG. 17. Prior art saturating magnetic element commonly 29 is operating at frequencies greater than 500KHz to achieve greater power levels. As a result practitioners 31 experience exponentially greater core losses (see FIG.

1 12A) at high frequencies. NSME support operation at lower 2 frequencies 20-600KHz further reducing switching losses 3 and magnetic element losses allowing operation at even 4 higher temperatures. See the loss density vs. flux density FIG. 16. Unlike the prior art, the instant 6 invention uses voltage mode control with over-current 7 shutdown. Material selection is also based upon mass and 8 efficiency. By increasing the mass of the magnetic 9 element, more energy is coupled more efficiently. Since there are reduced losses, the dissipation profile follows 11 I2R/copper losses. The magnetic element is operated at 12 duty cycles of 0%+ to 90%, which, when used to control 13 the primary side push-pull voltage, results in 14 efficiencies on the order of 900.
FIG. 18A is a schematic representation of the NSME
16 PFT1A Sub-circuit transformer PFT1A consists of a primary 17 winding 100 around a NSME 101 with a center-tapped 18 winding 102.
Figure 18A Table Element Value/part number 100 55 turns 230uh 101 2 x 77932-A7 102 14 turns 19 The primary winding 100 has nodes P1B and P1A for connections to external AC source. Secondary 102 winding 21 has center-tapped node S1CT and node S1H and S1L
22 connections to the upper and lower halves respectively.
23 Winding 102 are typically connected to external full-wave 24 rectifier assemblies. Magnetic element 101 comprises a non-saturating, low permeability magnetic material. The 26 permeability is on the order of 26u with a range of 1u to 1 550u, as compared to the prior art, which is on the order 2 of 2500u.
3 Flyback management is of concern when using such a 4 magnetic element 'because the magnetic element generates high drain source voltages across the primary switch 6 during the reverse recovery time of the flyback diode.
7 Flyback current is available for longer periods after the 8 primary switch opens. (See FIG. 5) For example, Kool Mu 9 (Materials from Magnetics are suitable for this application. This material is not identified by way of 11 limitation. The material comprises, by weight: 85% iron, 12 6o aluminum, and 9o silicon. Further, the magnetic 13 element may be air; (air magnetic element 14 permeability=1); a molypermalloy powder (MPP) magnetic element; a high flux MPP magnetic element; a powder 16 magnetic element; a gapped ferrite magnetic element; a 17 tape wound magnetic element; a cut magnetic element; a 18 laminated magnetic element; or an amorphous magnetic 19 element. During operation the temperature of the NSME
rises, the permeability slowly decreases, thereby 21 increasing the saturation point. Some materials such as 22 air exhibit no or very small changes in permeability or 23 saturation levels. Unlike prior art using high 24 permeability materials greater than 2000u permeability rapidly increases at high temperatures. See the 26 permeability vs. temperature FIG. 11. Prior art also 27 suffers from reduced magnetic element saturation levels 28 at high temperatures, making operation at high power 29 levels and temperature difficult and may require the use of expensive oversized magnetic elements. See the graph 31 brat vs. temperature FIG. 12 this invention takes 1 advantage of the desirable NSME properties. See the 2 permeability vs. temperature FIG. 17. Operation at lower 3 frequencies 20-600KHz reduces switching losses and 4 magnetic element igher losses allowing operation at h temperatures. See the loss density vs. flux density FIG.

6 16. Unlike uses the prior art, the instant invention 7 voltage mode control with over-current shutdown. Material 8 selection is also based upon mass and efficiency. By 9 increasing the mass of the magnetic element, more energy is coupled more efficiently. Since there are reduced 11 losses, the dissipation profile follows I2R/copper 12 losses. The magnetic element is operated at duty cycles 13 of Oo+ to 90°s, which, when used to control the primary 14 side push-pull voltage, results in efficiencies on the order of 90% .
16 FIG. 18B is a schematic representation of the NSME
17 BL1 Sub-circuit BL1 consists of a winding 100 around a 18 NSME 101.
Figure 18 Table Element Value/part number 107 40 turns 50uh 101 2 x 77932-A7 19 Magnetic element BL1 may also be constructed from one or more magnetic elements in series or parallel.
21 Assuming minimal mutual coupling the total inductance is 22 the arithmetic sum of the individual inductances. For 23 elements in parallel the (assuming minimal mutual 24 coupling) the total inductance is the reciprocal of the arithmetical sum of the reciprocal of the individual 26 inductances. In this way multiple magnetic elements may 27 be arranged to meet packaging, manufacturing, and power 1 requirements. The primary winding 100 has nodes P2B and 2 P2A for connections to external AC source. Magnetic 3 element 101 comprises a non-saturating, low permeability 4 magnetic material. The permeability is on the order of 5 26u with a range of 1u to 550u, as compared to the prior 6 art, which is on the order of 2500 to 5000u. Flyback 7 management is of concern when using such a magnetic 8 element because the magnetic element generates high drain 9 source voltages across the primary switch during the 10 reverse recovery time of the flyback diode. Flyback 11 current is available for longer periods after the primary 12 switch opens. (See FIG. 5) For example, Kool Mu 13 (Materials from Magnetics are suitable for this 14 application. This material is not identified by way of 15 limitation. The material comprises, by weight: 85°s iron, 16 60 aluminum, and 9% silicon. Further, the magnetic 17 element may be air (air magnetic element permeability=1);
18 a molypermalloy powder (MPP) magnetic element; a high 19 flux MPP magnetic element; a powder magnetic element; a 20 gapped ferrite magnetic element; a tape wound magnetic 21 element; a cut magnetic element; a laminated magnetic 22 element; or an amorphous magnetic element. During 23 operation temperature of the magnetic element rises, the 24 permeability slowly decreases, thereby increasing the 25 saturation point. Some materials such as air exhibit no 26 or very small changes in permeability or saturation 27 levels. Unlike prior art using high permeability 28 materials greater than 2000u permeability rapidly 29 increases at high temperatures. See the permeability vs.
30 temperature (FIG. 11). Prior art also suffers from 31 reduced magnetic element saturation levels at high 32 temperatures, making operation at high power levels and 1 temperature difficult and may require the use of 2 expensive oversized magnetic elements. (See the graph brat 3 vs. temperature FIG. 12) This invention takes advantage 4 of the desirable NSME properties. (See the permeability vs. temperature FIG. 17.) Prior art often operates at 6 high switching frequencies 100-1000 kHz to avoid the 7 saturation problem. Only to increase switching and core 8 losses. (See FIG. 12A) This inventions use of the 9 desirable NSME properties allows operation at lower frequencies 20-600KHz further reducing switching losses 11 and magnetic element. See the loss density vs. flux 12 density FIG. 16. Unlike the prior art, the instant 13 invention uses voltage mode control with over-current 14 shutdown. Material selection is also based upon mass and efficiency. By increasing the mass of the magnetic 16 element, more energy is coupled more efficiently. Since 17 there are reduced losses, the dissipation profile follows 18 I2R/copper losses.
19 FIG. 18C is a schematic representation of a distributed NSME PFT1D. This is shown to exemplify 21 distributed magnetics enable advantageous high voltage 22 converter design variations that support form factor 23 flexibility and multiple parallel secondary outputs from 24 series coupled voltage divided primary windings across multiple NSME. This magnetic strategy is useful in 26 addressing wire insulation, form factor and packaging 27 limitations, circuit complexity and.manufacturability. In 28 this example a 500W converter is required to fit in a low 29 profile package. Sub-circuit PFTD1 consists of three magnetic elements 120, 121 and 124 with series connected 31 primaries.

Figure 18C Table Element Value/part number 122 23 Turns 123 23 Turns 112 67uh (55 turns) 116 67uh (55 turns) 118 67uh (55 turns) 1 AC voltage is applied to 112 pin P1B then from P1C
2 through conductor 115 to 116 pin P1D. Winding 116 pin P1E
3 is connected through conductor 119 to 118 pins P1F then 4 to pin P1A. Original Sub-circuit PFT1 (FIG. 18) consists of a primary winding 100 around a NSME 101 with two 6 center-tapped windings 122 and 123. By way of example 7 sub-circuit PFT1D will be implemented as three magnetic 8 elements. For a 500-watt expression a total inductance of 9 203 uH is required in winding 100 (FIG. 18). Dividing the primary inductance by the number of elements, in this 11 case three requires elements 112, 116 and 118 have 67 uH
12 of inductance. The. energy storage is equally distributed 13 over the magnetic assembly 120, 121 and 124. The 500 watt 14 converter in (FIG. 1) employs two (Kool Mu part number 77932-A7) 0.9 oz (25 gram) NSME to form 101 (FIG. 18) .
16 Sub-circuit PFT1 magnetic element 101 (FIG. 18) may be 17 expressed as three 0.5-0.7 oz (14-19 gram) elements.
18 Three 0.5-oz Kool Mu elements (part number 77352-A7) were 19 selected. To realize 67 uH of primary inductance 55 turns are required for elements 112, 116 and 118. The primary 21 circuit has nodes P1B and P1A for connections to external 1 AC source. Secondary 102 winding has center-tapped node 2 S1CT and node S1H and S1L connections to the upper and 3 lower halves respectively. Secondary 123 winding has 4 center-tapped node S2CT and node S2H and S2L connections to the upper and lower halves respectively. Both 122 and 6 123 are connected to external full-wave rectifier 7 assemblies. Magnetic element magnetic element 120, 121 8 and 124 comprises a non-saturating, low permeability 9 magnetic material. The permeability is on the order of 26u with a range of 1u to 550u, as compared to the prior 11 art, which is on the order of 2500u. Flyback management 12 is of concern when using such a magnetic element because 13 the magnetic element generates high drain source voltages 14 across the primary switch during the reverse recovery time of the flyback diode. Flyback current is available 16 for longer periods after the primary switch opens. (See 17 FIG. 5) For example, Kool Mu (Materials from Magnetics 18 are suitable for this application. This material is not 19 identified by way of limitation. The material comprises, by weight: 85% iron, 6% aluminum, and 9% silicon.
21 Further, the magnetic element may be air (air magnetic 22 element permeability=1); a molypermalloy powder (MPP) 23 magnetic element; a high flux MPP magnetic element; a 24 powder magnetic element; a gapped ferrite magnetic element; a tape wound magnetic element; a cut magnetic 26 element; a laminated magnetic element; or an amorphous 27 magnetic element. During operation the temperature of the 28 NSME, the permeability slowly decreases, thereby 29 increasing the saturation point. Some materials such as air exhibit no or very small changes in permeability or 31 saturation levels. Unlike prior art using high 32 permeability materials greater than 2000u permeability 1 rapidly increases at high temperatures. See the 2 permeability vs. temperature FIG. 11. Prior art also 3 suffers from reduced magnetic element saturation levels 4 at high temperatures, making operation at high power levels and temperature difficult and may require the use 6 of expensive oversized magnetic elements. (See the graph 7 bsat vs. temperature FIG. 12) This invention takes 8 advantage of the desirable NSME properties. See the 9 permeability vs. temperature FIG. 17. Prior art saturating magnetic element commonly is operating at 11 frequencies greater than 500KHz to achieve greater power 12 levels. As a result practitioners experience 13 exponentially greater core losses (see FIG. 12A) at high 14 frequencies. NSME allows operation at lower frequencies 20-600KHz further reduces switching losses and magnetic 16 element losses allowing operation at even higher 17 temperatures. (See the loss density vs. flux density FIG.
18 16) Unlike the prior art, the instant invention uses 19 voltage mode control with over-current shutdown. Material selection is also based upon mass and efficiency. By 21 increasing the mass of the magnetic element, more energy 22 is coupled more efficiently. Since there are reduced 23 losses, the dissipation profile follows I2R/copper 24 losses. The magnetic element is operated at duty cycles of 0%+ to 90%, which, when used to control the primary 26 side push-pull voltage, results in efficiencies on the 27 order of 90%.
28 FIG. 19 is a schematic representation of the non-29 saturating push-pull magnetic element. sub-circuit PPT1.
Sub-circuit PPT1 consists of a center-tapped primary 31 winding 104 around a NSME 106 with one secondary center-1 tapped winding 105.
Figure 19 Table Element Value/part number 105 10 Turns 104 70 Turns 2 The primary winding 104 has nodes P2H and P2L for 3 connections to external AC sources, and common center-tap 4 node P2CT. Secondary 105 winding has center-tapped node 5 SCT and nodes SH and SL connections to the upper and 6 lower halves respectively. The invention is not limited 7 to a single output. More secondary windings may be added 8 for additional outputs. Secondary 105 is connected to an 9 external full-wave rectifier assembly (Example FIG. 25 or 10 26). The magnetic element magnetic element 106 comprises 11 a non-saturating, low permeability magnetic material. The 12 permeability is on the order of 26u with a range of 1u to 13 550u, as compared to the prior art, which is on the order 14 of 2500u. Flyback management is of concern when using 15 such a magnetic element as high drain source voltages 16 across the primary switch are generated during the 17 reverse recovery of the flyback diode. The falling 18 flyback current is available for a longer period. (See 19 FIG. 5) For example, Kool Mu (magnetic elements from 20 Magnetics are suitable for this application. This 21 material is not identified by way of limitation. The 22 material comprises, by weight; 85% iron, 6% aluminum, and 23 9o silicon. Further, the magnetic element may be air 24 (comprise an air magnetic element); a molypermalloy 25 powder (MPP) magnetic element; a high flux MPP magnetic 26 element; a powder magnetic element; a gapped ferrite 1 magnetic element; a tape wound magnetic element; a cut 2 magnetic element; a laminated magnetic element; or an 3 amorphous magnetic element. During operation the 4 temperature of the NSME rises, the permeability slowly decreases, thereby increasing the saturation point.
6 Unlike prior art using high permeability materials 7 greater than 2000u permeability rapidly increases at high 8 temperatures. See the permeability vs. temperature FIG.
9 11. Prior art also suffers from reduced magnetic element saturation levels at high temperatures, making operation 11 at high power levels and temperature difficult and may 12 require the use of expensive oversized magnetic elements.
13 (See the bsat vs. temperature FIG. 12) This invention 14 takes advantage of the desirable NSME properties. (See the permeability vs. temperature (FIG. 17) Operation at 16 lower frequencies 20-600KHz reduces switching losses and 17 magnetic element losses allowing operation at higher 18 temperatures. See the loss density vs. flux density FIG.
19 16. Unlike the prior art, the instant invention uses voltage mode control with over-current shutdown. Material 21 selection is also based upon mass and efficiency: By 22 increasing the mass of the magnetic element, more energy 23 is coupled more efficiently. Since there are reduced 24 losses, the dissipation profile follows I2R/copper losses. The magnetic element primary is driven in a push-26 pull fashion at a duty cycle of 48-49% resulting in 27 efficient use of the magnetic element volume.
28 FIG. 19A is a schematic representation of the non-29 saturating push-pull magnetic element sub-circuit PPT1.
Sub-circuit PPTl consists of a center-tapped primary 31 winding 134 around a NSME 136 with one secondary center-32 tapped winding 135. , Figure 19A Table Element Value/part number 135 10 Turns 134 70 Turns 1 The primary winding 134 has nodes P2H and P2L for 2 connections to external AC sources, and common center-tap 3 node P2CT. Secondary 135 winding has center-tapped node 4 SCT and nodes SH and SL connections to the upper and lower halves respectively. The invention is not limited 6 to a single output winding. More secondary windings may 7 be added for additional outputs. Secondary 135 is 8 connected to an external full-wave rectifier assembly 9 such as OUTA (FIG. 25), OUTB (FIG. 25A) and OUTBB (FIG.
25B). The magnetic element 136 comprises a non-11 saturating, low permeability magnetic material. The 12 permeability is on the order of 26u with a range of 1u to 13 550u, as compared to the prior art, which is on the order 14 of 2500u. Flyback management is of concern when using such a magnetic element as high drain source voltages 16 across the primary switch are generated during the 17 reverse recovery of the flyback diode. The falling 18 flyback current is available for a longer period. (See 19 FIG. 5) For example, Kool Mu (magnetic elements from Magnetics are suitable for this application. This 21 material is. not identified by way of limitation: The 22 material comprises, by weight; 85% iron, 6% aluminum, and 23 9% silicon. Further, the magnetic element may be air 24 (comprise an air magnetic element); a molypermalloy powder (MPP) magnetic element; a high flux MPP magnetic 26 element; a powder magnetic element; a gapped ferrite 1 magnetic element; a tape wound magnetic element; a cut 2 magnetic element; a laminated magnetic element; or an 3 amorphous magnetic element. During operation the 4 temperature of the NSME rises, the permeability slowly decreases, thereby increasing the saturation point.
6 Unlike prior art using high permeability materials 7 greater than 2000u permeability rapidly increases at high 8 temperatures. See the permeability vs. temperature (FIG.
9 11). Prior art also suffers from reduced magnetic element saturation levels at high temperatures, making operation 11 at high power levels and temperature difficult and may 12 require the use of expensive oversized magnetic elements.
13 (See the bsat vs. temperature FIG. 12) This invention 14 takes advantage of the desirable NSME properties. (See the permeability vs. temperature FIG. 17) Operation at 16 lower frequencies 20-600KHz reduces switching losses and 17 magnetic element losses allowing operation at higher 18 temperatures. See the loss density vs. flux density FIG.
19 16. Unlike the prior art, the instant invention uses voltage mode control with over-current shutdown. Material 21 selection is also based upon mass and efficiency. By 22 increasing the mass of the magnetic element, more energy 23 is coupled more efficiently. Since there are reduced 24 losses, the dissipation profile follows I2R/copper losses. The magnetic element primary is driven in a push-26 pull fashion at a duty cycle of 48-49% resulting in 27 efficient use of the magnetic element volume.
28 FIG. 20 is a schematic showing the inventions filter 29 and lightning input protection circuit for an AC line connected converter. The protection sub-circuit LL
31 comprises a Spark gap A1, diodes D20 and D21, capacitor 32 C1 and magnetic elements L1 and L2.

Figure Table Element Value/part number L1 375uH

L2 375uH

C61 O.OluF

C60 O.OluF

A1 400V Spark Gap C1 0.luF

C2 l.8uf 1 The AC line is connected to node LL2. The common 2 input frequencies of DC to 440Hz may be extended beyond 3 this range with component selection. Node LL2 is 4 connected to NSME L1 then to node LL5, the spark gap Al, anode of diode D22 and the cathode of diode D20. Filter 6 capacitor C60 is connected between node LLO and LL6.
7 Filter capacitor C61 is connected between node LLO and 8 LL5. The low side of AC line is connected to node LL1 9 then to magnetic element L2 the other side L2 is connected to spark gap Al, anode of diode D23 and the 11 cathode of diode D21 and to node LL6. Capacitor C1 is 12 connected to earth ground C1 attenuates noise generated 13 by the converter. The use of non-saturating magnetic 14 allows the input magnetic elements to absorb very large voltages and currents commonly generated by lightning, 16 often without causing spark gap A1 to clamp. During UL
17 testing sixty l6ms 2000V pulses were applied between LL1 18 and LL2 without realizing spark gap A1 was missing with 19 out damage. During normal operation the NSME L1 flux density is a few hundred gauss. The 75u material from the 21 graph of Flux Density v. Magnetizing Force (FIG. 15) will 22 accept flux densities at least 50 times greater with out 23 limitation. This is an example of the magnetic elements 24 ability to perform well at flux densities many times greater than prior art. Elements L1 and L2 will block 1 differential or common mode line transients. In the event 2 of a very large or long duration line to neutral 3 transient, spark gap A1 will clamp the voltage to a safe 4 level of about 400V. The NSME L1 and L2 have the added 5 benefit of reducing conducted noise generated by the 6 converter.
7 FIG. 20A is a schematic showing an alternate line 8 filter. The filter sub-circuit LF comprises capacitors C2 9 and C60-66, inductors L64 and L62, magnetic element L63 10 and diodes D20-D23.
Figure 20A Table Element Value/part number L64 270 uH
common mode H core bifilar L63 1.0 mH 125u differential mode L62 12 mH common mode H core bifilar C66 O.OluF

C63, C62 0.47 uF

C61, C61, C64, 2.2nf Y-cap C20 O.OluF

C2 - I 1 . 5uf 11 The AC line is connected to nodes LL2 and LL1. Node 12 LL2 connects through upper leg of inductor L64 to first 13 leg of y-cap C64 then to capacitor C63 then to upper leg 14 of Bifilar wound inductor L62. Node LL1 connects through 15 lower leg of inductor L64 to second leg of y-cap C65, 16 then to capacitor C63 then to lower leg of Bifilar wound 17 inductor L62. Capacitor C66 is connected between LL2 and 1 LL1. Second upper leg of inductor L62 connects to first 2 leg of y-cap C61 then to capacitor C62 then to anode of 3 D22 and cathode of D20. Second lower leg of inductor L62 4 connects to second leg of y-cap C60 then to capacitor C62 then to anode of D23 and cathode of D21. Center legs of 6 Y-caps C60, C61, C64 and C65 are connected to chassis 7 return LLO. Capacitor C69 connects node BR- to chassis 8 ground LLO. Anodes of diode D20 and D21 connected to 9 node BR-. Cathodes of diodes D22 and D23 connect to MSME
l0 L63 in parallel with C20 and node BR+. Capacitor C21 11 connects to BR- and the other side of L63 in parallel 12 with C20 forming node B+. Common mode inductors L64 and 13 L62 are constructed on a high permeability core material 14 H41-406-TC, H42-109-TC respectively manufactured by Magnetics inc. Butler Pennsylvania USA. This material is 16 offered by way of example and not limitation. Capacitor 17 C69 is connected to earth ground attenuates noise 18 generated by the converter. The instant invention takes 19 advantage of the high permeability properties of the ferrite used in inductors L64 and L62. (see FIG. 15A).
21 Making full use of the core material over all four 22 quadrants. Inductors L64 and L62 are effective in 23 removing common mode EMI components. Differential mode 24 noise generated by the main switch Ql is effectively blocked by NSME L63 in parallel with C20. Inductor L63 26 is operated in the first quadrant taking advantage of the 27 unique non-saturating properties of the Kool Mu core 28 material(manufactured by Magnetics Inc.). .This material 29 allows operation with large DC magnetizing currents without saturation. The 125u material from the graph of 31 Flux Density v. Magnetizing Force (FIG. 15) was selected 32 for this application. And is offered by way of example 1 and not limitation. This is an example of the magnetic 2 element's ability to perform well at high flux densities 3 many times greater than prior art. NSME L63 in parallel 4 with C20 forms a tuned tank effectively blocking high frequency from the AC line. Elements L64 and L62 will 6 block common mode line transients. In the event of a very 7 large or long duration line to neutral transient, sub-8 circuit TRN (FIG. 46) connected to BR+ redirects the 9 transient into the main storage capacitor C442. The l0 instant invention makes optimal use of the ferrite type 11 material in the AC side and the desirable NSME in the DC
12 side to provide high performance filtering at a low cost.
13 FIG. 21 is a schematic showing the inventions 14 alternate lightning protection sub-circuit LLA for an AC
line connected converter. The ~ protection circuit 16 comprises a fuse F1, Spark gap A1, capacitors C1, C60 and 17 C61 and NSME L3.
Figure 21 Table Element Value/part number L3 750uH

C61 O.OluF

C60 O.OluF

Al 400V Spark Gap C1 O.luF

C2 l.8uf 18 High side of AC line is connected to node LL2, fuse 1 F1 the load side of the fuse is connected to NSME L3 and 2 to capacitor C61. The load side L3 is connected to spark 3 gap A1 and the cathode of diode D20 and anode of D22 4 forming node LL5. The low side of AC line is connected to node LL6, capacitor C60, spark gap A1, and the cathode of 6 diode D21 and anode of D23. The anodes of diodes D20 and 7 D21 are connected to Capacitor C1. Capacitor C1 is 8 connected to earth ground. C1 attenuates radiated noise 9 or EMI generated by the converter. The cathode of diodes D22 and D23 are connected to Capacitor C2. Capacitor C2 11 decouples high frequency harmonic currents from the line.
12 Capacitors C1, C61 and C60 are connected to earth ground 13 node LLO. The use of non-saturating magnetics allows the 14 input magnetic element to absorb very large voltages and currents commonly generated on the AC line by lightning.
16 A transient on the AC line will be limited by capacitors 17 C60 and C61 and blocked by the non-saturating magnetic 18 L3. In the event of a very large or long duration line to 19 neutral transient, magnetic element L3 will allow the voltage to rise across spark gap A1, the spark gap will 21 clamp the voltage to a safe level protecting the 22 rectifier diodes D20-D23. The NSME L3 has the added 23 benefit of reducing conducted noise generated by the 24 converter. C1 connected to the ground plane is effective in attenuating conducted and radiated EMI.
26 FIG. 22 is a schematic showing the inventions AC
27 line rectifier. The rectifier sub-circuit BR1 comprises 28 diodes D20, D21, D22 and D23 and capacitor C2.
Figure 22 Table Element Value/part number C2 l.8uf 1 An AC or DC signal from the input filter is 2 connected to bridge rectifier to nodes BR1 and BR2. Node 3 BR1 connects diode D22 anode to D20 cathode. Node BR2 4 connects diode D23 anode to D21 cathode. Node BR+
connects diode D22 cathode to D23 cathode. Node BR-6 connects diode D20 anode to D21 anode. The common input 7 frequencies of DC to 440Hz may be extended beyond this 8 range with component selection. Capacitor C2 is selected 9 to improve power factor for a particular operating frequency and to de-couple switching currents from the 11 line. Diodes are selected to reliably block the expected 12 line voltage and current demands of the next converter 13 stage .
14 Fig. 23 is the inventions AC to DC controller sub-circuit. Sub-circuit PFA consists of resistors 8313 and 16 8316, capacitors C308, and C313 and PWM controller IC
17 UlA .
Figure 23 Table Element Value/part number C311 O.luf C308 .Oluf 8313 15k ohms 8316 15k ohms C313 4700pf 8308 25k ohms UlA MIC38C43 (Micrel) 18 Control element UlA connects to a circuit with the 1 following series connections: from pin 1 to feedback 2 node/pin PF1 then to capacitor C308 then to the pin 2 3 node of UlA. Internal 5.1-volt reference UlA pin 8 or 4 node PFA2 through resistor 8308 to the pin 4 node. UlA
S pin 4 is connected through capacitor C313 to return node 6 BR-. This arrangement allows the PFC output to be pulse 7 width modulated with application of voltage to PF1.
8 External feedback current applied to UlA pin 1 and node 9 PF1. Node PFVC is connected to resistor 8313 to pin 3 of 10 UlA. Resistor 8316 is connected to pin 3 then to return 11 node BR-Power pin 7 is connected to node PFA+. Control 12 element switch drive UlA pin 6 is connected to node 13 PFCLK. Return ground node of UlA pin 5 is connected to 14 return node BR-. In the event of a component failure in 15 the primary feed networks such as IPFFB (FIG. 40), FBA
16 (FIG. 40A) , IFB (FIG. 40B) and FB1 (FIG. 41) . The output 17 voltage of the boost stage may rapidly increase to 18 destructive levels. Fast over voltage feedback networks 19 IOVFB (FIG. 40C) or OVP2 (FIG. 42B) increases the current 20 into PF1 thereby limiting the output voltage to a safe 21 level. In addition latching type over voltage protection 22 networks such as OVP (FIG. 42) , OVP1 (FIG. 42A) and OVP2 23 (FIG. 42B) maybe used. The latching type kills power to 24 the control circuit thereby stopping the boost action.
25 The latching type networks require power to be cycled to 26 the converter to reset the latch. IFB Input node PFVC is 27 connected to resistor 8313 to internal zero crossing 28 detector connected to pin 3 and through 8316 to return 29 node BR-. PFVC is connected to a magnetic element winding 30 referenced to BR-. A new conduction cycle is started each 31 time the bias in the magnetic element goes to zero. Power 32 factor corrected is realized by chopping the input at a 1 high frequency. The average pulse width decreases at 2 higher line voltage and increases at lower voltage for a 3 given load. Frequency is lower at line peaks and higher 4 around zero crossings. In this way the converter operates with a high input power factor.
6 FIG. 24 is the alternate power factor controller 7 sub-circuit. Sub-circuit PFB consists of resistors 8313, 8 8339, 8314, 8315, 8328, 8340, 8341 and 8346, diode D308, 9 capacitors C310, C318, C338, C340, C341 and C342, transistor Q305, and control element IC U1B.
Figure 24 Table Element Value/part number 8339 432k ohms C338 0.22 of C318 0.22 of 8314 2.2MEG ohms 8315 715k ohms C341 0.33 of C342 0.01 of C340 0.001 of 8328 1MEG ohms 8346 7.15k ohms D308 lOBQ040 8340 449k ohms 8313 22k ohms U1B MC34262 (Motorola) 8341 499k ohms 11Control element U1B connects to a circuit with the 12following series PFl connections : from pin 1 to node/pin 13to capacitor C338 in series with resistor 8339, and then 1 to the pin 2 node of U1B. Pin 1 is the input to an 2 internal error amplifier and connection to external 3 feedback networks. (See FIG. 40, 40A, 40B, 40C and 41) 4 Increasing the voltage on pin 1 decreases the pulse width of the PFCLK node pin 7. Resistor 8328 is connected to 6 the fullwave rectified AC line haversine voltage on node 7 BR+ then to U1B pin 3 and then to resistor 8346 in 8 parallel with capacitor C342 to return node BR-. Node 9 PFSC connects to series resistors [R341+ 8340] which aree connected to UlB pin 4 then to diode D308 in parallel 11 with capacitor C340 to return node BR-. Power to PFC
12 controller is applied to node PFB+ and to U1B pin 8.
13 Output clock node PFCLK is connected to U1B pin 7, to 14 external buffer sub-circuit AMP (FIG. 29). Transistor Q305 collector is connected to the pin 2 node of U1B. The 16 base is connected in series through resistor 8314 to 17 capacitor C318, then to the pin 2 node of U1B. The base 18 is also connected to [C310~~ 8315], then to return node 19 BR- Emitter of Q305 is connected to return node BR-.
Transistor Q305 provides a soft start compensation ramp 21 to~the controller error amp reducing the stress and DC
22 overshoot in the converter at power up. Capacitor C341 is 23 connected from U1 pin 2 to return node BR-. U1B pin 1 is 24 connected to pin PF1, capacitor C338 in series with resistor 8339 to transistor Q305 collector and to U1 pin 26 2. Current switched by PFC power switch Q1 (FIG. 4 & 3) 27 is sensed by R26 (see FIG. 4). Series resistors 28 [R340+R341] to U1B pin 4 connect voltage developed across 29 R26. This voltage is compared to an internal 1.5-volt reference, comparator output turns off the switch drive 31 pin 7 of U1B during times of high current that occur 32 during startup or during very high load or low line 1 conditions. Capacitor C340 is connected between U1 pin 4 2 to return node BR- filter high frequency components.
3 Schottky diode D308 connected between U1 pin 4 to return 4 node BR- protects the controller (U1 pin 4) substrate from negative current injection. Maximum switch current 6 value is set by R26 over currents are automatically 7 limited in each cycle by the PFC controller. The 8 rectified fullwave haversine at pin 3 of U1B is 9 multiplied by the error voltage on pin 2. The product is compared to the magnetic element/switch current measured 11 by R26 on pin 4. Gate drive on pin 7 turns off when the 12 sensed magnetic element current increases to the current 13 comparator level. This action has the effect of 14 modulating the switch Q1 "on" time tracking the AC line voltage. External feedback networks are connected to node 16 PF1. In the event of a component failure in the primary 17 feed network such as IPFFB (FIG. 40), FBA (FIG. 40A), IFB
18 (FIG. 40B) and FB1 (FIG. 41). The output voltage of the 19 boost stage may rapidly increase to destructive levels.
Fast over voltage feedback networks IOVFB (FIG. 40C) or 21 OVP2 (FIG. 42B) increases the current into PFl thereby 22 limiting the output voltage to a safe level. In addition 23 latching type over voltage protection networks such as 24 OVP (FIG. 42), OVP1 (FIG. 42A) and OVP2 (FIG. 42B) maybe used. The latching type removes power to the control 26 circuit thereby stopping the boost action. The latching 27 type networks require power to be cycled to the converter 28 to reset the latch. Modulating the voltage at PF1 changes 29 the duty cycle of the PFC and the final output voltage.
In this way the PFC may be used as a pre-regulator to 31 additional output stages.

1 FIG. 25 is a schematic of a full wave rectified 2 output stage and filter sub-circuit OUTA. The rectifier 3 stage consists diodes D80 and D90. The filter consists of 4 of resistor R21, magnetic element and capacitors C26, C27, C28, C29, 0, C31 and C32.

Figure 25 Table Element Value/part number R21 100 ohms C26 500pf C27 200pf C28 O.luf C29 10,000uf C30 10,000uf C31 O.luf C32 200pf L30 l0uh 6 Input node/pin C7B is connected to the high side of 7 external center-tapped magnetic element secondary 8 winding. Node C7B connects to anode of diode D8 and to 9 capacitors C26 and C27 in the following arrangement.
Capacitor C27 is connected across diode D80, capacitor 11 C26 is connected in series to R21. Input node/pin C8B is 12 connected to the low side of external center-tapped 13 magnetic element secondary winding. Pin C8B is connected 14 to anode of diode D9 and to resistor R21, capacitor C32 is connected across diode D90. Capacitors C27 and C32 is 16 a small value to reduce high frequency noise generated by 17 rapid switching the high speed rectifier D80 and D90 18 respectively. Capacitor C26 and resistor R21 are used to 19 further dissipate high frequency energy. Anode of diodes D80 and D90 is connected to parallel capacitors C28~IC29 21 and NSME L30. Capacitors C28 and C31 are solid 22 dielectric types selected for low impedance to high 23 frequency signals. Capacitors C29 and C30 are larger 24 polarized types selected for low impedance at low 1 frequencies and for energy storage. Magnetic element L3 2 is connected to diode D8 cathode the second terminal of 3 L30 is connected to parallel capacitors C31 and C30 and 4 pin OUT+. Node OUT+ is the output positive and is 5 connected to external feedback sense line to isolated 6 feedback network. The other side of parallel capacitors 7 [C28~~C29I~C30~~C31] is connected to pin OUT- and the 8 center-tap of the magnetic element secondary forming the 9 return node. The combination of capacitors [C28~~C29], 10 L30 and capacitors [C30~~C31] form a low pass pi type 11 filter. Sub-circuit OUTA performs efficient fullwave 12 rectification and filtering.
13 FIG. 25A is a schematic of a full wave rectified 14 output stage. The rectifier stage consists of diodes D80 15 and D90 and capacitors C931 and C928.
Figure 25A Table Element Value/part number C928 .0luf C931 10,000uf 16Input node/pin C7B is connected to high side of 17external center-tapped magnetic element secondary 18winding. Node C7B connects to anode of diode D80. Input 19node/pin C8B is connected to low side of external center-20tapped magnetic element secondary winding is connected to 21anode of diode D90. Node OUT- is the negative output and 22return line to the external isolated feedback network and 23load not shown. Cathodes of diodes D80 and D90 are 24connected to parallel capacitors C931 and C928. Capacitor 25C928 is a solid dielectric type selected for low 26impedance to high frequency signals. Capacitor C931 is a 27larger polarized selected for low impedance to low 28frequency signals and for energy storage.
Node OUT+ is 29the output positive and is connected to external feedback 1 sense line to isolated feedback network. The other side 2 of parallel capacitors C928~~C931 is connected to the 3 center-tap of the magnetic element secondary forming the 4 node OUT-. The use of the NSME for the push-pull magnetic element requires only minimal filtering after 6 the rectifiers.
7 FIG. 25B is a schematic diagram of an alternate 8 final output rectifier and filter sub-circuit OUTB. The 9 rectifier sub-circuit OUTB comprises diodes D40, D41, D42 and D43 and capacitor C931 and C928.
Figure 25B Table Element Value/part number C928 .Oluf C931 10,000uf .

11An AC or DC signal is connected to nodes C7B and 12CBb. Node C7B
connects diode anode to cathode.

13Node C8b connects diode anode to cathode.
Node 14OUT+ connects diode D42 cathode to D43 cathode..
Node OUT-15connects diode anode to anode.
Diodes are 16selected to reliably block the expected line voltage and 17current demands of the load. For low voltage outputs, 18Schottky type diodes are used due to their low forward 19voltage drop.
Higher voltages would use high-speed 20silicon diodes due to their ability to withstand high 21peak inve rse voltage (PIV).
The use of the NSME
for the 22push-pull magnetic element requires only minimal 23filtering after the rectifiers.
Capacitor is shown 1 schematically as a single device. Capacitor C931 is a 2 larger polarized selected for low impedance to low 3 frequency signals and for energy storage a typical value 4 may be 200uF. To increase the capacitance or reduces the output impedance multiple capacitors may be used. C931 is 6 a solid dielectric type and is selected for it's low 7 impedance to high frequencies. As is selected to reduces 8 noise for a particular operating frequency and power 9 level. Capacitor C928 is selected for the operating frequency and power level. Sub-circuit OUTB performs AC
11 to DC rectification and filtering at slightly lower 12 efficiency due to the extra junctions.
13 FIG. 26 Floating 18 Volt DC control power sub-14 circuit CP. Sub-circuit CP consists of diodes D501, D502 and D503, resistor 8507, regulator Q504, and capacitors 16 C503, C504, C505, C506, and C507.
Figure 26 Table Element Value/part number C503 .33uF

C504 100uF

C505 .33uf C508 100uf C507 100uf 17 Node CT1A connects to anode of D503 and to the upper 18 external center tapped secondary winding. Node CT2A
19 connects to anode of D502 and to the lower external center tapped secondary winding. Node CTO connects to the 1 external winding center tap. Node CTO is also the return 2 line and it connects to Q504 pin 2, and capacitors C503, 3 C504, C505, C506, and C507. The cathode of each of diodes 4 D502 and D503 is connected to resistor 8507. 8507 is then connected to the pin 1 (input) node of voltage regulator 6 Q504. Voltage regulator Q504 Pin 3 is the l8vdc regulated 7 DC output is connected to the anode of blocking diode 8 D501. Three-pin voltage regulator Q504 is of the type 9 LM7818 a common device made by a number of manufacturers.
Capacitors C503, C505, C506 are O.luF solid dielectric 11 type and are used to filter high frequency ripple and to 12 prevent Q504 from oscillating. The junction of C503, C504 13 and D501 cathode is the output node CP1+. Isolated 18-14 volt DC is available between nodes CTO and CP+. Used for regulator circuits and output switch drive during normal 16 operation.
17 FIG. 26A Alternate control power sub-circuit CPl 18 Sub-circuit CPl consists of diode D260, resistor 8261, 19 transistor Q260, and capacitors C261-C265, and C260.
Figure 26A Table Element Value/part number C261-C263 0.33uF

C260 0.1 uF

C265 0.33uf C266 0.01 uF

L260 1 mh 8261 100K ohm 8262 10 ohm C264 ~20uf 1 Node CT1A connects to anode of D261 and to the upper 2 external center tapped secondary winding. Node CT2A
3 connects to anode of D262 and to the lower external 4 center tapped secondary winding. Node BR- connects to the external winding center tap. Node BR- is also the return 6 line and it connects to Q260 emitter, and capacitors 7 C261-C265 and 8261. The cathode of diodes D261 and D262 8 is connected inductor L260 and capacitor 266. The other 9 side of capacitor C266 connects' to node FSC. Resistor 8262 is then connected between the other side of inductor 11 L260 and node VCC. The junction of 8262 and L260 forms 12 node TP15. Node VCC connects the positive terminals of 13 capacitors C260-265, collector of Q260, and cathode of 14 D260. Anode of low leakage zener D260 connects to the .base of Q260, resistor 826.1 and capacitor C260. The 16 zener diode voltage is selected to begin regulation at 17 high boost levels. Thus VCC is allowed to follow the 18 load level as shown by 6260 (FIG. 26B). Voltage limiting 19 starts at levels near full load (maximum boost) . This is offered by way of example and not limitation. In a 1000-21 watt supply the VCC limiting is observed with the 22 increase in slope in segment 262 (FIG. 26B). This unique 23 behavior has three benefits. First at greater levels of 24 boost (load) additional voltage is automatically provided to the main switch Q1 when maximum gate power is 26 required. Lowering gate voltage at minimal boost reduces 27 the stress on the main switch Q1 gate and associated 28 buffer components, thus enhancing MBTF and efficiency.
29 Second vCC provides an internal load sense signal used to servo the output voltage for load sharing. The load 31 sharing aspects of the design will be taught in FIG. 4A.

1 Third, a signal is available that may be used to 2 communicate load magnitude with out additional current 3 sensors. Diodes D262 and D261 provide rectified power 4 capacitor C226 couples AC voltage to node TP17 of sub-s circuit FS1 (FIG. 45). The AC voltage on TP17 inhibits 6 the action of the fast start circuit when the converter 7 is operating. Regulator CP1 is a shunt regulator. The 8 components are selected such that the limiting begins 9 near maximum boost. In this way, power is not wasted at 10 small load levels . Additionally the main switch Q1 gate 11 voltage is modulated to provide additional power at 12 maximum boost insuring maximum efficiency under varying 13 load conditions.
14 FIG. 26B is a plot of VCC as a function of output 15 power. Plot G26 was generated by measuring VCC in 16 ACDCPF1 (FIG. 4A) as the load was veried from 0-1000 17 watts .
18 FIG. 27 second Floating 18 Volt DC push-pull control 19 power sub-circuit CPA. Sub-circuit CPA consists of diodes 20 D601, D602 and D603, resistor 8607, regulator B604 and 21 capacitors C603, C604, C605, C606, C607 and C608.
Figure 27 Table Element Value/part number C603 .33uF

C604 100uF

C605 .33uF

C608 100uF

C607 .22uF

8607 7.5 ohms 1 Node CT1B connects to anode of D603 and to the upper 2 external center tapped secondary winding. Node CT2B
3 connects to anode of D602 and to the lower external 4 center tapped secondary winding. Node CT20 connects to the external winding center tap. Node CTO is also the 6 return line and it connects to Q604 pin 2, and capacitors 7 C603, C604, C605, C606, and C607. The cathode of each of 8 diodes D602 and D603 is connected to resistor 8607. 8607 9 is then connected to the pin 1 (input) node of voltage regulator Q604. Voltage regulator Q604 Pin 3 is the l8vdc 11 regulated DC output and is connected to the anode of 12 blocking diode D601. Capacitors C603, C605, C606 are 13 solid dielectric type and are used to filter high 14 frequency ripple and to prevent Q604 from oscillating.
The junction of C603, C604 and D601 cathode is the output 16 node CP1+. Isolated 18-volt DC is available between nodes 17 CT20 and CP2+. To be used for regulator circuits and 18 output switch drive during normal operation.
19 FIG. 28 is the main switch over temperature protection sub-circuit OTP. The sub-circuit OTP comprises 21 thermal switch and resistors 8711 and 8712.
Figure 28 Table Element Value/part number THSl 67F105 (105C) 8711 20 ohms 8712 20 ohms 22 Gate drive power is applied to input node GAP and to 23 thermal switch THS1. Maximum FET gate voltage requires 24 the input power voltage be less than 20 volts, the 1 voltage selected was 18 volts . The other side of THS1 is 2 connected to parallel resistors [R711~~R712]. A single 3 resistor may represent the resistors. The figure depicts 4 the surface mount arrangement. The other side of [R711~~R712] connects to output node TS+. Normally closed 6 thermal switch TS1 is in contact with main switch 7 transistor Q1. In the event of temperature greater than 8 105C THS1 opens, thus removing power to the buffer sub-9 circuit AMP1 (FIG. 29) causing switch Q1 to default to a blocking state protecting the boost switch should the 11 optional cooling fan fail or the circuit reach high 12 temperatures. In this instant invention the speed up 13 buffer AMP (FIG. 29) non-saturating magnetics (FIG. 18, 14 18A and 19) allows the main switch and to run cooler than prior art for a given power level. When switch 16 temperature returns to normal range THS1 will close, 17 allowing the PFC to resume normal operation. Under normal 18 load and ambient temperatures the thermal switch THS1 19 should never open.
FIG. 29 PFC Buffer Circuit sub-circuit AMP, AMPl, 21 AMP2, AMP3 switch drive command from PFCLK (FIG. 23 and 22 24) or PWFM (FIG. 33) control elements are connected to a 23 gate buffer circuit. The sub-circuit AMP is comprised of 24 power FET Q702, Darlington pair Q703, capacitors C709 and C715, and resistors 8710 and 8725.
Figure Table Element Value/part number C715 1000pf C709 33uF

8710 0 ohms 8725 22.1k ohms 1 DC Power is applied to node GAT+ to transistor Q702 2 drain and to capacitor C709, which goes to ground.
3 Maximum gate voltage requires the input power voltage 4 must be less than 20 volts, 18-volts was selected. Input node GA1 is connected to the gate of FET Q702 is 6 connected to the base of BJT1 of the Darlington pair Q703 7 and to capacitor C715. C715 is connected across the 8 Darlington pair from the base, pin 1, to the collectors, 9 pins 2 and 4, Q703 collector node is also connected to l0 ground. The emitter of BJT2 is connected to the gate of 11 FET Q1. The source of FET Q702 is connected through small 12 optional series resistor 8710 to the gate of the output 13 switch or node GA2. Some power FETs under certain load 14 may tend to oscillate when driven from a low impedance source such as this buffer. A small resistance of 16 approximately 2 ohms or less may be required with out 17 significant slowing of the switch. In most cases 8710 is 18 replaced with a zero ohm jumper. Resistor 8725 is 19 connected from node GAO and source of Q702. The input switching signal to node GAP is in range of 20kHz to 21 600kHz. Very fast "on" times are realized by proving a 22 low impedance to rapidly charge the output switch gate 23 connected to node GA2. Capacitor C709 provides additional 24 current when Q702 switches on. Transistor Q703 provides low impedance to rapidly remove the charge from the gate 26 greatly reducing the "off" time. This particular topology 27 provides output switch rise times on the order of lOns, 28 as compared to the industry standard rise time of 250ns.
29 The corresponding fall time is <lOnS, again as compared 1 to an industry fall time of 200-300ns (See FIG. 13 and 2 14). In the event the converter is operated at very high 3 ambient temperatures a thermal switch may be placed in 4 series with input power pin GA+. This allows the switch transistor to be gracefully disabled. Sub-circuit AMP
6 greatly reduces switching losses allowing converter 7 operation in some cases with out the common prior art 8 forced air-cooling.
9 FIG. 30 is a schematic diagram of a snubber sub-circuit of the invention. The snubber sub-circuit SN is 11 comprised of diodes D804 and D805 and resistors 8800, 12 8817, 8818, and capacitors C814 and C819.
Figure 30 Table Element Value/part number 8800 12 ohms 8817 1 mohm 8818 1 mohm C814 33 pF

C819 560 pF

13Node SNL2 connects to the drain terminal of the 14external output switch and to flyback side of the 15inductive load. Input node SNL2 connects to 8800 in 16series with 805 capacitor C819 to node SNOUT.
Diode D

17anode is ors connected to node SNL2 with resist 18[R817I~R8 18] in parallel with D805. Resistors 8817 and 198818 may be combined to a single resistor. The cathode of 20D805 is connected to capacitor C814 that connects to 21node/pin SNL1. Node SNL1 connects to the supply side of 22external load magnetic element. The other leg of exter nal 23magnetic element is connected to the anode of D805 and 1 the anode side of external flyback diode D4. The one MEG

2 ohm resistors 8817 and 8818 bleed the charge from C814 3 resetting it for the next cycle. Capacitor C819 and 4 resistor 8800 captures the high frequency event from the 5 transition of external flyback diode D4 and moves part of 6 the energy into the external holdup capacitor connected 7 to node SNOUT. Since external flyback diode D4 and D805 8 isolate the drain of the output switch, faster switching 9 occurs because the output switch does not have to slew 10 the extra capacitance of a typical drain / source 11 connected snubber circuit. Note that this circuit does 12 not attempt to absorb the flyback in large RC networks 13 that convert useful energy to losses. Nor does it attempt 14 to stuff the flyback to ground, adding capacitance and 15 slowing the output switch and increasing switching 16 losses. This sub-circuit is used with it's mirror SNB
17 (FIG. 32) across the external push-pull switches. This 18 design returns the some of the flyback energy back to the 19 input supply or output load. The "snubbering" action 20 slows the rise of the flyback giving time for the 21 external flyback diode to start conduction. The circuit 22 efficiently manages high frequency flyback pulses.
23 FIG. 30A is a schematic diagram of a diode snubber sub-24 circuit of the invention. The snubber sub-circuit DSN is 25 comprised of diodes D51, D52, D53, D54 and D55 and 26 capacitors C51, C52, C53, C54 and C55.
Figure 30A Table Element Value/part number C51 220 pf 100v C52 220 pf 100v C53 220 pf 100v C54 220 pf 100v C55 220 pf 1.00v ~D51 Schottky 1-2ns 100v D52 Schottky 1-2ns 100v SMBSRlOlOMSCT

D53 Schottky 1-2ns 100v D54 Schottky 1-2ns 100v SMBSRlOlOMSCT

D55 Schottky 1-2ns 100v 1 Pin SNL2 is connected to the anode of D51 the 2 cathode of D51 is connected to the anode of D52 the 3 cathode of D52 is connected to the anode of D53 the 4 cathode of D53 is connected to the anode of D54 the cathode of D54 is connected to the anode of D55 the 6 cathode of D55 is connected to pin SNOUT. Capacitors are 7 connected across each diode forming a series parallel 8 combination of [D51~~C51] + [D52~~C52] + [D53~~C53] +
9 [D54~~C54] + [D55~~C55]. Node SNL2 connects to the drain terminal of the external output switch and to flyback 11 side of the inductive load. The external fly-back 12 rectifier diode D4 (FIG. 1, 3 and 4) anode is connected 13 to node SNL2. Node SNOUT connects to the storage 14 capacitors [C16~~C17] (FIG. l, 3 and 4) and to the cathode of the flyback diode D4. External diode D4 in 16 parallel with DSN forms a hybrid diode. The Schottky 17 diode has the desirable characteristics of fast recovery 18 time (less than 6 nanoseconds (6* 10~-9)) and low forward 19 voltage drop (0.4 - 0.9 Volts) at high currents. The Schottky diode suffers from limited reverse blocking 21 voltage currently 100 V maximum. Each diode will block 22 100V; the parallel capacitors distribute the reverse 23 voltage equally across the diode string. As the reverse 24 junction capacitance of each diode is less than 10 pf much smaller than the parallel capacitor. Thus the 1 reverse voltage is nearly equally divided across the 2 diodes. To guarantee even voltage division 5% or better 3 capacitor matching is required. High precision is common 4 and inexpensive for small capacitors. Different blocking voltages may be achieved by adjusting the number of diode 6 / capacitor pairs. By way of example not as a limitation 7 500V was selected. The main fly-back rectifier diode D4 8 will block high voltages but suffers from long reverse 9 recovery time 50-500 nanoseconds is common in fast recovery diodes. What is needed is a diode with low 11 voltage drop, high blocking voltage and very short 12 recovery time. The snubber DSN in parallel with the main 13 fly-back rectifier comes very close to that ideal diode.
14 The total blocking voltage is achieved by the adding the individual diode blocking voltages. The recovery time is 16 determined by the slowest diode in the string often less 17 than 5 nanoseconds. The low forward voltage drop is 18 achieved when the slower main rectifier begins 19 conduction. Low capacitance is also realized, as the capacitance is 1/5 of the individual capacitors. This 21 hybrid diode begins rectification immediately after the 22 main switch stops conduction and the non-saturating 23 magnetic begins releasing its energy. This effectively 24 limits the high voltage flyback over shoot to less than 40-70 volts. This keeps the switch well inside it's safe 26 operating area (SOA) allowing the switch to be run at 27 higher voltages for higher output power and additional 28 efficiency gain, or to use a less expensive lower voltage 29 switch while keeping the same voltage margins. Since external flyback diode D4 and D805 isolate the drain of 31 output switch, faster switching occurs because the output 32 switch does not have to slew the extra capacitance of the 1 typical snubber circuit. Note that this circuit does not 2 attempt to absorb the flyback in large RC networks that 3 generate additional heat. Nor does it attempt to stuff 4 the flyback to ground, adding capacitance and slowing the output switch, increasing switching losses. Sub-circuit 6 DSN may be used in parallel with any slower rectifier 7 such as flyback diode D4 to assist the main rectifier.
8 This providing additional protection to the switch and 9 rectifying the portion of the flyback pulse before the main rectifier begins condition. That high frequency 11 energy ends up as heat or radiated noise.
12 FIG. 30B is a schematic diagram of an alternate 13 snubber sub-circuit SNBB of the invention. The snubber 14 sub-circuit SNBB is comprised of resistor 8310 and capacitor C821.
Figure Table Element Value/part number 8821 470pF

8310 12 ohm 16 Node SNL2 connects through capacitor C821 to 17 resistor 8821 to node SNOUT. Node SNOUT connects to the 18 cathode of the flyback diode. Node SNL2 connects to the 19 drain terminal of the external output switch and to flyback side of the inductive load. The "snubbering"
21 action slows the rise of the flyback giving time for the 22 external rectifier diodes) to begin conduction.
23 FIG. 31 is a schematic diagram of a snubber sub-24 circuit of the invention. The snubber sub-circuit SNA is comprised of resistor 8810 and 8811 and capacitors C820 26 and C821.
Figure 31 Table Element Value/part number 8810 500pF

C811 330pF

C820 12 ohm C821 I10 ohm 1 Node SNA1 connects to series resistor 8810 to 2 capacitor C820 to node SNA2 then to capacitor C821 and 3 series resistor 8811 to node SNA3. Node SNAl connects to 4 the external magnetic element center tap. Node SNA2 connects to the drain terminal of the external output 6 switch and to flyback side of the inductive load. Node 7 SNA3 connects to the source terminal of the external 8 output switch. Resistor 8810 and C820 attempt to absorb 9 part of the flyback to reduce voltage transients across the switch. Part of the flyback is returned to ground by 11 C821. This sub-circuit is used with its mirror SNA (FIG.
12 31) across the external push-pull switches. The 13 "snubbering" action slows the rise of the flyback giving 14 time for the external rectifier diodes D8 and D9 of FIG.
25 or 25A to start conduction. The circuit efficiently 16 manages high frequency flyback pulses.
17 FIG. 32 is a schematic diagram of a snubber sub-18 circuit of the invention. The snubber sub-circuit SNB
19 comprises resistor 8820 and 8821 and capacitors C840 and C841.
Figure Table Element Value/part number C840 500pF

C841 330pF

88 2 0 12 ohm 8821 I10 ohm 21 Node SNB1 connects to series resistor 8820 to 22 capacitor C820 to node SNA2 to capacitor C841 and to 23 series resistor 8821 to node SNB3. Node SNB1 connects to 24 the external magnetic element center tap. Node SNB2 connects to the drain terminal of the external output 26 switch and to flyback side of the inductive load. Node 27 SNB3 connects to the source terminal of the external 28 output switch. Resistor 8820 and C840 attempt to absorb 1 part of the high frequency flyback to reduce voltage 2 transients across the switch. C841 and 8821 return part 3 of the flyback to ground. The "snubbering" action slows 4 the rise of the flyback giving time for the ext ernal S rectifier diodes D8 and D9 of FIG. 25 or 25A to start 6 conduction. The circuit efficiently manages high 7 frequency flyback pulses.

8 Fig. 33 is the inventions PWM (pulse width 9 modulator) and FM (frequency modulator) sub-circuit. Sub-10circuit PWFM consists of resistors 8401, 8402, 8403 , and 118404 capacitors C401, C402, C403, C404, C405 and C406, 12controller IC U400 and diode D401.

Figure 33 Table Element Value/part number 8404 50k ohms C406 100uf C401 0.22uF

C403 O.OluF

C405 2200pF

C404 470pF

C402 0.22uF

8403 50k ohms D401 RLS139(low leakage) 8401 2.2 MEG ohms 8402 150k ohms 13Control element U400 connects to a circuit with the 14following series connections: from pin 1 to feedback pin 15PW1 then to the wiper of adjustable resistor 8404 to 16return node PWFMO. Resistor 8404 may be replaced with two 17fixed resistors. Capacitor C403 is connected n from pi 2 1 to pin 1. Capacitor C403 is used to filter the error amp 2 output. The upper half of resistor 8404 is connected to 3 node REF1 pin 8 the 5.0-Volt internal reference. Internal 4 5.0-volt reference U400 pin 8 or Node REF1 is connected to the upper half of resistor 8403 and through capacitor 6 C402 to return node PWFMO. The reference provides current 7 to external feed back networks. Wiper of 8403 connects to 8 node FM1 to pin 4, through 8402 to pin 3, and through C404 9 to return node PWFMO. Resistor 8403 may be replaced with two fixed resistors. Pulse width timing capacitor C404 11 connects pin 3 to return node PWFMO. Low leakage diode 12 D401 anode is connected to pin 3 cathode to output pin 6 13 node CLK. Resistor 8404 sets the nominal pulse width of 14 output pin 6 node CLK. The pulse width can be adjusted from 0 (off) to 95%. Resistor 8403 and C404 determine the 16 nominal operating frequency. With application of power 17 20-volts between Nodes PWFM+ and PWFMO controller U400 18 generates an internal 5.0 reference voltage to pin 7 node 19 REF1. Output pin 6 node CLK is set high approximately 20-volts (see oscillograph trace G6 segment 60 FIG. 34).
21 C404 starts to charge through 8401 until the voltage 22 across C404 at pin 3 reaches the comparator level (see 23 oscillograph trace G1 segment 61 FIG. 34) at resetting 24 the pin 6 low (see oscillograph trace G6 segment 62 FIG.
34). Capacitor C404 rapidly discharges though D401 (see 26 oscillograph trace G1 segment 63 FIG. 34). Pin 3 remains 27 0.6-volts above PWFMO node during the period pin 6 is low 28 (see oscillograph trace G1 segment 64 FIG. 34). On the 29 rising edge of pin 6 capacitor C405 begins to rapidly charge until the voltage in pin 4 reaches the internal 31 comparator level (see oscillograph trace G4 segment 65 32 FIG. 34). The comparator triggers internal transistor to 1 rapidly discharge C404 (see oscillograph trace G4 segment 2 66 FIG. 34). The cycle repeats with output pin 6 being 3 set high . External feedback current applied to U400 pin 4 and node PW1 (see oscillograph trace G1 segment FIG. 34) follows the actual output voltage. Oscillograph trace G1 6 segment 67 (FIG.
34) is the period when the output switch 7 conducting storing energy in the NSME. Oscillograph trace 8 G1 segment 68 (FIG. 34) is the period when the output 9 switch is off allowing storing energy in the NSME to be transferred to the storage capacitor. Application of 11 external current source or feed back network to pin 1 or 12 node PWl allows the pulse width to be modulated. Removing 13 current from PW1 lowers the comparator level causing the 14 comparator to trigger at lower voltages across C404 reducing the pulse width. Introducing current into node 16 PW1 increases pulse width from nominal to maximum of 95%.
17 Resistor 8404 and C404 determine the nominal pulse width.
18 This design allows the CLK output to be pulse width 19 modulated. Application of external feed back network to pin 4 or node FW1 allows the frequency to be modulated.
21 Removing current from FW1 slows the charging of C405.
22 Longer charging time lowers the frequency from the 23 nominal setting. This arrangement allows the CLK output 24 to frequency modulated. When used with a resonant controller, 8403 and C405 determine the nominal frequency 26 typically equal to the tank resonant frequency. The 27 external feedback is configured to lower the frequency 28 from nominal (maximum output) to zero frequency "off".
29 When used as a pulse-width controller the nominal is set to maximum pulse width of about 90% feedback reduces the 31 pulse-width. Sub-circuit PWFM may be simultaneously 32 frequency and pulse width modulated. This configuration 1 and mode of operation is unique to this instant 2 invention. Feeding back of the output to the error 3 amplifier is a unique mode of operation for control 4 element U400. Sub-circuit PWFM combines large dynamic range, precise control and fast response.
6 FIG. 34 Oscillograph traces of the PWFM (FIG. 33) 7 controller in the pulse-width modulation mode.
8 FIG. 35 Oscillograph trace of the TCTP (FIG. 8) 9 resonant converter primary voltage. FIG. 35 is an oscillograph trace of the voltage developed across 11 capacitor C10 (FIG. 8). In this embodiment the supply 12 VBAT was only 18-volts.
13 The primary 100 (FIG. 18) inductance 203 uH was 14 achieved by 55 turns on a 26u 2.28 oz. KoolMu magnetic element 101. The secondary winding 103 (FIG. 18) is 15 16 turns on core 101. A 5.5-watt load is connected to 17 winding 103. The NSME primary 100 (FIG. 18) developed an 18 excitation voltage of 229 volts peak more than 10 times 19 VBAT. Tank converters TCTP and TCSSC (FIG. 7) take advantage of the desirable properties of the non-21 saturating magnetic to develop large flux biases. The 22 useful large flux may harvested into useful power by 23 addition of "flux nets" windings to the magnetic element.
24 FIG. 36 Regulated 18 Volt DC control power sub-circuit REG. Sub-circuit REG consists of resistor 8517, 26 regulator Q514 and capacitors C514, C515, C516, C518, and 27 C517 .
Figure 36 Table Element Value/part number C515 O.luF

C517 0.luF

C514 10 uF

C518 10 uF

1 Pin REGO connects to the external power source 2 return. Node REGO is also the return line it connects to 3 Q514 pin 2, and capacitors C518, C514, C515, and C517.
4 Resistor 8517 is connected to the pin 1 (input) node of voltage regulator Q514 and to input pin RIN+. Voltage 6 regulator Q514 Pin 3 is the l8vdc regulated DC output is 7 connected to the capacitors C515, C514 and output pin 8 18V. Capacitors C515, C517 are solid dielectric type is 9 used to filter high frequency ripple and to prevent Q514 from oscillating. Sub-circuit REG provides regulated 11 power for control circuits and output switch buffer AMP
12 (FIG. 29) .
13 FIG. 37 is a schematic for a non-isolated high side 14 switch buck converter sub-circuit HSBK. FIG. 37 is a non-isolated high side switch buck converter sub-circuit 16 HSBK. This converter topology consists of a non-isolated 17 high efficiency buck stage, which provides regulated 18 power to an efficient push-pull isolation stage. Sub-19 circuit HSBK consists of diode D8, capacitor C8, FET

transistor Q31, sub-circuit TCTP (FIG. 8), sub-circuit 21 HL1 (FIG. 18B), sub-circuit IFB (FIG. 40B), sub-circuit 22 AMP (FIG. 29) and sub-circuit PWFM (FIG. 33).

Figure 37 Table Element Value/part number C68 250uf 23 External power source VBAT connects to pins DCIN+

1 and DCIN-. Pin DCIN+ connects to transistor Q31 source, 2 sub-circuit PWFM pin PWFMO, sub-circuit AMP pin GAO, and 3 sub-circuit IFB pin FBE, sub-circuit TCTP pins DCIN+ and 4 B-. Regulated 18-volt output from sub-circuit TCTP pin B+
connects to sub-circuit AMP pin GA+ and to sub-circuit 6 PWFM pin PWFM+. This provides the positive gate drive 7 relative to the source of Q31. Power source VBAT return 8 is connected to pin DCIN-, sub-circuit TCTP pin DCIN-, 9 diode D68 anode, capacitor C68, RLOAD, sub-circuit IFB
pin OUT- , output pin B- and ground/return node GND . Sub-11 circuit PWFM is designed for adjustable pulse-width 12 operation from 0 to 90%, maximum pulse width occurs with 13 no feedback current to pin PW1. Increasing the feedback 14 current reduces ,the pulse-width and output voltage from converter HSBK. Sub-circuit PWFM clock/PWM output pin CLK
16 is connected to the input pin GA1 of buffer sub-circuit 17 AMP. The output of sub-circuit AMP pin GA2 is connected 18 to the gate of Q31. The drain of Q31 is connected to sub-19 circuit BL1 pin P1B and the cathode of D68. Pin P1A of sub-circuit BL1 is connected to capacitor C8, sub-circuit 21 IFB pin OUT- and RLOAD. With sub-circuit PWFM pin CLK
22 high buffer AMP output pin GA2 charges the gate of 23 transistor switch Q31. Switch Q31 conducts charging 24 capacitor C68 through NSME BL1 from source VBAT and storing energy in BL1. Feedback output pin FBC f rom sub-26 circuit IFB is connected to sub-circuit PWFM pulse-width 27 adjustment pin PW1. As the output voltage reaches the 28 designed level sub-circuit IFB removes current from PW1 29 commanding PWFM to reduce the pulse-width or on time of signal CLK. After sub-circuit PWFM reaches the commanded 31 pulse-width PWFM switches output pin CLK low turning off 32 Q31 stopping the current into BL1. The stored energy is 1 released from NSME BL1 into the now forward biased diode 2 D68 charging capacitor C68. By modulating the on time of 3 switch Q31 the converter "bucks" applied. voltage and 4 efficiently regulates to a lower voltage. Regulated voltage is developed across Nodes B- and B+. Sub-circuit 6 IFB provides the isolated feedback voltage to the sub-? circuit PWFM. When sub-circuit IFB senses the converter 8 output (nodes B+ and B-) is at the designed voltage more 9 current is conducted by the phototransistor. Sinking current from PM1 commands the PWFM to a shorter pulse-11 width thus reducing the converter output voltage. In the 12 event the feedback signal from IFB commands the PWFM to 13 minimum output. Gate drive to switch Q31 is removed 14 stopping all buck activity capacitor C68 discharges through RLOAD. Input current from VBAT is sinusoidal 16 making the converter very quiet. As such the switch Q31 17 is not exposed to large current spikes common to 18 saturating magnetic prior art. Thus placing less stress 19 on the switches thereby increasing the MTBF. Sub-circuit HSBK takes advantage of the desirable properties of the 21 NSME in this converter topology.
22 FIG. 38 is a schematic for an isolated two-stage low 23 side switch buck converter sub-circuit LSBKPP. This 24 converter topology consists of a high efficiency low-side switch buck stage, which provides regulated power to an 26 efficient push-pull isolation stage. An efficient center-27 tap fullwave rectifier provides rectification. Sub-28 circuit LSBKPP consists of diode D46, capacitor C46, FET
29 transistor Q141, sub-circuit REG (FIG. 36), sub-circuit OUTB (FIG. 25A), sub-circuit BL1 (FIG. 18B), sub-circuit 31 TCTP (FIG. 8), sub-circuit IFB (FIG. 40B), sub-circuit 32 AMP (FIG. 29), sub-circuit DCAC1, and sub-circuit PWFM
33 (FIG. 33).

Figure Table Element Value/part number C46 250uf 2 External power source VBAT connects to pins DCIN+
3 and DCIN-. From pin DCIN+ connects to sub-circuit REG pin 4 RIN+, D46 cathode, capacitor C46, sub-circuit TCTP (FIG.
8) pin DCIN+, and sub-circuit DCAC1 pin DC+. Voltage 6 regulator sub-circuit REG output pin +18V connects to 7 sub-circuit AMP pin GA+ and to sub-circuit PWFM pin 8 PWFM+. Sub-circuit REG provides regulated low voltage 9 power to the controller and to the main switch buffer.
VBAT negative is connected to pin DCIN- and ground return 11 node GND. Node GND connects to sub-circuit PWFM pin 12 PWFMO, sub-circuit AMP pin GAO, Q141 source, sub-circuit 13 IFB pin FBE, sub-circuit REG pin REGO and sub-circuit 14 TCTP pin DCIN-. Sub-circuit PWFM (FIG. 33) is designed for variable pulse width operation. The nominal frequency 16 is between 20-600Khz PWFM is configured for maximum pulse 17 width 90s (maximum buck voltage) with no feedback current 18 from sub-circuit IFB. Increasing the feedback current 19 reduces the Q111 on time reducing the voltage to the push-pull stage and the output from converter LSBKPP.
21 Sub-circuit PWFM clock output pin CLK is connected to the 22 input pin GA1 of buffer sub-circuit AMP (FIG. 29). The 23 output of switch speed up buffer sub-circuit AMP pin GA2 24 is connected to the gate of Q141. Floating isolated 18-volt power from sub-circuit TCTP pin B+ connects to sub-26 circuit DCAC1 pin P18V. The drain of Q141 is connected to 27 sub-circuit BL1 pin P1A and the anode of D46. The return 28 line of sub-circuit DCAC1 pin DC- connects to sub-circuit 1 BL1 pin P1B, sub-circuit TCTP pin B- and C46. With sub-2 circuit PWFM pin CLK high buffer AMP output pin GA2 3 charges the gate of transistor switch Q141. Switch Q141 4 conducts reverse biasing diode D46; capacitor C46 starts charging through NSME BL1 from source VBAT. During the 6 time Q141 is conducting, energy is stored in NSME ~sub-7 circuit BL1. Charging C46 provides power to final push-8 pull converter stage DCAC1. The output of the output 9 rectifier sub-circuit OUTB is connected to feedback sub-circuit IFB output pin FBC from sub-circuit IFB is 11 connected to sub-circuit PWFM pulse-width adjustment pin 12 PW1. Sub-circuit IFB removes current from PW1 commanding 13 PWFM to reduce the pulse-width or on time of signal CLK.
14 After sub-circuit PWFM reaches the commanded pulse-width PFFM switches CLK low turning off Q141 stopping the 16 current into BL1. The energy is released from NSME BL1 17 into the now forward biased flyback diode D46 charging 18 capacitor C46. By modulating the on time of switch Q141 19 the converter voltage is regulated. Regulated voltage is developed across C46 Nodes DC+ and GND. Providing energy 21 to the isolated constant frequency push-pull DC to AC
22 converter sub-circuit DCAC1 (FIG. 2). Sub-circuit DCAC1 23 provides efficient conversion of the regulated buck 24 voltage to a higher or lower voltage set by the magnetic element winding sub-circuit PPT1 (FIG. 19) ratio. The 26 center tap of the push-pull output magnetic is connected 27 to, sub-circuit OUTB pin OUT-, RLOAD, sub-circuit IFB pin 28 OUT- and the pin OUT- forming the return line for the 29 load and feedback network. Output of sub-circuit DCAC1 pin ACH is connected to sub-circuit OUTB pin C7B. Output 31 of sub-circuit DCAC1 pin ACL is connected to sub-circuit 32 OUTB pin CBB. Sub-circuit OUTB provides rectification of 1 the AC power generated by sub-circuit DCAC1. As the non-2 saturation magnetic converter is very quite minimal 3 filtering is required by OUTB. This further reduces cost 4 and improves efficiency as losses to filter components are minimized. Sub-circuit IFB provides the isolated 6 feedback current to the sub-circuit PWFM. When sub-? circuit IFB senses the converter output (nodes OUT+ and 8 OUT-) is greater than the designed/desired voltage, 9 current is removed from node PM1. Sinking current from PM1 commands the PWFM to a shorter pulse-width thus 11 increasing the buck action and reducing the first stage 12 converter output voltage. In the event the feedback 13 signal from IFB commands the PWFM to minimum output. Gate 14 drive to switch Q141 is removed stopping all buck activity capacitor discharging C46. Input current from 16 VBAT to charge C46 is sinusoidal making the converter 17 very quiet . In addition the switch Q141 is not exposed a 18 potentially destructive current spike. Placing less 19 stress on the switches thereby increasing the MTBF. Sub-circuit LSBKPP takes advantage of the desirable 21 properties of the NSME in this converter topology.
22 Adjusting the NSME BL1 (FIG. 18B) sets the amount of buck 23 voltage available to the final push-pull isolation stage.
24 Greater efficiencies are achieved at higher voltages. The final output voltage is set by the turns ratio of the 26 push-pull element PPT1 (FIG. 19). Converter LSBKPP
27 provides efficient conversion from high voltage sources 28 into high current isolated output.
29 FIG. 39 is a schematic for an isolated two-stage low side switch buck converter sub-circuit LSBKPPBR. This 31 converter topology consists of a non-isolated high 32 efficiency low-side switch buck stage, which provides 1 regulated power to an efficient push-pull isolation 2 stage. . A fullwave bridge rectifier provides 3 rectification. Sub-circuit LSBKPPBR consists of diode D6, 4 capacitor C6, FET transistor Q111, sub-circuit REG (FIG.

S 36), sub-circuit OUTBB (FIG. 25B), sub-circuit BL1 (FIG.

6 18B), sub-circuit TCTP (FIG. 8), sub-circuit IFB (FIG.

7 40B), sub-circuit AMP (FIG. 29), sub-circuit DCAC1 (FIG.

8 2), and sub-circuit PWFM (FIG. 33).

Figure 39 Table Element Value/part number C6 250uf 9 External power source VBAT connects to pins DCIN+
and DCIN-. From pin DCIN+ connects to sub-circuit REG pin 11 RIN+, D6 cathode, capacitor C6, sub-circuit TCTP (FIG. 8) 12 pin DCIN+, and sub-circuit DCAC1 pin DC+. Voltage 13 regulator sub-circuit REG output pin +18V connects to 14 sub-circuit AMP pin GA+ and to sub-circuit PWFM pin PWFM+. Sub-circuit REG provides regulated low voltage 16 power to the controller and to the main switch buffer.
17 VBAT negative is connected to pin DCIN- connects to sub-18 circuit PWFM pin PWFMO, sub-circuit AMP pin GAO, Q111 19 source, sub-circuit IFB pin FBE, sub-circuit REG pin REGO, sub-circuit TCTP pin DCIN-. Sub-circuit PWFM (FIG.
21 33) is designed for variable pulse width operation. The 22 nominal frequency is between 20-600Khz PWFM is configured 23 for maximum pulse width 90% (maximum buck voltage) with 24 no feedback current from sub-circuit IFB. Increasing the feedback current reduces the Q111 on time reducing the 26 voltage to the push-pull stage and the output from 1 converter LSBKPPBR. Sub-circuit PWFM clock output pin CLK
2 is connected to the input pin GA1 of buffer sub-circuit 3 AMP ( FIG . 2 9 ) . The output of switch speed up buf f er sub-4 circuit AMP pin GA2 is connected to the gate of Q111.
Floating isolated 18-volt power from sub-circuit TCTP pin 6 B+ connects to sub-circuit DCAC1 pin P18V. The drain of 7 Q111 is connected to sub-circuit BL1 pin PA1 and the 8 anode of D6. The return line of sub-circuit DCAC1 pin DC-9 connects to sub-circuit BL1 pin P1B, sub-circuit TCTP pin l0 B- and C6. With sub-circuit PWFM pin CLK high buffer AMP
11 output pin GA2 charges the gate of transistor switch 12 Q111. Switch Q111 conducts reverse biasing diode D6;
13 capacitor C6 starts charging through NSME BL1 from source 14 VBAT. During the time Q111 is conducting, energy is stored in NSME sub-circuit BL1. Charging C6 provides 16 power to final push-pull converter stage DCAC1. The 17 output of the output rectifier sub-circuit OUTBB is 18 connected to feedback sub-circuit IPB output pin FBC from 19 sub-circuit IFB is connected to sub-circuit PWFM pulse-width. adjustment pin PW1. Sub-circuit IFB removes current 21 from PW1 commanding PWFM to reduce the pulse-width or on 22 time of signal CLK. After sub-circuit PWFM reaches the 23 commanded pulse-width PFFM switches CLK low turning off 24 Q111 stopping the current into BL1. The energy is released from NSME BL1 into the now forward biased 26 flyback diode D6 charging capacitor C6. By modulating the 27 on time of switch Q111 the converter voltage is 28 regulated. Regulated voltage is developed across C6 nodes 29 DC+ and DC-. Providing energy to the isolated constant frequency push-pull DC to AC converter sub-circuit DCAC1 31 (FIG. 2). Sub-circuit DCAC1 provides efficient conversion 32 of the regulated buck voltage to a higher or lower 1 voltage set by the magnetic element winding sub-circuit 2 PPT1 (FIG. 19) ratio. The return node of the sub-circuit 3 OUTBB pin OUT- is connected to RLOAD, sub-circuit DCAC1 4 pin ACO, sub-circuit IFB pin OUT- and the pin OUT-. Node OUT- is the return line for the load and feedback 6 network. Output of sub-circuit DCAC1 pin ACH is connected 7 to sub-circuit OUTBB pin C7B. Output of sub-circuit DCAC1 8 pin ACL is connected to sub-circuit OUTBB pin CBB. Sub-9 circuit OUTBB provides rectification of the AC power generated by sub-circuit DCAC1. As the disclosed non-11 saturation magnetic converter has minimal output ripple, 12 less filtering is required by OUTBB. This further reduces 13 cost and improves efficiency as losses in filter 14 components are minimized. Sub-circuit IFB provides the isolated feedback current to the sub-circuit PWFM. Open 16 collector output of IFB pin FBC connects to PWFM pin PW1.
17 When sub-circuit IFB senses the converter output (nodes 18 OUT+ and OUT-) is greater than the designed/desired 19 voltage, current is removed from node PM1. Sinking current from PM1 commands the PWFM to a shorter pulse-21width thus increasing the buck action and reducing the 22first stage converter output voltage. In the event the 23feedback signal from IFB commands the PWFM to minimum 24output. Gate drive to switch Q111 is removed stopping all 25buck activity capacitor As the NSME does discharging C6.

26 not saturate the destructive noisy current spikes common 27to prior art are absent. Input current from VBAT to 28charge C6 is sinusoidal making the converter very quiet.

29In addition exposed a potentially the switch Q111 is not 30destructive less current stress spike. on the Placing 31switches thereby increasing the MTBF. Sub-circuit 32LSBKPPBR takes advantage of the desirable properties of 1 the NSME in this converter topology. Adjusting the NSME

2 BL1 (FIG. 18B) se ts the amount available of buck voltage 3 to the final push-pull isolation stage. Greater 4 efficiencies are achieved The final at higher voltages.

output voltage is set by the turns ratio of the push-pull 6 element PPTl (FIG. Converter LSBKPPBR provides 19).

7 efficient conversion from high voltage sources such as 8 high power factor AC to DC converters such as sub-circuit 9 ACDCPF (FIG. 4).
FIG. 40 is the schematic of the inventions isolated 11 over voltage feed back network sub-circuit IPFFB. Sub-12 circuit IPFFB consists of Resistors 8926, 8927, 8928, 13 8929 and 8930, capacitor C927, zener diodes D928 and 14 D903, transistor Q915 and opto-isolator U903.
Figure 40 Table Element Value/part number D903 ML5248B (18v) D928 1SMB5956BT3 (200v) 8926 20k ohms 8927 lOk ohms 8928 lOk ohms 8929 lOk ohms 8930 20k ohms Node PF+ connects through resistor 8927 to cathode 16 of D903 and of diode anode of opto-isolator U903. Cathode 17 D903 is connected to pin PF+.
Resistor 8928 is connected 18 from anode D928 to base of Q915. Capacitor C927 is of 19 connected parallel with zener diode D903. Resistor in 8928 limits maximum base current. Resistor 8929 is 1 connected between base and emitter of Q915. Resistor 8929 2 is used to shunt excess zener leakage current from the 3 base common in high voltage diodes. Two hundred-volt 4 zener diode cathodes D928 are connected to pin PF+. Anode of D928 is connected to 8930 and 8928. Resistor 8930 6 provides a path for leakage current from 200-volt zener 7 D928. Resistor 8926 limits the maximum current to U903 8 internal light emitting diode to about lOma. Resistor 9 8927 sets the maximum zener current at maximum boost voltage of approximately 200-volts to 20ma. Transistor 11 Q915 is biased off when the voltage from node PF+ and PF-12 is less than the zener voltage of 200-volts. Transistor 13 is in a cutoff or non-conducting state no current is 14 injected to U903 LED. The internal phototransistor is also in a non-conducting state. The attached external 16 control sub-circuit is not commanded to change its 17 output. With 200 volts or more applied to nodes PF+ and 18 PF- reverse biased zener diode D928 injects current into 19 the base of Q915. Resistor 8927, capacitor C927 and diode D903 provide 18-volts to the collector of Q915.
21 Transistor Q915 conducts current into U903 LED injecting 22 base current into the U903 phototransistor. Modulating 23 the LED current is reflected as variable impedance 24 between FBC and FBE. This phototransistor may be connected as a variable current source or impedance. This 26 sub-circuit senses excessive boost voltage and quickly 27 feeds back to the control sub-circuit (See PFA (FIG. 23), 28 PFB (FIG. 24) or (PWFM FIG. 33)) automatically reducing 29 the boost voltage.
FIG. 40A is a schematic diagram of the non-isolated 31 boost output voltage feed back sub-circuit FBA. Sub-32 circuit FBA consists of Resistors 81120, 81121, 81122, 1 81123 and 81124.
Figure 40A Table Element Value/part number 81123 499k ohms 81124 499k ohms 81122 6.65k ohms 81121 499k ohms 81120 1MEG ohms 2 Input node PF+ connected to series resistor 3 [81123+81124] then to parallel resistors [R20~~R21~~R22]
4 to the return node BR-. Resistors 81120, 81121, 81122, 81123 and 81124 values are selected for a nominal input 6 voltage of 385-volts and output feed back voltage of 7 3.85. (See oscillograph G1 FIG. 34) Resistors 81120, 8 81121, 81122, 81123 and 81124 are shown in surface mount 9 configuration but can be combined into two thru hole-resistors. Feedback output node PF1 is connected to node 11 PF1 of sub-circuit PFA (FIG. 23) or PFB (FIG. 24). Return 12 pin BR- is connected to BR- of PFA (FIG. 23) or PFB (FIG.
13 24). Nodes FBE and FBC it may also be connected between 14 nodes FM1 pin PWFMO or PW1 pin PWFMO of control sub-circuit PWFM (FIG. 33) .
16 FIG. 40B is the schematic of the inventions isolated 17 low voltage feed back network sub-circuit FBA. Sub-18 circuit IFB consists of Resistors 8900, 8901 and 8902, 19 zener diode D900, Darlington transistor Q900 and opto-isolator U900.
Figure 40B Table Element Value/part number 8900 1k ohms 8902 4k ohms 8901 40k ohms 1 Node OUT+ connects cathode of D900 to 8901. Anode of 2 diode D900 is connected to series resistor 8900 to base 3 of Darlington transistor Q900. Resistor 8902 is connected 4 from base to emitter to Q900. Resistor 8901 connects to anode of opto-isolator U900 LED (light emitting diode) 6 the cathode is connected to Q900 collector. Emitter of 7 Q900 is the return current path and connects to pin/node 8 OUT-. Resistor 8901 limits the maximum current to U900 9 internal light emitting diode to 20ma. Resistor 8902 shunts some of the zener leakage current from the base.
11 Zener diode voltage selection sets the converter output 12 voltage a typical value maybe 48-volts. The zener voltage 13 is the final desired output minus two base emitter 14 junction drops (1.4V). Once the OUT+ node reaches the zener voltage a small base current biases Q900 into a 16 conducting state turning "on" opto-isolator U900 internal 17 LED. Resistor 8900 limits the maximum base current to 18 Q900. Resistors 8900 and 8901 are selected to bias 19 Darlington transistor Q900 collector current with nominal voltage across nodes OUT+ and OUT-. Change in voltage 21 between OUT+ and OUT- modulates the opto-isolator U900 22 LED current in turn changing the base current of U900 23 internal photo transistor. Phototransistor emitter is 24 node FBE collector is node FBC. Modulating the LED
current is reflected as variable impedance between FBC
26 and FBE. This phototransistor may be connected as a 27 variable current source or impedance. When used with 1 control sub-circuit PFA (FIG. 23), PFB (FIG. 24) or (PWFM
2 FIG. 33) the phototransistor is connected as a current 3 shunt. Higher voltage applied to OUT+ and OUT- nodes 4 increases the feedback shunt current commanding the control sub-circuit (See PFA (FIG. 23) or PFB (FIG. 24) 6 or PWFM (FIG. 33)) to reduce the pulse-width or 7 frequency. IFB accomplishes high speed feed back due to 8 the very high gain of the Darlington transistor and the 9 rapid response of the internal converter stages) active ripple reduction and excellent load regulation are 11 achieved.
12 FIG. 40C is the schematic of the alternate PFC
13 isolated over voltage feed back network sub-circuit 14 IOVFB. Sub-circuit IOVFB consists of resistors of 8917, 8938, 8939 and 8940, diode D911, Darlington transistor 16 Q914 and opto-isolator U905.
Figure 40C Table Element Value/part number 8938 160k ohms 8939 70k ohms 8940 50k ohms 8917 40k ohms 17 The output of the PFC at pin PF+ is connected to 18 8917 then to collector of Q914. Resistor 8917 sets the 19 maximum current to U905 light emitting diode. Resistor 8938 is connected from return node PF+ to zener diode 21 D911 cathode and 8938. Resistor 8939 is connected from 22 return node PF- to zener diode D911 cathode and 8938.

1 Anode of D911 is connected to wiper arm of adjustable 2 resistor 8940. One leg of 8940 is connected to the base 3 of transistor Q914 the other to 8939 and U905 LED anode 4 and 8939. Emitter of Q914 is connected to anode of U904.
Adjustable resistor 8940 sets the maximum or trip voltage 6 before transistor Q914 is biased on. Providing current to 7 U905 LED. Phototransistor emitter is node FBE collector 8 is node FBC. Modulating the LED current is reflected as 9 variable impedance between FBC and FBE. This phototransistor is normally connected as a shunt to force 11 the control element to a minimum output. This sub-circuit 12 senses the boost voltage and feeds back to the PFC. Where 13 excessive boost voltage forces the PFC to automatically 14 reduce the boost voltage.
FIG. 40D is a schematic diagram of and alternate for 16 the non-isolated boost output voltage feed back sub-17 circuit FBD Sub-circuit FBD consists of Resistors 81120, 18 81121, 81122, 81123 and 81124.
Figure 40A Table Element Value/part number 81123, 499k ohms 81122 l.OOk ohms w 81121 l.OOk ohms 81123 66.5k ohms 81120 6.65k ohms 19 Input node PF+ connected to series resistor [81123+81124] then to parallel resistors [R1122~~R1121].
21 The other side of [R1122~~R1121] is connected to wiper 22 arm of 81121 and through to [R1123~~R1120] to the return 23 node BR-. Resistor values are selected for a nominal 1 input voltage of 385-volts. Resistors 81120-81124 are 2 shown in a surface mount configuration but, can be 3 combined into other series parallel combinations to form 4 other equivalent circuits. Feedback output node PF1 is connected to node PF1 of sub-circuit PFA (FIG. 23) or PFB
6 (FIG. 24). Return pin BR- is connected to BR- of PFA
7 (FIG. 23) or PFB (FIG. 24). Nodes FBE and FBC may also 8 be connected between nodes FM1 pin PWFMO or PWl pin PWFMO
9 of control sub-circuit PWFM (FIG. 33). Component values are selected to provide a 15-volt adjustment range.
11 FIG. 41 is the schematic of the alternate low 12 voltage feed back network sub-circuit FBI. Sub-circuit 13 FBI consists of Resistors 881, 882 and 883, zener diode-14 D80, NPN transistor Q80 and capacitor C80.
Figure 41 Table Element Value/part number 881 1k ohms D80 Zener Voltage = (Desired Output-0.65V) C80 1000pf 882 1k ohms 883 715k ohms 15Node OUT+ connects cathode of D80. Anode of diode 16D80 is connected to through resistor 883 to OUT- and 17resistor 882 to base of transistor Q80. Capacitor C80 is 18connected from base to pin OUT-. Capacitor C80 bypas ses 19high frequency to noise to OUT-. Resistor 881 is 20connected from emitter of Q80 to node OUT- . Resistor 881 21adds local negative feedback to reduces the effects of 22variation in transistor gain. Collector of Q80 is 23connected to pin FBC. The return current node connects to 1 pins FBE and OUT-. Resistor R82 limits the maximum base 2 current protecting Q80. Resistor R83 shunts some of the 3 zener leakage current from the base. Zener diode voltage 4 selection sets the converter output voltage a typical value maybe 48-volts. The zener voltage is the final 6 desired output minus one base emitter junction drop 7 (0.65-Volts). When the OUT+ node reaches the nominal 8 level reverse biased zener starts to conduct injecting a 9 small base current into Q80. Biasing transistor into a l0 conducting state. Change in voltage between OUT+ and OUT-11 modulates Q80 collector current. During normal operation 12 the zener diode is biased at it's knee thus small changes 13 in voltage result in relatively large collector current 14 changes. When sub-circuit FBI used with control sub-circuit PFA (FIG. 23), PFB (FIG. 24) or (FIG. 33) the 16 transistor is connected as a current shunt. Higher 17 voltage applied to OUT+ and OUT- nodes increases the 18 feedback shunt current commanding the control sub-circuit 19 (See PFA (FIG. 23) or PFB (FIG. 24) or PWFM (FIG. 33) to reduce the pulse-width or frequency. Sub-circuit FBI
21 provides high-speed feedback and gain to ripple 22 components. With the rapid response of the internal 23 converter stages) active ripple reduction and excellent 24 load regulation are achieved.
FIG. 41A is the schematic of an alternate over 26 voltage feed back network sub-circuit FB2. Sub-circuit 27 FB2 consists of Resistors 8419, 8418, 8414 and 8410, 28 zener diode D410, and NPN transistors Q414 and Q413.

Figure Table Element Value/part number 8414 22k ohms 8418 25.5K ohms 8410, 499k ohms 1 Node PF+ connects to series resistors 8410+8419+8418 2 then to common or ground forming voltage divider. The 3 junction of 8418 and 8419 connects to collector of Q414 4 and cathode of Zener diode D410. Diode D410 anode connects to base of transistor Q414. Emitter of Q414 6 connects to base of Q413 and through resistor 8414 to 7 ground. Emitter of Q413 is also connected to ground.

8 Collector of Q413 connects to node PF2 for connection to 9 regulator sub-circuit PFB pint. . Resistors 8410, 8419, 108418 and D410 are selected to forward bias transistors 11Q413 and Q414 when node PF+ exceeds 450VDC relative to 12common.
This regulates the boost activity until the fault 13condition subsides providing fast reliable alternative 14regulation thus meeting UL test requirements.

FIG. 42 is the schematic of the inventions over 16 voltage protection embodiment sub-circuit OVP1. Sub-17 circuit OVP1 consists of SCR (silicon controlled 18 rectifier) SCR1200, resistor 81200, capacitor C1200 and 19 zener diodes D1200, D1202 and D1203.
FIG. 42 Table Element Value/part number D1203 BZT03-C200 (200 V) D1202 BZT03-C200 (200 V) D1200 IN4753 (5.1v) C1200 220 pf 81200 lO,Ok ohms 1 Input pin PF+ is connected to cathode of zener diode 2 D1203, anode of D1203 is connected to series zener diodes 3 [D1202 + D1200] then to gate of SCR1200. Noise 4 attenuation network of [R1200~~C1200] is connected from SCR SCR1200 gate to the return node BR-. Diodes D1102 6 and D1103 are both 200-volt; D1101 is a 5.1-volt type the 7 sum of the zener voltages set the trip point of the OVP
8 at 405-volts. Other trip voltages may be implemented by 9 selecting other zener diode combinations. Capacitor C1200 and 81200 prevents leakage current and transients 11 from accidentally tripping the OVP. In the event of very 12 high AC line voltages or a component failure in a feed 13 back loop (FIG. 40A, 40B, 40C or 40) The boost voltage 14 may quickly rise increase to levels dangerous to the output switch or output storage capacitors. When the 16 output boost voltage of the at node PF+ rises above 405V, 17 zener diodes D1203, D1202 and D1200 conduct a small 18 current into the gate of SCR1200 turning SCR1200 on.
19 Turning SCR1200 on places a low impedance path across the AC line through the rectifier sub-circuit BR (FIG. 22).
21 SCR1200 and bridge rectifier diodes must be selected to 22 withstand the short circuit currents that may exceed 100 23 amperes until the input fuse opens. Thus quickly 24 limiting the boost output voltage to a safe level. This circuit should never operate under normal AC line 26 voltages. By changing zener voltages this sub-circuit 27 would also be suitable for use in the across the 28 rectifier output to protect the load from an over voltage 29 condition. Sub-circuits OVPl shuts down the converter with out opening the line fuse. Sub-circuit OVP may be 31 used in combination with OVPl (FIG. 42A) as a fail-safe 32 back up for critical loads.
33 FIG. 42A is the schematic of the inventions over 1 voltage protection embodiment sub-circuit OVP2. Sub-2 circuit OVP2 consists of SCRs (silicon controlled 3 rectifier) SCR1101 and SCR1100, resistors 81101 and 4 81102, capacitors C1100 and C1101 and zener diodes D1100, D1102 and D1103.
Figure 42A Table Element Value/part number SCR1101 S101E (Teccor) SCR1100 S601E (Teccor) D1103 BZT03-C200 (200 V) D1102 BZT03-C200 (200 V) D1100 IN4753 (5.1v) 81101 5.1 K ohms 81102 5.1 K ohms C1100 1200 pf C1101 1200 pf 6 Anode of SCR1101 is node/pin CP18V+ that is 7 connected to external control DC source. Return node BR-8 is connected to SCR1101 ca thode and capacitor C1100.

9 Input node PF+ is connected to cathode of zener diode D1103 and to series resistor 81100 then to anode of SCR

11 SCR1102. The anode of D1103 is connected to the cathode 12 of D1102. The anode of D1102 is connected to the cathode 13 of D1100. The cathode of SCR1 100 is connected to the gate 14 of SCR1101. The anode of D 1103 is connected to series zener diodes [D1102 + D1100] then to capacitor C1100 then 16 to the return node BR-. Capacitor [C1200 ~~R1200]

17 prevents leakage current and transients from accidentally 18 tripping OVPB. In the event f very high AC line voltages o 19 or a component failure in a feed back loop (IPFFB FIG.

40A, FBA 40B, IFB 40C or FBI FIG. 41) The boost voltage 1 may quickly rise increase to levels dangerous to the 2 output switch or output storage capacitors. When the 3 output boost voltage of the at node PF+ rises above 405V, 4 zener diodes D1103, D1102 and D1100 conduct a small current into the gate of SCR1101 latching SCR1101 on.
6 Resistor 81100 provides holding current for SCR1101.
7 Turning SCR1101 provides gate current to SCR1100, 8 resistors 81100 and 81101 limits the gate current and 9 provides the hold current to SCR1100. With gate current to SCR1100 the SCR is turned on providing a low impedance 11 path from nodes CP18V+ to BR-. This action removes the 12 regulated power to the main switch buffer and or PWM
13 controllers PFA (FIG. 23) or PWFM (FIG. 33) and or buffer 14 AMP (FIG. 29) thus turning off the main switch. The converter is held in an off state until boost voltage PF+
16 through 81100 can not maintain the holding current of 17 SCR1101. Typically power must be removed from the system 18 to reset SCR1101. The minimum holding current of SCR1101 19 is typically 5-lOma. The action of OVP1 quickly limits the boost output voltage to a safe level. This circuit 21 should never operate under normal AC line voltages. By 22 changing zener voltages this sub-circuit would also be 23 suitable for use across the output rectifier to protect 24 the load from an over voltage condition. Sub-circuit OVP1 gracefully shuts down the converter requiring manual 26 intervention to reset the fault.
27 FIG. 42B is the schematic of the isolated output 28 over voltage feed back network sub-circuit OVP2. Sub-29 circuit OVP2 consists of resistors of 8970, 8971, and 8972, capacitor C970, zener diode D970, SCR SCR970, 31 Darlington transistor Q970 and opto-isolator U970.

Figure 42B Table Element Value/part number 8970 160k ohms 8971 lOk ohms 8972 22k ohms C970 200pf 1 The output of the converter at pin OUT+ is connected 2 to 8972 and to the cathode of zener diode D970. The anode 3 of D970 is connected to series resistor 8970 then to base 4 of Q970. Resistor 8970 sets the maximum base current to Q970. Resistor 8971 is connected between the anode of 6 D970 and return node OUT-. Anode of light emitting diode 7 U970 is connected to resistor 8972 then to OUT+. The 8 cathode of U970 LED is connected to Q980 collector.
9 Emitter of Q980 is connected to return node OUT-. Zener diode D960 sets the maximum or trip voltage before 11 transistor Q970 is biased on providing current to U970 12 LED. Application of voltage greater than the zener 13 voltage of D970 injects a small base current into Q970.
14 Transistor Q970 turns on the internal LED of U970 placing phototransistor in a conducting state and low impedance 16 to pins OVC and OVC. External push-pull driver sub-17 circuit PPG (FIG. 43) is shut down immediately by 18 bringing pin PPEN high stopping the output stage. Sub-19 circuit OVP2 senses. the output voltage and quickly feeds back to the push-pull PFC. Where excessive boost voltage 21 forces the PFC to automatically reduce the boost voltage.

1 FIG. 42C is the schematic of the isolated output 2 over voltage crowbar network sub-circuit OVP3. Sub-3 circuit OVP3 consists of resistors of 8980, 8981, 8982, 4 8983, 8984 and 8985, capacitors C980, C981 and C982 zener diode D980, SCRs SCR980 and SCR981, Darlington transistor 6 Q980 and opto-isolator U980.
Figure 42C Table Element Value/part number SR980 S601E (Teccor) 8980 160k ohms 8981 lOk ohms 8982 22k ohms 8983 51k ohms 8984 1200 ohms 8985 510 ohms C980 200 pf C981 1200 pf C982 1200 pf 7 The converter output is sensed at pin OUT+ reference 8 to pin OUT-. Pin OUT+ is connected to resistor 8982 and 9 to the cathode of zener diode D980. The anode of D980 is connected to series resistor 8980 then to base of Q980.
11 Resistor 8980 limits the base current to Q980. Resistor 12 8981 is connected between the anode of D980 and return 13 node OUT- to provide a diode leakage current path. Anode 14 of light emitting diode U980 is connected through resistor 8982 then to OUT+. The cathode of U980 LED is 16 connected to Q980 collector. Emitter of Q980 is connected 1 to return node OUT-. Zener diode D960 sets the maximum 2 or trip voltage before transistor Q980 is biased on 3 providing current to U980 LED. Application of voltage 4 greater than the zener voltage of D980 injects a small base current into Q980.Emitter of opto-isolator U980 is 6 connected to the gate of SCR981 and through [R984 ~ ~ C982]
7 to return node BR-. Transistor Q980 turns on the internal 8 LED of U980 placing phototransistor in a conducting state 9 and supplying gate current to SRC SCR981 from the external 18-volt source connected to pin CP18V+. Network 11 [R984~IC982] prevents false triggering of SCR SCR981. The 12 cathode of SCR SCR981 is connected to the gate of SCR
13 SCR980 and through [R985~~C981] to return BR-. With SCR
14 SCR981 turned on gate current is provided to low voltage SCR SCR980. High voltage boost output is connected to pin 16 PF+ resistor 8983 supplies hold current to SCR SCR981 17 holding SCR SCR980 on. SCR SCR980 is selected for low 18 hold current and ability to block the maximum boost 19 voltage on PF+. SCR SRC980 anode is connected to pin CP18V+. SCR SRC980 cathode is connected to return pin BR-21 . SCR980 clamps the low voltage supply CP (FIG. 26) or 22 CPA (FIG. 27). With the low supply held down the gate 23 drive to the main switch is disabled turning off the 24 converter. With the main switch Q1 (FIG. 1,3,4) turned off holdup capacitor C17 charges to applied AC line peak.
26 With pin PF+ held near line peak SCRs SCR981 will hold 27 SCR SCR981 on until AC line power is removed to the 28 converter. Sub-circuit OVP3 senses the out of 29 specification output voltage and quickly stop the converter thereby protecting the load and converter with 31 out generating destructive currents like OVP (FIG. 42).
32 FIG. 43 Push-pull oscillator sub-circuit PPG FIG.

1 43 is the push-pull oscillator sub-circuit of the 2 invention. The current implementation uses a Motorola 3 MC33025 pulse width modulator IC to generate the clock 4 signals to drive the push-pull output stage. Sub-s circuit PPG consists of U14 a two-phase oscillator, 6 resistors 8126, 8130, 8131, 8132, 8133, 8134, 8135, 7 8136 and 8137, capacitors C143, C136, C139, 0140, C141 8 and C142.
Figure 43 Table Element Value/part number 8126 12k ohms 8130 10 ohms 8131 10 ohms 8132 47k ohms 8133 lOk ohms 8134 100k ohms 8135 15k ohms 8136 1.5 MEG ohms 8137 15k ohms C136 0.22uf C139 0.22uf C140 0.22uf C141 O.Oluf C142 O.OOluf C143 .33 of 9 The current implementation uses a Motorola MC33025 pulse width modulator IC to generate the clock signals 11 to drive the push-pull stage. But, any non-overlapping 12 two phase fixed frequency generator could be used. Pin 1 1 of U14 is connected to [capacitor C143~~Resistor 2 8132] then to pin 3. Resistor 8134 connects the 3 internal 5.1-volt reference output of U14 pin 16 to pin 4 1. Resistors 8135 in series with 8137 from 5.1-volt reference to return node PPGO form a voltage divider;
6 the center is connected to U14 pin 2 placing pin 2 at 7 2.55-volts. Resistor 8126 is connected from U14 pin 5 8 to return node PPGO. Resistor 8133 is connected from 9 U14 pin 1 to return node PPGO. Timing capacitor C142 is connected from U14 pins 6 and 7 to return node PPGO.
11 Resistor 8126 and capacitor C142 set the operating 12 frequency of the internal oscillator. Timing resistor 13 could be replaced) with a JFET, MOSFET, transistor, or 14 similar switching device to provide variable frequency operation. The drain of the transistor would be 16 connected to pin 5. The source would be connected to 17 return node PPGO. The variable frequency command 18 voltage/current is applied between gate and source.
19 Capacitor C141 is connected from U14 pin 8 to return node PPGO. Capacitor C136 is connected from U14 pin 16 21 to return node PPGO. Capacitor C140 is connected from 22 U14 pin 15 to return node PPGO. Capacitor C139 is 23 connected from U14 pin 13 to return node PPGO. Resistor 24 8136 is connected from U14 pin 9 to return node PPGO.
U14 pins 10 and 12 is connected to return node PPGO.
26 External power is connected to node/pin PPG+ to PWM
27 (pulse width modulator) IC U14 on pin 15 through 28 resistor 8130 connected to the 18-volt control supply.
29 Resistor 8131 connected to pin 13 of U14 and PPG+
provides power to the totem-poll output stage. The 31 power return line is connected to node PPGO. IC U14 is 32 designed to operate at a constant frequency of 1 approximately 20-600Khz with a fixed duty cycle of 35-2 49.9%. Resistors 8135, 8137, 8133 configure U14 to 3 operate at maximum pulse width. A two-phase non-over 4 lapping square wave is generated on pins 11 node PH2 and pin 14 node PHl and delivered to speed-up buffers 6 AMP described in FIG. 29. The two-phase generator is 7 configured to prevent the issue of overlapping drive 8 signals that would null the core bias and present 9 excessive current to the switches. Sub-circuit PPG
provides the drive to the push-pull switches making 11 efficient use of the NSME.
12 FIG. 44 inrush limiter sub-circuit SS1. Sub-circuit 13 SS1 consists of diodes D447, resistors 8441, 8442, 8443, 14 8444, 8445 and 8446, transistor Q446 and capacitors C449, C442, and C448.
Figure 44 Table Element Value/part number R441,R442 300K Ohm 8443-445 100 Ohm C448 0.33uF

C442 330 uF 450V

C449 0.1 uF

8446 4.7 MEG Ohm 16 Node PF+ connects to the positive input of storage 17 capacitor C442 and to series resistors 8441+R442. Series 18 resistors 8441 and 8442 may be replaced with a single 19 element. Series resistors 8441 and 8442 in parallel with provide a safety discharge path for C442. Drain of 21 transistor Q446 is connected to the negative terminal of 22 C442 and 8442. Source of Q446 is connected to return 1 node BR-. Resistors [R443~~R445] are connected in 2 parallel with Q446 source and drain terminals. Resistors 3 8443, 8444 and 8445 may be replaced with a single 4 element. Resistor 8446 connects to the rectified line voltage node BR+ and to gate of Q446. Cathode of Zener 6 diode D447 is connected the gate of Q446. Anode of Zener 7 diode D447 is connected to source of Q446. Diode D447 8 limits the maximum gate voltage to approx. 16 volts.
9 Parallel capacitors C448 and C449 are connected in parallel to D447. Resistor 8446 and capacitors 11 [C448~IC449] provide a time delay of (0.05 to 0.2 sec) at 12 power up. This delay range is offered by way of example 13 and not limitation. At power up transistor Q446 is in a 14 high impedance state. Thus capacitor C442 charging current is limited by [R443~~R444~~R445]. Referring to 16 Interval 441 oscillograph G44 (Fig 44A) is the period 17 when transistor is not conducting thus [R443~~R444~~R445]
18 provides the charging path thus limiting inrush current.
19 Greatly reducing stress on the line filter and rectifier components during power up. The exponential decrease in 21 inrush current is observed during interval 441. Soft 22 start-interval 444 (Fig 44A) of oscillograph GPF+ is also 23 marked with greater AC ripple voltage due to the series 24 resistance. As capacitors [C448~~C449] charges through 8446 the gate voltage of Q446 increases turning "ON"
26 Q446. Transistor Q446 turns on during interval 442 (FIG.
27 44A). This action is marked by an increase in charging 28 current 446 and a reduction in AC ripple during interval 29 445. Similarly an exponential decrease in charging current is observed during 442 as C442 charges.
31 Transistor Q446 is held in the conducting state until 32 power is removed from the converter. During interval 447 1 the boost converter begins operation. Additional inrush 2 limiting is provided by sub-circuit SST (FIG. 33B) 3 smoothly bringing up the output voltage during interval 4 448. Shown by the increase in line current to full load during 443. The instant invention provides settable 6 inrush limiting intervals with simple resistor/capacitor 7 value selection. Thus complementing the additional novel 8 soft start boost circuit SST. While maintaining high 9 power factor during the start up interval. The graceful start up greatly reduces stress in the external fusing 11 and components in the high current path. Enhancing MBTF
12 with a minimal addition of components. This instant 13 invention also permits "HOT" plugging multiple units in 14 parallel for higher power and or redundancy. The inrush limiter SS1 briefly isolates the storage capacitor from 16 the main DC bus. In this way "hot swapping" does no 17 create a large disturbance on the AC or main external DC
18 BUS. The unique master less load sharing method taught 19 in FIG. 4A allows any number of units to be connected in parallel for high power and reliability.
21 FIG. 44A is an oscillograph of line current and 22 output voltage during operation of sub-circuit SS1 (FIG.
23 44 ) .
24 FIG. 45 is a schematic diagram of the fast start sub-circuit FSl. Fast-start Sub-circuit FS1 consists of 26 diodes D452 and D451, resistors 8451, 8452, 8453, 8454, 27 8455 and 8456, transistors Q450 and Q451, and capacitors 28 C452, C453, and C451.
Figure 45 Table Element Value/part number D451 R1z5.1 ZENER 5.1v D452 R1z24 ZENER 24v 8451 1 MEG Ohm 8452- 2.2 MEG Ohm 453,8454 8455 4.3K Ohm 8456 499K Ohm C453 0.01 uF

C451 4.7 uF

C452 1.0 uF

2 Resistor 8451 connects node VCC to the base of 3 transistor Q450, then to resistor 8454 in parallel with 4 capacitor C451 to ground or BR-. Anodes of zener diodes D451 and D452 are connected to ground. Cathode of zener 6 diode D451 is connected to emitter of Q450. Cathode of 7 zener diode D452 is connected to collector of Q450, gate 8 of Q451 and through resistors 8452+8453 to node PF+.
9 Resistor 8455 connects from PF+ to drain of Q451.
Resistor 8456 connects from BR-(ground) to source of Q451 11 forming node TP15 and through capacitor C452 to the gate 12 of Q451. Capacitor C453 is connected between nodes TP17 13 and TP45. With application of AC power node PF+ voltage 14 increases rapidly. Transistor Q450 is not in a conducting state as VCC is zero (no boost). Resistors 8452+8453 16 charge C452 forward biasing Q451. Oscillograph G45 (FIG.
17 45A) is plot of the source gate voltage of Q451. During 18 interval 6451, transistor Q451 conducts providing power 19 to VCC though 8455 from PF+. Interval 6452 of osci.llograph GVCC shows the rapid rise of vCC. Thus full 21 power- is immediately available to the main switch Ql 1 switch buffer AMP (FIG. 29) and to the power factor 2 controller PFA, PFB or PFB1. With VCC at or above 12.6V
3 the boost converter gradually starts operation. This is 4 seen by the small AC voltage present on TP45 during interval 6454 (FIG. 45A). Transistor Q451 continues to 6 provide power to VCC while the boost operation ramps up 7 during the soft-start interval 6455. Once the soft-start 8 phase is completed, rectified AC via D261 and D260 9 provides power to VCC. Capacitor C453 couples HF boost energy to quickly charge C451. 8451 provides continuous 11 bias current to C451 to prevent the activation of Q451 12 when VCC is above 5 volts . Forward biasing Q450 reduces 13 the gate voltage on Q451. Past 6456 transistor Q451 gate 14 to source is reverse biased turning off the fast-start.
In the event of an over voltage condition from a high 16 line condition or sudden load removal, boost activity 17 will stop removing the AC voltage on TP45. Removal of 18 this base drive reduces current in the collector circuit 19 of 6450, thus allowing Q451 to become forward biased if VCC falls below 5 volts. Power will be provided to VCC
21 any time C451 falls below 5 volts. This novel circuit 22 provides a unique method to quickly provide control power 23 before boost operation begins and maintain control power 24 during extended over voltage or no load periods. Thus insuring rapid reliable start up and recovery under a 26 full range of load and fault conditions.
27 FIG. 45A is an oscillograph of sub-circuit Fsi during 28 operation of sub-circuit SS1 (FIG. 45).
29 FIG. 46. Transient protection ,Sub-circuit TRN
consists of diodes D460-D462, Bridge rectifier 461 and 31 capacitors C260, C260~.

Figure 46 Table Element Value/part number D460-D462 S3M 3amp/1000v C260 330 ufd 450V

461 Bridge l5Amp/800V

C2 1.5 ufd 630v 1 Line voltage AC plus a high voltage source HV1 are 2 connected to the AC-voltage terminals of bridge rectifier 3 461. Bridge DC+ terminal connects to node BR+ and to 4 Anodes of transient protection diodes D460-D462 and inductor L63 in parallel with capacitor C20. Inductor L63 6 and capacitor C20 do not substantially contribute to the 7 action of the transient protection circuit and are only 8 shown for completeness. Cathodes of D460-D462 are 9 connected to Boost output and storage capacitors C2 and C260. Boost circuit operation is taught in FIG., 18A, 30, 11 29, and 24. Three transient protection diodes are 12 offered by way of example and not limitation. The number 13 of devices is a function of the selected device forward 14 current capacity and the expected peak currents.
Capacitor C260 is a polarized electrolytic device and is 16 offered by way of example and not limitation. A solid 17 dielectric capacitor may be added in parallel to C260 18 lower the impedance and improve the high frequency 19 performance. During normal operation transient protection diodes D460-D462 are reverse biased due to the 21 action of the boost. With of a high the application 22 voltage event HV1 of any polarity to the AC line, the 23 rectified event appears on shown in node BR+, also 24 oscillograph 6463 (FIG. 46B).
If the transient voltage exceeds the voltage at C2, D460-D462 are forward biased 1 transferring the energy to storagQ capacitor C260.
2 Common art transient methods shunt the energy into spark 3 gaps or MOV type devices. These devices suffer from 4 limited life cycle's, excessive leakage currents or a catastrophic failure. With proper component selection 6 very large transients may be absorbed with out exceeding 7 device ratings. Thus insuring high reliability with 8 minimal parts counts and cost. The instant invention is 9 adaptable to other offline converters having a storage capacitor maintained (boosted) above the rectified peak 11 line voltage. This topology will work with positive or 12 negative reference converters.
13 FIG. 46A. Transient protection Sub-circuit TRNX
14 consists of resistor 8468, Bridge rectifier BR468 and capacitor C468.
Figure 46A Table Element Value/part number 8458 1 MEG ohm 8468 220 ufd 450V

BR468 35Amp/600V

16 Line voltage AC plus a high voltage source HV1 are 17 connected to the AC-voltage terminals of bridge rectifier 18 BR468. Bridge output positive terminal connects to node 19 BR+ and to resistor 8486 in parallel with C468. Bridge output negative terminal connects to node BR- and to 21 resistor 8486 in parallel with C468. Sub-circuit TRNX
22 may be connected in parallel with any AC or DC load 23 requiring transient protection. With application of 24 power to the bridge capacitor C468 charges to peak voltage. Resistor 8468 bleeds off a small charge from 26 C468. Once charging is complete only a small amount of 1 power is dissipated by 8468. During a transient event of 2 the type depicted in graph 6462 (FIG. 46b). The high 3 voltage transient will be directed into capacitor C468 4 the low internal impedance of C468 with the high forward current capability of BR468. Limits the magnitude of the 6 transient, by directing the transient energy into C468.
7 Generating a voltage oscillograph response 6461.
8 Additional capacitors may be added for higher voltages, 9 currents and or lower impedance.
FIG. 46B is an oscillograph of the converter 11 operation during a high voltage transient event.
12 Oscillograph 6461 is the output voltage PF+. Oscillograph 13 6462 is the rectified AC line voltage BR+. Oscillograph 14 6463 is the gate voltage to the main boost switch Q1.
FIG. 47 is a signal diagram of supply auto load 16 leveling. To teach the invention FIG. 47 only shows the 17 essential elements for clarity. Power supplied to 473 18 enters regulator stage 470. Regulator stage 470 may be 19 any type such .as series pass, variable reactance (AC), boost, buck and shunt. These are offered by way of 21 example and not limitation. The regulator 470 only 22 requires a control pin 479 that modulates the output N470 23 in proportion to the control signal. Power or load 24 sensing element 471 provides an output signal 472 that is proportional to the power delivered by 470 to load 476.
26 Load sensing element may be a hall effect sensor 27 (Current), resistor with differential amplifier, watt 28 sensor or current transformer. These are offered by way 29 of example and not limitation. The requirement being that signal 472 is proportional to the power delivered.
31 A simple inverting amplifier (not shown) may be required 32 to level shift, buffer or invert signal 472 polarity for 1 a specific sensor. By way of example VCC derived from 2 the sampling the boost magnetic element PFT1A (FIG. 4A) 3 via CP1 (FIG. 26A) provides such a signal. Signal 472 4 (VCC) varies as a . function of load as shown in FIG. 26B.
Load leveling is achieved with the addition of resistor 6 8476 connected between nodes 472 and 477. Resistor 8345 7 in FIG. 4A is the corresponding component in the 8 converter ACDCPF1. Power signal 472 is converted into a 9 current through 8476 and injected into summing junction 477. Summing junction 477 accepts current from 8473 11 proportional to the converter temperature from sensor 12 T473. In this way converter load sharing is based on 13 power and or temperature. Simple resistor ratios program 14 load-sharing rates while maintaining converter regulation. Resistor 8479 develops a voltage proportional 16 to the summing currents and applies it to the inverting 17 terminal of comparator 478. Reference voltage V470 is 18 applied to non-inverting input of comparator 478. The 19 comparator generates command signal 479 to modulate the regulator 470. The action of the comparator is to 21 maintain a minimal voltage difference between comparator 22 input terminals. External power sources) 475 and 475N
23 connect to output node N474 and to common load 476. This 24 configuration allows many converters to be connected in parallel. Signal 472 (VCC) varies as a function of load 26 as shown in FIG. 26B. Load leveling is achieved with the 27 addition of resistor 8476 connected between nodes 472 and 28 477. Thus regulating the output voltage lower as the 29 load increases. This unique action allows N units to be operated in parallel with out the typical master slave 31 connections and circuitry. In this way the lightly 32 loaded converters increase output voltage thus accepting 1 more load. Like wise the heavy loaded converters will 2 reduce voltage, automatically shedding load to other 3 converters or sources. In this way any number of 4 converters may be connected in parallel for high power or redundant applications. In common art master/slave 6 configurations, loss of the master unit is catastrophic.
7 In the instant invention failure or removal of a units) 8 causes the remaining units to increase output to absorb 9 the additional load. Optional temperature sensor T473 allows load sharing as a function of supply temperature 11 in addition to load. Thus minimizing thermal gradients 12 among multiple units. This auto load leveling method is 13 adaptable to AC or DC sources. Component selection sets 14 nominal operating voltages, and rates of load sharing.
This method allows dynamic load sharing .with out the 16 typical master slave connections, costs, and reduced 17 reliability. This method permits mixing of power supply 18 types i.e. auto load sharing and only requiring their 19 output voltages to be substantially equal. Thus providing excellent regulation, simple setup and configuration, 21 "hot swap" capability automatic recovery from fault 22 conditions.
23 FIG. 47A is an alternate signal diagram of supply 24 auto load leveling. To teach the invention FIG. 47A only shows the essential elements for clarity. Power supplied 26 to 473 enters the regulator stage 470. Regulator stage 27 471 may be any type such as series pass, variable 28 reactance (AC), boost, buck and shunt. These are offered 29 by way of example and not limitation. The regulator 470 only requires a control pin 479 that modulates the output 31 N470 in proportion to the control signal. Power or load 32 sensing element 471 provides an output signal 472 that is 1 proportional to the power delivered by 470 to load 476.
2 Load sensing element may be a hall effect sensor 3 (Current), resistor with differential amplifier, watt 4 sensor or current transformer and are offered by way offered example and not limitation. The requirement 6 being that signal 472 is proportional to the power 7 delivered. A simple inverting A470 amplifier may be 8 required to level shift, buffer or invert signal 472 9 polarity for a specific sensor. By way of example VCC
derived from the sampling the boost magnetic element 11 PFT1A (FIG. 4A) via CP1 (FIG. 26A) provides such a 12 signal. Signal 472 (VCC) varies as a function of load as 13 shown in FIG. 26B. Amplifier A470, resistor 8478 and 8475 14 provides signal inversion to correct the signal polarity.
Automatic load leveling is achieved with the addition of 16 resistor 8476 connected between nodes output of A470 and 17 477. Resistor 8345 in FIG. 4A is the corresponding 18 component in the converter ACDCPF1. Power signal 472 is 19 converted into a current through 8476 and injected into reference junction N476. Reference voltage V470 through 21 8470 to non-inverting input of comparator 478. Thus 22 effectively modulating the reference voltage to reduce 23 the converter output voltage with higher powers. Summing 24 junction 477 accepts current from 8475 proportional to the converter output N474. Thus enabling converter load 26 sharing based on power. Simple resistor ratios program 27 load-sharing rates and output voltages while maintaining 28 converter regulation. Resistor 8479 develops a voltage 29 proportional to the summing currents and is applied to the inverting terminal of comparator 478. The comparator 31 generates command signal 479 to modulate the regulator 32 470. The action of the comparator is to maintain a 1 minimal voltage difference between comparator input 2 terminals. Additional external power sources) 475 and 3 475N connect to output node N474 and turn to common load 4 476. This configuration allows many converters to be connected in parallel. Thus regulating the output voltage 6 lower as the load increases. This unique action allows N
7 units to be operated in parallel with out the typical 8 master slave connections and circuits. In this way the 9 lightly loaded converters increase output voltage thus accepting more load. Like wise the heavy loaded 11 converters will reduce voltage, automatically shedding 12 load to other converters or sources. In this way any 13 number of converters may be connected in parallel for 14 high power or redundant applications. In common art master/slave configurations, loss of the master unit is 16 catastrophic. In the instant invention failure or 17 removal of a units) causes the remaining units to 18 increase output to absorb the additional load. This auto 19 load leveling method is adaptable to AC or DC sources.
Component selection sets nominal operating voltages, and 21 rates of load sharing. This method allows dynamic load 22 sharing with out the typical master slave connections, 23 costs, and the reduced reliability. This method also 24 permits mixing of power supply types i.e. auto load sharing and constant voltage types. Only requiring their 26 stand alone output voltages to be substantially equal for 27 a given load. This provides excellent regulation, simple 28 setup and configuration, "hot swap" capability automatic 29 recovery from fault Conditions.
Although the present invention has been described 31 with reference to a preferred embodiment, numerous 32 modifications and variations can be made and still the 1 result will come within the scope of the invention. No 2 limitation with respect to the specific embodiments 3 disclosed herein is intended or should be inferred.

Claims

I CLAIM:

1. A converter comprising:
a power factor corrected flyback converter having a feedback circuit;
a push pull converter having a duty cycle;
said power factor corrected flyback converter providing a variable signal to said push pull converter;
a full wave rectified output circuit;
said push pull converter providing a signal having an operating frequency to said full wave rectified output circuit; and said push pull converter further comprising a magnetic element operating in a non-saturated region (NSME).

2. The converter of claim 1, wherein said NSME further comprises a low permeability.

3. The converter of claim 2, wherein the NSME further comprises a mixture of 85% by weight of iron, 6% by weight of aluminum, and 9% by weight of silicon, thereby providing a wide thermal operating range for the magnetic element.

4. The converter of claim 1, wherein the low permeability has a range of one to 500.

5. The converter of claim 4, wherein the NSME is an air magnetic element.

6. The converter of claim 1, wherein the NSME further comprises a B-H curve characteristic ranging from B=1 to 10,000 gauss and H=1 to 100 oersteds.

7. The converter of claim 1 further comprising a frequency modulating circuit to optimize an output signal from the NSME.

8. The converter of claim 7, wherein said push pull converter further comprises a double ended controller having a fixed pulse width.

9. The converter of claim 7, wherein said push pull converter further comprises a double ended controller having a variable frequency.

10. The converter of claim 7, wherein said push pull converter further comprises a double ended controller having a duty cycle ranging from 40% to 60% of a fixed pulse width.

11. The converter of claim 7, wherein said push pull converter further comprises a double ended controller having an optimizing circuit varying a relationship between pulse width and frequency.

12. The converter to claim 1, wherein said duty cycle is a constant.

13. The converter of claim 1, wherein said duty cycle is a variable.

14. The converter of claim 10, wherein the duty cycle is 50.

15. The converter of claim 1 further comprising a control circuit to monitor a bias of the NSME and controls a frequency and a pulse width for optimizing a NSME
efficiency.

16. The converter of claim 1, wherein the NSME is selected from the group consisting of:
an air magnetic element;
a molypermalloy powder(MPP) magnetic element;
a high flux MPP magnetic element;
a powder magnetic element;
a gapped ferrite magnetic element;
a tape wound magnetic element;
a cut magnetic element;
a laminated magnetic element; and an amorphous magnetic element.

17. A converter comprising:
a power factor corrected flyback converter having a feedback circuit;
a push pull converter having a duty cycle;
said power factor corrected flyback converter providing a variable signal to said push pull converter;
a full wave rectified output circuit;
said push pull converter providing a signal having an operating frequency to said full wave rectified output circuit; and said flyback converter further comprising a magnetic element operating in a non-saturated region (NSME).

18. The converter of claim 17, wherein said NSME further comprises a low permeability.

19. The converter of claim 18, wherein the NSME further comprises a mixture of 85% by weight of iron, 6% by weight of aluminum, and 9% by weight of silicon, thereby providing a wide thermal operating range for the magnetic element.

20. The converter of claim 17, wherein the low permeability has a range of one to 500.

21. The converter of claim 20, wherein the NSME is an air magnetic element.

22. The converter of claim 17, wherein the NSME further comprises a B-H curve characteristic ranging from B=1 to 10,000 gauss and H=1 to 100 oersteds.

23. The converter of claim 17 further comprising a frequency modulating circuit to optimize an output signal from the NSME.

24. The converter of claim 17, wherein said push pull converter further comprises a double ended controller having a fixed pulse width.

25. The converter of claim 17, wherein said push pull converter further comprises a double ended controller having a variable frequency.

26. The converter of claim 17, wherein said push pull converter further comprises a double ended controller having a duty cycle ranging from 40% to 60% of a fixed pulse width.

27. The converter of claim 17, wherein said push pull converter further comprises a double ended controller having an optimizing circuit varying a relationship between pulse width and frequency.

28. The converter to claim 17, wherein said duty cycle is a constant.

29. The converter of claim 17, wherein said duty cycle is a variable.

30. The converter of claim 17, wherein the duty cycle is 50.

31. The converter of claim 17 further comprising a control circuit to monitor a bias of the NSME and controls a frequency and a pulse width for optimizing a NSME efficiency.

32. The converter of claim 17, wherein the NSME is selected from the group consisting of:
an air magnetic element;
a molypermalloy powder(MPP) magnetic element;
a high flux MPP magnetic element;
a powder magnetic element;
a gapped ferrite magnetic element;
a tape wound magnetic element;

a cut magnetic element;
a laminated magnetic element; and an amorphous magnetic element.

33. A converter comprising:
a power factor corrected flyback converter having a feedback circuit;
a push pull converter having a duty cycle;
said power factor corrected flyback converter providing a variable signal to said push pull converter;
a full wave rectified output circuit;
said push pull converter providing a signal having an operating frequency to said full wave rectified output circuit;
said push pull converter further comprising a magnetic element operating in a non-saturated region (NSME); and said flyback converter further comprising a second magnetic element operating in a non-saturated region (NSME)

34. The converter of claim 33, wherein said NSME
further comprises a low permeability.

35. The converter of claim 34, wherein the NSME further comprises a mixture of 85% by weight of iron, 6% by weight of aluminum, and 9% by weight of silicon, thereby providing a wide thermal operating range for the magnetic element.

36. The converter of claim 33, wherein the low permeability has a range of one to 500.

37. The converter of claim 34, wherein the NSME is an air magnetic element.

38. The converter of claim 33, wherein the NSME further comprises a B-H curve characteristic ranging from B=1 to 10,000 gauss and H=1 to 100 oersteds.

39. The converter of claim 33 further comprising a frequency modulating circuit to optimize an output signal from the NSME.

40. The converter of claim 33, wherein said push pull converter further comprises a double ended controller having a fixed pulse width.

41. The converter of claim 33, wherein said push pull converter further comprises a double ended controller having a variable frequency.

42. The converter of claim 33, wherein said push pull converter further comprises a double ended controller having a duty cycle ranging from 40% to 60% of a fixed pulse width.

43. The converter of claim 33, wherein said push pull converter further comprises a double ended controller having an optimizing circuit varying a relationship between pulse width and frequency.

44. The converter to claim 33, wherein said duty cycle is a constant.

45. The converter of claim 33, wherein said duty cycle is a variable.

46. The converter of claim 33, wherein the duty cycle is 50.

47. The converter of claim 33 further comprising a control circuit to monitor a bias of the NSME and controls a frequency and a pulse width for optimizing a NSME efficiency.

48. The converter of claim 33, wherein the NSME is selected from the group consisting of:
an air magnetic element;

a molypermalloy powder(MPP) magnetic element;
a high flux MPP magnetic element;
a powder magnetic element;
a gapped ferrite magnetic element;
a tape wound magnetic element;
a cut magnetic element;
a laminated magnetic element; and an amorphous magnetic element.

49. The converter of claim 1 further comprising:
a voltage regulator having a capacitor, said capacitor having a voltage derived from a pulse width from said flyback converter;
said capacitor referenced to a boost voltage across said magnetic element;
said capacitor having a reference voltage for a primary of said push pull converter; and said voltage following a load.

50. The converter of claim 1 further comprising a power factor control (PFC) circuit, wherein said PFC circuit further comprises:
a first FET having a switching mode and a buffer;
said buffer comprising a second FET and Darlington transistor pair whereby a voltage is slewed to a gate of said first FET on a first cycle and a voltage is removed from said first FET gate on a second cycle.

51. A transformer for use in a converter of a power supply comprising:
a core;
a primary winding wrapped around the core;
at least one secondary winding wrapping around the core; and wherein the core comprises at least one magnetic element operating in a non-saturated region (NSME).

52. An AC-DC converter comprising:
an input for receiving a variable DC voltage;
a magnetic element sub-circuit electrically connected to said input;
at least one push-pull output switch electrically connected to said magnetic element sub-circuit; and wherein said magnetic element sub-circuit includes at least one magnetic element operating in a non-saturated region (NSME).

53. A converter comprising:
a power factor corrected flyback converter having a feedback circuit;

a forward buck converter;
said power factor corrected flyback converter providing an output signal to said forward buck converter;
a push pull converter having a duty cycle;
said forward buck converter providing a regulated voltage to said push pull convertera full wave rectified output circuit;
said push pull converter providing a signal having an operating frequency to said full wave rectified output circuit; and wherein each of said flyback converter, said forward buck converter, and said push pull converter include at least one magnetic element operating in a non-saturated region (NSME) .

54. In combination with a switch which generates a high voltage transient (flyback),a flyback management circuit comprising:
a power source mode;
a rectifier connected to the switch;
a first resistor/capacitor network having a resistor connected in parallel with said rectifier and a capacitor connected in series with both said rectifier and said switch;

a second resistor/capacitor network connected between the switch and an output mode; and wherein said flyback management circuit returns said high voltage transient to both the output and source modes.

55. In combination with a switch, a power source, an output mode, and an inductive energy storage element, a high voltage protection circuit for the switch, said high voltage protection circuit comprising:
a flyback rectifier diode;
a high speed rectifier in parallel with a capacitor sub-circuit;
said sub-circuit connected in parallel with said flyback rectifier diode; and wherein a closed switch high voltage spike is diverted first through the sub-circuit, and then through the flyback rectifier diode.

56. A transient protection network comprising:
a power input;
an output;
a first and a second input node, at least one of which having a series magnetic element operating in a non-saturated region (NSME);
a shunt capacitor(s) connected in parallel to a ground;

a shunt spark gap connected in parallel with said shunt capacitor(s);
a rectifier(s) connected in a bridge topology in parallel with said shunt spark gap;
a capacitor connected in parallel with said output; and a capacitor connected between an output negative and the ground.

57. The network of claim 56, wherein the NSME further comprises a low permeability having a range of 1 to 550 u.

58. The network of claim 57, wherein the NSME further comprises a substantially vertical B-H curve characteristics.

59. An improvement to a switch drive gate buffer having an amplifier function, said buffer comprising a high speed N-channel FET, a DC power source to a drain terminal of said FET, an input signal to a gate of the FET, the improvement comprising:
said input signal connected to a base of a high speed PNP transistor which in turn is connected between a FET source and the ground;
said PNP transistor having a base connected to a gate of the FET;

a capacitor connected between a base of the PNP
transistor and a collector of said PNP
transistor; and wherein an emitter of the PNP transistor is connected to the source of the FET.

60. The improvement of claim 59 further comprising a resistor connected between the source of the FET and the switch gate.

61. The improvement of claim 59 further comprising a shunt resistor connecting the source of the FET to the ground.

62. The improvement of claim 59 further comprising a temperature activated switch connected in series with the DC power source.

63. A distributed magnetic circuit comprising:
at least two magnetic elements operating in a non-saturated region (NSME); and wherein said elements are connected in series.

64. A distributed magnetic circuit comprising:
at least two magnetic elements operating in a non-saturated region (NSME); and wherein said elements are connected in parallel.

65. A converter feedback circuit comprising:
a positive and a negative input terminal each connected to an output of the converter;
circuit output terminals connected to a converter control circuit;
said positive input terminal connected in series to a regulating diode and in series to a resistor and further connected to a base of a transistor;
said negative input terminal connected to an emitter of the transistor and connected to a parallel resistor/capacitor sub-circuit which in turn is connected to the base of the transistor;
said transistor having a collector connected to a cathode of an optical isolator;
said optical isolator having an anode connected to a series resistor to said positive input terminal and having an output connected to the circuit output terminals.

66. An over voltage protection sub-circuit comprising:
a positive and a negative input terminal each connected to an output of a converter;
at least one zener diode connected to the positive input terminal;

said zener diode having an anode connected to a gate of a first silicon controlled rectifier (SCR) and further connector to a parallel resistor/capacitor sub-circuit connected to the negative input terminal;
said first SCR having an anode connected in series with a resistor to the positive input;
said negative input terminal having a connection to a second resistor/capacitor sub-circuit;
said second resistor/capacitor sub-circuit having a parallel connection to a gate of a second SCR and a cathode of the second SCR;
wherein said gate of the second SCR is connected to a cathode of the first SCR;
the cathode of the second SCR has a connection to a negative output terminal; and the anode of the second SCR has a connection to a positive output terminal.

67. A converter comprising:
a power factor corrected resonant mode controller;
a resonant mode converter having a feedback circuit;
a switch drive gate buffer;
a full wave rectified output circuit;

said power factor controller providing a variable frequency signal to the resonant mode converter; and said resonant mode converter further comprising:
a magnetic element operating in a non-saturated region (NSME) ;
a positive and a negative input terminal each connected to a power source;
said positive input terminal connected to a collector of a NPN transistor;
said positive input terminal further connected to a resonant capacitor and to a resistor and further connected to a collector of an optical isolator;
emitter of said optical isolator connected to a base of the NPN transistor;
a resonant capacitor connected to a first terminal of said NSME;
an emitter of the NPN transistor connected to a drain of a N-channel FET and second terminal of said NSME; and said negative input terminal connected to a source of the N-channel FET and to a return node of a switch buffer.

68. The converter of claim 67, wherein said NSME further comprises a low permeability.

69. The converter of claim 67, wherein the NSME further comprises a mixture of 85% by weight of iron, 6% by weight of aluminum, and 9% by weight of silicon, thereby providing a wide thermal operating range for the NSME.

70. The converter of claim 68, wherein the low permeability has a range of one to 550 u.

71. The converter of claim 67, wherein the NSME is an air magnetic element.

72. The converter of claim 67, wherein the NSME further comprises a B-H curve characteristic ranging from B=1 to 10,000 gauss and H=1 to 100 oersteds.

73. The converter of claim 67 further comprising a frequency modulating circuit to regulate an output signal from the NSME.

74. The converter of claim 67, wherein said resonant mode converter is driven by the power factor connected resonant mode controller via a variable frequency controller.

75. The converter of claim 67, wherein said NSME
further comprises a distributed magnetic element.

76. The converter of claim 67, wherein the NSME is selected from the group consisting of:
an air magnetic element;
a molypermalloy powder(MPP) magnetic element;
a high flux MPP magnetic element;
a powder magnetic element;
a gapped ferrite magnetic element;
a tape wound magnetic element;
a cut magnetic element;
a laminated magnetic element; and an amorphous magnetic element.

77. A resonant converter comprising:
a power factor corrected resonant mode controller;
a resonant mode converter having a feedback circuit;
a full wave rectified output circuit;
said power factor corrected resonant mode controller providing a variable frequency signal to the resonant mode converter;
said resonant mode converter further comprising:
a magnetic element operating in a non-saturated region (NSME);
a positive and a negative. input terminal each connected to a power source;

said positive input terminal connected to a collector of a NPN transistor;
said NPN transistor having an emitter connected to an emitter of a PNP transistor and to a first terminal of said NSME;
said negative input terminal connected to a resonant capacitor and to a collector of said PNP transistor;
said base of said PNP transistor connected to a base of the NPN transistor and to an output of said power factor corrected resonant mode controller; and said resonant capacitor further connected to a second terminal of said NSME.

78. The converter of claim 77, wherein said NSME
further comprises a low permeability.

79. The converter of claim 77, wherein the NSME further comprises a mixture of 85% by weight of iron, 6% by weight of aluminum, and 9% by weight of silicon, thereby providing a wide thermal operating range for the magnetic element.

80. The converter of claim 78, wherein the low permeability has a range of one to 550.

81. The converter of claim 77, wherein the NSME is an air magnetic element.

82. The converter of claim 77, wherein the NSME further comprises a B-H curve characteristic ranging from B=1 to 10,000 gauss and H=1 to 100 oersteds.

83. The converter of claim 77 further comprising a frequency modulating circuit to regulate an output signal from the NSME.

84. The converter of claim 77, wherein said resonant mode converter is driven by the power factor corrected resonant mode controller via a variable frequency controller.

85. The converter of claim 77, wherein said NSME
further comprises a distributed magnetic element.

86. The converter of claim 77, wherein the NSME is selected from the group consisting of:
an air magnetic element;
a molypermalloy powder(MPP) magnetic element;
a high flux MPP magnetic element;
a powder magnetic element;
a gapped ferrite magnetic element;
a tape wound magnetic element;

a cut magnetic element;
a laminated magnetic element; and an amorphous magnetic element.

87. A resonant sub-circuit comprising:
a capacitor having a connection to a magnetic element thereby forming a resonate relationship there between;
wherein said magnetic element further comprises a magnetic element operating in a non saturating region thereof (NSME).

88. The sub-circuit of claim 87, further connected to a filter circuit, thereby giving the filter circuit a lower mass, complexity and cost for a given filtering characteristic.

89. The converter of claim 88, wherein said NSME further comprises a low permeability.

90. The converter of claim 89, wherein the NSME further comprises a mixture of 85% by weight of iron, 6% by weight of aluminum, and 9% by weight of silicon, thereby providing a wide thermal operating range for the magnetic element.

91. The converter of claim 89, wherein the low permeability has a range of one to 500.

92. The converter of claim 89, wherein the NSME is an air magnetic element.

93. The converter of claim 89, wherein the NSME further comprises a B-H curve characteristic ranging from B=1 to 10,000 gauss and H=1 to 400 oersteds.

94. The sub-circuit of claim 88, wherein the connection is a parallel connection.

95. The sub-circuit of claim 88, wherein the connection is a series connection.

96. In a power conversion circuit having an energized magnetic element, the improvement comprising:
said magnetic element operating in a non saturating region thereof (NSME);
said magnetic element having a natural frequency;
and said energizing power approximately matched to said natural frequency thereby providing a higher power density, an improved thermal stability, and an increased conversion efficiency.

97. The converter of claim 96, wherein said NSME further comprises a low permeability.
98. The converter of claim 97, wherein the NSME further comprises a mixture of 85% by weight of iron, 6% by weight of aluminum, and 9% by weight of silicon, thereby providing a wide thermal operating range for the magnetic element.

98. The converter of claim 97, wherein the low permeability has a range of one to 500.

99. The converter for claim 97, wherein the NSME is an air magnetic element.

100. The converter of claim 97, wherein the NSME further comprises a B-H curve characteristic ranging from B=1 to 10,000 gauss and H=1 to 400 oersteds.

101. A transient protection circuit comprising:
a rectifier sub-circuit;
a parallel capacitor/resistor circuit having a path to a ground;
wherein a normal line voltage results in a passive mode, cap; and wherein a slight excess of line voltage results in a flow of current to the capacitor through a low impedance mode in the rectifier.

102. A method to prevent an excessive inrush current to a capacitor on a DC output of a power converter, the method comprising:
providing a series resistor to an output capacitor;
providing a switch across the series resistor;
generating a control signal upon an activation of the power converter, thereby closing said switch and shunting said series resistor to ground; and thereby creating a controlled charging of said output capacitor.

103. In a parallel multiple power supply topology for a load sharing and redundancy and hot swap power source, an apparatus for maintaining an approximately equal load level among N power supply units, said apparatus comprising:
for each (N1, N2, N x) power supply unit, a portion of the output voltage is fed to a comparison circuit having a comparator for comparing the portion of the output voltage to a reference voltage;

an output signal current load measuring circuit for each power supply unit;
an output from the measuring circuit forming a summed signal with the portion of the output voltage; and thereby providing a near equal power sharing among the N power supply units.

104. In a parallel multiple power supply topology for a load sharing and redundancy and hot swap power source, an apparatus for maintaining an approximately equal load level among N power supply units, said apparatus comprising:
for each (N1, N2, N x) power supply unit, a portion of the output voltage is fed to a comparison circuit having a comparator for comparing the portion of the output voltage to a reference voltage;
an output signal current load measuring circuit for each power supply unit;
an output from the measuring circuit forming a bias current to the reference voltage;
thereby providing a near equal power sharing among the N power supply units.

105. In a brown out and high temperature circuit startup environment, an apparatus to speed up a start up of a power supply control circuit in a power converter, said apparatus comprising:
a rectified voltage source having a same ground potential as a ground potential for said control circuit, and independent of said control circuit, functioning to initially start up the power supply control circuit;
a switch connecting a portion of the rectified voltage source to the power supply control circuit;
a detector circuit for determining an operational mode of the power converter functioning to shut off said switch;
thereby providing a fast start circuit with little energy dissipation under normal operating conditions.