CA2338564A1 - Single chip cmos transmitter/receiver and vco-mixer structure - Google Patents
Single chip cmos transmitter/receiver and vco-mixer structure Download PDFInfo
- Publication number
- CA2338564A1 CA2338564A1 CA002338564A CA2338564A CA2338564A1 CA 2338564 A1 CA2338564 A1 CA 2338564A1 CA 002338564 A CA002338564 A CA 002338564A CA 2338564 A CA2338564 A CA 2338564A CA 2338564 A1 CA2338564 A1 CA 2338564A1
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- CA
- Canada
- Prior art keywords
- signals
- frequency
- carrier frequency
- communication system
- coupled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K9/00—Demodulating pulses which have been modulated with a continuously-variable signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/16—Networks for phase shifting
- H03H11/22—Networks for phase shifting providing two or more phase shifted output signals, e.g. n-phase output
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
- H04B1/403—Circuits using the same oscillator for generating both the transmitter frequency and the receiver local oscillator frequency
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/04—Frequency selective two-port networks
- H03H2011/0494—Complex filters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Transceivers (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Superheterodyne Receivers (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Transmitters (AREA)
Abstract
A single chip RF communication system and method and a VCO-mixer (130) structure are provided. The RF communication system in accordance with the present invention includes a transmitter (1100) and a receiver (100), an antenna for receiving transmitting RF signals, a PLL (130) for generating multi-phase clock signals having a frequency different from a carrier frequency in response to the multi-phase clock signals and a reference signa l having the carrier frequency, a demodulation-mixing unit (140) for mixing th e received signal with the multi-phase clock signals having a frequency different from the carrier frequency to output the RF signals having a frequency reduced by the carrier frequency and an A/D converting unit (160) for converting the RF signals from the mixing unit into digital signals. The VCO (130) in accordance with the present invention includes a plurality of differential delay and the mixer includes a differential amplifying circuit (1200A) and combining circuit (1200B). The differential amplifying circuit (1200A) of the multi-phase mixer includes two load resistors (R2, R1) couple d to two differential amplifiers (1200A1, 1200A2) respectively. The combining circuit (1200B) includes bias transistors (1232, 1234), first and second combining circuits coupled to the bias transistors, respectively and a curre nt source coupled to the first and second combining units.
Claims (18)
1. A communication system, comprising:
a receiver unit that receives signals including selected signals having a carrier frequency;
a phase-locked loop that generates multi-phase clock signals having a frequency different from the carrier frequency and a reference signal having the carrier frequency; and a demodulation-mixing unit that mixes the selected signals received by the receiver unit with the multi-phase clock signals to output the selected signals having a frequency reduced by the carrier frequency.
a receiver unit that receives signals including selected signals having a carrier frequency;
a phase-locked loop that generates multi-phase clock signals having a frequency different from the carrier frequency and a reference signal having the carrier frequency; and a demodulation-mixing unit that mixes the selected signals received by the receiver unit with the multi-phase clock signals to output the selected signals having a frequency reduced by the carrier frequency.
2. The communication system of claim 1, wherein the frequency is smaller than the carrier frequency, and wherein the carrier frequency is greater than about 1GHz, and further wherein the phase-locked loop includes a clock generator.
3. The communication system of claim 1, wherein the receiver unit is a transceiver, further comprising:
a modulation mixer that mixes the multi-phase clock signals with transmission data to modulate the transmission data; and a power amplifier that amplifies the modulated transmission data and transmits the data to the transceiver for transmission.
a modulation mixer that mixes the multi-phase clock signals with transmission data to modulate the transmission data; and a power amplifier that amplifies the modulated transmission data and transmits the data to the transceiver for transmission.
4. The communication system of claim 1, further comprising:
a RF filter coupled to the receiver unit that filters the selected signals received by the receiver unit;
a low noise amplifier coupled to the RF filter that amplifies the selected signals filtered by the RF filter with a gain;
a low pass filter coupled to the demodulation-mixing unit that filters the selected signals having the frequency reduced by the carrier frequency;
an A/D converting unit that converts the selected signals from the mixing unit into digital signals; and a discrete-time signal processing unit that receives the digital signals.
a RF filter coupled to the receiver unit that filters the selected signals received by the receiver unit;
a low noise amplifier coupled to the RF filter that amplifies the selected signals filtered by the RF filter with a gain;
a low pass filter coupled to the demodulation-mixing unit that filters the selected signals having the frequency reduced by the carrier frequency;
an A/D converting unit that converts the selected signals from the mixing unit into digital signals; and a discrete-time signal processing unit that receives the digital signals.
5. The communication system of claim 1, wherein:
the communication system is a RF receiver portion;
the selected signals are RF signals;
the multi-phase clock signals have a frequency of (2*carrier frequency/N), wherein N is a positive integer; and the RF communication system is formed on a single CMOS chip.
the communication system is a RF receiver portion;
the selected signals are RF signals;
the multi-phase clock signals have a frequency of (2*carrier frequency/N), wherein N is a positive integer; and the RF communication system is formed on a single CMOS chip.
6. A single chip RF communication system, comprising:
a transceiver for receiving and transmitting RF signals;
a phase-locked loop for generating 2N-phase clock signals having a frequency 2*f o /N smaller than a carrier frequency, wherein N is a positive integer as a phase number and f o is the carrier frequency;
a demodulation mixing unit for mixing the RF signals from the transceiver with 2N-phase clock signals from the phase-locked loop to output the RF
signals having a frequency reduced by the carrier frequency, wherein the demodulation mixer comprises a plurality of two input mixers; and an A/D converting unit for converting the RF signals from the demodulation mixing unit into digital signals.
a transceiver for receiving and transmitting RF signals;
a phase-locked loop for generating 2N-phase clock signals having a frequency 2*f o /N smaller than a carrier frequency, wherein N is a positive integer as a phase number and f o is the carrier frequency;
a demodulation mixing unit for mixing the RF signals from the transceiver with 2N-phase clock signals from the phase-locked loop to output the RF
signals having a frequency reduced by the carrier frequency, wherein the demodulation mixer comprises a plurality of two input mixers; and an A/D converting unit for converting the RF signals from the demodulation mixing unit into digital signals.
7. The communication system of claim 6, wherein the demodulation mixing unit comprises a first mixer array comprising one half of the two input mixers and a second mixer array comprising the other half of the two input mixers, wherein the first and second mixer array inputs each corresponding N-phase clock signal of the 2N-phase clock signals together with the RF signals.
8. The communication system of claim 6, wherein each mixer array comprises multi-stages of mixers, each stage comprising at least one two-input mixer, and a first stage of the multi-stages inputs the RF signals and N-phase clock signals.
9. The communication system of claim 8, wherein the multi-stages have a corresponding reducing number of mixers K1 > K2 > K3 > ........ > Ki, where K1 is the first stage, K2 is a second stage, K3 is a third stage, and Ki is a ith stage.
10. A method of operating a RF communication system, comprising:
receiving signals including selected signals having a carrier frequency;
generating multi-phase clock signals having a frequency different from the carrier frequency, and a reference signal having the carrier frequency; and mixing the received selected signals with the multi-phase clock signals to output the selected signals having a frequency reduced by the carrier frequency.
receiving signals including selected signals having a carrier frequency;
generating multi-phase clock signals having a frequency different from the carrier frequency, and a reference signal having the carrier frequency; and mixing the received selected signals with the multi-phase clock signals to output the selected signals having a frequency reduced by the carrier frequency.
11. The method of claim 10, further comprising RF filtering the received selected signals;
amplifying the filtered selected signals with a gain;
low pass filtering the selected signals having the frequency reduced by the carrier frequency;
A/D converting the low pass filtered frequency reduced selected signals into digital signals; and discrete-time signal processing the digital signals.
amplifying the filtered selected signals with a gain;
low pass filtering the selected signals having the frequency reduced by the carrier frequency;
A/D converting the low pass filtered frequency reduced selected signals into digital signals; and discrete-time signal processing the digital signals.
12. The method of claim 10, further comprising:
modulation mixing the multi-phase clock signals with transmission data to modulate the transmission data; and power amplifying the modulated transmission data and transmitting the data to the transceiver for transmission.
modulation mixing the multi-phase clock signals with transmission data to modulate the transmission data; and power amplifying the modulated transmission data and transmitting the data to the transceiver for transmission.
13. A circuit comprising:
a clock generator that generates a plurality of first clock signals having different phases, each first clock signal having a first frequency which is less than a reference frequency; and a mixer coupled to said clock generator for receiving the plurality of first clock signals to generate a plurality of second clock signals having a second frequency which is substantially same as the reference frequency, wherein said mixer multiplies the plurality of second clock signals with input signals to provide output signals.
a clock generator that generates a plurality of first clock signals having different phases, each first clock signal having a first frequency which is less than a reference frequency; and a mixer coupled to said clock generator for receiving the plurality of first clock signals to generate a plurality of second clock signals having a second frequency which is substantially same as the reference frequency, wherein said mixer multiplies the plurality of second clock signals with input signals to provide output signals.
14. The circuit of claim 13, wherein said clock generator includes a plurality of delay cells coupled in series for providing the plurality of first clock signals having different phases.
15. The circuit of claim 13, wherein said mixer includes:
a differential amplifying circuit for receiving the input signals and providing the output signals; and a combining circuit for receiving the plurality of first clock signals from said clock generator.
a differential amplifying circuit for receiving the input signals and providing the output signals; and a combining circuit for receiving the plurality of first clock signals from said clock generator.
16. The circuit of claim 15, wherein said differential amplifying circuit includes:
at least one load resistor coupled for receiving a first potential; and at least one differential amplifier coupled to one of the said load resistors, and the combining circuit.
at least one load resistor coupled for receiving a first potential; and at least one differential amplifier coupled to one of the said load resistors, and the combining circuit.
17. The circuit of claim 15, wherein said combining circuit comprises:
a first combining unit for receiving corresponding first clock signals and coupled to said differential amplifying circuit to output a corresponding second clock signal;
a second combining unit for receiving corresponding first clock signals and coupled to said differential amplifying circuit to output a corresponding second clock signal; and a current source coupled to said first and second combining units and coupled for receiving a second potential.
a first combining unit for receiving corresponding first clock signals and coupled to said differential amplifying circuit to output a corresponding second clock signal;
a second combining unit for receiving corresponding first clock signals and coupled to said differential amplifying circuit to output a corresponding second clock signal; and a current source coupled to said first and second combining units and coupled for receiving a second potential.
18. The circuit of claim 17, further comprising first and second bias transistors respectively coupled between said first and second combining units and the differential amplifying circuit, wherein each of said first and second combining units comprises a plurality of transistor units coupled to each other in one of series and parallel.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/121,601 | 1998-07-24 | ||
| US09/121,863 US6194947B1 (en) | 1998-07-24 | 1998-07-24 | VCO-mixer structure |
| US09/121,863 | 1998-07-24 | ||
| US09/121,601 US6335952B1 (en) | 1998-07-24 | 1998-07-24 | Single chip CMOS transmitter/receiver |
| PCT/US1999/014162 WO2000005815A1 (en) | 1998-07-24 | 1999-07-23 | Single chip cmos transmitter/receiver and vco-mixer structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2338564A1 true CA2338564A1 (en) | 2000-02-03 |
| CA2338564C CA2338564C (en) | 2009-12-22 |
Family
ID=26819639
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002338564A Expired - Lifetime CA2338564C (en) | 1998-07-24 | 1999-07-23 | Single chip cmos transmitter/receiver and vco-mixer structure |
Country Status (9)
| Country | Link |
|---|---|
| EP (1) | EP1101285A4 (en) |
| JP (1) | JP4545932B2 (en) |
| KR (1) | KR100619227B1 (en) |
| CN (1) | CN1148873C (en) |
| AU (1) | AU764882B2 (en) |
| CA (1) | CA2338564C (en) |
| HK (1) | HK1040467B (en) |
| TW (1) | TW463464B (en) |
| WO (1) | WO2000005815A1 (en) |
Families Citing this family (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA2281236C (en) | 1999-09-01 | 2010-02-09 | Tajinder Manku | Direct conversion rf schemes using a virtually generated local oscillator |
| US6809567B1 (en) * | 2001-04-09 | 2004-10-26 | Silicon Image | System and method for multiple-phase clock generation |
| DE10211381A1 (en) * | 2002-03-14 | 2003-06-12 | Infineon Technologies Ag | Transmission unit for frequency modulation has frequency mixer converting modulated signal into a sending frequency |
| US7256740B2 (en) * | 2005-03-30 | 2007-08-14 | Intel Corporation | Antenna system using complementary metal oxide semiconductor techniques |
| CN100424481C (en) * | 2006-04-30 | 2008-10-08 | 天津菲特测控仪器有限公司 | High-precision radar difference frequency time base generation method and circuit based on monocrystal |
| JP2008035031A (en) * | 2006-07-27 | 2008-02-14 | Matsushita Electric Ind Co Ltd | Mixing device and high frequency receiver using the same |
| JP2008092476A (en) * | 2006-10-04 | 2008-04-17 | Niigata Seimitsu Kk | Receiver |
| CN101931386B (en) * | 2009-06-19 | 2014-03-26 | 鸿富锦精密工业（深圳）有限公司 | Pulse width modulation control system |
| US8811926B2 (en) * | 2010-03-23 | 2014-08-19 | University Of Washington Through Its Center For Commercialization | Frequency multiplying transceiver |
| JP5633270B2 (en) * | 2010-09-16 | 2014-12-03 | 株式会社リコー | Transceiver |
| CN102035471B (en) * | 2011-01-05 | 2014-04-02 | 威盛电子股份有限公司 | Voltage-controlled oscillator |
| JP2012217157A (en) * | 2011-03-30 | 2012-11-08 | Asahi Kasei Electronics Co Ltd | Mixer circuit |
| US8729968B2 (en) * | 2011-05-09 | 2014-05-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Built-in self-test circuit for voltage controlled oscillators |
| GB201115119D0 (en) | 2011-09-01 | 2011-10-19 | Multi Mode Multi Media Solutions Nv | Generation of digital clock for system having RF circuitry |
| US8803568B2 (en) * | 2011-11-28 | 2014-08-12 | Qualcomm Incorporated | Dividing a frequency by 1.5 to produce a quadrature signal |
| KR102136798B1 (en) | 2014-01-21 | 2020-07-22 | 삼성전자주식회사 | Super-regenerative receiver and super-regenerative reception method with improved channel selectivity |
| US9634607B2 (en) * | 2014-03-11 | 2017-04-25 | Qualcomm Incorporated | Low noise and low power voltage-controlled oscillator (VCO) using transconductance (gm) degeneration |
| EP2950447A1 (en) * | 2014-05-28 | 2015-12-02 | Nxp B.V. | Frequency converter |
| US9647638B2 (en) * | 2014-07-15 | 2017-05-09 | Qualcomm Incorporated | Architecture to reject near end blockers and transmit leakage |
| KR101764659B1 (en) | 2015-07-01 | 2017-08-04 | 청주대학교 산학협력단 | Voltage-to-current converter with high linearity and wide tuning range and its application to voltage controlled oscillator |
| CN105656824B (en) * | 2015-12-31 | 2019-01-11 | 华为技术有限公司 | The adjustable communication device of bias voltage and communication means |
| DE102016115785A1 (en) | 2016-08-25 | 2018-03-01 | Infineon Technologies Ag | Integrated RF circuit with possibility to test phase noise |
| US11095427B1 (en) * | 2020-09-25 | 2021-08-17 | Intel Corporation | Transceiver with inseparable modulator demodulator circuits |
| CN115549703A (en) * | 2022-10-09 | 2022-12-30 | 芯翼信息科技(上海)有限公司 | Integrated CMOS power amplifier wide voltage transmitter and transceiver |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5438591A (en) * | 1991-07-31 | 1995-08-01 | Kabushiki Kaisha Toshiba | Quadrature amplitude modulation type digital radio communication device and method for preventing abnormal synchronization in demodulation system |
| JP3359927B2 (en) * | 1991-10-17 | 2002-12-24 | 株式会社東芝 | Demodulator for quadrature amplitude modulation digital radio equipment. |
| JP3241098B2 (en) * | 1992-06-12 | 2001-12-25 | 株式会社東芝 | Multi-system receiver |
| JPH08223071A (en) * | 1995-02-08 | 1996-08-30 | Sony Corp | Transmitter and transmitter-receiver |
| US5794119A (en) * | 1995-11-21 | 1998-08-11 | Stanford Telecommunications, Inc. | Subscriber frequency control system and method in point-to-multipoint RF communication system |
| JP3476318B2 (en) * | 1995-11-22 | 2003-12-10 | 株式会社東芝 | Frequency converter and radio receiver using the same |
-
1999
- 1999-07-23 EP EP99935344A patent/EP1101285A4/en not_active Withdrawn
- 1999-07-23 WO PCT/US1999/014162 patent/WO2000005815A1/en active IP Right Grant
- 1999-07-23 KR KR1020017001063A patent/KR100619227B1/en not_active IP Right Cessation
- 1999-07-23 JP JP2000561705A patent/JP4545932B2/en not_active Expired - Lifetime
- 1999-07-23 CN CNB998087645A patent/CN1148873C/en not_active Expired - Lifetime
- 1999-07-23 CA CA002338564A patent/CA2338564C/en not_active Expired - Lifetime
- 1999-07-23 AU AU50840/99A patent/AU764882B2/en not_active Ceased
-
2000
- 2000-11-10 TW TW088112619A patent/TW463464B/en not_active IP Right Cessation
-
2002
- 2002-02-16 HK HK02101131.6A patent/HK1040467B/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010082016A (en) | 2001-08-29 |
| KR100619227B1 (en) | 2006-09-05 |
| EP1101285A4 (en) | 2001-10-04 |
| CN1148873C (en) | 2004-05-05 |
| HK1040467B (en) | 2005-03-04 |
| TW463464B (en) | 2001-11-11 |
| WO2000005815A1 (en) | 2000-02-03 |
| AU5084099A (en) | 2000-02-14 |
| CA2338564C (en) | 2009-12-22 |
| JP4545932B2 (en) | 2010-09-15 |
| AU764882B2 (en) | 2003-09-04 |
| CN1309835A (en) | 2001-08-22 |
| HK1040467A1 (en) | 2002-06-07 |
| JP2002521904A (en) | 2002-07-16 |
| EP1101285A1 (en) | 2001-05-23 |
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| EEER | Examination request |