CA2257657A1 - Restricted information distribution system apparatus and methods - Google Patents

Abstract

Authorized decoders (60) are provided with enable reception keys (66) so that subsequently transmitted data having an information identification code matching (65) a reception key (66) at a decoder-receiver may be retrieved for subsequent display on the video screen. Tile messaging (72.1) and cellular micrographic transmission techniques are used to reduce the volume of data transmitted to change update data, wherein cells (72.1) of characters are transmitted as one byte of data and cells (72.1) of pixel data are transmitted a plurality of bytes of data. Each decoder-receiver (60) may have a plurality of video screens separately and uniquely identified such that encoded update data and other messages are transmitted for specific video screens. The system includes multiplexing financial market information and television program information signals, and transmitting the multiplexed signals to the decoder-receivers for selectively displaying different combinations of information.

Description

CA 022~76~7 1999-01-12 -W093~23~ PCT/US93/04361 ORRI8-lC

RESTRICTED lN~h~ATION
DISTRIBUTION SYSTEM APPARATUS AND ~T~Q~S

F~eld of the Tnvent~on The ~ubject invention relates to the distribution of information and, more particularly, for distributing this information in a secure and restricted manner to a plurality of users.
Back~loulld Of The Invention Applicant and other related companies are in the busines6 of distributing realtime financial market information to various clients who use this information to cArry on their business. When a client subscribes for this service, an ~greement is entered into in which the client indicates what information i8 desired and how many video screens will be displaying the information. Based on these parameters, a fee is as~e~ to the client and the information then is transmitted to the client.
Typically, this fin~nci~l market information is transmitted to clients as one or more pages or records that may be displayed on a video screen, portions of which, from time to time, are updated to reflect changes in the market information. Various clients subscribe to view different specific yLOu~ of these pages and/or records.
An early method of distributing market information was ~ based upon the transmission of a single page of real time digital information over a single telephone line. Page-oriented information (ROW ~, COL t, C~R~TER STRING) was sent from the information vendor's computer over a telerhone network to a controller, provided by the information vendor, located at the client site. The page-oriented information CA 022~76~7 1999-01-12 W093/239~8 PCT/US93/~361 W_S ~"h-~quently 'O~Vt~ Led to video by _ video generation unit within the conL~oller. The video ouL~ was then connected to _ video screen by a single co_xial c_ble.
EAch full page WAs repeAtedly transmitted in video at a field rate for realtime display, similar to that of a television transmission. However, once the video signal was produced, there was nothing, except the personal integrity of the client, to ~e~el.L the client from cQnnecting any number of video screens to a video distribution amplifier co~nected to the ~G.. L.oller, driving a larger number of video screens above and beyond the number stated in the -agreement. This practice dilutes the revenues to which the information vendor would ordinarily be entitled.
This architecture was costly and unreliable because of the large amount of hardware needed to place financiAl information on A large number of trading desks. For ex_mple, if a client'~ trading room had thirty traders, each trader needed his own single-user system resulting in thirty keyboards, thirty controllers with thirty internal video generation units, thirty telephone cables, thirty modems, thirty coaxial video cables, and thirty video screens to receive and display the required financial information.
This technology _lso limited the screen presentation format to what was provided by the information vendor. When traders were only interested in one or two fields of information on a screen, they would have to display the entire page of information. If they wanted to look at one or more fields of information on a ~?con~ screen at the same time, an entire additional single-user system would be required. Further, when two traders wanted to look at the same page, they would either have to have two separate single-user ~ystems or the video information would be redistributed to a ~sl_ve~ video screen making it difficult for the information vendor to know how m_ny video screens 3s were connected to a given controller and hence how many people were viewing their information. This made billing CA 022~76~7 1999-01-12 W093~23958 PCT/US93/~ ~1 difficult and usually cre_ted a ~G~e38 of surprise client-site visits that left both information vendor and client llnhArry.
The development of multi-user systems re~l~ceA the amount of reguired hardw_re and enabled users to share resources and view common inform_tion. In multi-user sy~tems, each trader had one keyboard and sever_l video s~- eel~D- Through the use of video switching teGh~ues, thirty traders could sh_re perhaps ten or fifteen ~Gr-L-ollers and contend for their use. Since many trader~ are part of a trading group that uses essentially the s_me fi~AnciAl market information, - the probability of blocki~g (not having a cG,.L~oller available to fulfill a new page request) w_s small.
Such multi-user systems helped reduce costs by reducing the number of controllers, keyboards, and system c_bling, but did not solv~ either the billing problems or allow the user to customize screen present_tion form_ts.
Later, single telephone line, multi-page distribution systems were developed which re~l~ce~ the required number of telephone lines. The information syntAx for these multi-page sou~ces was slightly modified to (PAGE ~, ROW t, COL ~, CHARACTER STRING). Users of such systems also could create composite pages (fields from different p_ges displ_yed simultaneously on one video screen) and calcul_te and insert additional value-added information (e.g., bond yield to maturity). By doing so, customized vhL~L display p_ges could be cre_ted showing only the information and value-added c_lculations the user wanted to see.
Users developing value-_dded _pplications based upon page oriented dat_ had to assign a symbolic n_me to an '~ information field located at a specific display location of the input source p_ge. When the information vendor changed the ~.~-~nt_tion format of the information (i.e., the location of a specific data element), ac often hArr~nc when fin_ncial instruments are either _dded or deleted, the value-added _pplication had to be modified. To overcome . ~ .

CA 022~76~7 1999-01-12 W093t23 ~ PCT/US93/04361 this difficulty, and to supply basic information without display parameters, the information vendor created ~e~old-oriented 60U1~ 3 using the ~yntax (SY~RQTTC NAME, ~U~ACTER
STRING). Example~ of such a system are the Reuter~
Integrated Data Network and the Telerate TIQ Feed.
Despite the foregoing advances in the field of electronic f1nanC~Al information distribution sy~tems, current systems ~till allow video ~creens to be added and/or moved freely without either the information vendor'~ knowledge or con~nt. Further, each video ~creen must be co~nected by its own single-video ~home-run~ cable, i.e., a cable that typically runs for hundreds of feet between the trading floor where the video screen is located ~nd the eguipment room where either a ~G..~Loller, video ~witch ~u~y~ or a host computer i5 located.

Summary Of The Invention An object of the present invention i8 to provide a system capable of securely providing restricted information.
A further object of the present invention is to provide a system which is capable of uniguely identifying each of the video screens authorized to display information, to restrict this information to only these individual video screens, to identify which of the information these video screens are to display, and to present only authorized information on each and every video screen; unauthorized video screens would only ~ nt unintelligible transmogrified versions of the information.
It also is a object of the present invention to provide a financial information distribution sy~tem that is capable of taking inputs simultaneously from both multiple information page and/or record-oriented input 8~ es (e.g. video, digital and/or live television) and a multitude of keyboards, to create a multitude of different ou~u~
displays for conc~rrent displ~y on a multitude of video screens all interconnected by a single cable, such that the CA 022~76~7 1999-01-12 W093/23~ PCT/US93/~361 video screen6 may contain different combin_tions of portions of different input 60U~ cas of information.
It is a further object of the pre~ent invention to provide a f~n-~c~al information di~tribution ~y~tem in which each video ~creen ha6 a unigue display identification code that i6 used to authorize viewing and/or to permi6sion what input source information each individual video screen will be capable of displaying at any given time.
It is a another object of the present invention to facilitate the ability to provide each u6er's video screen(6) with a customized ouL~L display.
- It is yet another object of the present invention to reduce the cost of transmitting and displaying financial market updates to numeroug user6.
lS It i8 further object of the present invention to provide a single host computer device to ~U~G~ L a plurality of users and an even l_rger plurality of video screens for securely distributing restricted information to one or more authorized video screens simult~r~ ly. It is another object to allow rapid response to user request~ to view new or additional source of information.
It is _nother object to provide for distributing information in a tile format whereby each user cAn assign a location on that user'~ video screen for display of the 2S tile, and the same display information may be displayed on different locations on different video 6creens and simultaneously updated. It is another object to DU~pO~ L a larger video screen to provide for displaying tiles from a plurality of information input 80Uk~e5 simultAneo~ly.
Applicant has r~co~ni7ed that usu~lly only small portions of the input page or record source information change over a 6mall time, for example, the time ~GL~e~ ..Ajng to one field time of displayed video. It is, therefore, necesF-ry to transmit only the information which i~ changing as update 3S data and then to store th1s update data, along with the CA 022~76~7 1999-01-12 WO93/2~K~ PCT/US93/04361 ~nrhAnged d~ta, in a memory at the video ~creen for subseguent display.
It is, therefore, another object to preprocess video signals to identify the changed di~play information to be displayed prior to inputting the video information into a display information distribution system, thereby minimizing the amount of chAnnel bandwidth n~cesF~ry to distribute the information.
~t is another object of the invention to provide for preprocessing digital and analog video signals for display information including financial market information and - television ~Gy.am information signals. It is another object to provide for preprocessing composite and non composite video signals. It is yet another object to provide a switchable device that can process information in color and monochromatic video signals.
It is another object of the invention to provide a modular residual video converter device that can be constructed as a ~mall printed circuit assembly so that one assembly is used for each source of video signals and ~everal assemblies can be combined onto a single printed circuit board for ease of packaging and expansion.
It is another object of the present invention to improve the efficiency and messaging capacity of an information distribution system by converting incoming video signals having successive frames of display information to digital video messages identifying the pixel changes from one frame to the next.
Applicant also has rerognized that users typically want to view only a portion of a full page or record of source information provided by the vendor and therefore use several video screens displaying different sources of information so that the information they wish to view is concurrently displayed on multiple screens.
With these facts in mind, the above objects are achieved in a system for securely providing restricted information, CA 022~76~7 1999-01-12 t ~ ~

wherein the ~y~tem includes an ~ r for ~nco~ng update data for updating various tiles (i.e., portion~ of pages or records) of display information, and a plurality of ~co~rs for A~coA~ng said update data and generating said various ou~u~ displays on video screens, characterized in that ~aid encoA~r comprises means for generating a first data stream, said first data stream including ~e~e_~ive ~ets of one or more unique display identification codes identifying each video screen and one or more information identification codes for each of said tiles, said ~et~ being indicative of the tiles, i.e., each particular portion of display information, each video screen of each client or user is authorized to receive; means for generating a sequence of ~- DnA data streams, each of ~aid r~conA data streams including one of ~aid individual information identification codes, coordinates of an area in a relevant video screen that is to display update data for the portion of display information, and the respective update data; and ~eans for transmitting said firct data stream followed by ~aid sequence of s~:~nA data streams; and in that each of ~aid decoders comprises a video screen; means for identifying the relevant video screen with one of said unique display identification codes; means for ~e_Gy-.izing said one unique display identification code and for storing the information identification codes in the associated set with said one unique displ~y identification code; means for retrieving said di~play coordin~tes of the update data correerQnA1ng to each of said stored information identification codes; means for storing said update data at the related coordinates for subsequent display on the video screen; and means for selectively displaying said ~tored updated display information on the video screens.
In accordance with a preferred embodiment, the enco~Pr (also referred to as a transmitter) is a mic~G~ r based device that transmits a high bandwidth digital and/or analog signal over a single coaxial cable. The encoAPr CA 022~76~7 1999-01-12 WO93/2~K~ PCT/US93/W361 manages communications be~ce,. a host computer and the plurality of ~roA~rs (al~o referred to as receivers), cA~h~c those particular portions of display informAtion that are being viewed on video ~creens, and stores symbolic data element~. All dat_ changes and/or ~pecific instructions sent to any one or all of the ~coAPrs origin_tes in an applicAtion r~nn~nq on the host computer, and i~ transmitted via a digital-video (DV) bus from the ~nco~Pr to the decoder (8) . A delta-modulation type of communication protocol is used to gre_tly reduce the amount of transmitted information. Unlike a video ~witch environment, in which Almost the s_me information is transmitted sixty times a ~e-on~, only display screen changes are Fignaled.
Di~plny changes are transmitted by tile messaging, i.e., transmitting the portion of the page or record of fln~nci market information that contains the changed financial market information within a tile of horizontally and vertically ccntiguous cells. Each tile is given an information identification code and has cGl~6~po~ ng data such that authorized users of the data are enabled with the corresponding information identification code as a symbolic name or reception key for identifying the particular tile by its symbolic n_me or reception key and receiving and retrieving the upd_te data. Further, the tile m_y be given a default size and displ_y loc_tion on a video screen, a user-defined size and display location, or both, such that the transmitted data is mapped into any user-defined location as it is stored for display on the video screen.
Some of the transmitted data may not be stored or displayed when the user-defined tile is smaller than the transmitted tile.
The cost _ssociated with transmitting the same data for different tiles (pages or records) of information can be greatly reduced in accord_nce with the present invention, by initializing the location of an individual data field, through the use of a message identifying (i) the information CA 022~76~7 1999-01-12 W093~K8 PCT/US93/~361 _g_ identification code for a particular 60urce page or ~eCGld of di~play information, ($i) the information identification code for the specific information field tl~ou~l- the u~e of a symbolic name of a tile conta~n~ng the individual data field, and tiii) a location in which the data of the data field are to appear on the particular tile. After this initialization, the information identification code for the symbolic name can be transmitted along with data, without any display coordinate information, and each initiAl~ed video screen that displays the data associated with the symbolic name is updated simult~nDo~ly through the use of :this single data message and previously provided display coordinates.
Each decoder receives at least all transmitted messages for its video screens and stores the information to be displayed, i.e., the ~creen image, in an internal picture store memory. Each ~PcoAPr selects out and ~ G~ only those messages on the DV bus that are directed to its video screens or to the de~oAPr. Thus, each decoAer may have more than one video 6creen and a unique display identification code for each video screen. Each video screen has a unique identification code that supports permissioning of restricted display information to be viewed and is capable of displaying simult~nQo~ly either color or monochromatic 2S text and/or pixel based graphics, as well as live TV
pictures. In addition, the decoder can detect and directly pass through ~ne~coAP~ video signals to its video screens.
Commercially available keyboards and mice may be provided to send information request signals via the ~PcoAPr to a cG.. L.ol bus connecting the plurality of decoders to the encoder or host computer and to define tile size and display locations. The keyboard optionally may include an internal LCD display.
A residual video converter (RVC) device allows both view-only and interactive video sou~es to be utilized on the system. The RVC device accepts one or more video inputs, CA 022~76~7 1999-01-12 W093t~* -PCT/US93/04361 cv..~.Ls them into a DV bus mesfiage format contA~n~ng only video 6creen changes suitable for transmission to the ~eco~rs over the DV bus, and directly interfaces with the enco~r. Thus, the ~ncoA~r may transparently pass the RVC
v~L~L signals at a~o~Liate times.
A television feed ~G,Ive.Ler (TFC) device allows realtime television Qources to be utilized on the system. The TFC
device accepts one or more television inputs, ~o..~e,Ls them into a format ~uitable for transmission to the ~ coAers over the DV bus, and directly interfaces with the ~nGo~er. The ~nco~r may transparently pass the televi~ion ~Gy~am -information signals at a~p~v~liate times.
In addition, financial market information may be brought into the system via a commercially available Digital Interface Board (DIB) device. On larger systems, the DIB
device also may be configured to manage the control bus.
The DIB device also allows for authorized individual~ to gain remote access to the system, for example, by use of passwords. For example, the information vendor may use the interface remotely to ~authorize~ clients to use and/or view predefined subsets of their source information (e.g., to increase the number of authorized video screens). The vendor also is able to gather utilization statistics from each client site which is useful for marketing ~nd/or billing ~u~ e~. The operator of the system may use the ~interface remotely to provide routine software maintenAnce and upgrades, modification of existing composite page definitions, downloading of new composite pages and periodic monitoring of system performance. The client sygtem administrator may use the remote interface to log onto the ~ystem from home or any other remote location.
One advantage of the present invention is that it is ~ufficiently flexible to adapt for use as any of a stand- -alone system in a small system environment having only a digital data feed which the encoder distributes to a plurality of decoders, an enhancement to an existing system CA 022~76~7 1999-01-12 WO g3/23958 PCr/USg3/0436 having a video switc~ng system and user interface hardware ~uch that the e~coA~r o~L~u~ i~ connected to a ~ingle shared input and pa~E~A to one or more ~LpuLs on the video switch to the plurality of u6ers, a work station, and a large ~ystem including, for example, separate machine~ for providing value-added calculations.

DescriDtion Of The Draw~ngs With the above and additional ob~ects and advantages in mind as will hereinafter appear, the invention will be described with refe~e,.~e to the accompanying drawings, in which:
FIG. 1 is a block diagram of a system according to the invention;
FIG. 2 is a diagram representing the transmitted first data stream and the sequence of reconA data streams in a first embodiment of the invention;
FIG. 3A shows a diagram representing a characteristic first data stream, and FIGS. 3B-3F ehow diagrams representing characteristic se~)ences in the second data streams, all in the first embodiment of the invention;
FIG. 4 shows a video screen having a sample market information page thereon in which a block of data to be updated is shown in cross-hatch;
FIG. 5 shows a block diagram of an ~ncoAer in the system according to the first embodiment of the invention;
FIG. 6 shows a block diagr~m of a ~co~r in the system according to the first embodiment of the invention;
FIG. 7 is a diagram representing the transmitted video signals in a ~9~0n~ embodiment of the invention;
FIGS. 7A-7C illustrate the tec~n~ue of transmitting and displaying a plurality of television ~ro~am information 6ignals along with update data;
FIG. 8A shows a diagram ~e~esenting the transmitted first data stream, and FIGS. 8B and 8C show diagrams CA 022~76~7 1999-01-12 W093/2~ PCT/US93/04361 ~e~L~-çnting the ~ nA tr_nsmitted data stream in the reconA embodiment of the invention;
FIG. 9 is a block diagram of an enCoApr in the ~E: ~nA
embodiment of the invention;
FIG. 10 ig a block diagram of a ~eco~Pr in the rE~o~A
embodiment of the invention;
FIG. 11 is _ block diagram of a ~ystem according to a third embodiment of the present invention;
FIG. llA-llC illustrates the transmission of enable reception messages, enable ~ F _e~ion and init~ A l~7Ation messages, initialization messages, and data enable se~Pnces to produce the displays illustrated in FIGS. 12A - 12C
illustrating symbolic signAl~ng;
FIG. llD is a flow chart for ~ Gce~sing messages using symbolic ~ignaling according to one embodiment of the present invention;
FIG. 12 i8 an illustration of the format for a single page of dicplay information in accordance with the invention;
FIGS. 12A-12C illustrate the displays proA~ceA through the message sequences shown in FIGS. llA-llC, as described above;
FIG. 13 is an illustration of a composite page having a plurality of tiles;
FIG. 13A-13C are illustrations of tile messaging for updating different user defined tiles having common display information;
FIGS. 14A and 14B are illustrations of composite pages of display information;
FIG. 15 i~ an illustration of graphic tile messaging with graphic and alphamosaic cells;
FIG. 16 is a block diagram of DV bus signAl~g for the embodiment of FIG. 11;
FIG. 17 is a diagram of a DV bus message stream over two s~Ccescive video signal time period~;

. . ..

CA 022~76~7 1999-01-12 W093~9S8 PCT/US93/04361 FIG. 18 i6 a diagram of a quad level (8,9) modulated signal for a DV bus message;
FIG. 19 i6 a diagram of a ~e~A~r section of a digital message using the quad level t8,9) modulation;
FIG 20 is a diagram of a double buffered error detection and cG--e_-ion interleaving tec~n;que;
FIG 21 i6 A diagr_m of a packet mes~aging sequence including packets of varying length;
FIG. 22 is a diagr_m illustrating packet fieldQ;
FIG 23 is A diagram illustrating message fields;
FIG 24A-24G are diagr_ms of col,L~ol bus messaging - ignals;
FIG 25 is A block schematic diagram of the encoder of FIG 11;
FIG 26 is a block diagram of a desk interface unit of an alternate embodiment of the third embodiment of the present invention.
FIG 27 is a block schematic diagram of the decoder of FIG 11;
FIG 28 is a block schematic diagram of the video ouL~u~
circuit of FIG 27;
FIG 29 is a block diagram of a modular residual video converter device in accordance with a preferred embodiment of the present invention; and FIG 30 is a block schematic diagram of the video digitizer circuits of FIG 29 Description Of The Preferred ~mbod~ment As noted above, the object of the present invention is to distribute information This information i8 transmitted over, for example, telephone lines and converted on the client site into video signals similar to those for televi~ion .e~e~ion The information 6ubscribed to takes the form of pages or ~eCOld8 of market data, various portions of which are updated from time to time to reflect CA 022~76~7 1999-01-12 WO93~K~ -PCT/US93/04~1 changes ln the market, and ~h-esuently ~.~-ented on a video ~creen.
In a first embodiment of the invention, the ~q~Al5 ~e~ enting the market information are being transmitted asynchronously, that i8, there are no set characteristic times (e.g., television field or frame rates) to restrict the transmission. As shown in FIG. 1, one or more portions of source information 10 of market data are each given individual information identification (IID) codes, for example, ~JSN416~ and 'MDC2000~. These portions 10 are then - applied by an encoAPr-transmitter 12 to a digital video transmission line 14. Decoder-receivers 16 are ~hown cQ~nected to the transmission line 14 for receiving and displaying the encoAeA portions 10. As shown, each AecoAer receiver 16 has a unigue displ~y identification (DID) code, for example, ~PAMU0609~, ~BOBO1205~, ~LRN0122~ and ~TBD12??~.
FIG. 2 chows a diagram representing the digital video signals transmitted over the digital video tr~nsmission line 14. As shown in FIG. 2, a first line 20 of the transmission includes ~n encoded signal flag indicating to the APcoAer-receivers 16 that the following information is P~coAeA data.
The exact form of the flag is unimportant since the information cont~in~ is just one bit. The line or lines 22 contain enable reception messages. The lines 24 following the enable reception message lines 22, contain the various datA updates 1, 2 and 3.
Enable reception messageC are used to provide information identification (IID) codes or ~e~e~ion keys (RK) to decoders. The terms ~information identification codes~ and ece~ion keys~ are used interchangeAbly. ~ecoA~ use ~e_e~Lion keys to identify the portions of informAtion that are to be displayed on specifically identified video screens. FIG. 3A shows a ,e~Lesentative enable ~ece~ion (ER) message line 22 in detail. An ER ~ynchronizing signal 32 is sent indicating the ensuing transmission of enable CA 022~76~7 1999-01-12 W093/23~8 PCT/US93/~ ~1 .e_e~Lion me~sages and e~-hl~nq AecoA~r8 to Dy..~G--ize to the transmi88ion. The ER sync signal 32 is followed by display identificAt$on code (DID) - ~L_e~L$on key (RK) sets 34, each of which includes At lea~t one of the unique DID
codes and at least one of the IID codes as a ~e_e~Lion key (RK) for which the video screen identified by the ~eco~Pr-receiver DID is authorized to displAy. In the example shown, the ~ets are the DID/RK pAirs TBD12??/MDC2000, BOBO1205/JSN416 and LRN0122/MDC2000 and $ndic~te that the video screen connected to the AecoA~r-receiver having the DID code TBD12?? is authorized to display update data for the source information corresponAing to RK MDC2000, screen DID BOBO1205, RK JSN416; and screen DID LRN0122, RK MDC2000.
It should be noted that in the example, the video screen for the decoder-receiver having DID TBD12?? is not authorized to display update data for the source information ~GLLe~Gl.ding to RKs JSN416 and MDC2000. The enable ~e_eyLion message cont1n~e~ for as many lines (each including an ER
synchronizing signal 32) and includes as mAny sets 34 as are required to associate each of the authorized video screens, by their decoA~r-receiver DIDs, with one of the (many) subscribed-to yLo~ or portions of source information by their information identification codes/RKs.
The ~L~e~s for updating each ou-~u~ display is performed by replacing ~tiles~ in the relevant ou~u~ display. As shown in FIG. 4, the cross-hatched tile 36 to be updated is located by two row and two column (or two x-y pixel pair) coordinates. FIGS. 3B - 3F show samples of the data enable sequences, in which, in FIG. 3B, the sequence for the update of information having the IID code MDC2000 is illustrated.
In particular, a data synchronizing signal 42 indicates the ensuing transmission of a data enable sequence, and is followed by the IID code 44 for the source of information having IID code MDC2000 and then the coordinates 46 of the tile 36 to be replaced which, in this example, is 4 rows by 40 columns. The actual data for this tile 36 is presented CA 022~76~7 1999-01-12 WO93~K~ PCT/US93/04361 in a ~eries of line~, ~o~ on~7 i ng to the number of rows in the tile to be updated, following the data enable ~equence line. Note that the correspQnAPnce is not one line to one tile row and is explained below. Similar example~ are shown S for the information having IID codes JSN416 and MDC2000 in FIGS. 3C and 3D, in which in the information having IID code JSN416, a tile of 1 row by 11 col~mns i~ updated, and again in MDC2000, a r~ ~ ~nA tile of 6 rows by 40 columns is updated. Alternatively, as ~hown in FIG. 3E, the update -data may AppeAr on the ~ame line as the data enable sequence. In particular, the sync signal 42' is followed by the IID code 44. However, the coordinates 46' include the pixel ~tart number and the pixel ~top number of a single row of the update data, along with the line number of the particular line. The update data 48 then follows on the ~ame line. Each tile 36 i~ then com~:-e~ of the update data 48 Appe~ing in, for example, a plurality of con-ec~tive lines. Further, as shown in FIG. 3F, the update data may be presented imultAn~:u~ly on one line for more than one page at a time. In particular, the ~ync ~ignal 42~ is followed by two IID codes 44~, and then the coordinates 46 of the tile 36 to be replaced, which in this example, is 5 rows by 80 columns, toward the bottom of the portions of information -h~ving IID codes JSN416 and MDC2000. Additionally, all authorized displays co~nected to the video transmi~sion may be ~imultaneously updated at the same coordinates by using a 6pecial ~e_Ep~ion key, e.g., RK - 0.
An encoder for the fir~t embodiment of the invention i8 ~hown in FIG. 5. The encoA~r includes a modem 50 for receiving data from a 60urce of market information. This dAta may be in the form of entire pages or ~e~G~dS of financial information where portions are updated, or the update datA itself along with information for the positioning of the update data on the respective display ~creen. The ou~yuL of modem 50 is co~nected to an interface 51, which is, in turn, connected to the input of a CA 022~76~7 1999-01-12 W093/23~ PCT/US93/~361 microcomputer 52. The microcomputer 52 reAssigns the data to a~op~iate locations in new ouLp~ displays for clients of the information vendor. A keyboard 53 is co~n~~ted to the microcomputer 52 for ~G..Llolling the microcomputer. A
memory 54 is connected to the microcomputer 52 and 6upplies thereto the configuration of the new ouL~uL displays, the reception key (RK) codes for each of the new portions of displ~y information, and the display identification (DID) codes of the client's video screens authorized to receive each of the new portions of information. Based on this information, the microcomputer 52 generates the first data : stream and the ~equence of ~econA data streams.
The ouL~uL of the microcomputer 52 is applied through an interface 55, to A digital video generation unit 56 which reconfigures the o~L~L of the microcomputer into digital video lines. The digital video generation unit 56 also generates the Pn~oAPA signal flag and inserts the v_rious synchronizing signals at the begi nn~ ng of each of the digital video lines. A clock signal generator 57 is co~nncted to the digital video generation unit 56 and the mi~ocomputer 52 for applying timing signals thereto at the line freguency. In the event th_t the update information applied to the modem 50 is in the form of entire pages or records, a memory 58 is connected to the microcomputer 52 into which the pages or records are entered enabling the microcomputer 52 to compare one page or ~eCG~d with the update of the page or record to extract therefrom only the update data.
FIG. 6 is a block diagram of a APcoA~r for use with the encoAPr of FIG. 5. The AecoAPr includes a receiver 60 for receiving the data transmitted by the digital video generation unit 56. The o~L~L of the receiver 60 is applied to an analog switch 61 for selective application to a video screen in the event that stAnA~rd non-coded signals are being received. A coded signal detector 62 is coupled to the receiver 60 for receiving the encoded signal flag and CA 022~76~7 1999-01-12 .
WOg3~KX PCT/US93/~ ~1 for switch~nq the analog ~witch 61 accordingly. An ER
detection gate 63 i6 co~nDcted to the receiver 60 for receiving the enable ~e~e~Lion messages contAin1nq the DID/RK code sets. Each of the received DID codes is comp_red with a unique display identific_tion code stored in a ROM 64 by a compar_tor 65. Upon e_ch match of the DID
code, the individual RK code for the respective portion of information is stored in a memory 66.
The ouL~uL of the receiver 60 is further ~-c,-~ Led to a data detection gate 67 for receiving the data enable -se~nrefi. The individual RK codes in the received data : enable sequences are compared in _ comparator 68 with the individual RK codes stored in the memory 66. Upon _ match of one of these RK codes, the _ccompanying display coordinates of the update data are loaded into registers 69.
An analog-to-digital converter 70 proce~fi the appropriate update data at the o~L~L of the receiver 60 and applies its ouL~uL to ~a write buffer 71, which also receives the ouL~L
of the registers 69. The ouL~uL of the write buffer 71 is applied to a picture ~tore memory 72 in which the section therein co.~e~l~n~ing to the location of the update data is updated by using the display coordinates. A synchronizing signal detector 73 is ~onnected to the o~L~L of the ~receiver 60 for separating the message synchronizing signals. The ouL~uL of the synchronizing signal detector 73 is Applied to _ timing _nd ~..L~ol signal generator 74 for generating timing signals for the analog-to-digit_l CGI.Ve~ Ler 70, the data detection gate 67, the ER detection gate 63 and the picture store 72. The GuL~- of the picture store 72 is applied to a digital-to-analog converter 75 ~G.,L~olled by the timing and ~GIlL~ol signal generator 74.
The ouL~uL of the digital-to-analog converter 75 is applied through a low-pass filter 76 to Another input of the analog ~witch 61.
In a se_G.,d embodiment of the invention, the video signals representing the market information includes color CA 022~76~7 1999-01-12 -WOg3~Y~ PCT/US93/~361 information. In addition, s~nA-rd television ~y,am inform_tion signals are included in the digital video signals for selective viewing of realtime television ~L ~y~ ~ms on the video screens- This transmis6ion ig nece6r-~ily syn~l~G,.ous to the chosen television stanA-rd.
When the digital video signAla are being transmitted by co~Yi~l cable, the usable b~ndwidth is in e~c_~r- of 24 MHz.
FIG. 7 shows a pictorial repreRentation of the transmitted video signal6. The ~ncoAeA signal flag line 80, the enable .e_ey~ion messages lines 81 and the data enable sequence lines 82 ~re transmitted during the vertical bl~n~ing interval 83 between each field of the video signal.
During the active video portion of the field, in a first half of each ~cAnning line, the television R, G and B
signals 84, each originally having a bandwidth of 4 NHz and each time compressed by a factor of six to an eYranAeA
bandwidth of 24 MHz, are sequentially transmitted. In the se~QnA half of each rcAnning line, the update dat_ for individual pages of the mArket information are transmitted.
While the television ~lGy.~m information signals 84 are in color, the update information may be monochromatic, color or a mixture of both. In particular, as shown, the firOst 8 half-lines contain the monochrome update data 85 for the left half and right h_lves, ~e_~e-~ively, CO~LeO~-O~1;ng to RK code MDC2000. The update date 85 is followed by the update data 86 corresronAing to RK code JSN416. The update data 86 i6 presented in color as the three color signals R, G and B. The remainder of the right half of the first field is shown as being unused in this example. The left half of the rscG,.d field contains the G, B and R components of the - television y~oy.am information signals 78'. The right half of the ~e-onA field contains the monochromatic update data -. corresponAing to RX codes 208, 1234, 5, 19154 and 264.
FIGS. 7A - 7C illustrate the tec~nique of transmitting and displaying more than one television p-Gy~am information signal at a time along with update data for ouLy ~ displays on a plurality of video 8~ r~. Specifically, FIG. 7A
illustrates the transmi~sion of four field~ of digital video ~ignAl~ ~G.,~_ponAing to two televi~ion video frames. A
vertical blAn~ing interval 83, CO~L~~rOn~;ng to the vertical bl ~n~i ng interval 83 of FIG. 7, is shown. Nine different 8Gu~r~ of information are shown a8 being transmitted in the fields, nAmely televi~ion ~6Y~ ~m information ~ignals TV1-TV3 and ~ix tiles numbered TILE 1 to TILE 6 having co~e_l,o,.ling update data to particular portions of financial market information. The tran~mission of a field ~tru~L~ed in this manner is done at the television rcAnning rate, as mentioned above.
The television program informAtion signals TVl-TV3 are shown AS being time compressed in a well known manner. The TV1 signals are shown a8 being transmitted during a portion of every horizontal digital video line. Television ~y-am information signals TV2 and TV3 are shown a8 being transmitted only during certain horizontal digital lines, namely from line W to line X, in the c~se of TV2, and from line Y to line Z, in the ca~e of TV3. The television program information signals TVl-TV3 are shown as pluralities of lines having alternating odd line (TV~D) and even line (TVrn~) fields in s~cce~6ive video fields. The television ~Gy~am information signals are illustrated in FIG. 7A in the RGB format, i.e., three primary color signals, but also may be transmitted AS one luminA~ce and two color difference signal~, e.g., Y,U,V. Further, the television ~y.~m information signals may be digitized and compressed, e.g., using the JPEG or MPEG ~tandards or some other ~e~h~ique.
Also, the update data to o~L~L display tiles TILE 1 -TILE 6 Are transmitted in various lines at times when the television ~Gylam information signals Are not being transmitted.
The update data for an ~L~uL display tile may Appe~r anywhere in the video ~creen and may start and stop at any point or in any line of the digital video field, provided CA 022~76~7 1999-01-12 W093/2~ CTtUS93/~ ~1 that the update data doe~ not occur simultaneously with the television ~GYLom information signals. Thus, update data may occur during the vertical blAnking interv~l 83 as shown in the third digital video signal field for update data to TILE 3. Update data also may be a lengthy stream of data that fills tho~e portions of s~cce~-ive lines that are not filled by television ~.oy~am information signal~ as illustrated in the fourth digital video signal field with ~e_~e_L to the update to TILE 2 and signals TVl and TV2.
Further, update data may be a relatively short stream of data starting at the beginnin~ of a line time, or in the :middle of a line time, see, e.g., updates to TILE 6 and TILE

2 and TILE 1 in the fourth field.
In addition, there may be no update data for financial market information as in the first digital video signal field cont~inin~ television ~G~.~m information signals TVlo~, TV2~~, TV3 ~ , although there will be some digital data (not shown in the first field) that is transmitted, as described below.
The resulting di~play~ that are po~sible with this transmission structure are illustrated in FIGS. 7B and 7C
and 13. FIG. 7B illustrates the display of the television .am information signals TV1 and which, due to the transmission of such signal~ during each digital video scan line, produce full 6creen television di~plays. FIG. 7C, on the other hand, illustrates the display of both TV2 and TV3 ~ignals which, by virtue of their transmission within the stated interval~, are displayed within specific vertical hol~n~Aries within the video screen. Specifically, the TV2 display must be located between horizontal lines W and X in -c any horizontal location (with the provi60 that it not interfere with ou~uL display data) and TV3 must be - displayed between horizontal lines Y and Z, in any horizontal location (with the same proviso). The GUL~L
display ~o~ on~in~ to one of the source information in tiles TILE 1 - TILE 6 that the particular video screen is , . . . .

CA 022~76~7 1999-01-12 W093/~ PCT/US93/04~1 enabled to receive can be displayed above, below or alongside the TV2 and TV3 signals (only TILE 1 - TILE 3 are illustrated).
Due to the complex ordering of the update data in the first and recon~ fields, the dAta en~ble se~nces in the lines 82 must neceE--rily be more complex than those shown in FIGS. 3B - 3F. In addition, the enable reception messages also must indicate which of the video screens is authorized to receive the television ~r~ m information signals sent with the update data. In particular, as shown in FIG. 8A, the enable .ece~Lion messages are similar to those 6hown in FIG. 3A, with the exception that in addition to the DID/RK code sets, the messages include a set 87 indicating which of the video screens, for example, the screen with DID code 297, is authorized to receive which television ~,Gy.am information signals, for example, the television ~.oy.am information signal having an IID code TVl, which also may be used as a ~ccEyLion key (RK) if distribution is to be enabled. FIG. 8B shows a sa~ple data enable sequence which includes, in addition to that described with respect to FIGS. 3B - 3F, the coordinates of the update data in the source field. FIG. 8C shows a sample of the data enable sequence for identifying the television ~program information signal~, and includes a data synchronizing signal 88, a television RK code 89 and the starting coordinates 90 of the color signals, red, green and blue, or Y,U,V.
FIG. 9 shows a block diagram of an encoder for the second embodiment. The digital video generation unit 56' has a ~con~ set of inputs for receiving the three components of the color television ~.oy~m information signal, Y,CD~,CD2.
In particular, a source of television program information signal is connected to a synchronizing signal separation circuit 91 for detecting the vertical and horizontal synchronizing signals in the video signals. The source of the video ~ignals is also connected to a matrix circuit 92 , . . . . . . .

CA 022~76~7 1999-01-12 W093/~X~ PCT/US93/04361 for providing the three components. Each of the~e com~o..e"Ls i8 subjected to compre~sion in compression circuit 93 and the three components are then applied to the digital video generation unit 56~. The clock and ~ync ~ignal generator 57' applies synchronizing signals to both the digital video gener_tion unit 56' ~nd the microcomputer 52', and receives the synchronizing si~nalc from the separation circuit 91 for synchronization therewith.
FIG. 10 shows a block diagram of a A~coAPr for the ~Pcon~
embodiment. Components the same as those in FIG. 6 are designated with the ~ame reference number. The decoder is substantially cimilar as the ~ecoA~r of the first embodiment with the exception that the decoAPr i8 now capable of ~o~essing color ~ignals and the encoA~d data selectively includes televi~ion ~oy~am information 6ignals. In particular, a color decoder 101 is included between the output of the receiver 60 and the input of the analog ~witch 61.1 - 61.3. The register 69~ include~ a register element for storing the number of the picture Ftore. The synchronizing ~ignal detector 73' o~ Ls field synchronizing ~ignals in ~ddition to line 6ynchronizing signals. The write buffer 71 now ~Ccecr~~ three picture stores 72.1 - 72.3 cGLLLOlo..~ing to the three color components, red, blue and green. The ou~u~s of these picture stores 72.1 - 72.3 are applied to three digital-to-analog converters 75.1 - 75.3, and then to three low pass filtere 76.1 - 76.3 for application to the other inputs of the three analog ~witches 61.1 - 61.3.
Referring to FIGS. 11 to 29, a third embodiment of the present invention is ~hown, which reflects a number of im~G~ements to the first and r~ ~on~ embodiments described above. One system in accordance with the third embodiment includes an enco~r 312, a digital-video (D~) bus 314, a plurality of deco~r~ 316, a plurality of video ~creens 317, a conL.ol bus 318, a keyboard 319, optionally a mouse 319', and a CUpply (or ~ource) of display inform~tion 310 which CA 022~76~7 1999-01-12 , WOg3~ ~ PCT/US93/04361 may include realtime televi6ion p~6yL~m information signal~, _nd analog and digital video 6ignals ~y~e~enting f~nAnc~Al m_rket information. The DV bu6 314 i8 prefer_bly a ~Annel capable of transmitting digital and video information. This permits the use of stAnA~rd COAy~ A 1 cables or video switches as the DV bus 314.
As illu6trated in FIG. 11, each APcoA~r 316 has an A~ociAted video 6creen 317, prefer~bly constructed as _n integral unit in a common enclosure. Alternately, as shown in FIG. 26, each A~coAer 316 may be p_rt of a desk interface -unit (DIU) 321, which ~y~Gl Ls a plurality of video screens 317, e.g., four, And A plurality of user~ and their respective keyboards 319 and mice 319'. Each user may have one or more video screens 317 arrAnged in a work space, e.g., on a desk top 320. Each video 6creen may have a unique DID. Alternately, each user or desk top 320 may have a unique DID such that restricted display information may be displayed on _ny video ~creen of the enabled user or desktop.
One aspect of the present invention concerns improvements in the structure of the signals (also referred to as ~DV bus signals~ which are concatenated to form ~DV bus messages~) and their messaging along the DV bus 314 between the encoder 312 and the plurality of decoders 316, and their display on a video screen 317.
FIG. 12 illustrates the image produced on each video screen 317, which is a composite page 200 of finA~c~l market information and/or television pLGy~m information signals, as described below. Each composite page is organized as a plurality of cells 210. Each cell is organized as a plurality of pixels 220. Every cell 210 has an assigned location within composite page 200, by row R and column C, relative to an origin and cannot be arbitrarily placed. The origin may be 6elected to be in the upper left corner or elsewhere. Similarly, every pixel 220 has an assigned location within each cell 210, by row r and column CA 022~76~7 1999-01-12 W093/23~ PCT/US93/0436l c, relative to a cell origin and c_nnot be _rbitrarily placed. In accord_nce with the ~r~-ent invention, and as explained below, messages transmitted along DV bus 314 are either directly or indirectly add~'f--e~ to cells.
In a preferred embodiment, each composite page 200 is com,~ of 30 rows and 100 columns of uniform and fixed-size rectangular cells 210, as ~hown in part in FIG. 12.
The coordinates of the cell 210 in the upper left corner of the page 200 are (RO,C0). The cell 210 in the lower right ~GL__~r of the page 200 is at (R29,C99). Each fixed-size cell 210 has 128 pixels 220 organized into 8 columns by 16 rows. This represents a display screen 317 that is larger than the size of st~n~rd pages or records of f;~nci A
market information provided by commercial information vendors, and the size video screens provided by those vendors with their systems. Such ~t~n~rd pages and display screens have 18 or 25 rows by 80 columns or 12 rows by 64 columns. Advantageously, the larger display screen permits the user to create composite pages 200 cont~1n~ng more financial market information than previously possible with the prior systems, and further permits displaying television ~loy~am information signals and/or value added information without sacrificing the financial market information.
Each pixel 220 within a cell 210 may have up to 256 different colors, selected from a larger palette of 16,777,216 colors. The number of colors that may be displayed on any given video screen 317 Aep~nA~ on the amount of memory of the Aeco~Pr 316 operatively cQ~nected to the video screen. For example, if a Aeco~r has been loaded with one byte per pixel of screen store memory, or ~, approximately (800x480 ~ 384,000 pixels) 376 Kbytes of memory, it can display 256 colors per pixel. For another example, if a AecoAer, which has lower cost and functionality, has been loaded with only two bits per pixel of screen store memory, or approximately 96 Rbytes of memory, it can only display 4 colors per pixel.

. . . . . . . .

CA 022~76~7 1999-01-12 WOg3~ ~ PCT/US93/~361 ~ cin~ the number of colors to be ~ignaled also reAl~c~
the length of the messages needed to create or ~paint~ a composite page 200. For example, when four colors are being used, only the fir~t two significant bit6 of a color byte need be transmitted. Even when 256-color ~ecoAers are used, clever 6election of the color definitions can reduce the amount of messages ,~c_es6~ry to transmit information ronc~rning a ~mall tile on the page. For example, a first tile may have color~ 0, 1, 2, and 3 while a F e ~nA tile may '~have colors 16, 17, 18, and 19. Changing the colors in the '-econA tile only requires the transmission of two bits of information per pixel.
In this third embodiment also, DV bus messages are transmitted as tiles. As already noted, a tile is a rectangular region that will appear on the video ccreen 317 and is illustrated here by the bold black rectangle 250 on the right side of composite page 200 in FIG. 12. lt may contain any number of horizontally and vertically contiguous cells 210. Preferably, each tile is defined by the location of its first cell, i.e., the coordinates (row ~ and column C), in its upper left corner and either its size (i.e., number of rows and columns of cells in the tile) or the coordinates of the cell in its lower right corner.
This third embodiment of the invention preferably employs two concepts of tile messaging to reduce further the amount of overall data that is required to be transmitted. The first ronc~pt is called cell wrapping. This provides for FenAing one large single continuous message to a tile for one cell 210 after another (either horizontally or vertically aligned) within a tile having determined bo~nA~ries 80 that the first cell to cross the tile ho~ Ary in the direction of continuity automatically ~wraps back~
within the tile to the beginning of the next row or column so that each cell is successively filled. The tile ~o~nA~ries are preferably incG,~G~ted into the tile display boundary coordinates provided to the decoder for the update _, . . . .

CA 022~76~7 1999-01-12 W093~23~ PCT/US93/04361 data. This avoids having to monitor when the next cell 210 will be outside of a houn~ry of the tile and ~C~en~ either a new message or next row or next column indicator. The decision to u~e horizontally aligned mes6ages or vertically aligned messages may be based on the aspect ratio of the tile ho~lnAary so as to minimize the number of wrapping events and maximize painting speed. When combined with run length ~nco~ing of messages, described below, cell wrapping greatly improves messaging efficiency.
The r~con~ concept is the use of implied motion where portions of fin~nciAl market information contain regions -that must be moved, either vertically (scrolled) or horizontally (panned). For example, cG..ve.,~ional financial instrument tickers are usually panne~ horizontally acro~ a video ~creen, while news headlines are sometimes scrolled vertically. Thi~ movement can be aCcompli~h~ by either retransmitting all of the required information such that the relative location of each column (pAn~ng) or row (scrolling) is ad~usted for each incremental move, or in accordance with a preferred embodiment, by transmitting only the new information and 'implying~ the desired motion by the prior definition of a p~n~i~g or scrolling tile type.
Implied motion within a tile greatly im~Lo~es the messaging efficiency.
Referring to FIGS. 12, and 13, the video screen 317 may be referred to as the underlying tile 350. One top of the underlying tile 350, one or more of the following types of tiles, referred to as tile 250 with a letter suffix, can be displayed as illustrated in FIG. 13.
A graphic tile 250-G may be defined to display -- information on a pixel by pixel basis. It is used to display graphs, charts, Fr~n~e~ images, e.g., still - pi~L~es, value-added presentations of historical data, and similar non-alphanumeric character display information.
An alphamosaic tile 250-A is a tile entirely defined by an extended set of ASCII characters or the equivalent (i.e., ~ CA 022~76~7 1999-01-12 WOg3~2~ PCT/US93/04361 alphanumeric character6). It ic u~ed to display normal Alp~n~meric character text plus any predefined exten~e~
ASCII characters. Each pixel u~ually may have up to 256 colors. In FIG. 13, the alphamosaic tile 250-A is illustrated a~ displaying information ~-o- ~Ining U.S.
Government securities that are periodically updated.
Alrhanl~meric tile~ 250-A are static unle~s they are further defined for relative movement.
A rAnn~ng tile 250-P i~ an alphamosaic tile that ic -~6~.L~olled to create horizontal motion, left or right. In -FIG. 13, p~nn~ ng tile 250-P i~ illustrated as the (NYSE) Ticker which is being pAnneA right to left. The character ctring update ~NYSE~ has been received at the entry (partial ~S~ character) and is being automatically panned (partial ~E~ character) under the co-,L.ol of decoder 316 using implied movement. The pAn~ng effect may be a cell by a cell advance or a pixel by pixel advance, the latter providing a ~moother image transition and ~ entation of partial characterc.
A ~crolling tile 250-S is an alphamosaic tile that is controlled to create vertical motion, up or down. In FIG.
13, the scrolling tile 250-S is illustrated as the ~Financial News~ and is being scrolled upwardly. The entire lower row of characters has been received at the entry and ic being automatically scrolled (partial top and bottom rows) under the cGnL.ol of ~e~o~r 316 using implied motion.
The scrolling may be a cell by cell advance or pixel by pixel advance, the latter providing a smoother image transition and presentation of partial characters.
A video tile 250-V is used to display A realtime television ~Gy~m information signal. Each pixel within the video tile may take on any color ~ o~Led by the relative television transmission stAnAArd and the picture store memory size of the given decoder 316. ln ~n emho~iment wherein the ~eco~r 316 includes a picture store memory, different TV signals may be ~elected for di~play CA 022~76~7 1999-01-12 WOg3/23~ PCT/US93/04~1 within a video tile 250-V 80 long as they are being transmitted within the ~ame vertical format. If, hswe~er, a picture frame memory i~ u~ed, which can etore an entire frame of television yroyLam information signals, then the video tile 250-V need not be limited to the ~ me vertical format and may be located anywhere on underlying tile 350.
The size and di~play location of each tile 250 on underlying tile 350 i~ preferably initially es~ahl~rh~
using a tile default size ~nd position. Each tile 250 may be locally resized and repositioned by each user. Thus, for example, by using a mouse 319 or keyboard 319', each user : may redefine any tile 250 by (1) overlaying any one tile over any other tile and overwriting the di~play information of the other tile(~), (2) changing the fo~ey,o~.d/background attributes among the displayed tiles, (3) moving a tile to any new display location on the video screen (except for real time television video tiles 250-V, which may only be moved horizontally in the absence of a picture frame memory), and (4) changing its ~ize either to di~play more or less display information or to di~play the same information in larger or maller size.
In accordance with the third embodiment of the present invention, tile messaging embodies the following five principles:
1. Each tile 250 is uniquely named, i.e., it has a unique IID code that is used as a reception key, and is assigned system default display location and ~ize, typically as an offcet referenced to the origin cell (e.g., (RO,C0)) on the underlying tile 350 or to the origin cell of a tile 250 within the underlying tile 350. Thus, a tile 250 may be - nested within other tiles 250 on an underlying tile 350, such that relative offset of each tile in the chain to its antere~nt associated tile is respected and maintained by the APc~r.
2. Tiles 250 may be locally resized and repositioned from their system default conditions locations by individual .. , . . , . , , . . , _ CA 022~76~7 1999-01-12 WOg3~K~ PCT/US93/04361 users and may be given an offset ref~ to an origin cell on the underlying tile, or to an origin cell of any other tile. The remapping of the tile default location and size to the user-defined tile location and size o~u~ in each user'~ AecoAP~. DV bus message~ to update the u~er-defined tile are transmitted with the default display coordinates (unless the symbolic si~nAl~ng terhn1que de~cribed below ie used) and the default tile mes~age is mapped onto the user-defined tile within the picture store -memory of the ~ecoAPr. If ap~lo~liate, the user's -definition of the tile will provide display coordin_tes for eelecting a~ G~l iate cells selected by the user and disregarding other cells in the DV bus message of the default tile, so that only the di~play information in the user defined tile is stored and displayed. Thus, the user~s redefinition of the tile has no effect on the DV bus messages and only the user selected information is displayed and updated.

3. It is often more efficient to retransmit the whole tile using cell wrapping rather than transmitting just the updates. This is because computational efficiency is obt~in~ by filling in time lengths of DV bus 6ignals with useful data rather than blanks. This i~ not usually true for retransmitting the whole page of financial market information.

4. Related page or record update~ often occur in bursts and are usually received from the information vendor one row of financial market information immediately after the other.
It is far more efficient to store all of these received multiple contiguous-column row updates to a tile within a portion of financial market information for a very small time (perhaps 1/20th of a second) before transmitting them as a single group within a 6ingle tile on the DV Bus 314 to all of the deco~ 316. This technique avoids retransmitting the same tile each time one row of the tile i8 updated, and retransmitting each update data, but not the CA 022~76~7 1999-01-12 W093/239~ PCS/US93/04361 complete tile, with the a~,v~iate hPaAPr ~nd offset display coordinates, e.g., starting and PnAing row and column to di~play the update in the relevant di~play location of the video screen. Similarly, with ref t~ e~e to FIGS. 13A-13C where two users have defined tiles that include some common portions of the same page or ~e'O~d of financial market information, e.g., tile SA and tile SB, the update data for the underlying page or ~ecGLd of financial market information may be transmitted in one of three format~. The first format is to create two separate tiles SA and SB and transmit update data for those tiles as - nPc~ss~ry with a duplication of me~sage~. The r~conA and more useful ter~n~que is to decompose the overlapping tiles SA and SB into three tiles SAl which i~ unique to user A, SBl which is unigue to user B, and SAB which is common to users A and B. Then updates for the three tiles are separately provided as a~L~iate. A third tech~ique is to create a ~DU~e~ ~ile~ S which includes all of the financi~l market information. In this latter embodiment, user A i~
enabled to receive supêrtile S with display coordinate information for retrieving only those portions of information selected by user A, and user B is similarly enabled to receive supertile S with display coordinate information for retrieving only those portions selected by user B. Thus, the update message i8 only sent once, yielding im~ved DV bus messaging efficiency.

5. Both contiguous-column row messaging and contiguous-row column messaging should be Du~pGL~ed within tile messaging for efficient updating of tiles.
The application of tile messaging greatly reAl~ceC the amount of message traffic on the DV bus 314. One example is explained with reference to FIGS. 14A and 14B, which -. respectively illustrate composite page 200a having tiles Tl, T2, T3 and T, and composite page 200b having tiles Tl, Ts, T3 and T,~, ~uch that tiles T, and T,' are different user-.

CA 022~76~7 1999-01-12 .

WO93~K~* PCT/US93/04361 defined tile~ based on the sAme original portion of fi nanC; Al market inform_tion T~*.
Fir~t, it is noted th_t in prior art system , all vendors of video f;nAnciAl market information typically use contiguous-column row oriented mes~aging; all ~creen changes are sign_led by multiple individual mess_ges, each message concerning only contiguously loc_ted columns in one row of the page or record. A stAn~rd page from one commercial vendor may be tho~ght of a~ one large st_tic alphamo6aic tile 250-A th_t is 80 columns wide and 18 rows high. When the page is tr_nsmitted to the client site for the first time in response to a page reguest by a user, it may be sent using eighteen messages, one for each displ_y row. E_ch message will include a heA~r identifying the p_ge or record number of the source fin~nc~Al m_rket information, the row number, and the starting column number of the following message, and up to 80 columns of character data. Each message CO~e~yGl~ ls to a single row and is about 100 characters (one byte per character) in length. Thus, for an 18 row display, the total page reguires 1800 characters to be transmitted over the telephone line. At 180 characters per ~econ~, it takes about ten ~ecQnd~ to ~paint~ the screen for the first time.
When an information change o~ ., the information vendor updates the page by ~rn~ing only the new information. When one character changes, for example, a single message is sent having ~o"~.ol information (in brackets) and the new data as follows:
[{PAGE NO}{ROW}{STARTING COTU~N}] DATA
[{P16251}{R0}{C13}~1.
Thus, most update messages only represent one or two new data characters to be displayed on the video screen to be displayed on the video screen accompanied by about ten information ~G.,L,ol ~characters~ for placing the data characterc in the ~, G~e~ display locations. Further, when one fundamental data element changes it often causes a CA 022~76~7 1999-01-12 WOg3~ PCT/US93/04361 flurry of very small ind$vidual m~-r- e~ to update other rows or column~.
With the foregoing in mind, and referring to FIGS. 14A
and 14B, if the original portion T,* is defined as an alphamosaic tile 250-A, then, without tile me~saging and according to the prior art, receiving a new headline would reguire transmitting a total of nineteen messages (about 1900 characters); ~even messages to composite page 200a and twelve messages to compo~ite page 200b. Seven of the messages transmitted to composite page 200B would be identical to those transmitted to composite 200a except that - the row display location would be different to reflect the fact that the hD~ e information is displayed higher on composite p~ge 200b th~n on composite page 200a.
~eve., with tile messaging, receiving a new headline would require transmitting a total of one message (under one I hol--~n~ characters). Both composite pages 200a and 200b would receive the ~ame tile me~r~g~, e.g., T~', and use cell wrapping and the user-defined tile location off~ets and display coordinates to display ~ e~ly the information on the respective composite pages 200a and 200b.
If the original portion T~ was defined as a scrolling alphamosaic tile 250-S, then using tile messaging would have resulted in both composite pages 200a and 200b being ~Lo~c.ly led~wn by only one DV bus message of less than one h~.-d~cd characters. This ~e~,~~e~ts a nineteen times reduction in DV bus message traffic for this simple case.
The im~.ovement is even more prono~nce~ when more tiles and composite pages are involved.
The third embodiment of the invention preferably employs tile messaging of update data using a symbolic si~n~ g ter~nique, which will now be described with refe~e..~e to -- FIGS. llA, llB, llC, llD, 12A, 12B, and 12C. FIG. llA
illustrates a transmission terhn~ue similar to that ~i~c~ above with reference to FIGS. 3A - 3E. However, for the ~ of clarity, no synchronization signals are CA 022~76~7 1999-01-12 WOg3~W~8 PCT/US93/04361 shown, and only a single row and single column tran~mis~ion are ~hown. The tile row and column starting and enA ~ ng locations will be transmitted in the manner described e~ l.ere.
FIGS. llA-llC and 12A-12C illustrates message types for alternative techn~ques of customizing and di~playing composite pages 200 of display information and updating the display information for partiCl~lAr user6. With e~e:1fic refe~e~.~e to a FIG. llA, one techn~que u~es an enable ~e~Lion message 100 and data enable ce~lenc~e 102, 103 and 104 at time tl and data enable se~l~nceC 112, 113 and 114 at : time t2. The enable ,e~e~ion message 100 is shown as being comprised of display identification (DID) code 120 -reception key (RX) code 106 pair~, in this case, three code pair~ DID1/RKl, DID2/RK2 and DID3/RR3. The le~ ion key 106 is used to authorize the APcoAer to retrieve update data for a portion of financial market information having an IID
code that is the same as the ~e_ap~ion key. Thus, a AecoAer video screen 317 having the DID 120 of IDl is authorized to receive information for ~ece~ion key 106a RR1, the decoder video screen 317b with DID 120b of ID2 is authorized to display financial market information for reception key 106b of RK2, and so on. It ~hould be understood that, althol~gh t_e RK's 106 and DID'~ 120 are illustrated as Alrh~numeric characters RKn and IDn (n being an integer) in practice it i~ preferred that they be multibit, e.g., 21 or 24 bits, code words that e,.~.y~ the actual source of financial market information. This is so that an unauthorized user cannot identify and retrieve a certain financial market information by tapping into the DV bus.
Following the enable le~c~Lion message 100, at time t three separate data enable ~e~l~nces 102-104 are illustrated, each of which is comprised of a reception key 106, row and column display location information 108, followed by data 110. Although the data 110 is shown as directly following the reception key 106 and row and column CA 022~76~7 1999-01-12 W093/23~ PCT/US93/~361 information 108, it can be transmitted on a separate line, immediately following the data enabling ~equence.
For the purposeC of this example, the information displayed on the respective portionC of financial market S information having IID code6 RKl-RK3 can be different, but each contains at lea6t one common information field of data 110, which is represented by ~DATAl~ relating to a 30-year U.S. Treasury bond. By transmitting the information field data 110 with the foregoing data enable ~e~nces 102, 103 and 104 for the three reception keys 106, namely RKs 106a-106b of RKl-RK3, the three different video screens 317a, 317b and 317c, having cG~e~o~ g DIDs 120a-120c of DIDl-DID3, can display the ~ame information field 110 in different locations as illustrated by boxes llla, lllb and lllc in FIGS. 12A-12C ~e~e~ively, using dicplay coordinAtes 108a-108c.
For example, the data enable ~equence 102 places the data 110 in the upper left hand corner ~ey~ nted by di~play coordinates 108a (ROWl,CO~l) of video screen 317a (box llla) having the DID 12Oa of DIDl, which was enabled with reception key 106a of RKl. In a similar manner, ~eguence 103 places the information field 110 near the center of video screen 317b (box lllb) having the DID 120b DID2, represented by the display coordinates 108b (ROW10,COL40), which was enabled with ~L_e~ion key 120b of RX2. Sequence 104 places the information field data 110 toward the lower right hand corner of video screen 317c (box lllc) having the DID 120c of DID3, ~e~Le~ented by the display coordinates 108c (ROW3,COL3) which was enabled with the reception key 106c of RK3.
Thus, the information field data 110 is transmitted by three separate tile messages 102, 103 and 104 at a time t1 - such that each tile has a different offset relative to the upper left corner of the underlying tile 350. In order to customize the information displayed on various displays, separate tiles must be transmitted to each video display CA 022~76~7 1999-01-12 W093~L~ PCT/US93/04361 317. When it is nece---ry to update the f~n~nGi~l market information for information field data 110 during time interval t2, again three tile~, e.g., illustrated as data enable seq~r e- 112-114, mugt be transmitted, each having the a~. G~ iate ~e-~e~ion key 106, row and column 108, and the new financial market information for inform~tion field data 110, e.g., DATA2, as shown in FIG. llA.
The application of 6ymbolic ~i~n~l1ng is based on the realization that the traders of f~n~nGi~l instruments prefer to select the finAnc-iAl market information they use to formulate their trades, and that some of that financial - market information will be the ~ame as that used by other traders, and some information will be different. It also is based on the realization that the traders do not nececs~rily lS want to view all of the information provided by a commercial information vendor and prefer to customize their video screens to satisfy their desires.
Accordingly, the customization of the information displayed on multiple AecoAPr video screens is greatly facilitated, and at the same time, the overhead required to update information commonly used is greatly reA~ceA, according to the present invention, in the following manners. Referring to FIG. llB, one aspect of the present ~ invention provides for using enable ~e_c~Lion and ~initialization messages 116-118 and data enable seq~Pncec 128 at time tl and 134 at time t2. Each enable reception and initialization message 116-118 respectively includes a DID code 120 for a video screen, an IID code which, in this instance, is used as a r~con~ry reception key tSRR) 122, in this case ~LONGBOND~, and display coordinate information 108, e.g., row R and column C. The display coordinate information 108 row R and column C will place the data 110 associated with the recon~-ry ~E_e~ion key 122 in the designated display location only for the video screen identified in the DID/SRX set. The term ~reconAAry reception key~ is a reception key that is associated with .
W093~23~ PCT/US93/~361 another reception key such that a A~cQAPr must be enabled with the other first or primary reception key before it can be enabled by a reconA-ry reception key. The other .ece~Lion key al60 may be a ~econAAry ~e_epLion key as~ociated with yet another first or primary reception key as expl~ine~ below.
Thus, each enable ~e-e~ion and initiAli7ation message both en_bles a video screen to receive and display certain data and ini~i A li7es the rel_tive display location of th_t data on that video screen, even though no data hAs been sent. Importantly, thi~ permits each u~er to select the display location on the user'~ video ~creen to display the data ~G.~e~o"linq to the F~: a~A~ry .e~e~Lion key SRK
inAependently of the other users so that only the particul_r Fe~on~Ary .e~e~Lion key and the cu.. e_~o.. l;nq data need be ~ent to effect the co~e_L display. Again, the use of LONGBOND as an IID code and an SRK is for illustrative ~L~oses and in prActice an encrypted multibit bit code word would be used as the SRK.
Thus, using en_ble reception and initialization messages 116-118, video screen 317a hAving the DID 120a of DID1 is enabled in this example, e.g., at the beg;~n;nq of the day, with SRK 122 LONGBOND and will display the subsequently transmitted d_ta 110 information starting at display coordinates 108a (ROWl,COL1). Similarly, video screen 317b having the DID 120b of DID2 is enabled with the SRX 122 LONGBOND and to receive and display the data 110 information at its ~elected display coordinates 108b (ROW10,COL10).
Video screen 317c having the DID 120c of DID3 will likewise place the data 110 information at its selected display coordinates 108c (ROW20,COL60). Then, at time t, a single tile data message 128 is transmitted comprising the SRK 122 ~N~RON~ and the financial market information data 110, shown as DATA1. Upon receiving the tile data message 128, ~co~Pr video screen 317a will ~CG~ ; ze the SRK 122 LONGBOND as matching its previously enabled SRK 122 and . .

CA 022~76~7 1999-01-12 WOg3~3 ~ PCT/US93/~ ~1 place the data 110 DATA1 in the designated location according to the previously init~ 7ed display coordinates 108a, i.e., the upper left hand corner (ROWl,COL1) box llla as shown in FIG. 12A; video screen 317b will likewise display the data 110 DATAl of message 128 in its center (ROW10,COL40) box lllb, and video 6creen 317c will similArly display the data 110 DATAl of message 128 in its lower right hand corner (ROW20,COL60) box lllc. When it is n~ces~ry to update the financial market information at time t2, a single tile data message 134, is transmitted, comprising the SRR
122 LONGBOND and the data 110 DATA2 to update the video :screen. This data 110 is then displayed in the proper location of each video screen 317, in the 6ame manner, to update the display.
Referring now to FIG. llC, another aspect of the invention ronc~rns using three types of messages to display and update information, enable ~e~e~ion messages 100, initialization messages 136, 137 and 13~, and data enable sequences 128 and 134. The enable ~e_epLion messages 100 are used in the same manner and for the same ~U~05~ as described above in ~onnection with FIG. llA. Then, once a decoder is enabled with a reception key 106, the enabled decoder is initialized with a -?con~ry reception key SRK
122 for that enabled .e_a~ion key 106, and display coordinates 108 for displaying the subsequently transmitted data 110 in the selected display location 111 on a video screen 317. Thus, each initialization message 136, 137 and 138 includes a first IID code cGL.e~L,o..l;nq to a previously received Lece~ion key 106, a F~on~ IID code which is used as a -?con~Ary reception key (SRK) 122 (in this case LONGBOND), and display coordinate information 108, e.g., row and column or off~et f~nAnci~l market information, which may be unique for each video screen 317. Then, at times t1 and t2, the data messages 128 and 132 described above in 3s cQnnection with FIG. llB are transmitted, having the SRK
codes 122 LONGBOND, which will be received by the enabled , CA 022~76~7 1999-01-12 -W093~239~ PCT/US93/04361 and init~Al i 7eA ~COA~rg, and the data 110 for di6play at the indicated display location6 llla, lllb and lllc on the respective video ~creens 317a, 317b and 317c.
The init;Ali7ing me~sages 136, 137 and 138 are not enabling reception m~--~g~ 100. Thu~, if the AecoAPr i6 not fir6t enabled with the reception key 106 by an enable e-e~ion message 100, it will not retrieve the -~conA~ry reception key 122 by an initiAli~Ation message and will not retrieve the data 110 from a data enable sequence of the type 128 and 134 data message.
A comparison of the information that must be transmitted uging the 6cheme of FIG. llA, at time t2, with that of FIGS.
llB or llC at time t2 readily demG..~L.~tes the reduction in message transmis~ion overhead prod~ceA using either symbolic 6ignaling 6cheme in accordance with this form of the present invention. Al60, the techniques illustrated in FIGS. llB
and llC e~h~nce the flexibility for producing user-customized di6plays in accordance with particular client reque6ts while reducing the volume of data enable 6e~nreC
to display and update financial market information.
In this regard, the user who is enabled with a L~ ion key may select locally a new location for a tile of financial market information 6elected from the enabled finAnciAl market inform~tion. To do so, the user would select the tile using the keyboard 319 or a mouse 319', and define an offset of the 6elected information by moving the tile to its new display location on the video 6creen, relative to either the origin of the underlying source portion of the financial market information or to the origin of the default tile location. Thi6 new tile position -. information is communicated over co~-LLol bu6 318 to host CPU
425 (see FIG. 11) which may generate a new initiAli7~tion . message with the SRK for the tile (i.e., an information identification code) and new display coordinates.
Thereafter, any update data for that tile will be mapped from the position of the update data relative to the default CA 022~76~7 1999-01-12 W093/2~* PCT/US93/04361 origin onto the u~er-defined tile and di6played (to the extent the update data G~ in the user-defined tile).
The user may relocate the tile to a different position on the display screen. This change also will be either followed by an ini~ 7Ation mes6age so that any update data f~ ng within the first defined tile is mapped into the new display location, which remains the same with ~e_~e~L to the display location relative to the original page or is remembered so that any update data falling within the first defined tile is mapped into the new display location by the ~coA~r, e.g., by adjusting the display : coordinates as the update data are stored.
The use of ~?conAAry reception key6 provides a convenient technique to minimize message overlo~d. Moving a tile defined by an en~bled FeConAAry .e_c~Lion key and initial (or default) display coordinates, has the effect of changing the display coordinates so that the data ~OL ~ e~Ol~'1 i ng to the secQn~ry reception key will be mapped into the tile in its new location. Thus, the user may easily customize the provided datA for commonly used data by using ~e: DnA~ry reception keys and initializing the display coordinated for the financial market information.
Referring now to FIG. llD, an embodiment of a AecoA~r 316 employing symbolic s~gn~1~n~ operates in the following manner. The following definitions are used. DID is a unique decoder identification code; DIDR is a DID code in a message received by a given APcoAer; DIDo i~ the unique DID
code stored in a given decoder; RK is a reception key; RX~
is the first ,e~e~ion key in a message received by a A~coAer; RR~ i a ~Lce~ion key in a message received by ~
decoA~r that was not previously stored in the ADcoAer; RKo ie a reception key that was previously stored in the AecoA~r; Rt is a ~tart row number; Ct is a start column number; and D is a string of data to be displayed.

W093t23~ PCTtUS93/~361 There are at least seven types of me66ages, wherein the bracket6 contain the identified field6 of the me66age as follow6:
~nable Reoo~L~on Messaaes tDID, RX~]
tDID, R~, R#, C#]
Tn~ al~zation Messa~es tRKo~ ~#, C~]
tRKo, RK~]
tRKo~ RX~, R#, C#]
Data Fnable Se~uence : [RKo, D]
~RRo, R~, C#, D]
The enable reception mes6age that associates a DID and an RR~ provides the APcoA~r having a DIDo match1ng the DIDR code in the message with a new L eoeyLion key RK~, which i6 stored and thus becomes an RXo as to subsequent messages. The ~ecoAPr may store one or more RKos at any given time.
The enable ~e_ey~ion message that associates a DID, an RKN
and an R# and C# provides the ~coA~r having a DIDo matc~ing the DID~ in the message with a new reception key RKN and display coordinate information (R~, C~) for that RX~. The display coordinates are relative to the video screen origin (on the underlying tile). The ~ecoAer can store many different RX~s and their COLL~ ing display coordinates intenAeA for display on any particular video screen. Each enable ~e~cyLion message will be ignored by any APcoA~r not having a DIDo match~ng the DIDR in the received message.
The initialization message that associates an RKo and display coordinate information R~ and C# will provide the new display coordinate information for the already stored reception key RKo for each ~coA~r that was previously ; enabled with that ~e_cyLion key RXo~ The displ~y coordinate information defines the offset of RKo relative to the video screen origin (on the underlying tile).

CA 022~76~7 1999-01-12 W093K~8 PCT/US93/04361 The initiAl17Ation mes6age that a~,~oc-~Ates _n RKo and _n RK~ will enable each APco~Pr that wa6 previou~ly enabled with RKo with an additional new reception keY RK~ in the received me~sage for the ~ame portion of di6play information.
The initialization message that as~ociAtes an RKo, RKN and R~ and C~ enables each Aeco~Pr previously enabled with reception key RKo with an additional new ~e~c~ion key RKN
and display coordinate information (R~, C~). The display coordinate information defines _n off~et for the reception key RX~ relative to the video screen origin (on the underlying tile).
Each initialization message will be ignored by a AecoADr ~ that was not previously enabled with the reception key (RK~) that matchec the ~e~e~ion key RKR in the received message.
The data enable sequence that associate_ an RKo and dat~ D
is provided to each ~co~Pr and the data is retrieved by each ~eco~Pr that was previously enabled with the identified RKo and is ignored by the other ~coADr6. If no display coordinate information R~, C~ has been ~tored in the decoder for the identified reception key RKo in the received message, then the ~eco~Pr will store and display the data D
without an offset relative to the 6tored origin of the tile correspon~ing to RKo; when there is associated di~play coordinate information stored it will be u6ed.
The data enable ~equence that a~60ciates an RKo, data D to be updated and display coordinate information R~, C~ is provided to each ~Pco~er and is retrieved by each ~PcoAPr that was previously enabled with the identified RKo and i6 ignored by the other ~eco~Pr6. The data D i8 stored and di~played using the provided display offset information (R~, C~). Thus, the data ic displayed at a location offset by R#
and C~ relative to either the video 6creen origin (if no previous RKo offset was stored in the decoder) or the data is displayed offset by R~ and C~ relative to the previously stored offset of RX~ .
-CA 022~76~7 1999-01-12 W093/239~ PCT/~S93~04361 Referring ~till to FIG. llD, a flow chart for symbolic ~iqn~l~ng, from the ~eLD~e_Live of me~s_ges received at the ~coA~r, will now be ~rC~ ~A. The ~G~E~ing routine iB
entered at node 1200, and it par~- to step 1202, which tests for a received message. When no message iB received, the Ae~oAPr system ~eLuL..s to node 1200 and w_it~ for a message. When a meBBage iB received, the routine pLo~e~lC
to step 1204 where the meBsage iB evaluated first to determine if the fir~t .~_c~-ion key RX~ in the me~_ge is _ received code DIDR that matches the unigue DIDo (typically a code ~tored in a ROM device in the ~eco~Pr). Upon a match the system moves to ~tep 1206 where the ~econ~ received reception key RX~ in that message iB considered a new reception key RK~ and iB stored in the ~ecoADr. That RKN
thus becomes a stored ~e~e~Lion key RKo as to any subseguently received message.
Following storage of a L ~-E~Lion key at ~tep 1206, the routine advances to step 1208, which determines whether the message contains row R~ and column Ct information associated with the received and just stored ~e_e~Lion key. If offset information is present, the associated display coordinate information R~, Ct i8 stored in step 1210, and defines the offset for that received and stored L~_e~Lion key RX~. The offset is defined relative to the origin of the underlying tile. Following storage of the information, the 6ystem LeL~L"s to node 1200 for the next message. If there is no display coordinate information in the message, then the system returns to node 1200 for the next message.
If at step 1204 it is determined that the first Le~e~Lion key RX~ in the message does not match the DIDo code, then the routine moves to step 1212 and the message iB evaluated to determine whether the first received L e~e~Lion key R~R
; matches a previously stored ~L_e~Lion key RX~ for the ~ecoAP~. If it does not, then the routine ~eLu~l~s to node 1200 and waits for the next message. If it does, then the routine procee~C to step 1214 where the message is evaluated CA 022~76~7 1999-01-12 WOg3/2~8 PCT/US93/04361 to determine if it also contains a new Fecon~ ,L~ ion key If a new ~ece~Lion key RX~ is ~l&-ent, then the routine proceP~-e to step 1216 and the new ~econ~ ,ecc~Lion key RXN
is stored, and thus becomes a stored reception key RX~ as to any r~h~quently received message. After storage of a new ~e_c~Lion key, the routine next ~lOC~S to 6tep 1218 where the message is evaluated to determine if it contains display coordinate information R~, C~.
- If new display coordinate information R~, C~ is ~-ent at step 1218, the offset location information for RX~ is :stored at step 1220. If the message does not contain a new ~e__~Lion key RX~ as determined at step 1214, then the routine rA~r~~ to step 1226 where the message is evaluated ~5 to determine if new display coordinate information R#, C~ is .~ qnt. If it i~, it is stored at step 1228 to define the offset for the data as~ociated with the reception key RX~.
If the message does not contain display coordinate information, or after any 6uch information i6 stored, the routine rA-sFee to step 1222 where the message is evaluated to determine if any data is present. If no data D ig nt, then the routine ~eLu~,.s to node 1200 and wait6 for another message. If data D ic present, then it i6 stored and displayed ucing the dicplay coordinate information most recently ~ssociated w$th the stored .e_ey~ion key RX~
matching the received Lece~Lion key RX~ in the message at step 1212. Thereafter, the routine .eLu..-s to node 1200 and waits for the next message.
It is noted that the symbolic signaling routine may be combined with the nonsymbolic signAling techniques described above. It also is noted that other enabling, initiAli7ation and data messages and complementary messages for disabling reception and/or removing .c~eyLion keys and display coordinate information can be created, 6ent, and prores~e~
in a sim~lar manner.

CA 022~76~7 1999-01-12 WOg3t23~ PCT/US93/~36t According to the present invention, the encoAer stores _ composite page 200 ac _ number of tile definitions and messages. This allows the system to ~tore, tr_nsmit, and/or display information in an efficient manner using a technigue referred to a~ cellular mi~,oy-aphic~. Cellular mi~.Gy.aphics is described with reference to FIG. 15, Tables I and II, and an illustrative cellulAr mi~-Gy-aphics transmis~ion algorithm, using two (one fo~cy.o~.d/one backy.o~.d) color~ per pixel wherein: all cellc 210 in an alphamosAic tile 250-A are trAnsmitted as exten~ ASCII
characters, i.e., each character is represented by one byte -of data and there is one character per cell 210; cells of a graphic tile 250-G are transmitted as one or more bits per pixel and, hence, multiple bytes of data per cell 210;
grAphic tiles 250-G may contain both graphic cells (multiple bytes of data per cell) and alphAmosaic cells (a single byte of data per cell); and, for the sake of ~.ocessing efficiency, each tile 250 (except video tiles 250-V) may run-length encode the signal6 (either horizontally or vertically) prior to transmi~sion.
FIG. 15 shows a graphic tile 251-G that hss ten cell rows and ten cell columns and is described in Table I, where b=bl_nk character per cell, _-one ASCII character per cell, and p~pixel defined cell.

TART,I;~ ~
Cell Row Contents Notat~on R0 10 blank charActers lOb Rl 10 ASCII characters lOa R2 10 blank characters lOb -. R3 5 blank characters, 3 pixel defined 5b,3p,2b cells, 2 bl_nk characters R4 3 blank ch~racter~, 3 pixel defined 3b,3p,4b cells, 4 blank characters , . .. . . . . . . . .

CA 022~76~7 1999-01-12 wog3~n~ PCT/US93/~361 RS 2 blank characters, 2 pixel defined 2b,2p,6b cells, 6 blank characters R6 2 blank characters, 1 pixel defined 2b,lp,7b S cell, 7 blank characters R7 1 blank character, 2 pixel defined lb,20,7b cells, 7 blank character~
R8 10 blank characters lOb R9 10 blank characters lOb lS Because the cellular mic~Gy~aphic algorithm preferably uses run length PncoAing and cell wrapping within the tile - 2Sl-G, the tile 2Sl-G can be completely defined by the messages described in Table II. The calculations in Table II assume that single-bit-per-pixel signaling is being used and that each pixel-defined cell 210 is individually specified by 16 bytes of data (sixteen rows of eight columns of single bit values).

TAB~E II
2S Message number Represent~ng T~ngth rin bytes~
1 llb 1 [1]
2 8a 9 [1 + 8]
3 16b 1 [1]
4 3p 49 [1 + 3(16)]
Sb 1 tl]

6 3p 49 [1 + 3(16)]

7 6b 1 [1]

8 2p 33 [1 + 2(16)]

4S 8b 1 [1]
lp 17 [1 + 1(16)]
11 8b 1 11~

CA 022~76~7 1999-01-12 W093~23~8 PCT/US93/04361 12 2p 33 tl + 2(16)~
13 27b 2 tl ~ 1]
TOTALS: 100 cell~ 198 bytes Thus, by using the cellular mi~,oy-aphics teçh~ique of the ~ ent invention, the amount of reguired transmitted data to display the tile 251-G is reduced by a factor of approximately eight from 1,600 bytes to 198 bytes. The 1,600 bytes is based on 16 bytes per cell and 100 cells.
The 198 bytes ,e~ esent 13 cu-.L~ol bytes, 8 ASCII
characters, 11 pixel cells (16 bytes each), and 1 blank, or:
13 + 8 + 11(16) + 1 ~ 198 Still greater efficiencies may be accompli~he~ by using run length enroAing within pixel defined cells.
Referring to FIGS. 11, 16, and 25-27, a DV bus signal structure and signaling method, between the encoder 312 and a plurality of ~ProAPrs 316 and/or desk interface units 321, in accordance with a preferred embodiment of the invention, is shown. The encoAer 312 includes a receiver 510 for receiving input messages from a host central processing unit (CPU) 425 And a residual video converter (RVC) 400. These messages are then applied to ~n error detection and correction (EDAC) circuit 520, which adds parity and interleaving to protect against both single and burst errors. The o~L~u~ of the EDAC circuit 520 is passed to modulation circuit 530, which functions to incre~se the data throughput rate and facilitate subsequent signal ~o~e~sing and clock ~e~uvery in each AProAPr. References to a dProA~r should be understood to include desk interface units 321 where the context permits.
Modulation circuit 530 convert~ the binary digital data into a quad level (8,9) modulated signal, as described below. ~he vu~L of the modulation circuit 530 is passed to the multiplexor (MUX) circuit 540 which switches between, on the one h~nd, the digital data from CPU 425 and video CA 022~76~7 1999-01-12 WO g3~ PCT/USg3/~

data from RVC 400 and on the other hand time-compressed television y~Gy.am information signals which are received from television feed converter (TFC) 450. W X circuit 540 drives the ~uL~uL of encoAer 312 onto DV bus 314.
Each ~PcoA~r 316 (only one is Ai rctlc~~~ for the 6ake of convenience) includes an analog front-end signal yLGoPCsor (AFESP) circuit 610, which receives the DV bus cignals, recovers a clock signal from the modulAted ~ignal and establ~hes detection thresholds for yrGcessing the guad level DV bus signals. The ~uL~uL of AFESP circuit 610 is p~eA to demultiplexor (DEM m) circuit 620, which demultiplexes the television plG~Lam information signals and the digital-video signals, such that each may be further proce6~ and provided to video ccreen 317. DEN m circuit 620 r~ses~ the digital-video signals to demodulator circuit 630 which converts the quad level (8,9) modul_ted signals into binary signals.
The ouLyuL of demodulator circuit 630 is rAsre~ to error detection and ~Glle~Lion (EDAC) circuitry 640, which uses and then removes the p~rity bits to o~L~ùL digital ~ignals that COL~ eSpOl.d to the signals input to encoder EDAC circuit 520 as a best estimate of the inte~eA mess~ge. The message is then transmitted to circuit 650, which check~ the ~yntax of the message and stores the display information in the designated address locations of a picture store memory.
The television ~Gy~m information signals separated from the DV bus message by DEMUX circuit 620 are 6eparately pa~r6~ to circuit 670 which CG~.V~ Ls the compressed television ~Gy.am information sign~l into displayable television image signals, and then provides those image 6ignals to switch 680. Switch 680 selects between passing the television image signals and the digital display information to video screen 317.
As illustrated in FIG. 17, signals transmitted on DV bus 314 are transmitted in packets t. If no television ~Gy~am information signals ~re to be transmitted on the system, the CA 022~76~7 1999-01-12 WOg3~23~ PCT/US93/~361 packet t may have a time length th_t is variable, according to the amount of data in each message. If television ~oy,am information signals are to be transmitted, then the packet t has a fixed and uniform time length ~G~ ~ ~ fipon~ i ng to time length of the television stAn~Ard video scan line.
Thus, for NTSC television, the packet t time block is about 63.5 mic~-econA~.
Each packet t includes a digital display information packet d including a heA~r portion H, a data portion D and a parity portion P. The heA~er H contains information that allows each ~Pco~Pr 316 to identify the beginn;ng of a packet t, and to detect digital signal transitions to compensate for the transmission loss characteristics of the communication rhAnnel. The parity bits P are collectively illustrated as following the data D in FIG. 17, but in practice may be interspersed among the data D according to conventional parity and interleaving error detection and ~GL ~ ion coA i rl~ ~ echrl iques.
The digital packets d carry all the displ~y information except television ~oy~am information signals. One or more digital packets d constitute a DV bus ~message~ used by each dero~Pr 316 to modify the displayed screen image.
Each packet t also may include a television (signal) packet v, including one or more realtime television ~lGy-am signals illustrated as ~TV~- Signals for different television images are given different letters, such that TVA, TVB, and TVC ~e~,erent three different television display images. The r~h-cript numbers 1, 2, and 3, represent consecutive lines of a given television image field, such that signal TVAl is followed by TVA2 in a . following video packet v, thereby to provide the fir~t and ~?rQn~ lines of the odd line (or even line) field of television image TVA. As noted above in ronnection with FIG. ?A, the fields alternate odd and even video scan lines on the video ~creen, and two fields form a frame of video, e.g., about one-sixtieth of a serQn~ per field and one CA 022~76~7 1999-01-12 WOg3/2~ PCT/US93/04361 thirtieth of a r~:~nA per frame. The television ~Gy,am information signal6 TV are preferably time-compressed and may be either an analog signal, for example, using multiplexed analog component (MAC) PncoA~ng, or a digital S signal, for example, using digital compression methodology (e.g., JPEG, NPEG). In an embodiment where digital television ~oyl~m information si~Al~ are used, the video packet v may be omitted so that all the digital dat_ i8 transmitted in the portion data D of a digital packet d, and ~o~e re~ as a tile of pixel b_sed digital display information.
The digital packet d of each packet t may vary from one time length tD to the next t~l, APp~nA~ng on the amount of data D and television video information TV that is to be transmitted in each packet t. To reduce the _mount of memory required in each AecoAPr 316 that is equipped to receive a realtime television ~Gy.~m information signal, it is useful to signal an amount of information nPceSr~ry to generate about one TV scan line within the time period t of one TV line. With reference to FIG. 17, this meAns that the ~?conA TVB line TVB2 must occur no later than 63.5 mi~ sConAc after the first TVB line TYB1. This does not howeve~, require that the consecutive TVB line signals be uniformly or periodicAlly spaced.
Typically, DV bus messages are not ~ent to A dP. coA~r 316 faster than the decoAer 316 can buffer and act upon them.
Because the DV bus 314 is a simplex transmission chAnnel ~
the encoAPr 312 must keep track of the messages being sent to each AecoAer 316 and the time required to execute each message. ~hs~quent messages are queued until all of the decoAPrs 316 that have to receive and act upon a given message are able to do so.
Referring to FIGS. 16 and 18-19, modulation circuit 530 and demodulation circuit 630 are complementary for the selected modul_tion protocol. There are four considerations for selecting a signal modulation method: (1) clock CA 022~76~7 1999-01-12 W093~23958 PCT/US93/~ ~1 re~o~c~, (2) ~tart of message identification, (3) information tran6mi~sion rate, ~nd (4) bit error rate. All A~coAers 316 must recover a digital clock from the received DV bus signal. Therefore, the transmitted DV bus signal must have an adeguate number of digital transitions for this ~U~ ?, regardless of data D content. Further, the decoAPr 316 must be able to determine the 6tart of the message in a reliable manner.
In the ~ ont invention, a quad level digital signal, transmitting two bits of information every signaling interval SI is used as a reA~on~hle engineering trade-off :between data thro~ghp~t and bit error rate. Since e_ch ~ignaling interval SI carries exactly two bits of information, it is also referred to a8 a 'dibit~ interval.
An (8,9) interval modulation method is implemented to transfer one word (16 bits) of demodulated data D to the decoA~r EDAC 640 at a time. The structure of this modulation method is illustrated in FIG. 18, wherein SI is the signaling interval and MI is the modulation interval.
The rule for determining the signaling level of the modulation interval MI is to maximize the transition G~ ing at the leAAing edge of the modulation interval MI.
That is, if the 6ignal level in the sig~Ali~g interval SI
just before the modulation interval MI is level 2 or 3, then the modulation interval MI signal is set to level 0. If the signal level in the sign~l~ng interval SI just before the modulation interval MI is level 0 or 1, then the modulation interval MI signal is set to level 3.
Referring to FIG. ~9, the heA~ field H is 50 6ignaling intervals SI long and includes six subfields. The~e subfields provide information to each decoder for the decoder to ~e~o~er the clock signal and compensate for the transmission characteristics of the DV bus 314 and any interconnections.
Subfield one has a length of 9 signaling interval~ and contains eight dibits of the maximum value signal. This is .

CA 022~76~7 1999-01-12 W093~23958 PCT/USg3/04361 followed by subfield two, which also is 9 signaling intervals long and which contains eight dibits of the minimum value signal. These two subfields intentionally violate the modulation rule and set the maximum and minimum input signal range to allow the AeroAPr 316 to detect the ~tart of a packet d and fine-tune its decision thresholds to compensate for attenuated received-~ignal levels, and may be used to signal the possibility of the beginni~g of a he~Aer field H. However, the start of a data decision will only be made after all six subfields are properly received.
- Subfields three, four, and five each have a length of 8 - signaling intervals and may be used to fine-tune decision ~esholds to discriminate between signals at levels 1 and 2, Tl2, levels 2 and 3, T23, and levels 0 and 1, Tol, ~e~ectively. Thi~ is analogous to double-ended clamping of a binary digital signal.
Subfield six has a length of 8 cignaling intervals SI and is used as a delay and clock run-in prior to the start of data field D. It is also used to specify the interleaving depth for Error Detection and Co.,e_Lion (EDAC) as explained next.
Referring to FIGS. 16 and 19, the encoAPr EDAC circuit 520 adds parity bits to the message. This permits the AeroAPr 316 to detect and correct the errors that occur during signal transmission. Parity both increases the reliability of the messaging, as evidenced by a decreased bit error rate, at the eYre~-- of decreasing the message data throughput.
Development efforts indicated that an error detection (e.g., r~Pcksum) and replication ~G.. e~Lion method would likely be i~AP~uate. It was discu~e.ed that system performance was improved by using a single error ~G~-e_~ing and double error detecting code (e.g., Hamming) within a ~ingle level interleaving framework. While non-interleaved burst error ~G~.e_Ling codes exist (e.g., Reed-Solomon), their implementation was believed to be more difficult in an CA 022~76~7 1999-01-12 ASIC environment in which the present invention i6 preferably implemented.
Referring to FIG. 20, digitAl data D to be transmitted is written bit by bit horizontally into a double buffer. When the first row of data i8 filled, data is written into the next row and the parity bits P ~Gl ~ e~pon~i ng to the data D
in the fir~t row ~re calculated according to the EDAC
methodology rule selected. This ~G~eFS COnt~11t~P5 until the entire buffer is filled. The buffer i8 then locked to prevent further input, and trAnsmitted to the modulator circuit 530 bit by bit vertically. The buffer may be reused after its entire contents have been transmitted; double buffering sustains continuous message ouL~ from the ~ncoAPr 312.
Each buffer row includes both data D and parity P, ~nd represents one codewv~d. Assuming that a single error correcting double error detecting code has been used, without interleaving the following errors illustrated in FIG. 20 h~ve the results indicated in Table III:
TABLE TTI
~rror Codeword errors Action A,J,K,L Single in data field Correctable B Single in parity field Correct ble C,Z Double in data field Detectable, not correctable E,F Double Detectable, not correctable G,H,I Triple Not detectable, may not give error -- The nature of the digital video bus 314 is that errors occur in bursts. Apart from randomly oc~ ing ~ingle bit eL~V~ the probability of a ~econ~ error immediately following the first error is relatively high. For example, . _ . .

CA 022~76~7 1999-01-12 W093~ PCT/US93/~ ~1 if the probability of a first error i~ 10-~, the probability of the next bit being in error is not 10-~ but might be 0.9, and the probability of the following bit being in error might be 0.8. Therefore, a ~ingle cu~lacting methodology is ineffective in this type of transmi~sion chAnnel.
Interle_ving, i.e., buffering the data to be messaged horizontally and tran~mitting it vertically, causes bur~t e lO~D to be ~pread among several codc~oLds- In this regArd, a burst error J,K, and L of length three in the ~c~nnel is mapped into three ~ingle codewo.d e~ o~ and this i~ ~G~Le_Lable by the chosen error detection and correction , gcheme.
By choosing a large interle_ving depth of n codewords, e.g., 32 codewords, it is possible to protect against relatively long burst e,~o~s with a relatively simple single error correcting code. For ex_mple, when using an interleaving depth n of 32, a bur6t error of up to 32 bits is fully correctable, all errors of length 33 to 64 _re detectable, and all those with greater length could possibly result in errors. The occurrence of single bit errors plus burst errors will degrade the performance of the system in a manner determined by their location.
The maximum possible interleaving depth dep~nAs on both the maximum buffer size and tbe number of TV signals to be transmitted. This is because each time-compressed TV signal must o~-~u~y a time slot oc~L~ing once a line time, i.e., in s~rc~ssive packets t. Therefore, the maximum lengtb of digital packet d i6 determined by both the television ~GyLam information signal compression factor and the number of TV ~ignal~ being transmitted simultAneo~ly. Preferably, the interleaving depth n should be maximized within the time constraints imposed by tbe number of TV signal~ being transmitted. Thus, with reference to FIG. 7A, the possible interleaving depth n between lines U and W and between lines X and Y are the same, and is greater than the interleaving depth m between lines W and X and between lines Z and V.

CA 022~76~7 1999-01-12 Thi~ is hecA~-? the latter two ~erie~ of DV bus 6ignals also include TV lines for televiFion ~Gyl~m information ~ignals TV2 _nd TV3. Accordingly, the interleaving depth n will change with the amount of televi~ion ~GyL~m information 6ignals being trAn~mitted.
Referring to FIGS. 21-23, a plurality of digital video bus messages ~re now described. The me~ageC ~re ~G..L~olled in two layers, a trAn~rQrt layer, for detecting ~nd receiving data 6ent to a specific ~eco~r 316, ~nd a message layer, for executing ~pplication firmware or software.
Processing is done by ~ custom P~cket Reception Application-- Specific Integrated Circuit (ASIC) including ~
mi~ o~sFQr located in the receiver module 610 of the specific A~coA~er 316. The ASIC module 610 may have ~ny structural implementation so long as it performs the signal processing functions described ~nd illustrated.
Configuration of an ASIC is within the ability of a person of ordinary ~kill in the ~rt.
Regarding the transport layer, referring to FIG. 21, the transmission of variable length packets d are concatenated to form complete messages in the pre-once of time multiplexed television ~Gy~m information signals (e.g., TVA and TVB), _re shown. The mess_ge format is summarized in Table IV below:

T~!RT.F~ TV

Messaae ~M) Packet (t~ Tnterleavina Depth -. 35 2 D2 CA 022~76~7 1999-01-12 ~3~ ~ PCT/US93~04~1 3 1 Dl The interleaving depth is defined in terms of the total time of television ~.6~.sm information signal6 ~.a~ent in the video packet v of a packet t. For example, the fourth packet t in message 1, designated Ml-P4 in FIG. 21, has an interleaving depth of D2 cGL~eDlo.\lin7 to the time used by the two TV signal6.
Referring to FIG. 22, the location of the digital packet d fields are illustrated. Field 0 contains a message header. Field 1 contains the end of message (EOM) flag which indicates that the current packet d is the last one in the current message when the EOM flag is set. This enables the hardware to procees the ~e_e~Lion keys containe~ in fields 2 and 3 of the packet d, to determine whether further processing of thiC packet d is reguired.
Fields 2 and 3 contain the ~ece~ion key which is formed by the address type and address. More specifically, Field 2 contains the ~address type~ which is used to epecify the meAning and use of the contents in the address (Field 3).
In a preferred embodiment, the address type field contains two bits. A value of 00 indicates that the following address field contains a unique display identification code for a given a ~eco~r video screen, i.e., a DIDo. If the address field value is 01, then the addre6s field contains a new to be ~tored information identification code for a tile 250, i.e., an R~. If the address field is 10, then the address field contains a previously stored information identification code for a tile 250, i.e., an RKo~ If the address field value is 11, then the address field contains a packet sequence number tPSN), having a value of from 1 to 31, and the decoder 316 checks for _equential numbering of CA 022~76~7 1999-01-12 packets d within the message. An out-of-sequence number causes the entire message to be re~ected.
Field 3 i~ the ~address field~ and may have up to 21 bit~. Accordingly, there may be up to 221 - 2,097,152 different unique identification codes for each address type, i.e., video screens and pages, ~e_G~dS, portions and tiles of display information.
Field 4 has sixteen bits and provides the ~message length~ which i6 only transmitted in the first packet d of a message. It indicates the total length of the message in bytes.
Field 5 contains the data D used to form the display information message. It has a variable bit length.
Regarding the mes~age layer of the DV bus 314, there are two clAs-~fi of messages that can be accommodated, supervisory messages and image data messages. Supervisory messages direct one or more decoAPrs to perform ~G..L~ol and/or hook~eering actions, such as enabling a ~e_e~Lion key or defining a tile. Image data messages refresh or update the contents of a displayed tile. Such messages always cause the AeCoA~r video screen 317 to update even if the display information is ~nrh~nged.
All received packets d are concatenated into messages at the APcoAPr 316. The location of the received message fields is illustrated in FIG. 23. Field 0 is the ~e_e~Lion key (RK) and contains 3 bytes. Bit 0 is set to 0, bits 1 &
2 contain address type and bits 3-23 contain the address (cf. FIG. 22). Field 1 contains the ~message length~; it uses two bytes to specify the length of the message in bytes.
Field 2 is the ~message sequence number~ and is ~ one byte field. It contains a message sequence number for messages to the reception key RK ~pecified in Field 0. The decoder 316 verifies that the difference between the current and last received message sequence number is alway~ one modulo 256 to ensure that all messages to the ~ e..L

CA 022~76~7 1999-01-12 ' WOg3/2~K~ PCT/US93/04361 reception key RK are received in order. When an out of sequence number i6 detected, an error requect i6 trAnsmitted by the A~coAPr 316 over the conLLol bus 318 (See FIG. 11) indicating the last ~ol.e_Lly received message.
Field 3 i6 the ~Command~ field, and has one byte which indicates the operation to be performed on the contents of the data in following Field 4, the variable length part of the mescage. A Command mAy be ~elf acting, i.e., the data field contents immediately *ollowing is null. The byte -length of the data in Field 4 is limited by the time length t of each message and the video 6ignals v in each messAge.
In a preferred embodiment, the message Command field 3 has the following commands and data Field 4 has the following associated data: A messAge Command byte O
initializes AecoAPr hardware and clear~ the video screen.
There is no associated data. A message Command byte 1 sets the parameters to configure the video screen hardwAre And software. Associated data bytes 0-7 contain the ON and OFF
period for four blink counters, and data bytes 8-11 contain the motion period for four motion counters. A message Command byte 2 operates to clear the video screen, making all pixels the bAckground color. There is no associated data. A message Command byte 3 operates enable ~ece~Lion.
It instructs the uniquely identified decoder 316 to enable reception for the specified ~F_e~Lion key, and associates this ~e~e~ion key with the request string for the specific tile 250 sent by the decoA~r 316 to the host CPU 425 via the cG..~ol bus 318. For this message Command, the associated data is, for bytes 0-2, the tile ~e_e~lion key, and for bytes 3-23, the tile request string. A message Command byte 4 sets the tile definition. It defines the tile 250 whose number i6 specified in the address Field 3. The first associated data byte specifies the default color index for the portion of display information. The 6econd data byte specifies the default display attribute. The third data byte represents the number of 6ymbolic tile definitions (the CA 022~76~7 1999-01-12 W093/23 ~ PCT/US93/04361 _59_ number of 11 byte packet~ following). Each of these def initions contains a 16 bit symbol number ttile IID or RX), the two corner display coordinates (upper left and lower right; a rectangular tile ho~n~ry i~ assumed), the default symbolic tile attributec and the value of the motion counter if the tile i8 ~a r~nning or ecrolling tile. The as~ociated data bytes are:

byte 0 default color index byte 1 default display attribute byte 2-3 default upper left row and column number byte 4-5 default lower right row and column number byte 6 tile motion attribute byte 7 current motion index byte 8 default character table byte 9 number of text messages composing the tile byte lo current message sequence number(~) for tile messages l to n A message Command byte 5 sets the color table. It contains a number (specified in data byte 0) of definitions for the color table. Each definition contains four bytes.
The first dAta byte ic an index (0-255) into a color t~ble.
The three other data bytes represent backyLou"d color, foreground color and line color respectively. Each of these three data bytes is encoAeA internally as IIRRGGBB: two bits to define the overall INTENSITY (I), two bits to define the RED (R) intensity, two bits for the GREEN (G) and two bits for the BLUE (B). The as~ociated data bytes are:

byte 0 number of color definitions byte 1 new color index byte 2-4 background, forey.o~.d, line colors byte 5-8 next color definition (same as bytes 1-4) byte 9-12 next color definition (came as bytes 1-4) A message Command byte 6 operates to send new text to the video screen. ~he characters contained in the data section are put on the screen in contiguous columns or row~, CA 022~76~7 1999-01-12 W093t23958 PCT/US93/04361 depenAing on the aXiB of conr?c~tiveness, using cell wrapping. The ~roc~Ated data byte~ are:

byte 0 mes~ge id (Tile-relative) S byte 1 message seguence number byte 2 relative row number byte 3 rel~tive column number byte 4 number of data bytes following byte 5...... data in TEXT format A message Command byte 7 provides for downlo~;ng ~ -amming code into the ~co~Pr 316 application ~Loy.am memory. The associated data bytes ~re:
byte 0 ~Gy.am revision code byte 1-4 6ection address byte 5 last section flag byte 6...... program code A mess~ge Comm~nd byte 8 clears a tile. It causes ~11 pixel~ in the tile to be set to the default backy~ou..d color. There is no associated data. A message Command byte 9 is a ~Genlock~, which is functionally eguivalent to a vertical sync pulse in a video signal. There is no associated data. A message Command byte 10 is to define a character 6et. It downloads a pixel map for a character set for converting a one charActer byte to a multibyte pixel representAtion. The associated data bytes are:

byte 0 Character table ID
byte 1 Starting character code byte 2 Number of codes defined byte 3...... Bit map definitions (16 bytes each) When a tile 250 is defined in the encoder 312, a static array of messages is allocated to, And associated with, that tile 250. All messages in the enco~Pr 312 are kept in a gueue and Are sent out, in their entirety, in ~ message CA 022~76~7 1999-01-12 WOg3J23~ PCT/US93/04~1 cycle who~e period varies according to 6~ystem rch~A~lling constraints.
The ~ystem i6~ preferably tuned to optimize message ~c~DA~ ng for its particular mix of 6tatic alphamosaic tiles 250-A, graphic tiles 350-G, motion tiles 350-P, 350-S, RVC tiles 350-V, TFC ~tiles~ 350-V, and the number of A~coA~rs and video screens. One suitable message prioritizing rcheAl~le is the following order: individual AecoA~r directed messages, 6~eA~led me6sAges (tile motion ~GI---ol)~ tile update data messages, ~ProA~r re-requested tile update messages, alphamosaic refresh messages, administrative messages, and graphics refresh messages.
The message layer protocol ~p~G.L8 three kinds of attributes for cells 210: motion, cell and color. The motion attribute is an eight bit word that i~ encoA~ MOV, C1, C0, V, NU, NU, NU, NU, where MOV, C1, C0, V are movement, movement control byte 1, movement co..L~ol byte O, video and NU stands for ~ln~ bit6. The cell attribute is an eight bit word and it combines both software and hardware attributes. The byte is encoded REV, ULIN, NU, NU BR1, BR0 BE1, BE0 where BR1, BR0, BEl, BE0 are blink rate 1, blink rate 0, blink effect 1, blink effect 0, REV 6tands for reverse video and ULIN stands for underline. Thege last two attributes are implemented in software and therefore need not reside in the character cell. The color attribute is an index into the color table.
The message layer protocol uses a byte oriented TEXT
format to specify co..L.ol, alr~n~meric text, and graphics.
The lowest nine bytes are co..L.ol bytes and have the following special meAnings: Byte 0 specifies that the next byte will contain a repetition factor for run length encoAing to specify how many times the cell definition that follows should be repeated along the axi~ of rQnsec~tiveness. Byte 1 specifies that the next 2 bytes will contain the relative row and column number applicable to the following text. Byte 2 specifies that the next 16 CA 022~76~7 1999-01-12 W093~ PCT/US93/~ ~1 bytes define a graphic cell to be put in ~u~ L location.
8yte 3 ~pec~fies that the next byte i6 to become the current cell ~ttribute, me~ning that it will apply to every Q~h-equent cell defined in the mes6age. Byte 4 specifies that the next byte contains the size of the cell ~pecifications to come. The sizes allowed are O for normal ~ize, 1 for double size, 2 for triple size and 3 for guadruple ~ize. Byte 5 ~pec~fies that the next byte ic to become the current color index, me~ning that it will apply to every subseguent cell defined in the message. It i~ not used for graphic cells. Byte 6 specifies that the following cell specifications should be put in cQnFec~tive locations horizontally. In other words, to define the address of the next cell, the ~u~el~ column number ~ho~ be incremented.
Byte 7 specifies that the following cell specifications should be put in ron~ ,Live locations vertically. In other words, to define the address of the next cell, the current row number should be incremented. Byte 8 specifies that the ~ el~ cell location is not to be modified, e.g., if the cell cont~ins a character that is defined on another line.
For example, if the line 1 contains triple size characters, it also will use line 2 and 3 to display such characters.
Therefore, all characters on line 2 and 3 will be ~phantom characters.~ Byte 9 specifies that the next byte identifies the character table from which the following characters will be drawn. The new character set remains in effect until another change character set command, or the end of message.
Bytes OAH-OFH are not used and bytes 20H-FFH are normal cell representations. Printable ASCII character codes are preferably used wherever possible.
The following illustrates how the overall messaging efficiency and system thro~3~ , in accordance with thi~
third embodiment of the invention, may be calculated.
Consider a system in which signal bandwidth is 22.5 MHz, the packet time length t (including the header H) is 63.5 ~s, the error detection and correction code is a 24/30 CA 022~76~7 1999-01-12 HAmming code, interleaving efficiency is 100%, modulation is quad level (8,9), and packet efficiency is 100%.
The si~n~l~n~ interval SI may be determined from the system bandwidth as follows:
a) the signal edge rise time (tr) ~ho"l A be less than or equal to one-third of the signaling interval SI, and b) the bandwidth of the signal (fb) is related to the signal edge rise time by:
(fb) (tr) ~ 0.35 Hence, the minimum signal interval co~e~G.. ding to a 22.5 MHz bandwidth is:
SI~n ~ 3(tr) e l.OS/(fb) - 1.05/22.5 MHz ~ 46.6 ns.
The signaling interval is therefore cho-en to be:
SI e 50 ns.
Regarding information throughput, since quad level modulation i8 chosen, two bits are transported in every signaling interval. The capacity of the ~h~n~el is therefore:
~hAnn~l - 2/SI - 2/50 ns e 40.0 Mbits/sec = 5.0 Mbytes/sec.
This capacity is not actually at~in~ because first, every packet gtarts with a 50 SI hPaA~r, every ninth SI
after the header contains no information ((8,9) modulation is used to aid clock recovery), and the EDAC circuits 2S appends six parity bits to every twenty four data bits (a (24,30) Hamming code is used).
ceConA~ each packet maximally lasts 63.5 ~s. Thus, there can be a maximum of (63,500ns/50ns) ~ 1,270 SI per packet.
The 50 SI h~AA~r therefore reduces the capacity by a factor of (1270 - 50)/ 1,270 - 96.1%. The modulation efficiency is (8/9) ~ 88.8% and the EDAC efficiency is (24/30)c 80%.
Therefore, the overall efficiency of the DV bus signaling i8 approximately ~ 0.961 x 0.888 x 0.800 - 68.27%. This results in an effective DV bus capacity of:
3s 0.6827 x 40 - 27.3 Mbits/sec c 3.4 MBytes/sec.

CA 022~76~7 1999-01-12 WOg3~ ~ PCT/US93/04~1 In practice the DV bus 314 should be tranFpQrting information at a rate of about 20 Mbit6/sec or more, which is more than twel.Ly (20x) times that of conventional Ethernet sy~tems. It should be noted that Ethernet has a 10 Mbits/sec capacity of which perhaps only 1 Mbits/sec is realized after protocol and/or error ~oce~sing.
Referring now to FIGS. 11 and 26, ~o"L.ol bus 318 ~G~ O1S bi-directional communication between a AecoAPr 316 (or a desk interface unit 321) and the system. Host CPU 425 may issue messages targeted to a cpecific AecoAPr or to all decoders, or may request information from a ~pecific AecoAPr. A A~coAPr will send a message to the host CPU 425 when requested by the host CPU 425.
Typical uses of the conL.ol bus 318 from the host CPU 425 to AecoAPrs 316 are to poll a APcoAer 316 for a message, install a new A~coA~r 316 on the system, update an LED
display of a keyboard 319 at a decoAPr 316 and maintain the control bus protocol. Typical uses of the ~G.IL.ol bus 318 from the AecoAPr 316 to host CPU 425 are to transmit keyboard and/or mouse data (i.e., user requests for display information, or to define or move tiles), .e~o.~ decoAer malfunctions, and request 6ystem resources, e.g., DV bus 314 message retransmission due to a detected error in message seguences.
The structure of co.. ~.ol bus 318 is modeled after conventional industry-stAnA~rd shared bus models. A
preferred protocol is one similar to an ~DLC unbalAnGeA
configuration in normal ~e~,o.ce mode. A preferred control bus 318 ic a ~ystem-wide multi-drop RS-422 or 485 network, where the host CPU 425 serves as the primary station and up to 63 decoders 316 are ro~nected as ~econ~ry stations to each RS-422 or 485 strand. Bi-directional communic_tion between each decoAer 316 and the host CPU 425 is co..~.olled by a preselected polling scheme emitted by the host CPU 425.
At installation, the host CPU 425 assigns a unigue control bus address to each de~oAPr. This address consists CA 022~76~7 1999-01-12 W093~23958 -PCT/US93/04~1 of a strand ID, which identifies the RS-422 or 485 line to which the ~oc~r is co~nected, and a 5-bit polling ID. The polling sche~e allow~ the host CPU 425 to poll each AecoA~r using a single byte, thus making the most frequently used signal the shortest length.
In addition, the host CPU 425 sends commands to a specific AP~oAe~ 316 using its unique 21-bit APcoAer ID.
Unless there are any errors detected, every ~DCOAPr 316 along a strand is polled before any AeCoApr i8 polled a ~econd time. This polling ~equence represents a polling cycle. The suitable nominal polling frequency of .2 Fecon~
that is, an outst~nAing message at a dPCoAP~ will wait not longer than .2 second before it is solicited by the host CPU
425. The baud rate (nominally 9600 baud) is configurable, Aep6nAjng on the number of AecoA~rs in the system. This means that smaller systems may be able to realize a savings by using fewer communications co~ ollers. ~t also meAns that systems are easily upgradeable, since the cystem's CG~L~ ol bus capacity can be increa~ed by A~Aing communications controllers. Where desk interface units are used, CPU 425 assigns a polling ID for each video screen 317 and polling and command messages are sent for each video screen 317 on the system, rather than to each decoder 316.
Messages between the host CPU 425 and each AecodPr 316 are in the form of a transaction. All transactions are initiated by the host CPU 425 and take place between the host CPU 425 and a single AecoA~r. Referring to FIGS. 24A
and 24E, the host CPU 425 begins its signal by ~enAing a probe message (if it has no command for the decoA~r 316) or a command message (if it has a command outs~nAing for the AecoA~r) to a specific decoA~r. Alternately, the host CPU
425 may send a ~BroAAcA~t~ message to all AecoA~rs on that conl~ol bus ~trand 318. Broadcast messages serve a number of purposes (e.g., transmission failure, system-wide keyboard messages, changing communication parameters, etc.).

CA 022~76~7 1999-01-12 .

W093~K8 PCT/US93/04361 Both command and BroAAcAst messages consist of a PPAA~r, a ~equence element (Seg), and one or more requests (R-Frame).
Referring to FIG. 24B, each AProAPr ~r 7~-0~ S to A host CPU 425 signal with either _ ~olicitation mess_ge or, if no solicitAtion is ready, an idle mes~age. Idle messages consist of A Seq element only (mess~ge bit e o).
Solicitation messages consist of a Seq element (message bit ~ 1), a poll element, and one or more request frames. A
request frame (R-Frame) contains one or more requests from lo either the host CPU 425 or the APcoAer 316. No more than 64 requests can be sent in one R-Frame. FIG. 24C shows the structure of an R-Frame and FIG. 24D shows the structure of a ~ingle request.
Of the three message clAs~~c generated by the host CPU
425, two (Probe and Command) constitute ~ignals. The deroAPr must ~e~yond within a configurable L e~ol,se interval (nominally set at 5 charActer times), otherwise the host CPU
425 regards this as a failed transAction. If the number of failed transactions pA-sF~- a configurable Ai~ronnest threshold (nominally set at 5), the host CPU 425 logically Ai~co~nects the AecoAer from the network and displAys a suit_ble message to the system administrator.
The signaled decoAer ,e~o-,ds to each host CPU signal with a solicitation or idle message. The v_lue of the AR
bit in the Seq element (see FIG. 24G and the A; ~c~scion below) reflects the ~eccyLion status of the signal. If the signal was a Probe or a successfully received Command, the AK bit is 1. If the sign_l wAs a Command, and the R-Frame was not received s~lcrPscfully, the AK bit is 0.
The decoA~r regards the transaction as s~rc~ssful if the next message ~ent by the host is a signal to another AProAPr. Otherwise, a negative acknowledgement is assumed.
If the next host message is another signal to this A~roA~r, it retransmits the solicitation. On an error, the host CPU
425 will re-signal a A~coAPr up to a configurable number of times (nominally 5), ~nd then send a broadcast message.

CA 022~76~7 1999-01-12 W093/23~ PCT/US93/W361 This i~A~rAteS a communication failure without providing a ~e~yOnSe O~G~ L~.ity. The ho6t CPU 425 then contin~ its polling sequence.
As shown in FIG. 24E, bit 7 of the poll message is alway~
~et. Since a poll message can originate from either the ho6t CPU 425 or the ~ecoAPr 316, bit 6 i~ used to indicate the source of the poll (0 - Host, 1 ~ AecoAer). The rem~ n i ng six bits are the polling ID of the ~eroA~r (1 to 63).
lo Referring to FIG. 24F, Command and BroAAcA~t messages always originate in the host CPU 425. The structure of byte 0 of the6e two messages i8 identical; hlcwe~er, whereas the command message i6 6ent to a 6pecific decoA~r, wherein bytes 1, 2, _nd 3 of the command element contains the polling ID
of the dPCoA~r, the bro~Ac~t message i6 sent out to all AecoAPr6 on the entire 6trand, wherein bytes 1, 2, and 3 of the bro~Aca~t me66age have a polling ID - 0.
In addition to message-by-message acknowledgement6, each command and 601icitation mes6age is as6igned a ~equence number (6ee FIG. 24G). The sequence numbers are co~-~cutive, modulo 4. These are ~e~o~Led by each 6tation in the NR and NS bit fields of the Seq element. Commands ~re numbered in the NS field by the host CPU 425 and the NR
field by the decoAer 316; solicitations are numbered in the NR field by the host CPU 425 and in the NS field by the A~coA~r 316. In each case, the ~equence number fields contain the next e~E_Led sequence number. In other words, the NS field of the current message contains the 6equence number of the next message the s~nAing 6tation e~e_Ls to send. The host CPU 425 maintains a unique NR/NS pair for each AecoA~r. In Bro~Ac~t messages, only the NS field is meAningful.
This feature provides an additional means of error correction and detection, since a failure to match one station's NS with the other's NR is interpreted as a request to resend messages with prior sequence number6. This means CA 022~76~7 1999-01-12 W093~3 ~ PCT/US93/04~t th_t e_ch st_tion keeps a gueue of the last 4 messAge~
transmitted. In the event of _ sequence number mism_tch, _11 Reqs (up to 64) from _11 outstAnAing ou~bo~nA mess_ges m_y be concaten_ted into _ new message with the lowest outstAnAing sequence number.
Referring now to FIGS. 11, 16, _nd 25, a preferred embodiment of _n ~ncoAPr 312 of FIG. 11 is shown. ~ncoAPr 312 is constructed to interface with host CPU 425, _nd to _ccept sign_ls from digitAl 80U~'LS, analog 80ul~es~ digital --video sources~ _nalog video ~OUL~LS, _nd realtime television -image ~ignals, in _ddition to the host CPU 425. Preferably, : the encoder 312 receives video signals from one or more residual video converters 400 and television p~Gy.am information signals from one or more television feed converters 450.
~ncoA~r 312 is prefer_bly configured _s a single printed circuit bo_rd assembly th_t can be inst_lled in _ backplane of the host CPU 425, and may be ~u~v~Led by one of ISA, EISA, and VNE bus protocols, or an equivalent protocol.
The ~ncoA~r 312 originates messaging over the simplex DV
bus 314 to the plurality of individual A~coAers 316, and also provides duplex communication over the cGl.L~ol bus 318.
It includes an encoA~r CPU 505, which is preferably a high ~performance 32 bit central ~.oce~sing unit with direct memory address (DMA) and other integrated functions (e.g., counter-timer). A suitable CPU 505 is model 68332 available from Motorola. It is responsible for cGI,L.olling all of the encoA~r functions, including collection of incoming data, message manipul~tion, determination of transmis8ion priority, and dissemination of outgoing dat_.
The CPU 505 has an associated ROM memory 506, which contains a ~mall amount of ~Gy.am ROM code, e.g., the basic boot code and rudimentary ~.~y.am functions to allow the encoA~r 312 to perform self-test and communicate with the host CPU 425. The bulk of the ~ncoAer executable code is preferably stored in a RAM 507, and may be downloaded via CA 022~76~7 1999-01-12 1, W093/~ PCT/US93/04~1 the host ~nterface 427, thereby providing maximum flexibility for reconfiguring the function_lity of P~co~Pr 312. Alternately of cour~e, the exe_~able code could be contained in the ROM 506.
Dat~ received vi_ the host interface 427 or the ~erial interface 508 are transferred by DMA into the ~.Gy.am and Data RAM 507 along data buc 504. The encoAPr CPU 505 can then Acr~ss the~e me~ages and perform any necerr-ry man~r~lAtion or re~r ~e.
The Dual-Ported RAM 512 gtores current messages queued by the Cygtem~ for transmission on DV bus 314. When a new mes~age has been prepared by the en~oAPr CPU 505, it is then tr_nsferred via DMA bus 504 from the ~.Gy.am and Data RAM
507 into the Dual-Ported RAM 512. These transfers occur during the h~AAPr period of the signals on the DV bus 314, and are initiated by a high-level interrupt provided by a timing generator 513. The Message Formatter and Sequence circuit 514 _ccesses new messages loaded into the Dual-Ported RAM 512, and formatc the message as discussed for transmission over the DV bus 314.
The host interface and FIFO 427 allows bi-directional communication between the host CPU 425 and the encoAPr 312.
Host messages that are to be tr~nsmitted by the encoder 312 on DV bus 314 are p~-c~e~ from the host CPU 425 to the enco~Pr 312 via the interface 427. Because these messages are only composed of changes to displayed 8~ ee~.~ , i.e., update data, the average bandwidth requirements are much lower than for ~realtime~ video switched systems.
Messages from the host CPU 425 are loaded into an input FIFO memory device in interface 427 for retrieval by the encoder CPU 505. Configuration information i8 also passed from the host CPU 425 to the encoder 312. The enco~Pr CPU
505 will periodically DMA transfer the incoming messAges from the FIFO memory in interface 427 to its local P,G~am and Data RAM 507 over bus 504.

CA 022~76~7 1999-01-12 WOg3/23 ~ PCT/US93/04~1 The host interface 427 can al~o be u~ed for limited information flow in the other direction. Re~ and commAnd a~n~wledgements from the ~ncoA~r 312 are communicated to the host 425 via interface 427. In addition, data received over the ~G~LLO1 bus 318, e.g., data generated by the user'6 keyboard 319 or mouse 319~, are transferred to the host CPU 425 through this s~me interface 427 via ~G~ ol bus mi~Loco..~.oller 550. Altern~tely, the ~G---,ol bus 318 may be acceFFe~ by host CPU 425 directly through host I/F and FIFO device 426 as illugtrated in FIG.
25.
The RVC interface 509a consi~ts of a mono-directional data port 509 and a bi-directional ~G..L~ol port 509b that communicate between external RVC modulec 400 and a bus mic~ocG.. LLoller 509c. RVC modules 400 send messages to the enroA~r 312 that identify pixel change data on video display adapter~ to which they are connected as described below.
The encoAer data bus 504 could possibly be busy when multiple RVC modules 400 attempt to send messages asynchronously to the encoA~r 312. Arbitration and flow cG..~Lol i~, therefore, reguired. Further, bus and priority arbitration by the interface circuit 509a is preferably provided by RVC bus controller and FIFO 509c in a ~conventional manner. Typical techniques include: interrupt requests generated by RVC modules 400 and subsequent polling of data by the encoder CPU 505; ~token passing~ between co~nected RVC modules 400 to enable sequentiAl access to the interface bus 504; and time domain multiplexing (TDM) of the interface bus 504 to allow periodic access by each RVC
module 400.
Messages delivered by the RVC modules 400 are identical in structure to those created by the encoAPr CPU 505 and are DMA'ed directly into the Dual-Ported RAM 512. Therefore, messages delivered by the RVC modules 400 ~ ent no processing overhead to the encoA~r CPU 505. However, the encoder 312 may apply cellular mi~,Gylaphic te~hni~ues CA 022~76~7 1999-01-12 !
W093t23~ -PCT/US93/~ ~1 (optionally with run length en~oA~ng) to further reduce message volume on the DV bus 314.
The serial interface 508 allow6 easy communication and downloa~ing of executable code, even when the host Interface 427 is not operational. Typically, this port will not be used during normal operation of the ~ystem.
The DV bus si~n~l;ng protocol described above incGL~o,ates robust EDAC circuity 520 Pnh~c~A by interleaving of data. The likelihood of errsn~ data being displayed on a monitor is, therefore, extremely low.
The signal to noise performance should have a bit error rate better than lO-l~ in a 38 dB signal to noige ratio, interleaving for bur~t error protection greater than 16 bits and decompressed TV ~ignal to noise ratio better than 40 dB.
Nevertheless, a further added level of protection is provided by replication coAing~ i.e., retr~n6mi~sion of previously transmitted data, termed ~refre~h;ng.~ In other words, undetected CO~L ~yLed data is displayed for only a brief period of time, since the ~ame information will be periodically retran~mitted (refreshed) and co,~e~ed a short time later, e.g., 0.5 F~c~A~. Thus, the probability of erroneous data being displayed for a significant period of time is further reduced by the number of refreshes, until the message is eventually displaced from the Dual-Ported RAM
512 by more recent data. Thus, the Dual-Ported RAM serves as a cache for each portion of display information that is transmitted to a video screen on the system.
Yet another level of protection i6 i~-LGd~Ced with ~e_~E_~ to ~ncoA;~g and refresh~ng. In this regard, an ESF
time-out period is used (see FIG. 2) such that an enable signal flag and enable ~eoe~Lion messages must be retransmitted before the time-out period expires or else the previously enabled decoA~r will become ihtentionally disabled. Further, retransmission of enable reception messages permits periodically changing the information identification codes for each portion of restricted display CA 022~76~7 1999-01-12 WO g3/239S8 PCr/US93~04361 information. This will minimize the 11kel~hood that an unauthorized A~coAPr will be able to retrieve and display re~tricted display information, and because all display information data will be retransmitted, removes the l~l~el~hos~A of ~.o.. ~l ed data being displayed for any significant period of time.
The encoAPr 312 i8 designed to use as much of the DV bus 314 bandwidth as possible. Priority is given to transmission of new data to keep latency time low. Once this requirement has been $ulfilled, the remaining DV bus bandwidth i~; used for refre~h1ng recently transmitted data.
In one embodiment, the DV bus 314 may include up to 2000 feet of type RG-8U coA~Al cable, and may have attached to it up to 128 AecoA~r~ 316 with a 3 dB bandwidth on the order of from 100 Hz to 25 MHz.
The Message Formatter and Se~lencer 514 performs a hardware function ~ ,on~ible for retrieving prepAred messages (in proper priority) from the Dual-Ported RAM 512 and generating the ~lo~er hP~APr and message for transmission on DV bus 314. The preferred DV bus definition reguires th~t one packet is transmitted every 63.5 l~s corresponAing to a television video scan line for ~ VGA
format; for other television formats, other packet time lengths could be used. Long messages are thus broken into several con~ec~tive digital packets d. The MecsAge Formatter and Seq~ncer 514 performs division of long messages into multiple digital packets d with ronrQc~tive packet ~equence number~.
The Dual-Ported RAM 512 is preferably implemented as a circular message store buffer, with new messages loaded by the CPU 505 overwriting the oldest messages left in the RAM
512. Every movement of the starting data pointer by the CPU
505 causes the Message Formatter and Seql~P~cPr 514 to begin rend~ J the new messages before resuming the transmission of refresh messages.

CA 022~76~7 1999-01-12 W093/23 ~ -PCT/US93/04361 The interleave encoAPr 522 burst error protects the outgoing packet data 6tream. In summary, the outgoing packet datA D and parity p Are stored in the interleaving RAM buffer 524 in ~ra~ter 6can~ format. The interleave ~ncoAPr 522 then reads the data D and parity P with the axes rever6ed. Consequently, each AecoA~r 316 i6 able to detect and cG~ L most errors cau6ed by burst noi6e. As noted, the de~.ee of interleaving in each pAcket is ~penA~nt upon the number of television ~Gy m information 6ign~ls TV
being multiplexed onto the DV bus 314. The interleave level in each packet d is oonL~olled by the ~ncoAPr CPU 505 and is : communicated to the decoders 316 via the aforementioned messAge field.
The timing generator 513 generates the various DV bus dependent timing 6ignals used by the encoAer 312. An interrupt to the encoder CPU 505 is timed to allow new messages to be loaded into the Dual-Ported RAM 512 during the period when the Message Formatter and Se~ncer 514 is not acces6ing the RAM 512. Horizontal and vertical 6ync 6ignals are provided at ou~uL 515 of timing generator 513 for dissemination to an optional Television Feed Converter (TFC) 450. Multiplexor cGnL.ol 6ignals are al60 generated at ouL~uL 516 for use by an ou~uL multiplexor device 540 to inject the converted TV signals at the a~G~liate time in a video packet v during each TV 6can line time length t.
Regarding TFC 450, A number of live TV 6ignals may be time compressed and transmitted over the DV bus 314 for di6play by remotely located decoder6 316. These 6tAn~rd NTSC video signal6 will be time compre6sed (e.g., by A
Multiplexed Analog Component (MAC) tec~n~que), And then ~. injected onto the DV Bus 314 in a Time Domain Multiplexed (TDM) fashion. Further, the 6ame televi6ion ~oy.am - information 6ignal can be provided with different line tlUmber6 80 that one video screen can display the signal at full 6ize and another can display it at a different 6ize, e.g., 1/4 size.

WOg3/2395X PCT/US93/04361 Thu~, TFC ~ncoAer interf~ce 451 accept~ the MAC analog signals from several different TFCs 450. When other televi~ion ~G~,am information signal compres~ion format~
are used, interface 451 is a~o~Liately modified. In addition, interface 451 provides horizontal and vertical ~ync signals to the TFCs 450 to ~genlock~ these ~ignals to the master time clock in encoA~r 312. Configuration ~nd ~ol.L~ol mess~ges are also pAQre~ ~cL~n the host computer 425 and the TFC 450 via a conventional low bandwidth Qerial communic_tions link (not ~hown).
Digit_l eignals generated by the Message Formatter and : Seguence 514 are modulated in the ~dibit~ format, i.e., with four discrete analog levels ~ey~ eRenting two binary bits of information per si~n~ljng interval. Signals supplied by the lS TFC Interface 451 are typically high freguency MAC analog signal6. These two signal types are time multiplexed together by multiplexor 540 to form a hybrid signal for transmi~sion over the DV bus 314.
The multiplexor 540 performs this selection y~ GC~;S in ~e~o,l~e to cG,-L,ol signals provided by timing generator 513. The exact number of TV signals, and their location within the DV bus packet, ~re determined by configuration information pA~re~ from the host computer 425.
The DV bus driver 516 interfaces the analog ouL~uL signal from the multiplexor 540 onto the 75 ohm DV bus co~YiAl . .
cable 314 in a conventional manner.
The ~onL~ol bus mi~,o~G--~-oller 550 polls the ~G--L,ol bus interface 552 collects the data from remotely located ~ecoAPrs 316 and pA~6~fi the data to host computer 425. On large systems, this functionality may be performed on a ~eparate Digital Interface Board (see DIB 426 FIG. 11.) The co,.L,ol bus interface 552 connects the encoA~r 312 to a multi-point twisted pair ~G-.LLol bus 318. Driver~ are used to send and receive differential ~ignal~ on this ~..L,ol bus 318.

. ~

CA 022~76~7 1999-01-12 W093/23 ~ PCT/US93/04361 In one version of the third embodiment of the ~L~-~nt invention, the ~ncoAPr 312 was designed using Application-~p~C~ fic Integrated Circuits (ASICs). Three Field oy.~mmable G~te Array (FPGA) ASICs were defined using commercially available devices. Increa~es in FPGA densities will allow partitioning the design into fewer FPGAs. The functions of the three FPGAs are distributed a8 follows.

~~ FUNCTIONS
1. Host Interf~ce Host Interface & FIFO 427 (e~e~L the FIFO itself) (ISA bus) 2. Video Dual-Ported RAM 512 3. ~essage Message Formatter & Sequencer 514 Timing Generator 513 Interleave ~coAPr 522 Referring now to FIG. 29, a modular residual video ~GIl~e~ Ler (RVC) 400 in accordance with a preferred embodiment of the present invention is shown. In this embodiment, RVC 400 includes a video front end and sync separator circuit 710, three video digitizer circuits 720, a video data switch 730, a gystem image RAM bank 740, a last frame RAM bank 750, a pixel comparator 760, and a pixel change circuit 770 for identifying which cells 210 of a composite page 200 of digplay information have changed pixel information and the pixel change information.
Preferably, each RVC 400 operates under the ~G~ ol of a mic~G~G~e~-or (CPU) 780. CPU 780 has associated memory RAM
781 and memory ROM 782 and a direct memory address capability, and a DMA control and data bus 785. CPU 780 also has an PnCo~er interface 783, for interfacing with an ~nco~r data bus interface 509a and cGnLlol bus interface 509b (FIG. 25) and a host CPU interface 784, for interfacing with a host CPU 425.
The RVC 400 may be configured to accept one of three different types of input video signals, namely monochrome, CA 022~76~7 1999-01-12 WOg3~ ~ PCT/US93/04~1 EGA/CGA, or VGA. For monochrome video signals, three BNC
connector~ 711 are provided to accept video feeds from three ~nAel-l..3~nt monochrome video signal feeds. For EGA/CGA
video ~ignals, one type DB-9 ronn~ctor 712 is provided to accept one EGA or one CGA input video ~ignal feed. For VGA
video Q~qnA~ one type DB-15 cG- o~Lor 713 is provided to accept a single VGA input video signal feed, ~uch that the ~ignal may be anAlog or digital RGB sign_l6. These cQnn~ctors and their pin ro~nections, are conventional and known in the art. Preferably, RVC 400 includes a jumper or switch selection (not shown) to select which connector ou~u~, cGl~e~G--ding to the type of video signal feed, will be input to the RVC 400. This may be inco~o~ted into front end circuit 710 or into a cable converter h_ving A
stAn~Ard connector on one end.
Referring to FIG. 29, the front end circuit 710 includes circuits to separate the horizontal and vertical sync sign_ls from the input video signals. In the case of non composite video inputs, the a~ .iate video connector pins must be selected for provision of these same 6ignals. When RVC 400 is to be used to digitize a three color signal, e.g., CGA, EGA, or VGA, the sync signals respectively fed to the three video digitizers 720 are synchronous. Further, front end circuit 710 may include an analog color matrixing circuit to convert color R,G,B signals into Y,U,V signals for more efficient digital enCoAing of the signals. When the RVC 400 is used to digitize three monochrome video signals, all three 6ets of sync signals may be asynchronous.
Alternately, each RVC could be configured with one type of connector~ e.g., ron~rtor 711, 712 or 7~3, in a dedicated manner for processing only the corresponAing type of video signal. This configuration would simplify the manufacture of modular circuits, 80 that different RVC 400~s would be used for processing the different format video signals. Thus, the user of the RVC 400 may select the a~Lo~.iately configured module and insert it into the CA 022~76~7 1999-01-12 W093/23~ PCT/US93/~361 printed circuit board for cG..ve~Ling the received video signal.
Referring to FIGS. 29 and 30, the three video digitizer circuit~ 720 have the same construction and operate in the same manner, and therefore only one such circuit is described. Each video digitizer circuit 720 receives from front end circuit 710 one video signal video input feed at input 721, a vertical sync signal VSYNC for that video signal at input 721v, and a horizontal sync signal HSYNC for that video signal at input 721h. The vertical sync signals are r~ directly through circuit 720 to o~L~L 722v.
: A double-throw switch 723 is provided to configure circuit 720 to ~LG~Ess digital video signals and analog video ~ignals. Switch 723 may be manually configured or, more preferably, configured by RVC CPU 780 by a~o~Yiate commands over the cG,-~ol and data bus 783. Switch 723 is illustrated in FIG. 30 in the position for accepting and digitizing analog video signals. In this configuration, the ~ignal VIDEO at input 721 is p~ to a flash analog to digital converter (flash ADC) 724 and a digital threshold comparator 725.
Flash ADC 724 accepts differential analog video signal~, for minimization of common-mode ground noise, where it is locally converted to a single ended signal. The flash ADC
724 is preferably capable of operating at the 32 MXz VGA
video rate, and its ou~u~ may be asynchronous, and not ~epen~nt on any timing clock. Thus, flash ADC 724 converts the 6ampled analog signal VIDEO into, e.g., an eight bit digitized ou~u-.
In the preferred embodiment, the digital threshold - comparator 725 performs a combinatorial logic function that maps the m-bit ouL~uL value of flash ADC 724 into an n-bit - pixel value, e.g., a two bit value. This renders the analog signal VIDEO compatible with conventional video signals that are digitally transmitted. Digital threshold comparator 725 uses three programmable binary thresholds that define four .
W093/2~ PCT/US93/04361 video signal amplitude regions. The bin_ry t~ old value~
are p~Gy.~med by CPU 780 at input 725. Thus, the two bit digital signal assigns the analog input ~ignal amplitude to four levelc. More particularly, the 8-bit digital value is S mapped into a quad level (8,9) modulated ~ignal which hAs two bits of dAtA per signaling interval.
This is ucually adequate when ~oce~sing monoc~ome signals. P~we~e~, when ~.Gcessing color ~ignals, this results in four pos~ible values for each of the R,G,B, (or Y,U,V) signals. Hence, only sixty-four different colors may be represented by the RVC 400. Further, assigning two bits :to each of the R,G,B (or Y,U,V) signals does not nece~eF~rily represent the best use of digital bandwidth.
In an alternate embodiment more than two bits could be used. For ex_mple, R~3, G=3, and B=2 bits (and similArly Y~3,U=3, and V=2 bits) may be used when _~.o~iate for the video eignals being ~c~ ~e~. Also, when other transmission system formats are used, fla~h ADC 724 digital threshold comparator 725 ~ho~ be ad~usted to provide _nd _n appropriate m-bit digital conver~ion rate and the desired mapping of the m-bit digital value of the sampled analog video data to an n-bit pixel data signal compatible with the system.
~ When the video signals VIDE0 at input 721 _re digit_l, typically a two bit signal, switch 723 i~ placed in the digital position (not shown), the video ~ignals VIDE0 are ~imply ~A~Fe~ through for further ~.oces~ing. Thus, in the present embodiment, the two bit digital pixel data representing the input video signal~ VIDE0 are available at node 726. The ouL~uL of circuit 720 provides the pixel data at ouL~uL 726 to video data ewitch 730, along with the vertical sync ~ E~ VSYNC at ouL~u~ 722v, the horizontal sync p~ es HSYNC at ou-~u~ 722h, and the phase locked horizontal sync p~lses PHASE T~D at ouL~u~ 722pl.
It has been realized that simply eampling the video ~ignals at the pixel frequency is not likely to be : CA 022~76~7 1999-01-12 W093/23958 -PCT/US93/~ ~1 ~ufficient to digitize the incoming video data at the proper sampling rate and phase. Sampling the analog video signals at a frequency different from the pixel rate of the video signal would result in aliasing the frame of pixel data and its sync pulse resulting from the difference between the two frequencies.
Sampling near the middle of each pixel minimizes any th~eshold ambiguity. H~wev6~, 6imply matchin~ the 6ampling frequency and the pixel rate frequency does not guarantee this will occur. ro~-equently, in accordance with the current invention, each video digitizer circuit 720 also contains two phase locked loop (PPL) circuits to meet the two criteria of frequency matc~in~ and mid-point 6ampling (collectively referred to as ~pixel phase lock~).
lS The video signal at input 721 can be arbitrary.
Therefore, it i8 impossible to determine the pixel clock frequency from the video data alone. However, the nominal horizontal scan rate and exact number of pixels n per horizontal line are known from configuration information supplied to RVC CPU 780. As noted, each display has a defined number of cell6 per row and a defined number of pixels per line in a cell and the video scan line used to display a line of pixels across the video screen is known, e.g., 63.5 ~s. This information may be used to generate a 2S divisor value for a ~divide by n~ counter 727, which value n is provided by CPU 780 at input 728. The ~divide by n~
counter 728 is thus loAded with a p,Gy,~mmed divisor n such that n is equal to the number of pixels per horizontal video scan line of the video 6creen 317 (total pixel~, not just visible pixels). The ouL~uL from counter 727 may be a pulse, since only the rising edge of the signal is used for phase lock ~U~ Çfi.
The 1~A~ i~g edge of the horizontal sync pul~e HSYNC input at 721h is p~SFe~ through an adjustAble delay circuit 728, and then is pAS~~ to one input of a first phase comparator 731. The other input to phase comparator 731 is the ouL~u~

CA 022~76~7 1999-01-12 W093/23 ~ PCT/US93/04361 of divide by n counter 727. Phase comparator 731 pro~lces an error signal that L~yL~-çnts the phase difference between the delayed pulse HSYNC and the vuL~uL of counter 727. This error 6ignal i6 then u6ed to adjust the frequency of a voltage cG.. L.olled oscillator (VC0) 732 so that sampling frequency matching phase lock is maintA~ne~. The error 6ignal i8 amplified a~Lv~,iately such that VC0 732 GuL~uL
frequency is driven in the direction to minimize the sampling frequency phase error.
: This phase comparator 731 is preferably a state-machine variety, since only the rising edges of the incoming signals are used for phase comparison. The phase comparator 731 also may incGL~o~ate sample-and-hold circuitry to minimize VC0 732 ouL~ frequency ripple, while maintaining an acceptably fast loop response. The Motorola MC145159 Frequency Synthesizer IC in~GL~GLates a sample-and-hold phase detector plus ~LG~Lammable counters, and may be used to implement much of the PLL circuitry of video digitizer 720.
The ouL~uL of the VC0 732 may not necess~rily be a precise 50/50 duty factor. Therefore, the oscillator is designed to run at twice the pixel frequency, and its output is fed into a ~divide by 2~ flip-flop 733. The ouL~uL from flip-flop 733 is a uniform square wave that is the sample clock rate at ouL~ 729 and, as noted, is input to divide -by n counter 727.
The phase ~G~L~ ol circuitry described above thus assures that the pixel sample clock at ouL~uL 729, which is generated by the RVC 400, matches the incoming video pixel data frequency at ouL~u~ 726.
A recon~ phase comparator 734 is used to compare the pixel phase with the sample clock at ouLyu~ 729. Thus, one input is the digital pixel data at node 726, and the other input is the sampling rate GuL~ from divider 733. The ou~ùL from the pixel phase comparator 734 i6 used to control delay circuit 728, which is preferably linearly CA 022~76~7 1999-01-12 WOg3/23g~ PCT/US93/~361 adjustable. The delay may be implemented as a simple variable RC circuit, ~ince only ~1/2 pixel delay must be proA~c~. When the delay is ad~u~ted by the pixel phase comparator 734, the phase reference for the pixel frequency is changed. This, in turn, proA~ce6 a comparable shift in the phase of the pixel sample clock at ou~uL 729.
Preferably, phase comparator 734 also is a state-machine variety to compare only rising edges of the input signals.
~owever, ~pecial consideration must be made in pha~e comparator 734 to acco~.~ for the arbitrary nature of the incoming video signal d~ta. In this regard, ph~se : comparator 734 must in~o-~G~ate a sample-and-hold type circuit, because phase error information may be proAl~c~ by only a dozen or 80 pixels (one character), while the ouL~
signal must be held stable for an entire video frame. The respon~e of the phase control loop must take into account the fact th~t phase error sampling may occur only once per video frame (e.g., every 16.7 ms).
Referring to FIG. 29, the 0~ 8 from the three video digitizer circuits 720 ro~ect to a 2-bit video data switch 730. Switch 730 is preferAbly operated in rotary fashion, 80 that each video input (illustrated a8 numbers 1, 2, and 3) is connected in turn for one video frame of pixel data.
As a result, each video ~ignAl input is sampled for changes once every three frames, for a signal transmission latency of about 50 ms. In the case of asynchronous monochrome inputs, the average latency may be slightly longer, and is ~epen~nt upon the frame phase relationships between the non gen-locked video signals.
The high sampling rate of each video signAl input assures that minor screen changes (e.g., blink;ng characters) are rapidly detected and broA~c~st quickly enough to maintain the desired visual effect on the video screens 317 of the decoders 316.

CA 022~76~7 1999-01-12 W093~ 8 PCT/US93/04361 Switch 730 also may be cv..L~olled by CPU 780 to cQnn~ L
selectively to one particular video input more or less frequently than the other inputs.
The v~L~L of switch 730 is a stream of pixel data cG~espon~g to one current frame of display information.
This pixel data i8 passed to a ~sy~tem image~ RAM bank 740, a ~last frame~ RAM bank 750, and a pixel comparator 760.
The pixel comparator 760 has a~ inputs the stream of pixel data from the ou~L of video data switch 730 cG~.e_ponAing to the one current frame of display information for a given video signal, the pixel data ~L e~ ,..i j ng to the last frame -of display information for the given video sign~l, which was previously ~tored in last frame RAM bank 750, and the pixel data correspon~;ng to the frame of dieplay information that is currently displayed for the given video signal, which was previously stored in system image RAM bank 740. The pixel comparator 760 u_es these three inputs to test for changes in successive frames.
The system image RAM bank 740 i6 a memory device (or an area of memory in a large memory device) contA;~ng a cache of pixel data correspondin7 to the images displayed on a system video screen 31~ for each particular portion of display information that i8 transmitted by the three video signals inputs. The cached pixel data match the ~net pixel change data~ previously transmitted to the encoADr 312, i.e., the pixel data for displaying the ouL~u~ display information co~ cpQn~; ~g to the video signals VIDEO and any ~ubsequent messages providing update data (pixel change data) for updating the ouL~u~ display ba_ed on differences between ~ccecsive frames of the source VIDE0. The net pixel change dat~ also is stored in 8 picture memory of each remotely located decoA~r 316 and i8 used to generate the G~ L images di~played on a video ~creen 317. As explained in more detail below, the pixel data contained in RAM 740 for any given frame is only updated when update data messages are broadcast, e.g., to or by an encoder 312, CA 022~76~7 1999-01-12 W093/23958 PCT/US93/~361 thereby to update the pixel data digplay information held in the ~_~e_Live memories of the remotely located AecoA~r~ 316 and ~ystem image bank 740.
The last frame RAM Bank 750 i5 a memory device (or an 2 5 area of memory in a large memory device) contAin;nq pixel data for the la~t frame of display information for each input video signal. The 'G~ ~e~ron~ing pixel data for each ~la~t~ frame of display information in RAM 750 is completely updated with the ~current~ pixel data for that frame (from video data switch 730) as the ~current~ frame pixel data is compared with the cGL.esponAing prior last frame and the - sy~tem image frame.
The ~yetem image and last frame RAM banks 740 and 750 are organized with byte-wide (8-bit) data paths. This allows the data to be read and written with a 120 ns cycle time at the VGA data rate. Buffering and wider memory organization may be used, if necefir-ry, to further increase cycle time.
Once the video data switch 730 h~s selected a new video ~ignal input c~nn~l ~ the last frame RAM Bank 750 is operated in a ~Read-Modify-Write~ mode. This allows the contents of the RAM 750 to be read into pixel comparator 760, while new data from the ou~u~ of video switch 730 is written into RAM 750 later in the same cycle.
The pixel comparator 730 ~G~e~re~s the three input frames of pixel data to determine if a valid pixel change has G~ Led. If the current frame pixel data (2-bit value) matches the last frame pixel data, and the~e data are different than the corresponA~ng pixel data retrieved from the system image RAM bank 740, then a change over two successive frames has been detected and it is considered that a valid pixel change has been detected. If, instead, the current pixel data does not match the last frame data, - then it is considered that either the last frame or the ~LLê~-~ frame cont~n~ an error (noise) or it does not ~oLLeO~o~.d to a valid change. In other words, the system waits for correspon~ing pixels in two s~ccesfiive frames to CA 022~76~7 1999-01-12 W093/2~ PCT/US93/04361 be different than the ~v,,~,po,~ g pixel in the system image frame before ~clAring that a valid pixel change has G~ ed .
Even though the RAMs 740 and 750 may be delivering byte-S wide data, each set of correrponAi~g 2-bit pixels is preferably compared ~nAep~nAPntly. The two bits represent four possible different inten ity levels. The vu-~L from the pixel comparator 760 ic a two bit value ~e~ enting the absolute value of the pixel intensity change. The ouLpuL i8 pA~e~ to pixel data change circuit 770 for ~.v~e~sing and identifying pixel change data that is to be provided to an ~ncoA~r 312.
The foregoing comparison algorithm is highly immune to noise, ~ince only ~table (but changed) pixel data is flagged as changed. If gre_ter noise immunity i8 desired, additional ~next to last~ frame RAM devices could be used and the algorithm modified to wait for more than two conse~tive frames to have the same changed pixel data different from the system image.
Referring to FIG. 29, pixel data change circuit 770, in the preferred embodiment of the present invention includes a cell change RAM device 771, a change threshold comparator 772, a ~Gl.L.ol logic device 773, a cell address change fir~t-in-first-out (FIF0) device 774, and a binary adder 775.
The cell change RAM 771 is a small RAM memory bank (or an area of memory in a large memory device) partitioned into cells 776 6uch that each cell 776 ~Gl.~v~O~ to one cell 210 of a video screen image of display information and each cell 210 (FIG. 12) can display a display character, e.g., an alphAnl~meric or ascii character. Each cell 776 contains an 8-bit binary value representing the sum of the absolute value of the intencity level rhAng~ of the pixels in the cell. Thi~ ~um is referred to as a 'weighted sum~ because it reflects the magnitude of the intensity level difference of the pixel~, and not just the number of pixels that have CA 022~76~7 1999-01-12 W093~239~8 PCT/US93/~361 changed. In other words, a larger inten~ity change i~ more significant than a smaller intensity change and the magnitude of the change is weighted accordingly.
In the present invention, there are eno~gh cell~ 776 in cell change RAM 771 to compare each cell 210 of a video frame of di6play information transmitted by the input video ~ignals, and thus RAM 771 need only be 1/16th the size of either ~y~tem image or last frame RAM bank 740 and 750.
Preferably, RAMs 740, 750 and 771 are di~crete memory devices with DMA access so to minimize the time required to read and write data.
: The cell change RAM 771 is operated in Read-Modify-Write mode. The contents of one cell 776 are read and numerically added, at binary adder 775, to the pixel change value that is supplied by the pixel comparator 760 for the cGL~e~o..ling cell 210 of display information. The weighted sum is then rewritten into the same cell 776 in the same cycle. Thus, each cell 776 acts as a cumulative counter that is incremented by the pixel change value from comparator 760 corresponAing to the absolute value of the intensity change. The data in a given cell 776 of cell change RAM 720 is reset to zero when the RYC CPU 780 or the encoder 312 broadcasts the pixel change data co~e~lo.~ling to the given cell 776 to the encoder 312 or decoA~r 316 respectively.
In a preferred embodiment, the corresponAing cells 210 of the current video frame, last video frame and pixel map for a complete page 200 of display information are compared, one cell at a time, and the corresponAing cells 776 are updated with pixel change values. At the end of each complete frame 200, each cell 776 for that frame 200 contains a binary value that represents the weighted ~um of the absolute values of the number of pixel data changes in the corresponAi~g cell 210, since the cell 210 was last updated and the cell 776 count was last reset. Each cell 776 thus CA 022~76~7 1999-01-12 WO93/~K~ PCT/US93/04361 holds the weighted sum of 128 pixel change values, since each cell 210 contains 128 pixels.
For example, referring to FIG. 29, no pixel changes have been detected for the cells labeled 776a and 776b. However, 7 weighted pixel counts have been detected for the cell labeled 776c in row 1 column 3. The cell labeled 776d in row 2 column 2 holds the value FF, indicating that at least 255 weighted pixel changes have been detected. Since each cell 776 only holds an 8-bit value, the binary adder 776 must Jclamp~ the total at FF, and not allow the weighted count data to rollover. Note, the maximum possible weighted sum for a cell having 128 pixels and four intensity levels (two bits per pixel) is 512.
The change threshold comparator 772 is a binary comparator whose threshold is ~LoyLammed by the CPU 780.
Whenever a cell change value, i.e., the weighted ~um ouL~uL
from adder 776, reaches that preset count threshold, the ~G.IL.ol logic device 773 is actuated to load the address of the cell 210 ~Gl.e~l,on~;ng to cell 776 into the cell change address FIFO device 774. The comparator 772 is enabled only during the comparison of the last pixel 220 of each cell 210 (i.e., the lower right-hand pixel) to minimize multiple detection of cells 210 with substantial changes.
During periods of minimal change activity, the CPU 780 may ~LGyLam the count threshold as low a 1, thereby enabling it to detect single-level single-pixel changes in a given cell 210. However, during periods of high sy~tem activity, or during rapidly changing video frames, the count threshold may be selectively ~lG~.ammed at a level high ~no~-gh to reduce message traffic to an acceptable level and still detect ~ignificant changes in the video information that will provide an accurate di~play to the user.
The cell address data that is contained in cell change address FIFO 774 is later used by the ~Gl~Ve~ Ler CPU 780 to identify those cells 210 with cumulative weighted pixel changes at or above the predetermined count threshold. In CA 022~76~7 1999-01-12 W093/239~8 PCT/US93/04361 this regard, the CPU 780 may ~imply ~CCeF6 the FIFO 774 to determine the cell 210 addresse~ cG~.~~pQn~i~g to cells 776 with above threshold changes, rather than 6equentially r~A~ing every cell 776 in the cell change RAM 771.
Further, by lo~ing the cell ch~nge values into the FIFO
774 along with the cell 210 addresses, the cG..ve~Ler CPU 780 can make further priority decisions reg~rding the order in which cell 210 pixel change data is bro~c~st.
The cG..L.ol logic device 773 is ~e_~G..~ible for coordinating and synchronizing the actions of the RAM banks 740 and 750, pixel comparator 760, threshold compar_tor 772, - and cell change address FIF0 774. It also interrupts the CPU 780 at the _~G~li_te time to initiate retrieval and manip~ tion of pixel data.
RVC CPU 780 is responsible for configuring all the various cGI.~Lol registers within the RVC 400 and for retrieving and m~nipulating the pixel data in the indicated or identified cells 210 with changes. After a complete video frame has been digitized and compared, the CPU 780 is interrupted by the control logic 773. The CPU 780 then performs the following functions: (1) Addresses of cel}s 210 with correspon~i~g cells 776 having counts at or above the predetermined count threshold are read from the FIFO
774; (2) Pixel data for changed cells 210 co..e~~,G~.ling to cells 726 in RAM 775 are transferred to the CPU RAM 781 from the system image and last frame RAM banks 740 and 750 (this dual transfer G~ because the ~current~ frame pixel data has by this time already been written into the last frame data via DMA bus 785); (3) new pixel change data are written from the last frame RAM bank 750 into the system image RAM
- bank 740 (viA DMA bus 785); (4) Updated cells 776 in the cell change RAM 771 are zeroed for detection of new change - data and non updated cells 776 are left as incremented, if at all, such that pixel changes in subsequent frames may cause such cells to exceed the established count threshold;
~nd (5) Message(s) containing update data, i.e., the pixel CA 022~76~7 1999-01-12 W093/23 ~ PCT/US93/04361 change data from the changed cell6, are prepared for broAAcA~t to the system encod~r 312, for distribution to remotely connected A~coAers 316 during sAmpling of the next frame of display informAtion.
The CPU 780 should be fast enough to handle modest _mounts of video changes during the vertical blanking interval (1.4 ms). ~ho~lA the CPU 780 become overloaded with ~,~,o.-e~ changes, the ~G-.L,ol logic 773 may be configured to insert blank video frames between actual frame comparisons, thereby allowing the CPU 780 to access the RAMs 740, 750 and 771 for extenA~A periods of time. The only side-effect of inserting blank frames is a temporary increased latency for broA~cAfit of pixel change information.
The CPU 780 software should be capable of detecting certain special case video changes. For example, a screen going completely blank should be detected and ~n~o~A
without requiring direct messaging of each pixel.
The CPU RAM 781 preferably contains exe~uLable code, ~L Gy~ -m data, and pixel data. Pixel data are temporarily moved from the system image and last frame RAM banks 740 and 750 via bus 775 to the CPU RAM 781 for generation of pixel change data messages as explained below.
In a preferred embodiment, RVC 400 is configured with an interface 783 that con~?cts to an ~ncoA~r 312 via two buses:
a mono-directional data bus 783d and a bi-directional co.,L,ol bus 783c. This allows the RVC 400 to format complete messages, and transmit each message to the encoAer 312 when instructed to do so by the encoder 312 or host CPU
425. By completely formatting the messages, and notifying the ~ncoA~r 312, the ~ocessing burden on the ~ncoA~r CPU
(not shown in FIG. 30) is substantially reduced. This results in increasing the message hAnAling capacity and thro~ L of the ~ncoA~ 312 and its ability to distribute more display information and update data more quickly to the plurality of AecoA~rs 316.

. . .

CA 022~76~7 1999-01-12 W093~23~ PCT/US93/~361 The encoA~r interface 783 typically receive~ polling signal6 from an ~nroAPr 312 to determine whether an RVC 400 has any penA~ng me~r~ . At the poll, the RVC 400 empties its ou~ message gueue into an input message gueue for the ~ncoAer 312. The polling i6 preferably performed at a configurable rate (nominally .25 sec).
Further, the RVC 400 is preferably ~nLlolled by host CPU
425 and include6 a host computer interface 484. The host CPU 425 provide~ the RVC 400 with co..L~ol information, over ~ bus 784b. From the pe~D~e_Live of the ~ncoAPr 312, messages originating from RVC 400 appear to be updates to a pixel-based video or graphic tile rather than a ch~racter cell-based alphamosaic tile.
The host CPU 425 can, for example, tell the RVC 400 to:
tl) generate a test image, (2) enable/disable sampling of a specific video signal input, (3) set the input sampling interval (nominally .25 ~econA~), (4) assign a tile identification code to messages derived from a specified portion of a video image, (5) assemble a ~ ell~ complete image derived from a video input (rather than ~ust the changes), and (6) empty its ou~u~ gueue.
There are two types of user requests for an ouL~
display to which the RVC 400 is adapted to e_~G~d, a new page delivered by the information vendor, and an old page requested by a new viewer.
For a new page, RVC 400 creates and sends a blank screen message and thus reset6 the ~System Image~ and ~Last Frame~
RAM banks 740 and 750 for that video signal to all blanks.
As the new portion of display information i6 received from the information vendor, it may be 6ent to the encoAPr 312 for transmi6sion to the AecoAPr 316 and video screen 317.
There is a 3-frame latency delay that is insignificant when - compared to the time required for transmitting the new di6play information from the information vendor site over a telephone line to the client (i.e., subscriber) 6ite.

CA 022~76~7 1999-01-12 WOg3/23g58 PCT/US93/04361 When a new viewer reguests a portion of di~play information that is ~u-.e..Lly 6tored in the ~y~tem image RAM
bank 740, the RVC 400 immediately tran~mits the entire portion as an update message to the encoAPr 312 for transmission to the user reguesting the display. This latency is less than one frame time. Thereafter, the new user will receive only update data messages for that page in the ~ame manner as the existing user~.
It ~hould be understood that more or less than three - video digitizer circuits 720, with a~L~liate changes in the cG..e~ponAing ~witch 730 and data ~.G~e~sing circuits, - could be used in other embodiments for ~Gce~sing more or less than three discrete video signals and composite, non composite or both composite and non composite video signals using the ~ame residu~l video converter unit 400.
Advantageously, the ~e~Qnt invention provides for a reduced time to respond to a user'~ reguest to view a page - or ~2co~d of display information that i8 already being viewed by another user by cA~h;ng the ou~L di~play at the client's site, and providing the complete ou~L di~play as change information to the new user and cont;n~;ng to provide only relative changes in each of the plurality of cached portions to other existing users of that display - information. Further, the invention prorP~~?s video information in a manner that is essentially transparent to the user and does not add ~ignificantly to the time required to display a new page of information and reAllces the burden on an enco~Pr type device at the subscribers ~ite. Further, because each converter can be made as a module, ~ ll,ol~ing additional video signal ~ou~ea can easily be obt~;ne~ by adding more modules, without ~ignificantly burAen;ng the encoAP~ device.
Referring to FIGS. 11, 16 and 26 to 28, a ~eroAPr 316 in accordance with a preferred embodiment of the ~.&-ent invention i~ chown.

CA 022~76~7 1999-01-12 W093/23g58 ~CT/US93/~361 In the ~~ent invention, and with reference to FIG. 26, the ADcoA~r 316 of the present invention may be resident inside a de~k interface unit (DIU) 321, which is ~dapted to handle AecoA~r functionality, including mouse 319' handling, keyboard 319 and message retransmission/flow redirection, and to drive several video screens 317, and which may be positioned for the uee of one or more than one user on one or more trading diske 320. Preferably, a single DIU 321 is designed to ~u~oLL up to four individual users and thus includes ~onnectors for four keyboards 319, four mice 319~, and four color video ~creens 317. Alternately, the four color monitor ports may be configured to drive a total of twelve monochrome video screens 317.
As Aircl~r~~~ above in connection with FIG. 11, the decoAPr 316 may be installed as a separate printed circuit board assembly inside an enclosure also housing the video ~creen 317. This provides for a moAl~l~r-6ystem whereby each video screen has a unique display identification code stored in memory of the decoder 316, and thereby enh~nces restriction of ~ecure di~play information to authorized and permitted video screens.
Regardless of its location, each Ae~oAPr 316 (or DIU 321, and herein collectively referred to as ~decoder 316~) is provided to connect each user'~ input devices 319, 319' and video screens 317 to both the DV bus 314 and the control bus 318.
Referring to FIGS. 16 and 27, a preferred embodiment of a decoder 316 is shown. The Analog Front-End circuit 610 connects to the DV bus 314 and (1) receives the DV bus ~ignalc and maintains proper impeAAnce matching; (2) post-- egualizes the DV bus analog signal; (3) double-end clamps the signal for threshold setting; and (4) converts the quad-- level signal into a 2-bit binary signal.
The Analog Front-End circuit 610 provides a high impeA~nce input to maintain proper transmission line imp Ance matching; Overvoltage protection also is provided CA 022~76~7 1999-01-12 W093~3958 PCT/US93/04361 to make A~co~r 316 tolerant of electrical diD~u~AnceF.
The DV bu~ ro~Y~Al cable 314 will exhibit freguency A~penA-nt loss _nd group delay (dispercion) characteristics.
The magnitude of these effects AeponA~ upon the length and type of cable selected. For example, RG-59U will exhibit much higher loss per unit length at high frequencie~ than will RG-8U fo_m core cable. The Analog Front-End circuit 610 i~ thus preferably designed to accept widely varying signal levels and high freguency rolloff, AepPnAing upon its location along the DV bus 314.
Some form of additional adaptive equalization may be used : to correct for loss and Aispersion effects. This signal egualization improves the error performance and noise tolerance of the system.
To cG~el ~ the guad-level analog signal received from the DV bus 314 into _ 2-bit binary signal, detection thresholds are established by the analog circuitry. By double-end clamping the DV bus packet d hPAAer H signal, the Analog Front-End circuit 610 can determine the upper and lower signal levels and the three signAl thresholds as described.
The Front-End circuitry 610 then converts the guad-level signal into 2-bit binary input signal for processing by the Packet Reception ASIC 622.
The Analog Front-End circuit 610 also may be adapted to -receive, reconAition, and repeat the DV bus messaging data if the received signal level falls below a predetermined threshold. This repeater function could be bypA~s~~ by _ mechAnical relay ~ho~lA signal levels be adeguate, or if the decoAPr 316 i8 inoperative. The decoder 316 also may reconAition and repeat the television ~r ~y~am information signals on the DV bus 316 by using information contAined within the message he~APr H.
The Packet Reception ASIC 622 receives signals from the Analog Front-End circuit 610, and (1) A~coA~s the header H
to identify the beginning of e_ch packet d, p~Gyrams the dibit threshold levels, and determines the interleaving .

WOg3/23~ PCT/US93/~ ~1 depth; (2) creates horizontal and vertical 6ync r~l6~n for use by the Video OuLp~ Circuits 660 and TV n c~Pr 670; (3) performs error de~tection and co~le_tion (EDAC) on each data packet d received; (4) compares each data packet against the stored ~reception key~ information (a display identification code or an information identification code) to determine if the data requires further p~-~e-~ing by the ~eco~er CPU 690;
(5) inte~u~L~ the AecoAer CPU 690 at the begin~i~g of vertical blAnking so th~t updates m~y be made to the Video RAM 662 and Attribute RAM 664 of the Video Ou~u~ Circuit 660 (see FIG. 28); and (6) loads accepted data packets d - into the Mesr-ge Buffer 625, and interrupts the A~co~er CPU
690 for further ~locessing.
The incoming data is first stored in the Interleave RAM
642. The Packet Reception ASIC 622 then reads the data with the axes rever~ed, and performs the EDAC function. The Packet Reception ASIC 622 decodes the hPAAer bits to determine the interleave factor to reconfigure the interleave structure on a packet-by-packet basis. As with the encoA~r circuit, the AecoAer ASIC may be implemented by any number of circuits and structures, 80 long as the described functions are performed, which is within the abilities of a person of ordinary skill in the art.
The Message Buffer 62S is a dual-ported static RAM device that can be acc~Fe~ by both the Packet Reception ASIC 622 and the decoder CPU 690. Arbitration is provided by the co..vel.tional RAM co..Llol circuitry within the Mesr-ge Buffer 625 to prevent ~imult~neo~s access. Messages that have been decoAeA and error co~e_Led are compared against hardwired or previously enabled reception keys, which also are stored -- in the RAM of MessAge Buffer 625. Those messages that match ~e_eyLion key6 are then loaded into the RAM of Message - Buffer 625 from the Packet Reception ASIC 622. Once a complete message (that matches a reception key) has been loaded into the Message Buffer 625, the CPU 690 is notified via an interrupt from ASIC 622 over bus 623. The CPU 690 CA 022~76~7 1999-01-12 W093/23 ~ PCT/US93/W361 may then inte..~L its normal ~lGy~am operation and retrieve the complete messAge from the Message Buffer 625.
In the preferred embodiment, ~eco~Pr CPU 690 is a 32-Bit R~A~f-~ Instruction Set Computer (RISC) CPU having a S ~uit_ble y~Gy.am for cG.. ~olling ~PcoA~r 316 operations.
One such device is the LSI Logic Model No. LR33000 CPU, which i8 capable of executing an average of slightly less than one instruction per clock cycle, providing an execution speed of approximately 20 million instructions per FÇCQ~
~ (MIPS). The CPU 690 is preferably c_pable of both high speed ~ Gy~ am execution, and high speed dat_ transfer~ via its two ~Gylammable direct memory access chAnne~ DMAo and DMAl. It is responsible for (1) collection and processing messages that match ~ece~ion keys; (2) ~e_l,ot,lin~ to ~LO~Se~ messages by specific actions and modification of displayed information; (3) DMA transfer of video and _ttribute inform_tion to/from the v_rious video displ_y memories; (4) delivery and collection of data to/from the CGI.LLOl Bus Interface 626; and (5) collection of input information from keyboards 319 and mice 319'.
In an alternate embodiment, the functionality previously described may be accompli~hPA by a lower performance 16-bit CISC CPU such that a single decoAPr 317 may contain a CPU
690 which is a type 80188 CPU, thereby reducing the cost of ~ the decoder 317.
The CPU 690 has an associated ROM device 692 and an associated ~Gy~am and Data RAM device 694. ROM 692 preferably contains a 6mall amount of ~Gy~am ROM including, for example, the basic boot code, and rudimentary ~oy~am functions to allow the ~eco~Pr to perform self-test and communicate with the host computer 425 via the DV and cG-.~ol buses 314 and 318. Only basic operating functions are executed from ROM 692, thereby allowing system flexibility with executable code downloaded via the DV bus 314. Thus, upon power up, the CPU 690 will begin execution of the ~oy~am stored in ROM 692 first performing self-test CA 022~76S7 1999-01-12 W093/23958 PCT/US93/~361 _95_ of all circuitry, then acknowledging the ~tatus to the host 425 via the cv,.L~ol bus 318.
RAM 694 contains both executable code (instructions) and ~.oy~m data. In this embodiment, the bulk of the executable code for AocoAPr 316 i~ 6tored in the RAM 694, thereby providing maximum flexibility for reconfiguring the ~ecoAor operation. Alternately, of course, the entire ~vy m code could be cont~in-~ in ROM 692. Upon interrupt by the Packet Reception ASIC 622, the CPU 690 operates to DMA transfer the incoming message from the Message Buffer 625 to the ~vy~am and Data RAM. The CPU 690 may then resume normal ~oy.~m execution, and perform interpretation of the newly received message at a later time.
In one embodiment, a AocoAor 316 using a 20 MIPS
~v~e~-~Qr 690 can ~edLaW a complete bit-mapped graphics image (2 bits/pixel) in approximately 165 ms. ~he DV bus 314 can deliver a full screen graphics image in approximately 32 ms. Because the encoder 312 will not repeat a DV bus message until its refresh period (nominally 200 ms) has elapsed, no decoAPr 316 will lose a message due to overflow even under worst-case conditions.
Referring to FIGS. 27 and 28, the decoAer 316 preferably contains a number of identical video ~u~uL circuits 660.
Four are illustrated in FIG. 28. All video signals are preferably delivered to a single 60-pin connector 668 and conventional ouL~uL cables may be attached to connector 668 to drive four or twelve video screens.
Each video v~L~- circuit 660 (only one is described) accepts bit-mapped pixel data from the CPU 690 and displays the pixels on associated video ~creens 317 (not 6hown in -- FIGS. 27 and 28). Functions sUch as p3rning, ~crolling, bl;nking and insertion of live TV are ~ ' performed by the - video ouL~uL circuit 660. A single vic vuL~L circuit 660 can provide ~ignals to one VGA color video screens, or to three VGA scan rate monochrome video ~creens. When configured for three monochrome video screens, all three _ . .

CA 022~76~7 1999-01-12 W093~ ~ PCT/US93/04361 video 6creens may contain different information, with separate tiles and sync ~ignal~. ~c~e~er, limitations within the illustrated architecture of video G~ circuit 660 prevent use of the p~nn~ng and scrolling features when configured for non genlocked monochrome video screens.
Referring to FIG. 28, the video RAM 662 is preferably configured as 512K words of 32 bits each. During the active video time (non-blAnk~n~), the video ou~y~L circuit 660 reads pixel data from the video RAM 662 on a realtime basis.
-~At VGA scan rates, the video RAM 662 must supply a 32-bit ~word to the video data register 663 every 120ns.
The address bus 661 driving the video RAM 662 is multiplexed between the video ASIC 665 and the CPU 690.
During active di~play time, the video ASIC 665 ~GI.L~ols the address bus 661. During vertical blan~i~g the CPU 690 has control over the address bus 661. The Packet Reception ASIC
622 provides an interrupt to the CPU 690 to notify it that vertical blAn~1ng has begun, and commence any required data transfer6 by the CPU 690.
The CPU 690 utilizes the time during vertical blAn~i~g to load new pixel data into the video RAM 662 via DMA transfer.
When the video o~u~ circuit 660 is configured to drive a single color video screen, all the video data ~o~ ,on~C to the same video screen, and the CPU 690 may simply overwrite ~old pixel data with new data. Hcwe~e~, when configured to -drive three monochrome video screens, the pixel data contained in a 6ingle 32-bit word may relate to three ~ercn~nt screens. Therefore, the CPU 690 must first read the pixel data from the video RAM 662, modify the bits relating to the updated tile, and rewrite the pixel data into the video RAM 662.
Assuming a 120ns cycle time on both the video RAM 662 and ~-Gy~am and Data RAM 694, the CPU 690 can transfer approximately 6000 words during a single vertical retr~ce period (assuming negligible inte,.~L latency and DMA setup time). This is sufficient data to update approximately 188 CA 022~76~7 1999-01-12 W093/23 ~ PCT/US93/04361 cells on a single color video 6creen. Read and write transfers may be pipel;ne~, 60 that the read and write data may not relate to the ~ame cell6 on the ~creen. This reAl~ceF the number of cell6 that can be updated on a 6ingle monochrome screen during the retrace period to a~.oximately 94. Even 60, the data transfer bandwidth ~etlaen the CPU~s ~,Gyl~m and Data RAM 694 and the video RAM 662 far eYceeA~
the ability of CPU 690 to ~coA~ messages and format pixel data.
The video data register 663 receives a 32-bit word from the video RAM 662 approximately every 120ns during active video time. The ouLyuLs from register 663 directly drive the pixel multiplexor 666. Alternatively, multiplexor 666 may be an integral part of regi6ter 663 with 6election performed by tri-state ~G.-L~ol.
pAnning and gcrolling of display information is ~G..L~olled by the video ASIC 665, and m_y be implemented by a combination of video RAM 662 address manip~ tion and multiplexor 666. Implied movement may be performed by reading the stored data and rewriting it in the memory in the new addresses (one pixel at a time) or by adjusting the address when reading stored data for display.
The video palette DAC 667 is stAnAArdly available and provides RGB o~L~L signals based on a ~o~ammable color lookup table. It contains a 256 element lookup table, where each entry contains an 8-bit value for each of the three color ouL~L signals. The table is ~G~.ammed directly by the CPU 690 using data bus 661 and address bus 661A.
The video palette DAC 667 is capable of ouL~uLLing the three analog video signals (RGB) at VGA pixel rates (approximately 32 MHz). The values for each ouL~L are determined by indexing the internal RAM array of pallet DDC
667, based upon the address supplied by the video data multiplexor 666. The three GuL~Ls can represent RGB
signals for a single VGA color video 6creen, or can be used independently for three monochrome video screens. The video CA 022~76~7 1999-01-12 WOg3~W~8 -PCT/US93/04361 palette DAC 667 also can also be u~ed to combine sync 6~nAl~ with the video ~u y~L~, thereby providing composite video, if desired.
The video switc~ing circuit 680 allows the ~Pco~Dr 316 to feed alternative video input signals through to the video Gu~ from the AecoAPr 316. This swit~h1n~ is under realtime y~Gy~am ~v"L.ol. In addition, the Video Switching 680 provides a high speed video switch to select either the palette DAC 667 ~uLy~s or ouLyuLs from an optional TV
~ecoA~r 670. Signals provided by the video ASIC 665 co-,~,ol ~the actuation of these video switches, ba~ed upon the TV
signals selected, and the beam position on the video ~creen 317.
T~Aep~nA.~nt attributes may be assigned for each cell on the video screen(s). Therefore an Attribute RAM 664 is included for storage of these attribute values. Typical attributes include blink, highlight, cursor, panni n~
scrolling, etc. As with the video RAM 662, the CPU 690 may update the Attribute RAM 664 during the vertical blAnk;ng interval by enabling its address A and data D drivers.
The video ASIC 665 reads the Attribute RAM 664 during active video time once for every horizontal cell location (approximately every 240ns). The video ASIC 665 also coordinates the display of video information from the video ' RAM 662 and Attribute RAM 664. Once the CPU 690 has loaded ~the nececsAry data into RAMs 662 and 664, the video ASIC 665 will continuously display the stored information without the intervention of the CPU 690.
The video ASIC 665 co..L.olc (1) reA~ing data from the video RAM 662, and clocking it into the video data register 663; (2) r~A~;ng data from the Attribute RAM 664, and clo~king it into its internal registers; (3) cGl.~Lolling the video multiplexor 666 selection of data input to the video DAC 667 (neCe~-~Jy for pAnning); (4) generating pIo~e horizont_l sync, vertical sync, and blAnking signals for use by the video palette DAC 667 and video switchi ng circuits CA 022~76~7 1999-01-12 W093/23958 -PCT/US93/04~1 _99_ 680; and (5) generating co,.L~ol signal6 for actuation of the video switching circuit 680 to diQplay realtime television G~l am information signal6 and stored financial market information. Video ASIC 665 also may be implemented by any number of circuits and structure 80 long as the described functions are performed, which is within the abilities of a pereon of ordinary skill in the art.
Referring to FIG. 27, the ~G.,L.ol bus interface 626 connects A~coA~r 316 to a multi-point twisted-pair cGr.LLol bus 318. RS-422 or 485 drivers (or ~imilar interface devices) are used to send and receive differential signals : on cG-.L~ol bus 318. The COnLLO1 bus interface 626 is interrupt-driven using industry-~tA~d~rd techniques.
The keyboard interface 682 provides a serial interface to a number of, for example, four, Qh~k,~ type keyboards 319.
Keyboard data is retrieved from the keyboard interface 682 via the data bus 661D once an interrupt has been received.
Keyboard 319 is preferably operated in a block transfer, multidLo~ed, polled mode. Key~L-okes are not made 20 - available to the ~ystem until a block terminator i8 entered.
At least two types of keyboards may be used: One with an internal LCD display and one without. The LCD display preferably Du~GLLs two lines of data with forty characters each. The keyboard may be similar to a sta~rd IBM
keyboard with twelve function keys across the top.
Keyboards 319 are connected to the host CPU 425 through the cG..LLol bus 318. The ~G~ ol bus 318 allows a maximum of 63 desk interface unit 321 per cable, or a theoretical maximum of 252 keyboards (assuming 4 keyboards are attached to each DIU 21). Sy~tem response time is a function of the information content, the number of DIUs 321 per cable, and the transmission rate. A polling period of approximately .2 ~econds can be achieved with 63 DIUs 321 at a 38.4 Kbaud rate. This means that an outst~nAing request on control bus 318 will be presented to the syctem in at most .2 seconds, CA 022~76~7 1999-01-12 wOg3~ PCT/US93/~ ~1 even if all DIUs 321 on the same cable have outs~anA~ng reguests.
-Typed characters are displayed on a video ~creen without any ~a~cE~Lible delay. The polling cycle of .2 reoonAC is ~nAAe~uate for thi6 purpo6e. Therefore, the A~coAer 316 ~e-:rq- the keycLLokec, buffers them and al~o immediately creates a display ouL~L in the ~elected location on the - selected video ~creen 317. When the next poll O~ULD~ the APcoApr 316 will not respond with the buffered characters ~unless a block terminator has been entered prior to the , ~ A .p O 1 1 --If there is an individual APcoAer 316 for each display monitor 317 rather than a DIU 321, keyboard and mouse commands are ~till communicated to all ~coAers by interco~ne~Ling them. This configuration i~ functionally identical to a DIU configuration, exce~L that the ability to gen-lock must be externally messaged.
The mouse interface 684 provides a serial interface to, for example, four mice 319~. Mouse data is retrieved from the mou~e interface 684 via the data bus 661D, once an interrupt has been received. Simply providing mouse 319' functionality to A trading desk can ~ignificantly raise the cost of A trading room. Without the present invention, the ~workstation must either be located at the trading desk or PYpPncive cabling and signal amplifiers must be used to transport the mouse signal between the eguipment room and the trading desk. Advantageously, according to the present invention, the encoA~r and AecoAPr information distribution system performs most mouse signal ~ocessing locally at the desk and when a~G~iate communicates the result to the eguipment room via the multid~pad cGllLLol bus 318. ~his design also reA~ce~ the ~G~e~sing load on the host CPU 425.
Mouse 319' functions are broadly classifiable as (1) cursor motion and/or field highlighting, (2) clicking, and (3) dragging. All mouse 319' actions exce~L clicking are handled locally at the tr_der's desk. Mouse clicks are CA 022~76~7 1999-01-12 WOg3/23958 PCT/US93/~361 transmitted tl~uyh the polled keyboard 319 to the host CPU
425, which then acts upon them.
Referring to FIG. 12, each video screen 317 has page-APpPnADnt default settings for cursor style and/or field S h~ghl ~ghting for each tile 250. The mou~e position on the ~creen is communicated instantly through the keyboard 319 to the APcoA~r 316 which then temporarily overwrites the selected cells in the required manner. The cursor (not ~hown) is ~moothly moved on a pixel-by-pixel basi6.
Ovcl~itten cell~ 210 are buffered within the AecoAPr 316 and are repl~ced when the cursor position i~ moved away.
: When required by the application generating the displayed page, the cursor may be replaced by automatic field highlighting without any required click input.
Clicking, the ~o~e5s of pressing and releasing a mouse button, or double clicking, the ~IG~e_S of clicking a mouse button twice in rapid F~ccescion, indicatec that the application generating the ou~L display muet take some computational action in ~e ~G..se to a user request. Mouse clicks (and/or double clicks) are transmitted through the polled keyboard 319 to the host CPU 425. The host CPU 425 then executes the indicated action and the results (e.g., new tiles 250) are then transmitted through the encoA~r 312 to the appropriate video screen 317. The polling rate is sufficiently high that no perceptible delay is generated by this signaling methodology.
Dragging is the ~o~e~s of holding down a mouse button while moving the mouse. Most mouse applications do not drag the ~contents~ of the window. That is, the window and its contents remains stationary while a new temporary substitute marguee border i6 drawn and moved across the video ~creen.
When the button i8 released the temporary substitute marquee border is removed and the contents of the window are redrawn at the new location on the screen. The contents of the window are not continually redrawn as it is dragged across the page to reduce the amount of CPU processing that would CA 022~76~7 1999-01-12 .
WO93/2~K~ PCT/US93/04361 be reguired to constantly rewrite the video memory.
Applications th~t ~edlaw the contents while being dr~gged ~ignificantly load the CPU as evi~nceA by the inability of all but the fastest machiner to Xeep up with rapid dragging.
It is not practical to have a ~ingle host CPU machine ~lG~e~S multiple composite pages of windo~ d~agging simultaneously unless this border substitution methodology ic employed.
The ~malle~t part of the composite page 200 that may be -- dragged is a tile 250. The tile ~ubstitute marquee border _v may be moved to ~ny location on the display ~creen; the tile 250 will be ~snapped~ to the nearest cell 210 ho~nA~ry when ~e~-~wn.
When a mouse button is pressed, the ~button down~ command is sent to the host CPU 425; when it is released, the ~button up~ location of the mouse and ~elected tile 2S0 identifier are transmitted through the polled keyboard 319 to the ho~t CPU 425 which acts upon them by (1) transmitting ~ Define Tile Location command byte to the ap~. G~L iate A~coA~r redefining the new location for only that video ~creen, and (2) refrech~ng the entire tile 250 to all A~coAers 316 pL~-ently displaying the tile 250. Symbolic signaling is preferably employed 60 that all ~h~equent updates to that composite page 200 will be transmitted only once, regardless of how many ~PcoA~rs 316 have had their -- tile locations moved.
Mouse y~o~e~sing is effectively decomposed into two parts (1) local yLoce2sing of all high bandwidth video redrawing operations and (2) remote application processing followed by a one-time redrawing of the video screen. Local (i.e., di_tributed) handling of high bandwidth page drawing associated with mouse motion reduces the CPU load on the remote application generating the ouL~uL display. This can be significant when the remote application is generating many interactive mouse tile changes.

CA 022~i76~i7 1999-01-12 W093/239~8 PCT/US93/~361 Provision iô also mAde for the host CPU 425 to ~ .d to e~ and other requests. Each me~sage that goes out to a coA~ 316 i~ ~eguentially numbered. When a given ~Pco~er 316 ~e~-?S an out-of-sequence message number, it re-requests the missing messages by 6en~ing the number of the la~t message received to the host CPU 425 via the ~ ol bus 318. To save ~GceOsing time, all keyboard 319 requests are concatenated and action iô only t_ken after all keyboards 319 on the CGl~L~ ol bus have been polled at least once. In effect, this means that the host computer 425 will make one polling loop around all decoAPrs 316 on the cG,.L.ol bus before respQn~jng to an error request. If the Bit Error Rate is 10-9 at A throughput of 25 Mbit/sec, then on average there will be 0.025 error requestO per ~ecG.,d or 1 error retransmission reguest every 40 ~ DnAC.
In a preferred embodiment, the encoder 312 is capable of caching at least 500 composite pages 200 (100 x 30 characters per page) including cell attributes, and Otoring at least 4,000 tile names and have a memory base address set to any one of four locations using a Berg clip. The Host CPU 425 input/ouL~u~ ôh0uld include a base address set to any one of four locations using a Berg clip and an interrupt (if reguired) may be set to any one of four locations using a Berg clip. The data throughput is at about 2.5 MB/Oec (20 Mbit/Oec) after protocol processing in the Ah-ence of any co-transmitted TV signals, and each co-transmitted full screen TV signal may not degrade the data throughput by more than 0.5 MB/sec (4 Mbits/Oec). Codeword lengths for the video screen display ID code may be 21 bits (2,097,152 possibilities) and the tile information ID code may be 24 bits (16,777,216 possibilities). A preferred diOplay screen 317 includes screen attributes of 100 horizontal cells and 30 vertical cellO, each cell having 8 horizontal pixels and 16 vertical pixels, with each cell blinking at 4 rates of on/off; ~crolling for 2 separate alphamosaic tiles of any size, up or down, with ô0ft or hard scrolling, with 4 soft WOg3/2~ PCT/US93/04361 rates; r~nn1ng for 4 ~eparate alphamosaic tiles of any ~ize, left or right, with 4 soft p~nning rates. Also, the character size may be ~ingle, double, triple, or quadruple height and width. Up to 8 different simultaneous realtime S TV 6ignals, having a total di~play area of not more than four video screens, each diFplayable at full, 1/4 or 1/8 screen size may be ~ Gl ~ed. Each TV eignal may be shifted horizontally to within 1 cell, but may not be vertically shifted (unless a frame store RAM i6 used in place of a picture store RAM 662 in the ~eco~r8).
Numerous alterations of the ~tructure herein disclosed - will suggest themselves to those skilled in the art.
However it is to be understood that the embodiment~ herein disclosed are for purposes of illustration only and not to be construed as a limit~tion of the invention.

Claims (18)

1. A method of transmitting display information including alphanumeric characters suitable for display on a pixel-based video screen comprising the steps of:
defining the pixel-based display area as a plurality of cells arranged in rows and columns, each cell having a plurality of pixels arranged in rows and columns, each cell having a preselected location relative to an origin, and each pixel in each cell having a preselected location relative to a cell origin;
selecting the cell dimensions to correspond to the dimensions of a normal-sized alphanumeric character of display information;
providing each alphanumeric character to be displayed with a unique byte of data representing that character;
providing the display information in digital form so that there is one or more bits of data for each pixel;
processing the digital display information to identify each display cell containing an alphanumeric character and replacing the bits of data for each pixel in said identified display cell with the byte of data corresponding to the identified alphanumeric character; and transmitting the processed digital display information so that one byte of data per cell is transmitted for each identified cell containing an alphanumeric character and one or more digital signals per pixel are transmitted for each cell not containing an alphanumeric character.

2. The method of claim 1 wherein the one or more bits per pixel are transmitted either pixel row by pixel row or pixel column by pixel column in each cell.

3. The method of claim 1 wherein the transmitting step further comprises transmitting the display information one cell at a time.

4. The method of claim 3 wherein transmitting the display information one cell at a time further comprises transmitting the display information either cell row by cell row or cell column by cell column.

5. The method of claims 1-3 further comprising run length encoding the display information to be transmitted for contiguous cells having the same alphanumeric character and transmitting run length encoded signals for the same byte of data in said contiguous cells.

6. The method of claim 5 further comprising run length encoding the display information to be transmitted for contiguous pixels having the same display information and transmitting run length encoded signals for the same bits of data in said contiguous pixels.

7. The method of claim 1 wherein processing the display information further comprises identifying the portion of the display information that has changed since the display information was last received, and wherein transmitting display information further comprises transmitting a selected portion of the display information in the form of a tile comprising a selected number of contiguous rows and columns of cells, an offset from the origin, and at least the changed display information.

8. The method of claim 7 wherein transmitting a tile of display information further comprises successively transmitting the display information for the cells in the tile, one cell at a time, either cell row by cell row or cell column by cell column, using cell wrapping so that the successively transmitted cells are capable of being stored in a memory relative to the tile offset and the selected number of tile rows and columns.

9. The method of claim 8 further comprising receiving the transmitted signals at a receiver, processing the received signals to convert the one byte of data for cells having one byte per cell into multiple bytes of data per cell corresponding to the pixel representation of the character, and storing the received and any converted signals in a memory device.

10. The method of claim 9 further comprising mapping the transmitted tile of display information onto a display tile having a second selected number of rows and columns of cells and a second offset in the memory of the receiver so that the transmitted tile of display information not falling within the second selected rows and columns of the display tile are not stored in the memory.

11. The method of claim 1 further comprising receiving the transmitted signals at a receiver, storing the transmitted display information in a memory device at the receiver and displaying the stored contents of the memory device on a video screen associated with the receiver, and optionally updating the memory to display the memory contents with implied motion.

12. Apparatus for transmitting display information including alphanumeric characters suitable for display on a pixel-based video screen comprising:
a pixel-based display area organized as a plurality of cells arranged in rows and columns, wherein each cell includes a plurality of pixels arranged in rows and columns and has a preselected location relative to an origin, and each pixel in each cell has a preselected location relative to a cell origin, the cell dimensions corresponding to the dimensions of a normal-sized alphanumeric character of display information;
means for providing each alphanumeric character to be displayed with a unique byte of data representing that character;
means for providing the display information in digital form so that there is one or more bits of data for each pixel;

means for processing the digital display information to identify each display cell containing an alphanumeric character and replacing the bits of data for each pixel in said identified display cell with the byte of data corresponding to the identified alphanumeric character; and means for transmitting the processed digital display information so that one byte of data per cell is transmitted for each identified cell containing an alphanumeric character and one or more digital signals per pixel are transmitted for each cell not containing an alphanumeric character.

13. The apparatus of claim 12 wherein the transmitting means transmits the display information one cell at a time, either cell row by cell row or cell column by cell column.

14. The apparatus of claims 12 or 13 further characterized by a processor for run length encoding the display information to be transmitted for contiguous cells having the same alphanumeric character wherein the transmitting means transmits run length encoded signals for the same byte of data in said contiguous cells.

15. The method of claim 14 wherein the run length encoding processor also run length encodes the display information to be transmitted for contiguous pixels having the same display information, wherein the transmitting means transmits run length encoded signals for the same bits of data in said contiguous pixels.

16. The apparatus of claim 12 wherein the processing means further comprises means for identifying the portion of the display information that has changed relative to previously received display information, and wherein the transmitting means transmits a selected portion of the display information in the form of a tile comprising a selected number of contiguous rows and columns of cells for displaying at least the changed display information, and an offset from the origin for positioning the tile in the proper relative location for updating the portion of display information.

17. The apparatus of claim 12 further comprising means for storing the transmitted display information in a memory device at a receiver and means for displaying the stored contents of the memory device on a video screen associated with the receiver, optionally with implied motion.

18. The apparatus of claim 17 wherein the processing means further comprises means for identifying the portion of the display information that has changed relative to previously received information, and wherein the transmitting means transmits a selected portion of the display information in the form of a tile comprising a selected number of contiguous rows and columns of cells relative to the origin and including at least the changed display information, and wherein the storing means stores the transmitted display information by writing the transmitted cells of display information over the contents of the memory relative to the origin so that the contents of the overwritten memory contains the changed and unchanged display information.