CA2134012C - Interface card for testing personal computer main boards - Google Patents

Abstract

An interface is provided in the form of a card, for plugging into an expansion bus socket of a personal computer main board including a microprocessor, the card having an external interface through which it may be connected to a further personal computer acting as a test controller. The card carries random access memory which can be written sequentially through the external port and located to a portion of the memory space of the microprocessor normally occupied by a read only memory on the main board. Once written, the content of the memory can be accessed in a random access basis by the main board in response to addresses appearing on the expansion bus which are in that portion of the memory space. The board also provides for communication between the test controller and the main board via an address in the input/output port space of the microprocessor. This arrangement enables the test controller to test both programs for use in said read only memory space, and the hardware of the main board, without a substantial investment in specialized hardware.

Description

213~012 INTERFACE CARD FOR TESTING PERSONAL COMPUTER MAIN BOARDS

This invention relates to apparatus for the testing of the main boards of personal computers, and for aiding the development of program code and other data intended to be written into read only memory located on or associated with such boards.

The most widely utilized personal computer configuration has a main board, also known as a planar board, or colloquially as a "mother" board, which carries a number of sockets or groups of sockets whose contacts are connected to an expansion bus in the form of a standardized array of signal, ground and power connections so that printed circuit cards implementing various peripheral functions may be plugged into the planar board. In most cases, a microprocessor, at least some random access memory (RAM), some read only memory (ROM), bus interface circuitry, and at least some further functions are located on the planar board, but in some cases these also may be located on a card which plugs into one of the bus sockets. For the purposes of this specification such an arrangement will be regarded as equivalent to one in which at least the microprocessor, ROM and interface logic are normally installed on the planar board.

A function of the ROM in a typical personal computer is to provide program routines which initialize the computer at power-on or following a reset of the microprocessor, usually following some power-on self test (POST) routines, and which initiate loading into memory of an appropriate operating system providing a user interface to the computer and its peripherals. The program contained in ROM will also typically provide for the operating system various low-level ~340 ~2 functions interfacing the operating system to basic hardware of the computer. The nature of the functions performed by the ROM
make in situ testing and diagnosis of both the ROM program and the hardware controlled by it quite difficult to accomplish (except for diagnostic test routines built into the ROM program) because proper function of the ROM program and the hardware it controls are a precondition to loading of the operating system which provides a user interface to the computer, while the operating system itself will normally require the presence of appropriately initialized peripherals such as a disk subsystem and console components in order to function.

Pr;or Art To date, resolution of the testing problem has required the use of specially developed test equipment, which is complex, expensive, and insufficiently portable to be useful except under factory conditions. It also needs in most cases to be configured specifically for a particular design of planar board so as to accommodate the characteristics of that board. Such devices typically provide plugs which are inserted in the board or card under test (CUT) in place of its regular microprocessor and ROM
chips, usually together with further connections which may involve special connectors or test jigs. Such an arrangement does not, of course, test the actual microprocessor to be used on the CUT, and depends among other things upon the accuracy of the emulation of the microprocessor by the test system. Examples of such units are described in U.S. Patents Nos. 4,868,822 (Scott et al); 4,989,207 (Polstra); 5,068,852 (Locke); and 5,136,590 (Polstra et al); all assigned to John Fluke Mfg. Co. Inc.; 4,622,647 (Sagnard et al) assigned to Rank-Xerox S.A.; and 4,796,258(Boyce et al) assigned to Tektronix, Inc.

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It has also been proposed to provide ROM emulators for diagnostic testing and program development purposes, as in U.S. Patent No. 4,691,316 (Phillips). Read only memory is comparatively easy to emulate, but an emulator which 5 provides simply a plug in replacement for conventional ROM
chips cannot provide on its own sufficient facilities for monitoring the operation of the CUT, thus requiring additional monitoring equipment which must be connected to the card, as exemplified for example by U.S. Patent No.
4,691,316. Other emulators, such as that of U.S. Patent No.
4,691,316 rely on overdriving control lines of the card under test in order to superimpose the emulation over resident ROM, and thus operate the CUT under abnormal conditions.
There is, therefore, a need for a means for testing planar boards, or programs incorporated in ROMs on such boards, which is economical, versatile, and requires no special connections to or overdriving of the CUT.
Statement of Invention The invention provides an interface for testing hardware or firmware of or accessed through a main board of a personal computer, the main board as tested including a 25 microprocessor, provision for receiving firmware comprising a control program in read only memory located in a defined portion of an address space of said microprocessor, and having multiple sockets providing access to an expansion bus including data, address and control lines. According to the 30 invention, the interface comprises a printed circuit board for plugging into one of said multiple sockets, an external port on said board providing data and control lines and adapted for connection to a complementary external port on a computer programmed to act as a test controller, said board further including random access memory and control logic which, responsive to signals received through said external port, first controls sequential writing of program data into said random access memory using data received through said external port, and locates said random access memory in said defined portion of said address space of the microprocessor, and thereafter monitors addresses appearing on the address lines of said expansion bus and applying addresses within said defined portion of the address space to said random access memory to present program data at such addresses in said random access memory to data lines of said expansion bus.

Preferably the control logic further includes means to recognize a combination of signals on said expansion bus representing a predetermined input/output port address, and register means for transferring data between the data lines of said external port and data lines of said expansion bus in response to such recognition.
IN THE DRAWINGS
Figure 1 is a diagrammatic drawing illustrating the interface of the invention and its relationship to a card under test and to a test controller;
Figure 2 is a diagrammatic drawing similar to Figure 1, but illustrating in more detail the programming of the interface;
Figure 3 is a diagrammatic drawing similar to Figure 2, but illustrating in more detail the testing of the card under test; and Figure 4 is a diagram showing in more detail the functions of the logic module shown in Figures 1-3.

Preferred Embodiment .. . . ~ . . . .

For the purpose of description, and referring to Figure l, it will be assumed that the card under test (CUT) 2 is the planar or main board of a computer utilizing the ISA (Industry Standard Architecture) bus as originated in the PC/AT (Trademark) computer or extensions thereof. This bus provides access to twenty address lines necessary to define a 20 bit address, and 16 data lines defining a sixteen bit data word, as well as numerous control lines, power supply lines and ground lines. As such it is typical of microcomputer expansion buses which provide access to address, data, control, power and ground lines adequate to provide full communication between a microprocessor MPU and its memory and peripherals, and the principles of the invention are also applicable to such other similar buses.
Access to the bus is provided through a number of sockets 4 mounted on the CUT, each of which is adapted to receive a plug-in peripheral card. The interface of the invention is implemented as such a peripheral card 6 which has a card edge connector 8 plugged into one of the sockets 4 and establishing connection to as many of the available bus lines as it is required to use, including, in the present instance, access to all of the address and data lines, access to ground and power supply lines, and access to at least those control lines applicable to reading memory and reading and writing from and to input and output ports, as well as a reset line which resets the microprocessor. The card 6 also carries an externally presented connector 10, typically a multiple pin connector by which data and control connections of a parallel port may be connected by a suitable connection cable 12 to a bidirectional parallel printer port 14 of a test controller 16 which may itself be a suitably programmed personal computer.

The card 6 carries static random access memory (SRAM) 213-~01~

18 of suitable capacity, typically 64 kilobytes, and control logic 20, shown in more detail in Figure 4, which may be implemented by a mask or electrically programmable logic array chip or chips which have been programmed to provide the logic functions described below. The control logic operates to receive bytes of data from the parallel port through connector 10 and load them into sequential addresses in the SRAM 18, and to enable random access to data stored in the SRAM 18 by the data lines of the bus of the CUT. If sixteen bit data is to be presented to the CUT, it may be necessary to divide the SRAM into two blocks containing odd and even bytes (as has been common practice in ROMs utilized on planar boards) and to utilize two logic array chips in parallel to implement the control logic 20 if the chips can only handle 8 bit wide data. For simplicity of description it will be assumed that data is to be presented to the CUT
in 8 bit format.

The control logic 20 implements various functions best seen in Figure 4. The control logic interconnects respectively the connector 10, the edge connector 8, and the SRAM 18, which is static ram to avoid the complications associated with the refreshing of dynamic RAM. The connector 10 includes conductors representing data bits D0-D7, a strobe line -STROBE, further control inputs, in this instance utilized for register addressing purposes and designated A0 and Al, as well as at least one control output (BUSY), the control lines being those normally used for printer control, but utilized here for the purposes of the present invention. The SRAM 18 has data lines SD0 through SD7, address lines SA0 through SA15, and conventional chip enable and read/write control lines. The card edge connector 8 includes address lines CA0 through CAl9, data lines CD0 through CD7, and control lines including a reset - 2l3~nl~

line (RESET) and control lines (not shown) utilized by the bus for reading from addresses on the card and reading from and writing to ports on the card. The connector 8 also provides a power supply line to provide power to the interface, and all of the connectors include usual ground connections.

The A0 and A1 lines, when enabled by the -STROBE line, which also acts as a clock signal, are decoded by the function select/clock block 22, so as control access of data lines D0-D7 to a function control port register 24, and to an SRAM address/size control register 26. The value loaded in the control port register determines the routing of data within the control logic, respectively from the test lS controller 16 on lines D0-D7 to lines SD0-SD7, while the latter is write enabled, and from the SRAM 18 on line SD0-SD7 to lines CD0-CD7 of the CUT while the SRAM is read-enabled by signals from the CUT.

The value loaded in the SRAM address/size control register 26 firstly determines the address of the SRAM
within the memory space of the CUT. In the present example, assuming that the SRAM has a 64 Kbyte capacity, necessitating a 16 bit address to identify uniquely an address within the SRAM, the register 26 provides the 4 most significant bits of a complete address within a 1 Megabyte address space of the CUT. The value loaded also contains bits which define the size of the SRAM in the event that it is less than 64k. Data from this register is applied to an address comparator 28 which also receives twenty bit addresses from the CUT and determines by comparison of the four (in this example) most significant bits whether a valid address (as determined by the relevant bus control lines) appearing on the bus of the CUT is within the address space ~340 ~2 of the SRAM as defined by the register 26. The validity of the address (in relation to the timing required by the microprocessor on the CUT, as signalled by the appropriate control lines on the expansion bus) is verified by the address condition block 30. If the control port register indicates that the SRAM 18 is read-enabled, the least significant 16 bits of the valid address are passed by an address multiplexer 32 under control of the register 26 to the address lines SA0-SA15 of the SRAM 18 so that the data from the address identified within the SRAM are passed by data lines SD0-SD7 to the data lines CD0-CD7 of the bus of the CUT.
If the control port register is conditioned to change the condition of the multiplexer and write-enable the SRAM 18, it causes a sixteen bit address counter 34 to be clocked by the -STROBE signal and supply 16 bit sequential addresses via an address latch 36 to the multiplexer 32 from whence they are applied to the SRAM on lines SA0-SA15 together with data on lines SD0-SD7 transferred from data lines D0-D7 under control of a bidirectional communication register pair 38. In this phase of operation, the control port register 24 activates the RESET line of the CUT to prevent any data transfer to or from the CUT.
In computers following or incorporating the specification of the PC/AT computer from IBM Corporation, the program contained in ROM on the planar board accesses a "phantom" input/output port (MFG-PORT) at address 0x80 in the I/O space of the microprocessor.
A selector circuit 40 monitors the address lines and I/O control lines of the CUT to identify accesses to this port by the CUT, and the required direction of communication so that data may be transferred to and from the connector 10 under control of CA9-94-O19 9 ~ i 3 4 0 ~ 2 the register pair 38.
In use, the card 6 is inserted in a socket 4 of the CUT 2, where a ROM chip (or chips), which is to be emulated by the card, has not been inserted in, or has been removed from, its socket on the CUT. The CUT is powered by a power supply PSU. In the case of buses which implement a PHANTOM or equivalent control line, it may be possible to use the address comparator 28 to generate a control signal disabling only on board memory on the CUT at an address detected by the comparator as corresponding to an address to which the SRAM 18 has been mapped within the memory space of the CUT, in which case ROM on the planar board forming the CUT may remain in situ but will be inoperative.
The connector lO is connected by the cable 12 to a bidirectional parallel printer port 14 of a personal computer acting as the test controller 16, under control of a suitable application program. The form of this program forms no part of the present invention, provided that it implements the functions discussed below. In a first phase of operation, illustrated in Figures 2 and 4, the application program controls the printer port so that the control lines designated A0 and A1 select the control port register 24 and apply to it data on lines DO-D7 which cause it to set up the inbound register of register pair 38 for passing data to the SRAM 18, and also select the SRAM address/size control register 26 and apply to it the necessary address and size data for the SRAM 18. Successive bytes of data to be written to the SRAM 18 are then strobed via the communication register 38 to addresses in the SRAM 18 counted by the address counter 34. This data represents a program to be accessed by the CUT in place of that in its regular ROM. This substitute program may either be a program modified to 5,;:
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provide extra test or diagnostic facilities, or a program under development which is to be evaluated, i.e. either the program or the CUT may be tested. While the SRAM 18 is being loaded, the CUT is maintained by the control port register in a reset condition by the RESET line so that there is no possibility of it being affected by the data transferred, and so that the CUT will commence operation from a known reset condition and a known address within the SRAM address space when the reset signal is removed.
This occurs when the control port register 24 is reloaded with data from the test controller after again being addressed by the latter by control lines A0 and A1, and sets the SRAM to a read-enabled condition, and the address multiplexer 32 to pass addresses from the comparator 28 instead of the counter 34. In this phase of operation, as shown in Figures 3 and 4, the comparator 28 reviews the most significant 4 bits of addresses appearing from the CUT
on the address lines CA0-CAl9, and if it detects an address within the address space of the SRAM, the address when latched as valid by the block 30, has its 16 least significant bits applied through the multiplexer to the SRAM
18, which is thus enabled to place the data from the address identified on the data lines SD0-SD7, whence they can be accessed by the CUT through the data lines CD0-CD7. If the decoder 40 detects an access by the CUT to the port MFG-PORT, it activates the control line BUSY at the connector 10 to alert the test controller to the port access, and selects the register of the bidirectional communication register pair 38 according to whether input or output is required so that the controller may either read a byte from the register or write a byte to it, depending on direction. This enables the program loaded into the SRAM to control communication between the CUT and the test controller, for example by ~ 2134012 reporting on progress of a power-on self test, or receiving instructions from the controller responsive to such reports.
This permits the use of debugging subroutines for both hardware and software without the need of an in-circuit emulator or other external hardware. If appropriately written, these routines may remain in the code placed in ROM
during normal operation of the CUT without interfering with normal operation, provided that there is no physical hardware accessed by MFG-PORT. The content of these subroutines forms no part of the present invention.

As will be appreciated from the foregoing, an interface card of quite simple construction, in conjunction with simple control routines for the card as outlined above, provides the wherewithal for testing of a microprocessor based CUT, and of control hardware for such a CUT, without the necessity for specialized and expensive test equipment.
Although the device has been exemplified as controlled through the parallel port of a personal computer acting as test controller, it will be appreciated that alternative interfaces could be implemented. For example, with the inclusion of suitable serial to parallel and parallel to serial conversion facilities, control could be exercised through a serial port. Other examples of possible control connectors would be SCSI or IDE-type interfaces, or the use of a specialized interface card plugged into the bus of the test controller computer. While the emulation of ROM
providing start-up, self-test and basic input-output system routines has been exemplified, ROM performing other functions on the CUT or cards plugged into the CUT expansion bus, could also be emulated, for example, ROM provided basic input-output system routines for video graphics adaptors or disk controllers.

Claims (3)

1. An interface for testing hardware or firmware of or accessed through a main board of a personal computer, the main board as tested including a microprocessor, provision for receiving firmware comprising a control program in read only memory located in a defined portion of an address space of said microprocessor, and having multiple sockets providing access to an expansion bus including data, address and control lines, said interface comprising:
a printed circuit board for plugging into one of said multiple sockets, an external port on said printed circuit board having data and control lines adapted for connection to a complementary external port on a computer programmed to act as a test controller, said printed circuit board further including random access memory and control logic, said control logic, in response to signals received through said external port, controlling sequential writing of program data received through said external port into said random access memory, locating said random access memory in said defined portion of said address space of said microprocessor, and thereafter monitoring addresses appearing on the address lines of said expansion bus and applying addresses within said defined portion of said address space to said random access memory to thereby present program data located at such addresses in said random access memory to data lines of said expansion bus.

2. An interface according to Claim 1, wherein said control logic further includes means for recognizing a combination of signals on said expansion bus representing a predetermined input/output port address, and register means for transferring data between said data lines of said external port and said data lines of said expansion bus in response to recognizing said combination of signals.

3. An interface according to Claim 1 or 2, wherein said control logic further controls a reset line of said expansion bus to disable said microprocessor during writing of said program data.