CA2104340A1 - Hermetic protection for integrated circuits - Google Patents

Hermetic protection for integrated circuits

Info

Publication number
CA2104340A1
CA2104340A1 CA002104340A CA2104340A CA2104340A1 CA 2104340 A1 CA2104340 A1 CA 2104340A1 CA 002104340 A CA002104340 A CA 002104340A CA 2104340 A CA2104340 A CA 2104340A CA 2104340 A1 CA2104340 A1 CA 2104340A1
Authority
CA
Canada
Prior art keywords
silicon
ceramic
integrated circuit
bond pads
coatings
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002104340A
Other languages
French (fr)
Inventor
Grish Chandra
Keith Winton Michael
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dow Silicones Corp
Original Assignee
Dow Corning Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dow Corning Corp filed Critical Dow Corning Corp
Publication of CA2104340A1 publication Critical patent/CA2104340A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B41/00—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone
    • C04B41/45—Coating or impregnating, e.g. injection in masonry, partial coating of green or fired ceramics, organic coating compositions for adhering together two concrete elements
    • C04B41/4505—Coating or impregnating, e.g. injection in masonry, partial coating of green or fired ceramics, organic coating compositions for adhering together two concrete elements characterised by the method of application
    • C04B41/455—Coating or impregnating, e.g. injection in masonry, partial coating of green or fired ceramics, organic coating compositions for adhering together two concrete elements characterised by the method of application the coating or impregnating process including a chemical conversion or reaction
    • C04B41/4554—Coating or impregnating, e.g. injection in masonry, partial coating of green or fired ceramics, organic coating compositions for adhering together two concrete elements characterised by the method of application the coating or impregnating process including a chemical conversion or reaction the coating or impregnating material being an organic or organo-metallic precursor of an inorganic material
    • C—CHEMISTRY; METALLURGY
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    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B41/00—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone
    • C04B41/45—Coating or impregnating, e.g. injection in masonry, partial coating of green or fired ceramics, organic coating compositions for adhering together two concrete elements
    • C04B41/52—Multiple coating or impregnating multiple coating or impregnating with the same composition or with compositions only differing in the concentration of the constituents, is classified as single coating or impregnation
    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02107—Forming insulating materials on a substrate
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    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02115—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
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    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
    • H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
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    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
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    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
    • H01L21/3144—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers on silicon
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
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    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
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Abstract

HERMETIC PROTECTION FOR INTEGRATED CIRCUITS

ABSTRACT

This invention relates to integrated circuits which are protected from the environment. Such circuits are hermetically sealed by applying ceramic layers to the top metallization.

Description

2 1 ~

HERMETIC PROTECTION FOR INTEGRATED CIRCUITS

The present invention relate~ to integratéd circuits which are protected from the environ~ent. Such circuits are hermetically sealed by applying ceramic layers to the top metallizationO These circuits are inexpensive to fabricate and have improved perfo~mance and reliability.
Modern electronic circuits must be able to withstand a wide variety of environmental conditions such as moisture, ions, heat and abrasion. A significant amount of work has been directed toward various protective measures to minimize the e~posure of such circuits to the above conditions and thereby increase their reliability and life.
Many prior art processes for protecting electronic circuits involve sealing or encapsulating the circui~s after they have been interconnected. For example, it is known in the art to use protective layers of s:ilicones, polyimides, epoxies, other organics, pla~tics and the like. Such materials, however, are of only limited value since most are permeable to environmental moisture and ions.
Similarly, interconnected c:ircuits have also been sealed within ceramic packages. This latter approach has proven to be relati.vely effective in increasing device reliability and is currently used in select applications.
The added size, wei~ht and co~t invol~ed in this approach, however, inhibits widespsead application in the electronic indu~try.
The use of lightweight ceramic protective coatings on electronic devices has also been sug~ested in U.S. Patents 4,756,977 and 4,749,631. The use of ceramic silica coating~

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are described therein which are derived from hydrogen silsesquioxane and ~ilicate esters, respectively, as well as the use of additional ceramic layers as hermetic barriers.
We have discovered that when such coatings are applied specifically to integrated circuits at the wafer sta~e and, even though the bond pads are subse~uently opened by removing a portion of the coating, the resultant circuits remain hermetically sealad and exhibit increased reliability and life.
Sealing circuits at the wafer stage is also known in the art. For example, it is known in the art to coat fabricated integrated circuits with ceramic materials such as silica and/or silicon nitride by chemical vapor deposition (CVD) techniques. These coatings are then etched back to the bond pad~ for the application o~ leads. The wafers coated in this manner, however, have inatequate reliability and liie.
We have found a solution to the above problem~ -;
associated with the hermetic protection of integrated circuits by replacing the conventional passivation layers on integrated circuits with the silicon-containing ceramic coatings described herein.
The present invention relates to hermetically sealed integrated circuits. These circuits comprise circuit subassemblies having a top layer of metalli~ation including one or more bond pads. To this top layer of metallization is applied a silicon-containing ceramic layer 'oy a process comprising coating the circuit with a composition comprising a preceramic silicon-containing material followed by converting said material to a ceramic. The ceramic layers covering the bond pads may optionally be removed and the resultant open bond pads sealed with one or more non-corroding, conductive layers.

: . . , . . ~

- . . . :

2 1 ~
The present invention also relates to a method for producing the above sealed integrated circuits. The method involves applying one or more ceramic layers over the top layer of metallization cn the circuit followed by removing at least a portion of the ceramic layer covering the bond pads.
The present invention is based on our finding that integrated circuits can be hermetically sealed by the application of the ceramic coatings taught herein over the top layer of metallization on the circuit. These sealed circuits have increased reliabili~y and performance. In addition, sillce this process is unexpectedly performed at the wafer stage, production can be simplified and costs reduced.
The integrated circuit subassemblies used in the process of this invention are not critical and nearly any which are known in the art and/or produced commercially are useful herein. The processes used to produce such circuits are also known and not critical to the invention. Exemplary of such circuits are those comprising a semiconductor s~bstrate, such as silicon or gallium arsenide, having an epita~ial layer grown thereon. This epitaxial layer is appropriately doped to form the PN-~unction regions which constitute the active regions of the device. These active regions are diodes and transistors wh:ich form the integrated circuit when appropriately interconnected by a properly patterned metallic layer. This metal:Lic interconnect layer terminates st the bond pads on the exterior surface of the circuit subassembly.
As described above, the prior art discloses passivating such circuits with one or more ceramic coatings ~ -applied by CVD techniques. These coatings included, for example, silica, silicon nitride or silicon oxynitride derived from precursors such as silane and oxygen, nitrous oxide~ nitrogen, ammonia or the like. Circuits coated with ' : .. , . . : - .
~., ' . ~.- .

., . , : ~ .

7 : : `:

s~lch a passivation layer, howevQr, are still prone to damage by the environment. For examplel the passivation is prone to penetration of water and/or variou9 destructive ions through defects and cracks. As noted above, the circuit indu~try has attempted to solve these problems by the use of additional protective measl~res after the circuits are interconnected.
The pre~ent invention, on the other hand, describes the application of specific ceramic coatings before the interconnection.
In the process of the present invention, the above circuits are sealed by covering the circuit's top metallization with one or more ceramic layers. The first layer is generally a silicon-containing ceramic material which is applied by a process co~prising coating the circuit with a composition comprising a preceramic silicon-containing material followed by converting the preceramic silicon-containing material to a ceramic. Typically~ the preceramic material is converted to a ceramic by heating it to a sufficient temperature.
A~ used in the present invention, the term "preceramic silicon-containing material" describes material which can be rendered sufficiently flowable to impregnate and coat the surface of a circuit and which can be subsequently converted to a solid layer exhibiting properties generally recognized by those skilled in the art as characteristic of a ceramic. These materials include, for example, precursors to silicon oxides, silicon nitride, silicon oxynitride, silicon o~ycarbide, silicon carbonitride, silicon oxycarbonitride, silicon carbide and the li~e.
The preferred preceramic compounds to be used in the process of this invention are precursors to silicon oxides, especially silica. The silica precursors which may be used in the invention include hydrogen silsesquioxane ~ - , . : ' - :.
. . .

2 L ~ 3 ~1 ~
resin (H-resin), hydrolyzed or partially hydrolyzed RnSi(OR)4 n' or their combinations, in which each R is independently an aliphatic, alicyclic or aromatic substituent of 1-20 carbon atoms, preferably 1-4 carbon atoms, such as an alkyl (e.g., methyl, ethyl, propyl), alkenyl (e.g., vinyl or allyl), alkynyl (e.g., ethynyl), cyclopentyl, cyclohexyl and phenyl and n is 0 3, preferably 0-1.
H-resin is used in this invention to describe a variety of hydridosilane resins having units of the structure HSi(OH)x(OR)yOz/2 in which each R is independently an organic group which, when bonded to silicon through the oxygen atom, forms a hydrolyzable substituent, x = 0-2, Y = 0-2, z = 1-3 and x ~ ~ + z = 3. These resins may be either fully condensed (x = 0, ~ = 0 and z = 3) or they may be only partially hydrolyzed (y is not 0 over all the units of the polymer) and/or partially condensed (x is not 0 over all the units of the polymer). ~lthough not represented by this structure, various units of these resins may have either zero or more than one Si-H bond due to various factors inYolved in their fo~lation and handling. Exemplary of substantially condensed (less than about 300 ppm si].anol) H-resins are those formed by the process in U.S. Paltent 3,615,272. This polymeric material has units of the formula (HSiO3~2)n in which n is generally 8-1000. The pref~rred resin has a number average molecular weight of from 800-2900 and a weight average molecular weight of between 8000-28,000 (obtained by gel permeation chromatography (GPC) analysis using polydi-methylsiloxane as a calibration standard). When heated suficiently, this material yields a ceramic coating essentially free o SiH bonds.

' . ' :~. `

, , 210l~3l11) Exemplary H-resins which may not be ully condensed include those described in U.S. Patent 5,010,15~ or U.S.
Patent 4,9g9,397. Exemplary H-re~in3 which are not ully hydrolyzed or condensed are formed by a procsss which comprises hydrolyzing a hydrocarbonoxy hydridosilsne with water in an acidified oxygen-containing polar organic solvent.
A platinum, rhodium or copper catalyst may also be admixed with the hydrogen silsesquioxane to increase the rate and extent of its conversion to silica. Any platinum, rhodium or copper compound or complex that can be solubilized with the catalyst will be operable. For instance, an organo-platinum composition such as platinum acetylacetonate or rhodium catalyst Rhcl3[s(cH2cH2cH2cH3)2]3~ obtain~ble from Dow Corning Corporation, Midland, Michigan are all within the scope of this invention. The above catalysts are generally added to the solution in an amount of between about 5 and SOO
ppm platinum or rhodium based on the weight of resin.
The second type of silica precursor material useful herein includes hydrolyzed or partial:Ly hydrolyzed compounds of the formula RnSi(OR)4 n in which R and _ are as defined above. Some of these materials are commercially available, Eor example, under the tradename ACCUGLASS. Specific compounds of this type include methyltriethoxysilane, phenyltriethoxysilane, diethyldiethoxysilane, methyltri-methoxysilane, dimethyldimethoxysilane, phenyltrimethoxy-silane, vi~yltrimethoxysilane, tetrametho~ysilane, ~etra-ethoxysilane, tetrapropoxysilane and tetrabutoxysilane.
After hydrolysis or par~ial hydrolysis of these compounds, ~ -the silicon stoms therein may be bonded to C, OH or OR
groups, but a substantial portion of the material is believed to be condensed in the form of soluble Si-O-Si resins.
Compounds in which x = 2 or 3 are generally not used alone as ' ~' .

.-. . .
-~ . ' '.. : : ~ ' . ~ ;
..

2 1 ~!13i'L~
volatile cyclic ~tructure~ are gene~ated during pyrolysis, but small amounts of ~aid compounds may be cohydroly~ed with othQr 9ilanes to prepare useful preceramic materials.
In addition to the above SiO2 precursors ~ other ceramic oxide precursors may also be advantageou~ly used herein either solely or in combination with the above SiO2 precursors. The ceramic oxide precursors specifically contemplated herein include compounds of various metals ~uch as aluminum, titanium, zirconium, tantalum, niobium and/or vanadium as well as various non-metallic compounds such as those of boron or phosphorous which may be dissolved in solution, hydrolyzed and subsequently pyrolyzed at relatively low temperatures to form ceramic oxides.
The above ceramic oxide precursor compounds generally have one or more hydrolyzable groups bonded to the ~ :
above metal or non-metal, depending on the valence of the metal. The number of hydrolyzable groups to be included in these compounds is not critical as long as the compound is soluble in the solvent. Likewise, selection of the e~act hydrolyzable substituent is not critical since these substituellts are either hydrolyzed or pyrolyzed out of the system. Typical hydrolyzable groups include alkoxy, such as methoxy, propoxy, butoxy and hexoxy; acyloxy, such as acetoxy, other organic groups bonded to said metal or non-metal throu~h an oxygen atom such as acetylacetonate or amino groups. Specific compounds, therefore, include ~irconium tetracetylacetonate, titanium dibutoxy diacetyl-acetonate, aluminum triacetylacetonate, tetraisobutoxy titanium and Ti(N(CH3)2)4.
When SiO2 is to be combined with one of the above ceramic oxide precursors, generally it is used in an amount such that the final ceramic contains 70 to 99.9 percent by weight SiO2.

,, ; ;: - : : :
:. :.; ~ :

~10 !13 ~
Examples of suitable silicon carbonitride precur~ors include hydridopolysila~ane (HPZ) resin and methylpolydi~ilylazane (MPDZ) resin. Processes for the production of thesa materials are described in US Patents 4,S40,803 and 4,340,619. Examples of silicon carbide precursors inclu~e polycarbosilanes and examples of silicon nitride precursors include poly3ilazanes. Oxygen can be incorporated into the ceramics resulting from the above precursors by pyrolyzing them in an oxygen-containing environment.
The above preceramic material is then used to coat the integrated circuit. The material can be used in any practical form but it is preferred to use a solution comprising the preceramic material in a suitable solvent. If this solution approach is used, the preceramic solution is generally formed by simply dissolving or suspending the preceramic material in a solvent or m:ixture of solvents.
Various facilitating measures such as stirring and/or heat may be used to assist in the dis~olut:ion. The solvents which may be used in this method include alcohols such as ethyl or isopropyl; aromatic hydrocarbons such as benzene or toluene;
alkanes such as n-heptane or dodecane; ketones; cyclic dimethylpolysiloxanes; esters and glycol ethersl in an amount sufficient to dissolve the above materials to low solid For instance, enough of the solvent should be included to form a 0.1-85 weight percent solution.
The circuit is then coated with this solution by means ~uch as ~pin, spray, dip or ilow coating and the solvent is allowed to evaporate. Any suitable means of evaporation such as simple air drying by exposure to the ambient environmant~ heating or the application of a vacuum may be used.

-, ~ :' ': ~ : ' :

:
- ~ ,,:, .' :

2 ~ 3 1 ( Although the above described methods primarily -focus on using a solution approach, olle skilled in the art would recognize that other e~uivalent means (eg., melt impregnation) would also function in the process of this invention.
The preceramic ~aterial is then typically converted to a silicon-containing ceramic by heating it to a sufficient temperature. Generally, the temperature is in the range of 50 to 800C. depending on the pyrolysis a~mosphere and the preceramic compound. Preferred temperatures are in the range of 50 to 600C. and more preferably are 50-400C. Heating is generally conducted for a time sufficient to ceramify, generally up to 6 hours, with less than 2 hours being preferred.
The above heating may be conducted at any effective atmospheric pressure from vacuum to superatmospheric and under any effective oxidiæing or non-oxidizing gaseous environment such as those comprising air, 2~ an inert gas tN2, etc.), ammonia, amine3, moisture, N20 and the like.
Any method of heating such as the use of a convection oven, rapid thermal processing, hot plate or radiant or microwave energy is genera]ly functional herein.
The rate of heating, moreover, is also not critical, but it is most practical and preferred to heaLt as rapidly as possible.
Additional coatings may be applied over these coatings if desired. These can include, for example, SiO2 coatings, SiO2/ceramic oxide layers, silicon-containing coatings~ silicon-carbon containing coatings, 9ilicon-nitrogen containing coatings, silicon-oxygen-nitrogen coatings, silicon-nitrogen-carbon containing coatings and/or diamund-like carbon coatings. Methods for the application of such coatings are known in the art and many are described in , .

..

,. - . :: ' , ' ~,' :' :; ~

21~ i~ 3 !~¦) U.S. Patent 4,756,977. An especially preferred coating is ~ilicon carbide applied by CVD of silacyclobutane as is de~cribed in U.~. Patent 5,011,706.
After the ceramic layer~ are applied, the coating covering the bond pads can be etched or partially etched to allow for attachment of leads. The method of etching i9 not critical and nearly any process known in the art will function herein. This includes, for example, dry etching (eg., with plasma), wet etching (eg., with hydrofluoric acid) and/or laser ablation. If desired, the open bond pads can then be sealed by covering them with one or more non-corroding, conductive layers. The material used for this layer is not critical and can comprise any which is qtable in the environment, electrically conductive and useful for interconnecting the circuit. Examples of such materials incl7~de gold, copper, silver, tungsten, solder, silver-filled epoxy and the like.
The method for applying this layer or layers is likewise not critical. Examples of such processes include sputtering, electron beam evaporation or by merely dispensing the material at the bond pad. These and other processes are known in the art for use within the m~ltiple layers of the circuit and are functional herein.
It should be noted that the materials of the bond pad (eg., aluminum) are often incompatible with the materials of the non- corroding, conductive layer (eg, gold~ such that when they are brought into contact with each other intermetallic formation ("purple plague7') can damage the circuit. To prevent such damage, it is within the scope o this invention to first apply a diffusion barrier metal layer to the bond pads followed by application of the conductive layers as set forth above. The diffusion barrier metal layers useful herein are known in the art for use within - . . :
.

. . .
:,'' ,'~ '' '' ;' ' ' .: -. .

2 . O i ~ `il () integrated circuits for building the multiple layers of the circuit. Generally, such layers comprise mPtals such as tungsten or metal alloys such as titanium-tungsten, titanium nitride and the like.
The method for forming the diffusion barrier metal layers is not critical and many techniques are known in the art. A common approach involves sputtering the diffusion barrier metal layer on the surface of the circuit ollowed by etching.
If the bond pads are sealed with this conductive layer, additional ceramic coatings may be added to the above ceramic layers by the methods described above to further seal the circuit.
The above sealing processes can be performed at the wafer stage or after dicing. It is preferred herein, however, to seal the devices at the wafer stagP for efficiency reasons.
The integrated circuits formed in the manner of this invention are hermetically sealed such that their reliability is increased. In addition, the circuits can be handled and manipulated witllout damage. Furthermore, many of the ceramic layers are opaque to W and visible light.
Such circuits are then interconnected with each other, with a lead frame, with a circuit board or other external components. Such interconnection can be by conventional leads or by methods such as TAB or "flip chip"
processes which are well known in the art.
After interconnection, the device can also be packaged by con~entional techniques known in the art. For instance, the device can be embedded within an organic encapsulant such as a polyimide, an epoxy or PARYLENETM. It can also be embedded within a silicone encapsulant or it can be included in a plastic package for additional protection.

Claims (13)

1. An integrated circuit having top metallization and one or more bond pads, said circuit characterized by a ceramic layer covering over the integrated circuit, wherein the ceramic layer comprises a silicon-containing ceramic material which is deposited by a process comprising (A) coating the circuit with a composition comprising a preceramic silicon-containing material followed by (B) converting said material to a ceramic and wherein at least a portion of the ceramic layer covering the bond pads has been removed to yield open bond pads for interconnection of the circuit and thereby leaving the ceramic layer in intimate contact with bond pads.
2. The integrated circuit of claim 1 wherein the ceramic layer is selected from the group consisting of silicon oxides, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride and silicon carbide.
3. The integrated circuit of claim 1 wherein the preceramic silicon-containing material is hydrogen silsesquioxane resin.
4. The integrated circuit of claim 1 wherein the preceramic silicon-containing material is a hydrolyzed, partially hydrolyzed or their combinations of a formula RnSi(OR)4-n, in which R is an aliphatic, alicyclic or aromatic substituent of 1-20 carbon atoms and n is 0-3.
5. The integrated circuit of claim 1 wherein the ceramic layer is covered by one or more additional ceramic layers selected from SiO2 coatings, SiO2/ceramic oxide coatings, silicon coatings, silicon carbon containing coatings, silicon nitrogen containing coatings, silicon oxygen nitrogen containing coatings, silicon carbon nitrogen containing coatings and diamond-like carbon coatings.
6. The integrated circuit of claim 1 wherein the open bond pads are sealed with one or more non-corroding, conductive layers.
7. The integrated circuit of claim 6 wherein the non-corroding, conductive layers comprise a material selected from the group consisting of gold, silver, tungsten, solder, silver filled epoxy and copper.
8. The integrated circuit of claim 1 wherein the open bond pads are sealed with a diffusion barrier metal layer and a non-corroding, conductive layer.
9. The integrated circuit of claim 8 wherein the diffusion barrier metal layer is selected from titanium, an alloy of titanium and tungsten and titanium nitride.
10. The integrated circuit of claim 1 which is interconnected and embedded within a material selected from organic encapsulants and silicone encapsulants.
11. The integrated circuit of claim 1 wherein the ceramic coating is opaque to ultraviolet and visible light.
12. A method for hermetically sealing an integrated circuit having top metallization and one or more bond pads, the method comprising:
(A) applying a silicon-containing ceramic layer to the integrated circuit by a process which comprises (i) coating the circuit with a composition comprising a preceramic silicon-containing material and followed by (ii) converting said material to a ceramic; and (B) removing at least a portion of the silicon-containing ceramic layer covering the bond pads.
13. An integrated circuit comprising:
(A) a circuit subassembly having bond pads;
(B) one or more ceramic layers covering the surface of the subassembly around the bond pads; and (C) a non-corroding, conductive layer covering the the bond pads;
characterized by one or more of the ceramic layers comprising a silicon-containing ceramic material which is deposited by a process comprising coating at least the primary passivation layer with a composition comprising a preceramic silicon-containing material followed by converting the preceramic material to a ceramic layer.
CA002104340A 1992-08-31 1993-08-18 Hermetic protection for integrated circuits Abandoned CA2104340A1 (en)

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Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995028737A1 (en) 1994-04-18 1995-10-26 Micron Technology, Inc. Method and apparatus for automatically positioning electronic die within component packages
JP3149739B2 (en) * 1995-07-14 2001-03-26 ヤマハ株式会社 Multilayer wiring formation method
JP3070450B2 (en) * 1995-07-14 2000-07-31 ヤマハ株式会社 Multilayer wiring formation method
JPH09102666A (en) * 1995-07-31 1997-04-15 Ngk Insulators Ltd Film formation
US5753374A (en) * 1995-11-27 1998-05-19 Dow Corning Corporation Protective electronic coating
US5609925A (en) * 1995-12-04 1997-03-11 Dow Corning Corporation Curing hydrogen silsesquioxane resin with an electron beam
US6072236A (en) * 1996-03-07 2000-06-06 Micron Technology, Inc. Micromachined chip scale package
US5682065A (en) * 1996-03-12 1997-10-28 Micron Technology, Inc. Hermetic chip and method of manufacture
US5965270A (en) * 1996-07-19 1999-10-12 National Science Council Metal/amorphous material/metal antifuse structure with a barrier enhancement layer
US5956605A (en) 1996-09-20 1999-09-21 Micron Technology, Inc. Use of nitrides for flip-chip encapsulation
JP3082688B2 (en) * 1996-11-05 2000-08-28 ヤマハ株式会社 Wiring formation method
US5920081A (en) * 1997-04-25 1999-07-06 Taiwan Semiconductor Manufacturing Co., Ltd. Structure of a bond pad to prevent testing probe pin contamination
US6008070A (en) 1998-05-21 1999-12-28 Micron Technology, Inc. Wafer level fabrication and assembly of chip scale packages
US5935638A (en) * 1998-08-06 1999-08-10 Dow Corning Corporation Silicon dioxide containing coating
US6544880B1 (en) 1999-06-14 2003-04-08 Micron Technology, Inc. Method of improving copper interconnects of semiconductor devices for bonding
DE19930782A1 (en) * 1999-07-03 2001-01-04 Bosch Gmbh Robert Process for the selective coating of ceramic surface areas
US6605526B1 (en) 2000-03-16 2003-08-12 International Business Machines Corporation Wirebond passivation pad connection using heated capillary
US6524881B1 (en) * 2000-08-25 2003-02-25 Micron Technology, Inc. Method and apparatus for marking a bare semiconductor die
US7642202B1 (en) 2001-06-28 2010-01-05 Novellus Systems, Inc. Methods of forming moisture barrier for low k film integration with anti-reflective layers
US7169685B2 (en) * 2002-02-25 2007-01-30 Micron Technology, Inc. Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach adhesive
US6777349B2 (en) * 2002-03-13 2004-08-17 Novellus Systems, Inc. Hermetic silicon carbide
US7335980B2 (en) * 2004-11-04 2008-02-26 International Business Machines Corporation Hardmask for reliability of silicon based dielectrics
ES2859458T3 (en) 2009-10-27 2021-10-04 Silcotek Corp Coating, article and chemical vapor deposition method
US9340880B2 (en) 2009-10-27 2016-05-17 Silcotek Corp. Semiconductor fabrication process
KR101854162B1 (en) 2010-10-05 2018-06-20 실코텍 코포레이션 Wear resistant coating, article, and method
EP2996819A1 (en) 2013-05-14 2016-03-23 Silcotek Corp. Vapor phase treatment of amorphous carbon films with (perfluoro 1,1,2,2 tetrahydroalkyl)trialkoxysilane
US11292924B2 (en) 2014-04-08 2022-04-05 Silcotek Corp. Thermal chemical vapor deposition coated article and process
US10151195B2 (en) * 2014-04-29 2018-12-11 China Petroleum & Chemical Corporation Electronic devices for high temperature drilling operations
US9915001B2 (en) 2014-09-03 2018-03-13 Silcotek Corp. Chemical vapor deposition process and coated article
US10316408B2 (en) 2014-12-12 2019-06-11 Silcotek Corp. Delivery device, manufacturing system and process of manufacturing
WO2017040623A1 (en) 2015-09-01 2017-03-09 Silcotek Corp. Thermal chemical vapor deposition coating
US10323321B1 (en) 2016-01-08 2019-06-18 Silcotek Corp. Thermal chemical vapor deposition process and coated article
US10487403B2 (en) 2016-12-13 2019-11-26 Silcotek Corp Fluoro-containing thermal chemical vapor deposition process and article
WO2020252306A1 (en) 2019-06-14 2020-12-17 Silcotek Corp. Nano-wire growth

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3615272A (en) * 1968-11-04 1971-10-26 Dow Corning Condensed soluble hydrogensilsesquioxane resin
US4340619A (en) * 1981-01-15 1982-07-20 Dow Corning Corporation Process for the preparation of poly(disilyl)silazane polymers and the polymers therefrom
JPS6035525A (en) * 1983-08-08 1985-02-23 Hitachi Micro Comput Eng Ltd Semiconductor device
US4540803A (en) * 1983-11-28 1985-09-10 Dow Corning Corporation Hydrosilazane polymers from [R3 Si]2 NH and HSiCl3
JPS62242333A (en) * 1986-04-15 1987-10-22 Nec Corp Structure of bonding pad of semiconductor device
US4756977A (en) * 1986-12-03 1988-07-12 Dow Corning Corporation Multilayer ceramics from hydrogen silsesquioxane
US4749631B1 (en) * 1986-12-04 1993-03-23 Multilayer ceramics from silicate esters
JPS63213347A (en) * 1987-02-27 1988-09-06 Mitsubishi Electric Corp Semiconductor device
US4849296A (en) * 1987-12-28 1989-07-18 Dow Corning Corporation Multilayer ceramic coatings from metal oxides and hydrogen silsesquioxane resin ceramified in ammonia
US4888226A (en) * 1988-08-08 1989-12-19 American Telephone And Telegraph Company Silicone gel electronic device encapsulant
US5011706A (en) * 1989-04-12 1991-04-30 Dow Corning Corporation Method of forming coatings containing amorphous silicon carbide
US4999397A (en) * 1989-07-28 1991-03-12 Dow Corning Corporation Metastable silane hydrolyzates and process for their preparation
US5010159A (en) * 1989-09-01 1991-04-23 Dow Corning Corporation Process for the synthesis of soluble, condensed hydridosilicon resins containing low levels of silanol
CA2027031A1 (en) * 1989-10-18 1991-04-19 Loren A. Haluska Hermetic substrate coatings in an inert gas atmosphere
US5116637A (en) * 1990-06-04 1992-05-26 Dow Corning Corporation Amine catalysts for the low temperature conversion of silica precursors to silica
US5145723A (en) * 1991-06-05 1992-09-08 Dow Corning Corporation Process for coating a substrate with silica
US5136364A (en) * 1991-06-12 1992-08-04 National Semiconductor Corporation Semiconductor die sealing

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