CA2045662C - Binary floating point arithmetic rounding in conformance with ieee 754-1985 standard - Google Patents

Abstract

A method and a high speed processor (HSP) incorporating that method are set forth for processing signals representing outputs generated by remainderless division algorithms (102) and remainderless square root algorithms so as to obtain rounded outputs (112) conforming to the IEEE 754-1985 binary floating point arithmetic standard. The method and procedure of the present invention allow the solutions of floating-point computations to be rounded such that sign bits, as well as binary bits, of the rounded results are in full compliance with all guidelines of the stated standard.

Description

wo gl/10189 2 0 ~ 5 6 6 2 pcr/us9o/o735l ~-.

. .
BINARY FLOATING POINT
ARITHMETIC ROUNDING
IN CONFORMANCE WITH
IEEE 754-1985 STANDARD `
ir B~ck~round Qf The ~nventiQn i ~ .
Fixed point division and square root algorithms have lon~
been in use. Such algorithms comply with the IEEE 754-198S
binary floating point anthmetic standard, hereafter designated IEEE FPS, for rounding because each iteration of the aigorithm ,~
computes a bit that is identical to the corresponding bit in the ~;~
infinitely precise result and because the remainder of the calculation can always be determined. x Remainderless algorithms have ~ been utilizedj to provide 1 5 faster computation for division and square root ~ determinatio~
in that such ~algorithms may often~ be eomputod more quickly ;~
than the fixed point counterparts. In particular, utilizing - restoring and non-restoring algorithms, computation time is proportionàl ~to a word length divided by a radix; more 2 0 ~particularly, algorithm computation time is linearly related to the word length. Utilizing convergent algorithms, computation time is proportional to a log, to a base of a convergence rate~ of a ward length di~rided by an initial approximation accuracy;
more particularly, ~algorithm computation time is related to the log of the word Iength.
However, remainderless algorithms for ~division and ~-~ - squarc root~ determination may generate results that are numcrically very near, but bitwise very different from the infinitely precise result. Hence such a!gorithms may provide rounded results that are not in compliance with lhe IEEE FPS.
Thus, there is a need for a method of rounding results from remainderless algorithms for division and square root determination such that the rounded result conforms with the ~, .
cited standard. ~
~. ..

:

' WO 91/10189 PCr/US90~07351 ~

~04S6~2 Summar~.~ Of The ~n~ention The need for a method of rounding results obtained by utilizing remainderless algonthms for division and square root 5 determination such that the results are in accordance with the IEEE FPS is substantially mct by the mcthod and high speed processor incorporating that method of the present invention. -The present invention sets forth a method and high speed processor for processing electrical signals representing outputs 10 gcneratcd by implement?tion of remainderless division algorithms and remaindcrless square root algorithms, the x outputs being rounded to a rounding precision having a least significant bit. the rounding precision specified by a precision given in an IEEE FPS, and the desired rounding mode 15 implcmented being applied corrcsponding to an IEEE FPS
rounding mode. The output utilized, C, is generated by ~`
remainderless division utilizing a dividend value N, having a . magnitude, INI, aod a sign, and a divisor value D, having a magnitudc, IDI, and a sign, or by rcmainderless square root 2 0 determination utilizing an input value S, having a magnitude~
: ISI, and a sign. C has a magnitude, a sign conforming to the IEEE
FPS, and a round bit that is the bit to the right of the leas~
significant bit of thc specified rounding precision, C being in an extcnded~ prccision wherein the extended precision has a 5 grcatcr prccision than the rounding precision.
In one cmbodimcnt of the present invention, for rcmainderlcss division, INI, D, and C are obtained and for - remaindcrless squarc root dcterminations, ISI and C are ; obtained. C is utilized to determine at least one of two 3 0 rounding valucs, L and H, each having a magnitude and a sign~
and H having a least signif~lcant bit (lsb), in the rounding precision relatcd to at least one of the following: thc magnitude of C, the sign of C, and thc rounding mode specified by the IEEE
FPS.

WO 91/10189 ; PCl/US90/07351 ~0~56~2 At least one of the two rounding values, L and H, is .utilized to generate an intermediate value A that is related to .
at least one of the following: the magnitude of C, the sign of C, and the desired rounding mode specified by thc IEEE FPS. ~.
Then the implementation of the invention method obtains a ;;
magnitude of a product value: for remainderless division, by multiplying, the intermediate value A times the divisor value D, disregarding the sign of A ~ D, to obtain a magnitude IA * Dl or for remaindcrless square root determination, by multiplying !3`
the in~ermcdiate value A times itself to obtain a magnitude IA * Al.
The implementation then generates a status: for a .~remaindcrless division algorithm, a divide status comprising ~.
"less than" if IA ~ Dl is less than INI, "equal to" if IA * Dl equals 1~1, and "greater than" if IA ~ Dl is greater than INI; and, for a `
remainderlcss squarc root algorithm, a square root status comprising "less than" if IA ~ Al is less than ISI, "equal to" if IA * Al equals ISI, and "greatcr than" if IA ~ Al is greater than ISI.
The implcmentation selects the rounding value L or H
2 0 relative to at least thc divide status or the square root status ~s a rounded result value R in the rounding precision in conformance with the desired rounding mode specified by the EEE FPS.

Brief De~riotion Qf The Drawin~c FIG. 1 depicts a flow diagram of the method of the prescnt invention for remainderless division rounding pursuant to the EEE FPS.
FIG. 2 dcpicts a flow diagram of the method of the 3 0 present invention for remainderless square root rounding pursuant to the IEEE FPS.
FIG. 3 illustrates relative numberline positions in remainderless division for L, H, and C pursuant to a Rounding To Nearest.(Even) modc with the round bit set.

wo gl/10189 i O 9~ ~ 6 6 2 Pcr/usso/o73s1 FIG. 4 illustrates relative numberline positions in remainderless division for L, H, and C pursuant to a Rounding :
TQ ~'e~rest (Even) mode with the round bit clear.
FIG. 5 illustrates relative numberline positions in 5 remainderless division for L, H, and C pursuant to a Round Toward Zero mode with the round bit set. ~ ;-FIG. 6 illustrates relative numberline positions in remainderless division for L, H, and C pursuant to a Round ~
Toward Zero mode with the round bit clear. j !
l O FIG. 7 illustrates relative numberline positions in remainderless division for L, H, and C pursuaht to a Round Toward Positivc Infinity modc with the round bit set and the sign of C positive. ,~`
FIG. 8 illustrates relative numbe!line positions in l 5 remainderless division for L, H, and C pursuant to a Round Toward Positivc Infinity mode with the round bit clear and the sign of C positive. !;~
FIG. 9 illustrates relative numberline positions in remalnderless division for L, H, an~ C pursuant to a Round 20 ~ Toward;~ Positive Infinity mode with thc round bit set and the ` slgn of C ncgative.
FIG. 10 itlustrates relative numbcrline positions in `
remainderless division for L, H, and C pursuant~to a Round Toward ~Positivc ~Infinity mode with the round bit clear and the 2 5 sign~ of C ncgative.
FIG. 1 l illustrates relative numberline positions in remdndcrless division for L, H, and C pursuant to a Round Toward~ Ncgative Infinity mode with the round bit set and the ; sign of C positive.
3 0 FIG. 12 illustrates relative numberline positions in remainderless ;division for L, H, and C pursuant to a Round Toward Negative Infinity mode with the round bit clear ~nd the sign of C positive.

' ~ ~ .

wo 91/10189 Pcr/usso/o73sl i ~, . 1.

FIG. 13 illustrates relative numberline positions in ~
remainderless division for L, H, and C pursuant to a Round ^i' Toward Negativc Infinity mode with the round bit set and the sign of C negative. ~, FIG. 14 illustrates relative numberline positions in remainderless division for L, H, and C pursuant to a Round Toward Negative Infinity mode with the round bit clear and the sign of C negative.
FIG. 15 illustratcs relative numberline positions in remainderless square root dctermination for L, H, and C
pursuant to a Round To Nearest (Even) mode with the round bit set.
FIG. 16 illustrates relative numberline positions in -remainderless square root determination; for L, H, and C
pursuant to a Round To Nearest (Even) mode with the round bit clear.
FIG. 1~ illustratcs relative numberline positions in remainderless square root determination for L, H, and C
pursuant to a Round Toward Zero mode with` the round bit set.
2 0 FIG. 18 illustrates relative numberline positions in remainderless square root detcrmination for L, H, and C
pursuant to a Round Toward Zero mode with the round bit clear.
FIG. 19 illustrates relative numberline positions in 2 5 rcmaindcrlcss squarc root determination for L, H, and C
pursuant to a Round Toward Positive Infinity mode with the round bit sct.
FIG. 20 illustratos relative numberline positions in remainderless square root determination for L, H, and C
3 0 pursuant to a Round Toward Positive Infinity mode with the round bit clear.
FIG. 21 illustrates relative numberline positions in :

wo gl/10189 Pcr/usso/o73s1 ? ~ 4~i66~ 6 remainderless square root determination for L, H, ~nd C
pursuant to a Round Toward Negative Infinity mode with the -round bit set.
FIG. 22 illustrates relative numberline positions in remainderless squarc root determination for L, H. and C
pursuant to a Round Toward Negative Infinity mode with the round bit clear.
FIG. 23 is a general flow chart of an implcmentation of -the invention that shows IEEE FPS rounding for remainderless division utilizing a Round To Nearest (Even) rounding mode.
FIG. 24 is a general flow chart of an implementation of the invention that shows IEEE FPS rounding for remainderless ~;
division utilizing a Round Toward Zero rounding mode. ``
FIG. 25 is a gencral flow chart of; an implementation of the invention that shows IEEE FPS rounding for remainderless ~: division utilizing a Round Toward Positive Infinity rounding mode.
FIG. 26 is a gcncral flow chart of an implementation of ~; ~ the invention that shows IEEE FPS rounding for remainderless 2 0 ~ division utilizing a Round Toward Negativc Infinity rounding modc.
FIG. 27 is a gencral flow chart of an implcmentation of the invention that shows IEEE FPS rounding for remainderless division utilizing a Round Toward Zero rounding modc with 2 5 truncation. ~-FIG. 28 is a general flow chart of an implementation of thc invention that shows IEEE FPS rounding for rcmainderless - division udlizing a Round To Nearest (Even) rounding mode with truncatiôn.
3 0 FIG. 29A and 29B is a gencral flow chart of an implemcntation of the invention that shows IEEE FPS rounding for remaindcrless division utilizing a Round Toward Positive Infini~y rounding mode with truncation.

wo gl/10189 ` Pcr/usso/o735l ~

FIG. 30A and 30B is a general flow chart of an implementation of the invention that shows IEEE FPS rounding for remainderless division utilizing a Round Toward ~e~aaive Infinity rounding mode with truncation.
S FIG. 31 is a general flow chart of an implementation of ;
the invention that shows IEEE FPS rounding for remainderless square root determination utilizing a Round To Nearest (Even rounding mode.
FIG. 32 is a general nOw chart of an implementation of the invention that shows IEEE FPS rounding for remainderless square root determination utilizing a Round Toward Zero or Round Toward ~cgative Infinity rounding mode.
FIG. 33 is a gencral flow chart of an implementation of the invention that shows IEEE FPS rounding for remainderless square root determination utilizing a Round Toward Positive Infinity rounding mode.
FIG. 34 is a gencral flow chart of an implementation of the invention that shows IEEE FPS rounding for remainderless square root determination utilizing a Round To ~earest (Even 2 0 rounding modc with truncation.
FIG. 35 is a general flow chart of an implementation of the invention that shows IEEE FPS rounding for remainderless - ~ squarc root detcm~ination utilizing a Round Toward Zero or Round Toward Ncgative Infinity rounding mode with truncation.
FIG. 36 is a gcneral flow chart of an implementation of thc invention that shows IEEE FPS rounding for remainderless squarc root detcrmination utilizing a Round Toward Positive Infinity rounding mode with truncation.
FIG. 37 dcpicts a block diagram of a computer hardware implementation of the present invention.

WO 91/10189 ~ O ~ ~ 6 6~ PCr/US90/07351 8 :

~est Mode For Carrvin~ Out The InventiQn - FIG. 1, generally depicted by thc numeral 100~ illustr~tes one embodiment of steps executed by a high speed processor (HSP) incorporating a method of the present invention for rounding an output C (102) of a rounding precision having a least significant bit, the rounding precision typically specified by a precision given in the IEEE 754-1985 binary floating point . `
arithmetic standard, hereafter referenced as IEEE FPS, utilizing a desired rounding mode defined by a IEEE FPS rounding mode the output generated by remainderless division utilizing a ``
dividend value N, having a magnitude, INI, and a sign, and a divisor value D, having a magnitude, IDI, and a sign. As used herein, certain terms are defined as follows:
trunc (x) is defincd as a number in thc rounding precision nearest to x which has a magnitude that is less than or e~ual to a~ magnitude of x;
for IEEE FPS sign magnitude format trunc (x) can be !' computed by discarding all bits to the right of the least significant bit of thc rounding precision;
2 0 nextaway (x) is defined as: ~
nextafter (x, +oo3 if signed x is positive, and nextafter (x, -~) if signed x is negative;
this function is the next representable floating point number in tho rounding precision after x that has a magnitude ' largcr than Ixl;
and the nextaftcr function is defined according to the IEEE defini~on of same.
A first data storage and manipulation unit obtains and utilizes an output C, rcpresented by at least one electrical signal 3 0 and generatcd by remainderless division implementing a dividend value N, having a magnitude, INI~ and a sign, and a divisor valuc D, having a magnitude, IDI, and a sign, wherein C
has a magnitude, a sign conforrning to the IEEE FPS, and a round bit tbat is the bit to the right of the least significant bit WO 91/10189 PCr/US90/07351 9 .
, . . . .

of the specified rounding precision, and C is in an extended precision wherein the extended precision has a greater precision than the rounding precision ~102).
A first determining unit generates at least one of two 5 rounding values L and H, each having a magnitude, a sign. ~nd being represcnted by at least one electrical signal, and H ~
having a least significant bit (lsb), in the rounding precision ~;related to at least one of the following: the magnitude of C, the sign of C, and the rounding mode speci~led by the IEEE FPS
lO (104)-Single extended precision, double extended precision~ as well as higher extended precisions may be utilized as the extended precision.
The magnitude of L is less than the magnitude of H, and l 5 the magnitude of H is the ncxt representable magnitude greater than thc magnitude of L in the rounding precision.
The first determining unit determines the rounding values L and H (104) as follows:
incorporating an IEEE Round To Nearest (Even) procedure.
2 0 as set forth in FIG. 3, FIG. 4, and FIG. 23, the rounding value L
is trunc (C) and the rounding value H is equal to nextaway (L
(2304);
incorporating an IEEE Round Toward Zero procedure, as set forth in FIG. 5 and FIG. 24, the round bit of C (2402) is set 25 and the rounding value H is equal to nextaway [trunc (C)~, ~nd L - nextafter (H,0) (2404);
incorporating an IEEE Round Toward Zcro procedure, ~s set forth in E:IG. 6 and FIG. 24, the round bit of C (2402) is clear and the rounding value H is equal to trunc(C), and L = nextafter 3 0 (H,0) (2406);
incorporating an IEEE Round Toward Positive Infinity proccdure, as set forth in FIG~ 7 and FIG. 25, the round bit of C
(2402) is sct, the sign of C (2502) is positive, the value of i is equal to nextaway Itrunc(C)l, and H = nextaway (L) (2504);

WO 91/10189 PCI`/US90/07351 incorporating an IEEE Round Toward Positive Infinity procedure, as set forth in FIG. 8 and FIG. 25, the round bit of C
(2402) is clear, the sign of C (2502) is positive, the value of L is equal to trunc(C), and H = nextaway (L) (2506);
S incorporating an IEEE Round Toward Positive Infinity procedure, as set forth in FIG. 9 and FIG. 25, the round bit of C
(2402) is set, the sign of C (2S02) is negative, tbe value of H is equal to nextaway [trunc~C)~, and L = nextafter (H,O) (2508);
incorporating an IEEE Round Toward Positive Infinitv procedure, as set forth in FIG. 10 and FIG. 25, the round~ bit of C
(2402) is clear, the sign of C (2502) is negative, the v~lue of H
is equal :to trunc(C), and L = nextafter (H,O) (2510);
incorporating an IEEE Round Toward Negative Infinity ~!
procedure, as set fonh in FIG. 11 and FIG. 26 the round bit of C
(2402) is set, the sign of C (2602) is positive, thc value of H is equal to nextaway [tNnc(c)~ and L = nextafter (H,O,~ (2608);
: incorporating an IEEE Round Toward Negative Infinityproccdure, as sct forth in FIG. 12 and FIG. 26, the round bit of C
(2402) is clear, the sign of C (2602) is positive, the value of H is : ~ ?0 equal:to trunc(C), and L = nextafter (H,O) (~610) incorporating an IEEE Round Toward Negative Infinity proccdure, as;~set forth in FI&. 13 and FIG. 26, thc round bit of C
(2402) is sct, the sign of C (2602) is negative, the value of L is equal to nextaway Itrunc(C)l,and H = nextaway (L) (2304); and ;~: 25 ~ incorporating an IEEE Round Toward ~egative Infînity procedure, ~as set forth in FIG. l4 and FIG. ~6, thc round bit ot C
:~ (2402)~ is clear, the sign of C (2602) is negative, the value of 1 is cqual to trunc(C), and H = nextaway (L) (2604).
A second determining unit then determines A (FIG. 1, 3 0 106), reprcsented by at least one electrical signal and related : to at least one of the following: the magnitude of C~ the sign of C, and the desired rounding mode specified by the IEEE FPS
(104), whcrein A is determined as follows:

`

wo 91/1ot8s Pcr/usso/073sl !, 11 2045662 ' ' incorporating an IEEE Round To ~earest (Even) procedure~ .`
as set fonth in FIG. 23, the valuc of A is set to one-half the sum of the value of L plus the value of H (2306); ;
incorporating an IEEE Round Toward Zero procedure, as set forth in FIG. 24, thc value of A is set to thc ~alue of H .
(2408);
incorporating an IEEE Round Toward Positive Infinity procedure and the sign of C (2502) is positive, as set forth in FIG. 25, the value of A:is set to the value of L (2512);
incorporating an :IEEE Round Toward Positive Infinity procedure, and the sign of C (2502) is negative, ~as set forth in FIG. 25, the value of A is set to the value of H (2514);
incorporating an IEEE Round Toward Negative Infinity '`
procedure and the~ sign of C (2602) is positive, asi set forth in FIG. 26, ~the value of A is sct to thc value of H (2514); ~nd ncorporating an IEEE Round Toward Negative Infini~y procedure and the sign of C (2602) is negative, as set forth in FlG. 26,::the:value of A is set to the value of L (2512). -A third determining unit then determines a magnitude of : ~ 20 a product value, IA ~ Dl (108), represented by at least one electrical signal, by multiplying the intermediate value A simes the divisor value D, disregarding the sign of A ~ D, to obtain q magnitude IA ~ ~DI.
Ncxt. a fourth :detennining unit compares IA ~ Dl with 1~1 ~5 and gènetatcs~ a status (110), represented by at least one elec~caI~:signal, as follows: a divide status comprising "less than" if ~IA ~ Di is less than INI, "equal to" if IA ~ Dl equals 1~ nd "greater than" if IA ~ Dl is greatcr than lNI.
A fifth determining unit thcn determines a rounded 3 0 result value R (112), relativc to at least the fourth dctermining means and rcpresented by at Icast one elcctrical signal, in the : rounding prccision in conformance with the desired rounding mode spccified by thc IEEE FPS, as follows:
~' wo 91/10189 PCr/US90/07351 ~-incorporating an IEEE Round To ~earest (Even) rounding mode, as set forth in FIG. 23, selecting L or H using the divide .' status further includes a step of setting R equal to H if t~e divide status is "less than" (2312). and equal tO L if the divide 5 status is "greater than" (2314);
incorporating an IEEE Round To Nearest (Even) rounding mode, as set forth in FIG. 23, using the divide status of "equ~l to" further includes a step of setting R equal to L if the lsb of H
(2310) is equal to one (2314), or setting R equal to H if the Isb l~
1 0 of H `(2310) is equal to zero (2312);
incorporating an IEEE Round Toward Zero :rounding mode. 6 as set~forth in FIG. 24, selecting L or H using the divide status ~l further includes a step of setting R equal to H if ~the divide status is "less than" (2312), equal to L if the divide status is l 5 "greater than" t2314), or setting R equal`to H if ~he divide l!3 :status:is "equal to!' (23:12); :
ncorporating:an IEEE Round ~Toward Positive Infinity r~
rounding~mode, as set forth in FIG. 25, selecting L or H using the di~ide status ~and whcrcin the sign of C (2502) is positive 0 further: includes a step of :setting R equal to H if the divide status is :"less than" (2312), equal to L if the divide status is "greater than" (2314), or setting R equal to L if the divide : status is "equal tOn~ (2314~; r`
incorporating ~an IEEE Round Toward Positive Infinity - ~ 5: rounding~m~ade,: as set~ forth in FIG. 25~ selccting L or H using -: : thc diYide:sta~us; and~whcrein the sign of C ~2502) is negative -~h~ : further includes a step of; setting R equal to H if thc divide status is "less~ than" (2312), cqual to L if thc dividc status is - "greater than" (2314), or sctting R equal to H if the divide ~: ~ ` 3 0 status is "equal to" (2312);
: ~: : incorporating an IEEE Round Toward Negative Infinity `
~; rounding mode, as sct forth in ~:IG. 26, sclecting L or H using the dividc status and whcrein the sign of C (2602) is positive '.
: further includes a step of setting R equal to H if the divide ~::

WO 91/10189 PCI`/US90/07351 13 ~:
2~a66~ ~

status is "less than" (2312), equal to L if the divide status is "greater than" (2314), or setting R equal to H if the divide -~
status is "equal to" (2312); and incorporating an IEEE Round Toward Negative In~lnity rounding mode, as set forth in FIG. 26, selecting L or H
using the divide status and wherein the sign of C (2602) is -negative further includcs a step of setting R equal to H if the divide status is "less than" (2312), equal to L if the divide status is "grcater than"(23 14), or setting R equal to L if the divide status is "equal to" (23 14). :~
Another embodiment of the present invention ;
incorporates a truncation of IA ~ Dl to the precision of INI ~
after determination of IA ~ Dl, determination of whether the -~-inexact statu$. as defined by the IEEE FPS, of the truncated IA *
1 5 Dl is set or clear ~116), obtaining the divide status (110), and determining R ( 11 2), rcprcsented by at least one electrical signal, as follows: -incorporating an IEEE Round Toward Zero procedure, as ~:
set fonth in FIG. 27, thc value of the rounded result R (112) is 2 0 determined as follows:
for a divide status of "greatcr than," R is set equal to the value of L (2314), for a divide status of "equal to," and a set inexact status bit, R is set cqual to the value of L (2314), 2 5 for a divide status of "equal to," and a clear inexact status bit, R is set cqual to thc valuc of H (2312), and -~
for a divide status of "less than," R is set equal to the value of H (2312);
incorporating an IEEE Round To Nearest (Even) procedure~
as set forth in FIG. 28, the value of the roundcd result R (11'~
is dctermined as follows:
for a divide status of "greater than," R is set equal to ~he :
valuc of L (2314), wo 91/10189 . PC~/US90/07351 l 14 :
`36~`2 for a divide status of "equal to," and a set inexact status bit, R is set equal to the value of L (23i4), for a divide status of "equa~ toi" a least significan~ bit of H = O (2310), and a clear inexact status bit, R is set equal to the 5 value of H (2312), for a divide status of "equal to," a least significant bit of H = I (2310), and a clear inexact status bit, R is set equal to the value of L (2314), and for a divide status of "less than," R is equal to the value of H (2312), and `
incorporating an IEEE Round Toward Positive Infinity procedure where the sign of C is positive as set forth in FIG.
29A and 29B, the value of the rounded result R (112) is `
determined as follows:
for a divide status of "less than," R is set equal to the value of H (2312), and for a divide status of "greater than" or "equal to," R is set equal tO the value of L (2314).
incorporating an IEEE Round Toward Positive Infinity ' 0 procedure wherc the sign of C is negative as set forth in FIG.
29A and 29B, the value of the rounded result R ( I 12) is determined as follows:
for a dividc status of "greater ~han," R is set equal to the value of L (2314), 2 5: for a divide status of "equal to," and a set inexact status bit, R is set equal to the value of L (2314), for a divide status of "equal to,'` and a clear inexact status bit, R is set equal to the ~ralue of H (2312). and for a divide status of "less than," R is set equal to the value of H (2312);
incorporating an IEEE Round Toward Negative Infinity procedure wherc thc sign of C is positive as set forth in FIG.
30A and 30B, the value of the roundcd result R (112) is `
determincd as follows:

WO 91/10189 PCl /US90/07351 2~662 ~

for a divide status of "greater than," R is set equal to the value of L (2314).
for a divide status of "equal to," and a set inexact~status bit, R is set equal to the value of L (2314), for a divide status of "equal to," and a clear inexact st~tus bit, R is set equal to the value of H (2312), and ::
for a divide status of "less than,' R is set equal to the value of H (2312);
incorporating an IEEE Round Toward Negative Infinity :~
procedure where the sign of C is negative, as set forth in FIG.
30A and 30B, the valuc of the rounded result R ( 1 12) is determined as follows~
for a divide status of "less than," R is set equal to the value of H (2312), and for a divide status of "greater than" or "equal to," R is set equal to the valuc of L (2314).
: FIG. 2, gencrally depicted by the numeral 200, illustra~esonc embodiment of steps executed by a high speed processor (HSP) incorporating a method of the present invention for 2 0 rounding an output C (202) of a rounding precision having a least significant bit, the rounding precision typically specified by a- precision given in ~he IEEE 754-1985 binary floating point arithmetic stantard, hereafter referenced as IEEE FPS, utilizing a desired rounding mode defined by a IEEE F'PS rounding mode~
~5 thc output goneratod by remainderless square root determination utilizing an input value S, having a magnitude, ISI, and a sign. Certain terms, as used herein, arc defined as stated above: trunc (xj, nextaway (x), and the nextaftcr function. `~
3 0 A first data storagc and manipulation unit obtains ~nd utilizcs an output C, represented by at least one electrical signal and generated by remainderless square root determination, implementing an input ~ralue S, having a magnitude, ISI, and a sign, wherein C has a magnitude, a sign conforming to the IEEE

wo 91/10189 2 0 4 5 6 6 2 P~/usso/o73s1 16 `

FPS, and a round bit that is the bit to the right of the least significant bit of the speci~led rounding precision~ and C is in an extended precision or a modified mode simulating exten~ded precision wherein ~he extended precision has a greater S precision than the rounding precision (202).
A first determining unit generates at least one of two rounding values L and H, each having a magnitude, a sign, and being represented by a~ least one electrical signal, and H
having a least significant bit (lsb), in the rounding precision related tO at least one of the following: the magnitude of C, the `~
sign of C, and the rounding mode speci~led by the IEEE FPS
(104).
Single extended precision, double extended precision, as well as higher extended precisions may be utilized as the `
extended precision.
The magnitudc of L is less than the magnitude of H, and the magnitude of H is the next representable magnitude greater than the magnitude of L in the rounding precision.
The first de~ermining unit determines the rounding :: 20 values L and H (1~4) as follows:
incorporating an IEEE Round To Nearest (Even) procedure~
as set forth in ~G. 15 and FIG. 31, thc rounding value L is equal to trunc (C) (2304);
incorporating an IEEE Round To Nearest (Even) procedure, ' 25 as set forth in ~IG, 16 and FIG. 31, the rounding value H is equal to nextaway (1~) (2304);
incorporating an IEEE Round Toward Zero procedure as set forth in FIG. 17 and FIG. 32, or an IEEE Round Toward Negative Infinity procedure as set forth in FIG. 21 and FIG. 32, 30 where the round bit of C (2402) is sct, the rounding value H is equal to ncxtaway [trunc(C)], and the rounding value L is equal `, to nextafter (H,O) (2404);
incorporating an IEEE Round Toward Zero procedure as set forth in FIG. 18 and FIG. 32, or an IEEE Round Toward WO 91/10189 PCr/US90/07351 2~5662 ~Jegative Infinity procedure as set forth in .FIG. 22 ~nd FIG 3~.
wherc the round bit of C (2402) is clear. the rounding value H
is equal to trunc(C)~and the rounding value L i's e~qual to~
nextafter (H,O) (2406);
incorporating an IEEE Round Toward Positive Infinity -procedurc, as set forth in FIG. 19 and FIG. 33, where the round bi~ of C (2402) is set, the rounding value L is equal to nextaway ~trunc(C)l, and the rounding value H îs equal to nextaway (L
(2504); and l O incorporating an IEEE Round Toward Positive Infinity procedure, as set forth in FIG. 20 and FIG. 33, where the round .
blt of C (2402) is clear, the rounding value L is equal to trunc(C), and the rounding value H is equal to nextaway (~) :
(2506).
A second determining unit then determines A ( 1 06) as follows:
incorporating an IEEE Round Toward Zero procedure or an IEEE Round Toward Negative Infinity procedure, as set forth i n FIG. 32, the value of A is set to the value of H (2408);
2 0 incorporating an IEEE Round Toward Positive Infinity proccdure, as set forth in FIG. 33, the value of A is set to the .value of L (2512);
- A third determining unit then determines IA * Al (204) by multiplying the intermcdiate value A timcs itself to obtain 2 5 magnitudc IA * Al.
Next. a fourth determining unit compares IA * Al with ISI-and generates a status (206) as follows: a square root status comprising "1css than" if IA * Al is less than ISI, "equal to" if IA * Al equals ISI, and "grcater than'' if IA * Al is greater than ISI.
3 0 A fifth determining unit then dctermines a rounded result valuc R (112) in the rounding precision in conformance with thc dcsircd rounding modc spccificd by the IEEE FPS~ ~s follows:

WO 91/1018g Pcr/usso/o73 2o4~66~ 18 incorporating an IEEE Round To ?~earest (Even~ rounding mode, as set forth in FIG. 31, selecting L or H using the square root status further includcs a step of setting R equal to H if the square root status is "less than" (2312), and equal to L if the square root status is "greater than" (2314); .
incorporating an IEEE Round To Ncarest (Even) rounding mode, as set forth in FIG. 31, using the square root status of "equal to" further includes a step of setting R equal to L if the lsb of H (2310) is equal to one (2314), or setting R equal to H if ;
1 0 the lsb of H (2310) is equal to zero (2312);
incorporating an IEEE Round Toward Zero or an IEEE
Round Toward Negative Infinity rounding mode, as se~ forth in FIG~ 32, selecting L or H using the square root status further includes a step of setting R equal to H if thc square root status I S is "less than" (2312), equal to L if the square root status is --"greater than" (2314), or setting R equal to H if the square root status is "equal to" (2312?, and ~-incorporating an IEEE Round Toward Positive Infinity `;
rounding mode, as set forth in FIG. 33, selecting L or H using ;:
2 0 the square root status further includes a step of setting R equal to H if the square root status is "less than"(2312), equal to L if the square root status is "greater than" (2314), or setting R
equal to L if the square root status is "equal to" (2314). ,-Anothcr embodiment of the present invention ? 5 incorporatcs a truncation of IA ~ Al to the precision of ISI (?08) "`
after determination of IA * Al (204), determination of whether ~
the inexact status, as defined by the IEEE FPS, of thc truncated .-IA * Al is set or clear (210), obtaining the square root status (206), and determining R (112) as follows:
3 0 incorporating an IEEE Round Toward Zero procedure or a Round Toward Negative Infinity, as set forth in FIG. 35, the value of the rounded result R (112) is determined as follows: i for a square root status of "greater than," R is set eqùal to the value of L (2314), WO 91/10189 ` ~ PCT~/US90/07351 19 20~S662 for a square root status of "equal to," and a set inex~ct status bit, R is set equal to the value of L (231 4), for a square root status of "equal to," and a clear inex~ct status bit, R is set equal to thc value of H ~2312), and for a squarc root status of "less than," R is set equal to the value of H (2312);
incorporating an IEEE Round To Nearest (Even) procedure, as set forth in FIG. 34, thc value of the rounded result R (Il' is determined as follows:
for a square root status of "greater than," R is set e~ual to the value of L (2314), for a square root status of "equal to," and a set inexact status bit, R is set equal to the value of L (2314), for a square root status of "equal to," a least significant bit of H - 0 (2310), and a clear inexact status bit, R is set equal to the value of H (2312), : for a square root status of "equal to," a least significant bit of H = I (2310), and a clear inexact status bit, R is set equal to :the value of L (2314), and for a square root sta~us of "less than," R is equal to the value of H (2312), and incorporating an IEEE Round Toward Positive Infinity procedure, as sct forth in FIG. 36, the value of :he rounded result R ( 112) is determined as follows:
2 5 for a square root status of "less than," R is set equal to the value of H (2312), and for a square root status of "greater than" or "equal to," R is set cqual to thc value of L (2314).
for a square root status of "equal to," R is set equal to the value of L (2314).
FIG. 37, generally depicted by the numeral 3 illustrates a bloclc diagram of a computer hardware implementation of the invention. In one embodiment the ~irst data storage and manipulation unit obtains the inputs, 1~1, D, wo 91/10189 Pcr/usso/073sl 20451~62 20 and C for remainderless division, and ISI and C for remainderless square root determination and sends those values to the program control unit (3702). The said values traverse the bus (3710)? and arc placed in memory (3712).
5 The ALU (3706) performs thc computations as previously described, utilizing thc status register (3708~ to indicated inexact status. The program memory (3704) maintains the instructions for carrying out the invention. A first determining unit in the ALU (3706) generates L and H as previously 1 0 described. Thc second determining unit in the A~U (3706) determines A as prcviously described, a !.~lird determining unit in thc ALU (3706) determincs IA~Dl or IA~AI as previously set forth, a fourth determining unit in the ALU (3706) determines - the divide status or the square root status as dcscribed above, 1 S and a fifth determining unit in the ALU (3706) selects the correct rounding result R as previously described.
In another embodiment, as in FIG. 23 - 36, a digital sign~l processing method of the prcscnt invention for generating IEEE
754- 1985 binary floating point arithmetic standard, hereafter 2 0 designated EEE FPS, compliant remaindcrless division and square root dctcrmination outputs in systems utilizing those operations allocates at Icast onc first data storage and manipulation device for selection, storage, and manipulation of - an output value C from a remainderless division of a dividend 25 valuc N and a divisor value D, or a remainderless square root detennination of an input value S (102, 202), utilizing a dividcnd value N, having a magnitude, INI, and a sign, and a divisor value D, having a magnitude, IDI, and a sign, or by remaindcrless square root determination utilizing an input 30 value S, having a magnitude, ISI.
That method allocates at least one data storagc and manipulation device for manipuladng the output value C ~o ob~ain at least one of two possible rounding values, H and L, one that will be compliant with the IEEE F'PS (104)~ and further .

2o4~662 allocates at least one data storage and manipula~ion device for manipulating at least one of the possible rounding values, H
and L~ to determine an intermediate value A.
The method also allocates at least one data storage and S manipulation device for obtaining a magnitude of a product of thc intermediate value A and a predetermined checking value in the following manner: for remainderless division, by multiplying the intermediatc value A times the divisor value D~
disregarding thc sign of A ~ D, to obtain a magnitude I A * D I or for remainderless square root determination, by multiplying the intermediate value A times itself to obtain a magnitude `
IA ~ Al.
The method allocates at least one data storage and manipulation devicc for obtaining a comparison output of the `
magnitude of thc product IA ~ Dl or IA ~ Al with a second predctcrmined chec~ing value as follows: for a remainderless division algorithm, a divide status comprising "Icss than" if ~`
IA ~ Dl is less than INI, "cqual to" if IA ~ Dl equals INI, and ;
"greater than" if IA ~ Dl is grcatcr than INI, and for a 2 0 remaindcrlcss square root algorithm, a square root status comprising "less than" if IA ~ Al is lcss than ISI, "equal to" if IA ~ Al equals ISI, and "greater than" if IA ~ Al is greater than ISI.
The method further allocates at least one data storage 2 5 and manipulation device for selecting the possible rounding value R relativc to at least the comparison output such that the `
rounding valuc corrcsponds to the output value C roundcd in `
compliancc with thc IEEE FPS. The selection of R will be depcndent on other factors, as stated above.
In another cmbodimcnt a systcm utilizes the mcthod of the invention to enablc correlation of rounding an output C
from remaindcrlcss division or rcmaindcrlcss squarc root dctcrmination with an IEEE 754~1985 binary floating point arithmctic standard, hereaftcr designated IEEE FPS, utilizing WO 91/10189 PCI~/US90/07351 ~o ~566~ 22 control signal sets and inputs, and process control devices rcsponsive to control signal sets for controlling the computation process. Control signal sets and inputs include, among ~thers~
for remainderless division inputs values of a dividend value ~, having a magnitude, INI, and a sign, and a divisor value D, having a magnitude, IDI, and a sign, and an output value C or for remainderless squarc root determination an input value S, having a magnitude, ISI, and a sign, and an output value C.
Proccss control devices and a plurality of sensors include manipulation and data storage devices for carrying out the procedures set forth in the flow diagrams described above.
A controller includes at least one manipulation device for utilizing the input values to obtain a rounding value corresponding to the output value C rounded in compliance with the IEEE FPS, according to the method of the inventior~
described abovc.
It will be apparent to one skilled in the art that:
- the present invention may be entirely embodied in the ALU itself, 2 0 the status determining step may be accomplished in many fashions, including subtraction, the least significant bit of L may be alternatively utilized to determine a rounded result in conformance with the IEEE FPS, and the divide and square root status determinations may bc otherwise designated.
Although FIG. 3 through Fig. 22 would appear to indicate that the difference bctwcen the approximation C and an infinitcly precise result P is required to be less than one-half of 3 0 an lsb for proper opcration of this invcntion, the actual difference bctween C ant P must bc one-quarter of an lsb. The resolution between adjacent numbcrs changes when an exponcnt, as dcfined by the EEE FPS~ changes by one. As the IEEE cxponent increments, thc resolution of the significand, ~s wo 91/10189 2 0 ~ S 6 62 Pcr/usgoto7351 23 `:

defined in the IEEE FPS, is cut in half. Thus the difference between thc infinitely precise result P and the approximation C :
must be less than one-half of an lsb of the smallest resohltion, or equivalently, that difference must bc lcss than one-quarter S of an lsb of a coarser resolution so that that difference is less :
than one-half lsb of a finer resolution. ~:
What is claimed is:

..
: .
,

Claims (12)

1. A digital arithmetic unit for a high speed processor (HSP) for performing a set of mathematical operations to obtain a value R in conformance with a IEEE 754-1985 binary floating point arithmetic standard, hereafter referenced as IEEE FPS, of rounding pursuant to acquiring an output value C, in extended precision, in response to a remainderless division utilizing a signed dividend value N, having a magnitude, ¦N¦, and a sign, and a signed divisor value D, having a magnitude, ¦D¦, and a sign, or in response to a remainderless square root determination utilizing an input value S, having a magnitude, ¦S¦, and a sign, characterized by:
A) first data storage and manipulation means for manipulating and storing the output value C such that C has a magnitude, a sign, and a round bit that is the bit to the right of the least significant bit of the specified rounding precision, C
being in an extended precision where the extended precision has a greater precision than the rounding precision;
B) first determining means responsive to the first data storage and manipulation means for generating at least one of two rounding values L and H, each having a magnitude and a sign, and H having a least significant bit (Isb), in the rounding precision related to at least one of the following: the magnitude of C, the sign of C, and the desired rounding mode specified by the IEEE FPS;
C) second determining means responsive to the first data storage and manipulation means and to the first determining means for generating an intermediate value A
related to at least one of the following: the magnitude of C, the sign of C, and the desired rounding mode specified by the IEEE FPS;

D) third determining means responsive to the second determining means for generating a magnitude of a product value: for remainderless division, by multiplying the intermediate value A times the divisor value D, disregarding the sign of A * D, to obtain a magnitude ¦A * D¦ or for remainderless square root determination, by multiplying the intermediate value A times itself to obtain a magnitude ¦A * A¦;
E) fourth determining means responsive to the third determining means for generating, for a remainderless division algorithm, a divide status comprising "less than" if ¦A * D¦ is less than ¦N¦, "equal to" if ¦A * D¦ equals ¦N¦, and "greater than"
if ¦A * D¦ is greater than ¦N¦, and for generating, for a remainderless square root algorithm, a square root status comprising "less than" if ¦A *
A¦ is less than ¦S¦, "equal to" if ¦A * A¦ equals ¦S¦, and "greater than" if ¦A * A¦ is greater than ¦S¦;
F) fifth determining means responsive to the first determining means relative to at least the fourth determining means, for selecting L or H from step (B) above relative to at least the divide status or the square root status in step (E) as a rounded result value R in the rounding precision in conformance with the desired IEEE FPS rounding mode.

2. The HSP of claim 1, wherein the extended precision is one of: single extended precision and double extended precision.

3. The HSP of claim 1, wherein the rounding precision is one of: single precision and double precision.

4. The HSP of claim 1, wherein one of:
the magnitude of L is less than the magnitude of H;
the magnitude of H is the next representable magnitude greater than the magnitude of L in the rounding precision.

5. The HSP of claim 1, wherein one of:
A) for remainderless division incorporating an IEEE Round To Nearest (Even) procedure, the rounding value L is trunc (C) and the rounding value H is equal to nextaway (L);
the value of A is set to one-half the sum of the value of L plus the value of H;
selecting L or H using the divide status further includes a step of setting R equal to H if the divide status is "less than" and equal to L if the divide status is "greater than";
and using the divide status of "equal to" further includes a step of setting R equal to L if the Isb of H is equal to one, or setting R equal to H is the Isb of H is equal to zero;
B) for remainderless division incorporating an IEEE Round Toward Zero procedure, wherein the round bit of C is set, the rounding value H is equal to nextaway [trunc (C)] and L = nextafter (H,O);
the value of A is set to the value of H; and selecting L or H using the divide status further includes a step of setting R equal to H if the divide status is "less than," equal to L if the divide status is "greater than", or setting R equal to H if the divide status is "equal to;"

C) for remainderless division incorporating an IEEE Round Toward Zero procedure, wherein the round bit of C is clear, the rounding value H is equal to trunc(C) and L =
nextafter (H,O);
the value of A is set to the value of H; and selecting L or H using the divide status further includes a step of setting R equal to H if the divide status is "less than," equal to L if the divide status is "greater than", or setting R equal to H if the divide status is "equal to;"
D) for remainderless division incorporating an IEEE Round Toward Positive Infinity procedure, wherein the round bit of C
is set and the sign of C is positive, the value of L is equal to nextaway [trunc(C)] and H
= nextaway (L);
wherein the sign of C is positive, the value of A is set to the value of L; and selecting L or H using the divide status and wherein the sign of C is positive further including a step of setting R
equal to H if the divide status is "less than," equal to L if the divide status is "greater than," or setting R equal to L if the divide status is "equal to;"
E) for remainderless division incorporating an IEEE Round Toward Positive Infinity procedure, wherein the round bit of C
is clear and the sign of C is positive, the value of L is equal to trunc(C) and H = nextaway (L);
wherein the sign of C is positive, the value of A is set to the value of L; and selecting L or H using the divide status and wherein the sign of C is positive further including a step of setting R
equal to H if the divide status is "less than," equal to L if the divide status is "greater than," or setting R equal to L if the divide status is "equal to;"

F) for remainderless division incorporating an IEEE Round Toward Positive Infinity procedure, wherein the round bit of C
is set and the sign of C is negative, the value of H is equal to nextaway [trunc(C)] and L
= nextafter (H,O);
wherein the sign of C is negative, the value of A is set to the value of H; and selecting L or H using the divide status and wherein the sign of C is negative further including a step of setting R
equal to H if the divide status is "less than," equal to L if the divide status is "greater than," or setting R equal to H if the divide status is "equal to;"
G) for remainderless division incorporating an IEEE Round Toward Positive Infinity procedure, wherein the round bit of C
is clear and the sign of C is negative, the value of H is equal to trunc(C) and L = nextafter (H,O);
wherein the sign of C is negative, the value of A is set to the value of H; and selecting L or H using the divide status and wherein the sign of C is positive further including a step of setting R
equal to H if the divide status is "less than," equal to L if the divide status is "greater than," or setting R equal to L if the divide status is "equal to;"
H) for remainderless division incorporating an IEEE Round Toward Negative Infinity procedure, wherein the round bit of C
is set and the sign of C is positive, the value of H is equal to nextaway [trunc(C)] and L
= nextafter (H,O); and wherein the sign of C is positive, the value of A is set to the value of H; and selecting L or H using the divide status and wherein the sign of C is positive further including a step of setting R
equal to H if the divide status is "less than," equal to L if the divide status is "greater than," or setting R equal to H if the divide status is "equal to;"
I) for remainderless division incorporating an IEEE Round Toward Negative Infinity procedure, wherein the round bit of C
is clear and the sign of C is positive, the value of H is equal to trunc(C) and L = nextafter (H,O);
wherein the sign of C is positive, the value of A is set to the value of H; and selecting L or H using the divide status and wherein the sign of C is positive further including a step of setting R
equal to H if the divide status is "less than," equal to L if the divide status is "greater than," or setting R equal to H if the divide status is "equal to;"
J) for remainderless division incorporating an IEEE Round Toward Negative Infinity procedure, wherein the round bit of C
is set and the sign of C is negative, the value of L is equal to nextaway [trunc(C)] and H
= nextaway (L);
wherein the sign of C is negative, the value of A is set to the value of L; and selecting L or H using the divide status and wherein the sign of C is negative further including a step of setting R
equal to H if the divide status is "less than," equal to L if the divide status is "greater than," or setting R equal to L if the divide status is "equal to;" and K) for remainderless division incorporating an IEEE Round Toward Negative Infinity procedure, wherein the round bit of C
is clear and the sign of C is negative, the value of L is equal to trunc(C) and H = nextaway (L);
wherein the sign of C is negative, the value of A is set to the value of L; and selecting L or H using the divide status and wherein the sign of C is negative further including a step of setting R
equal to H if the divide status is "less than," equal to L if the divide status is "greater than," or setting R equal to L if the divide status is "equal to."

6. The HSP of claim 1, wherein one of:
A) for remainderless square root determination incorporating an IEEE Round To Nearest (Even) procedure, the rounding value L is equal to trunc (C);
the value of A is set to one-half the sum of the value of L plus the value of H;
selecting L or H using the square root status further includes a step of setting R equal to H if the square root status is "less than" and equal to L if the square root status is "greater than"; and using the square root status of "equal to" further includes a step of setting R equal to L if the Isb of H is equal to one, or setting R equal to H if the Isb of H is equal to zero;
B) for remainderless square root determination incorporating an IEEE Round To Nearest (Even) procedure, the rounding value H is equal to nextaway [trunc (C)];
the value of A is set to one-half the sum of the value of L plus the value of H;
selecting L or H using the square root status further includes a step of setting R equal to H if the square root status is "less than" and equal to L if the square root status is "greater than"; and using the square root status of "equal to" further includes a step of setting R equal to L if the Isb of H is equal to one, or setting R equal to H if the Isb of H is equal to zero;
C) for remainderless square root determination incorporating an IEEE Round Toward Zero procedure or an IEEE

Round Toward Negative Infinity procedure, wherein the round bit of C is set, the rounding value H is equal to nextaway [trunc(C)]
and the rounding value L is equal to nextafter (H,O);
the value of A is set to the value of H; and selecting L or H using the square root status further includes a step of setting R equal to H if the square root status is "less than," equal to L if the square root status is "greater than", or setting R equal to H if the square root status is "equal to;"
D) for remainderless square root determination incorporating an IEEE Round Toward Zero procedure or an IEEE
Round Toward Negative Infinity procedure, wherein the round bit of C is clear, the rounding value H is equal to trunc(C) and the rounding value L is equal to nextafter (H,O);
the value of A is set to the value of H; and selecting L or H using the square root status further includes a step of setting R equal to H if the square root status is "less than," equal to L if the square root status is "greater than", or setting R equal to H if the square root status is "equal to;"
E) for remainderless square root determination incorporating an IEEE Round Toward Positive Infinity procedure, wherein the round bit of C is set, the rounding value L is equal to nextaway [trunc(C)]
and the rounding value H is equal to nextaway (L);
the value of A is set to the value of L; and selecting L or H using the square root status further includes a step of setting R equal to H if the square root status is "less than," equal to L if the square root status is "greater than," or setting R equal to L if the square root status is "equal to;" and F) for remainderless square root determination incorporating an IEEE Round Toward Positive Infinity procedure, wherein the round bit of C is clear, the rounding value L is equal to trunc(C) and the rounding value H is equal to nextaway (L);
the value of A is set to the value of L; and selecting L or H using the square root status further includes a step of setting R equal to H if the square root status is "less than," equal to L if the square root status is "greater than," or setting R equal to L if the square root status is "equal to."

7. A method of rounding outputs to a rounding precision having a least significant bit, the rounding precision typically specified by a precision given in the IEEE 754-1985 binary floating point arithmetic standard, hereafter referenced as IEEE FPS, utilizing a desired rounding mode defined by a IEEE
FPS rounding mode, the output C generated by remainderless division utilizing a dividend value N, having a magnitude, ¦N¦, and a sign, and a divisor value D, having a magnitude, ¦D¦, and a sign, or by remainderless square root determination utilizing an input value S, having a magnitude, ¦S¦, and a sign, the said method comprising the steps of:
A) obtaining an output value C that has a magnitude, a sign conforming to the IEEE FPS, and a round bit that is the bit to the right of the least significant bit of the specified rounding precision, C being in an extended precision wherein the extended precision has a greater precision than the rounding precision, C being obtained from an indicated remainderless division algorithm utilizing a signed dividend value N and a signed divisor value D or a remainderless square root algorithm utilizing an input value S, and the signed output value C being represented by at least one electrical signal;
B) generating at least one of two rounding values L
and H, each having a magnitude and a sign, and H having a least significant bit (Isb), in the rounding precision related to at least one of the following: the magnitude of C, the sign of C, and the rounding mode specified by the IEEE FPS, and represented by at least one electrical signal;
C) generating an intermediate value A related to at least one of the following: the magnitude of C, the sign of C, and the desired rounding mode specified by the IEEE FPS, and represented by at least one electrical signal;
D) generating a magnitude of a product value: for remainderless division, by multiplying the intermediate value A times the divisor value D, disregarding the sign of A * D, to obtain a magnitude ¦ A * D ¦ or for remainderless square root determination, by multiplying the intermediate value A times itself to obtain a magnitude ¦ A * A ¦, wherein ¦A * D¦ or }A * A ¦ is represented by at least one electrical signal;
E) generating, for a remainderless division algorithm, a divide status comprising "less than" if ¦A * D¦ is less than ¦N¦, "equal to" if ¦A * D¦ equals ¦N¦, and "greater than" if ¦A * D¦ is greater than ¦N¦, and generating, for a remainderless square root algorithm, a square root status comprising "less than" if ¦A * A¦ is less than ¦S¦, "equal to" if ¦A * A¦ equals ¦S¦, and "greater than" if ¦A * A¦
is greater than ¦S¦, the status generated being represented by at least one electrical signal;
F) selecting L or H from step (B) above relative to at least the divide status or the square root status in step (E) as a rounded result value R in the rounding precision in conformance with the desired rounding mode specified by the IEEE FPS, the rounded result value R selected being represented by at least one electrical signal.

8. The method of claim 7, wherein the extended precision is one of: single extended precision and double extended precision.

9. The method of claim 7, wherein the rounding precision is one of: single precision and double precision.

10. The method of claim 7, wherein one of:
the magnitude of L is less than the magnitude of H;
the magnitude of H is the next representable magnitude greater than the magnitude of L in the rounding precision.

11. The method of claim 7, wherein one of:
A) for remainderless division incorporating an IEEE Round To Nearest (Even) procedure, the rounding value L is trunc (C) and the rounding value H is equal to nextaway (L);
the value of A is set to one-half the sum of the value of L plus the value of H;
selecting L or H using the divide status further includes a step of setting R equal to H if the divide status is "less than" and equal to L if the divide status is "greater than";
and using the divide status of "equal to" further includes a step of setting R equal to L if the Isb of H is equal to one, or setting R equal to H is the Isb of H is equal to zero;
B) for remainderless division incorporating an IEEE Round Toward Zero procedure, wherein the round bit of C is set, the rounding value H is equal to nextaway [trunc (C)] and L = nextafter (H,O);
the value of A is set to the value of H; and selecting L or H using the divide status further includes a step of setting R equal to H if the divide status is "less than," equal to L if the divide status is "greater than", or setting R equal to H if the divide status is "equal to;"
C) for remainderless division incorporating an IEEE Round Toward Zero procedure, wherein the round bit of C is clear, the rounding value H is equal to trunc(C) and L =
nextafter (H,O);
the value of A is set to the value of H; and selecting L or H using the divide status further includes a step of setting R equal to H if the divide status is "less than," equal to L if the divide status is "greater than", or setting R equal to H if the divide status is "equal to;"
D) for remainderless division incorporating an IEEE Round Toward Positive Infinity procedure, wherein the round bit of C
is set and the sign of C is positive, the value of L is equal to nextaway [trunc(C)] and H
= nextaway (L);
wherein the sign of C is positive, the value of A is set to the value of L; and selecting L or H using the divide status and wherein the sign of C is positive further including a step of setting R
equal to H if the divide status is "less than," equal to L if the divide status is "greater than," or setting R equal to L if the divide status is "equal to;"
E) for remainderless division incorporating an IEEE Round Toward Positive Infinity procedure, wherein the round bit of C
is clear and the sign of C is positive, the value of L is equal to trunc(C) and H = nextaway (L);
wherein the sign of C is positive, the value of A is set to the value of L; and selecting L or H using the divide status and wherein the sign of C is positive further including a step of setting R
equal to H if the divide status is "less than," equal to L if the divide status is "greater than," or setting R equal to L if the divide status is "equal to;"
F) for remainderless division incorporating an IEEE Round Toward Positive Infinity procedure, wherein the round bit of C
is set and the sign of C is negative, the value of H is equal to nextaway [trunc(C)] and L
= nextafter (H,O);
wherein the sign of C is negative, the value of A is set to the value of H; and selecting L or H using the divide status and wherein the sign of C is negative further including a step of setting R
equal to H if the divide status is "less than," equal to L if the divide status is "greater than," or setting R equal to H if the divide status is "equal to;"
G) for remainderless division incorporating an IEEE Round Toward Positive Infinity procedure, wherein the round bit of C
is clear and the sign of C is negative, the value of H is equal to trunc(C) and L = nextafter (H,O);
wherein the sign of C is negative, the value of A is set to the value of H; and selecting L or H using the divide status and wherein the sign of C is positive further including a step of setting R
equal to H if the divide status is "less than," equal to L if the divide status is "greater than," or setting R equal to L if the divide status is "equal to;"
H) for remainderless division incorporating an IEEE Round Toward Negative Infinity procedure, wherein the round bit of C
is set and the sign of C is positive, the value of H is equal to nextaway [trunc(C)] and L
= nextafter (H,O); and wherein the sign of C is positive, the value of A is set to the value of H; and selecting L or H using the divide status and wherein the sign of C is positive further including a step of setting R
equal to H if the divide status is "less than," equal to L if the divide status is "greater than," or setting R equal to H if the divide status is "equal to;"

I) for remainderless division incorporating an IEEE Round Toward Negative Infinity procedure, wherein the round bit of C
is clear and the sign of C is positive, the value of H is equal to trunc(C) and L = nextafter (H,O);
wherein the sign of C is positive, the value of A is set to the value of H; and selecting L or H using the divide status and wherein the sign of C is positive further including a step of setting R
equal to H if the divide status is "less than," equal to L if the divide status is "greater than," or setting R equal to H if the divide status is "equal to ;"
J) for remainderless division incorporating an IEEE Round Toward Negative Infinity procedure, wherein the round bit of C
is set and the sign of C is negative, the value of L is equal to nextaway [trunc(C)] and H
= nextaway (L);
wherein the sign of C is negative, the value of A is set to the value of L; and selecting L or H using the divide status and wherein the sign of C is negative further including a step of setting R
equal to H if the divide status is "less than," equal to L if the divide status is "greater than," or setting R equal to L if the divide status is "equal to;" and K) for remainderless division incorporating an IEEE Round Toward Negative Infinity procedure, wherein the round bit of C
is clear and the sign of C is negative, the value of L is equal to trunc(C) and H = nextaway (L);
wherein the sign of C is negative, the value of A is set to the value of L; and selecting L or H using the divide status and wherein the sign of C is negative further including a step of setting R
equal to H if the divide status is "less than," equal to L if the divide status is "greater than," or setting R equal to L if the divide status is "equal to."

12. The method of claim 7, wherein one of:
A) for remainderless square root determination incorporating an IEEE Round To Nearest (Even) procedure, the rounding value L is equal to trunc (C);
the value of A is set to one-half the sum of the value of L plus the value of H;
selecting L or H using the square root status further includes a step of setting R equal to H if the square root status is "less than" and equal to L if the square root status is "greater than"; and using the square root status of "equal to" further includes a step of setting R equal to L if the Isb of H is equal to one, or setting R equal to H if the Isb of H is equal to zero;
B) for remainderless square root determination incorporating an IEEE Round To Nearest (Even) procedure, the rounding value H is equal to nextaway [trunc (C)];
the value of A is set to one-half the sum of the value of L plus the value of H;
selecting L or H using the square root status further includes a step of setting R equal to H if the square root status is "less than" and equal to L if the square root status is "greater than"; and using the square root status of "equal to" further includes a step of setting R equal to L if the Isb of H is equal to one, or setting R equal to H if the Isb of H is equal to zero;
C) for remainderless square root determination incorporating an IEEE Round Toward Zero procedure or an IEEE
Round Toward Negative Infinity procedure, wherein the round bit of C is set, the rounding value H is equal to nextaway [trunc(C)]
and the rounding value L is equal to nextafter (H,O);

the value of A is set to the value of H; and selecting L or H using the square root status further includes a step of setting R equal to H if the square root status is "less than," equal to L if the square root status is "greater than", or setting R equal to H if the square root status is "equal to;"
D) for remainderless square root determination incorporating an IEEE Round Toward Zero procedure or an IEEE
Round Toward Negative Infinity procedure, wherein the round bit of C is clear, the rounding value H is equal to trunc(C) and the rounding value L is equal to nextafter (H,O);
the value of A is set to the value of H; and selecting L or H using the square root status further includes a step of setting R equal to H if the square root status is "less than," equal to L if the square root status is "greater than", or setting R equal to H if the square root status is "equal to;"
E) for remainderless square. root determination incorporating an IEEE Round Toward Positive Infinity procedure, wherein the round bit of C is set, the rounding value L is equal to nextaway [trunc(C)]
and the rounding value H is equal to nextaway (L);
the value of A is set to the value of L; and selecting L or H using the square root status further includes a step of setting R equal to H if the square root status is "less than," equal to L if the square root status is "greater than," or setting R equal to L if the square root status is "equal to;" and F) for remainderless square root determination incorporating an IEEE Round Toward Positive Infinity procedure, wherein the round bit of C is clear, the rounding value L is equal to trunc(C) and the rounding value H is equal to nextaway (L);

the value of A is set to the value of L; and selecting L or H using the square root status further includes a step of setting R equal to H if the square root status is "less than," equal to L if the square root status is "greater than," or setting R equal to L if the square root status is "equal to."