CA2032922C - Anti-copying video signal processing - Google Patents

Abstract

Counting circuitry in the vertical synchronizing circuit of a video receiver is prevented from generating vertical control signals at a fixed, standard periodicity when the video signal transmitted to that receiver exhibits a changing field interval which varies above and below that standard period. At least one of the vertical pulses in the vertical period of each field interval as well as plural equalizing pulses in the post equalizing period in that field interval are deleted from the video signal. To minimize perturbations in the video picture displayed from that video signal, the time of occurrence of the first vertical pulse in selected field intervals is shifted.

Description

BACKGROUND OF THE INVENTION
This invention relates to improvements in the apparatus of U.S. Patent No. 4,914,694 whereby video picture distortion, interference and perturbations are prevented when a video signal which is processed in accordance with the teaching of the aforementioned patent is received by a video receiver of the type having digital vertical synchronizing circuitry.
Broadly, the apparatus disclosed in the aforementioned patent processes a conventional video signal, such as an NTSC
television signal, such that a video picture may be derived and displayed therefrom by a conventional television receiver without additional decoding, decryption, or further processing, yet a conventional video recorder is prevented from recording and playing back that processed video signal. This copy prevention is achieved by increasing and decreasing the length of respective field or frame intervals above and below their conventional lengths. Although conventional television receivers can "follow such variable frame lengths, conventional video recorders cannot.
For example, a conventional frame in the NTSC standard is formed of 525 horizontal line intervals. In accordance with the aforementioned patent, the frame length is increased by adding more line intervals thereto and is decreased by providing less than the standard 525 lines. The rate at which the frame length increases and decreases, the maximum and minimum lengths or durations of a frame and the number of frames which remain at the 20329~2 maximum and minimum lengths constitute what is referred to in the aforementioned patent as a "profilen. The profile determines frame lengths and varies from time to time.
Notwithstanding such changes in the video frame lengths as well as changes in the profiles which control those lengths, conventional television receivers nevertheless are capable of detecting the vertical synchronizing signals included in each video field and, thus, produce accurate video pictures from those video signals without undesired picture interference. However, the usual servo control systems included in virtually every video tape recorder (VTR) are unable to ~lock" onto the vertical synchronizing signals which occur at increasing and decreasing periods in the processed video signal. Thus, whereas accurate video pictures are reproduced by conventional television receivers, the video signals which are processed with varying profiles, as disclosed in the aforementioned patent, are not accurately recorded and reproduced by conventional VTR's.
Recently, television receivers having digital vertical synchronizing circuits have been introduced. Such circuits generally are of two different types but both typically lock onto the received synchronizing signals after several frames have been received and both "release" the lock-on mode after several frames have been received with noncoinciding synchronizing signals. One type of digital circuit merely counts the horizontal synchronizing pulses included in a field interval. After a predetermined number ~ ~,, .

2o32922 of such horizontal synchronizing pulses have been counted, the circuitry simply assumes that the beginning (or end) of a field interval has been reached and a vertical retrace signal is generated to retrace to its initial position the scanning electron beam which is used to produce the video picture. For example, in a standard NTSC video signal, once the beginning of a field interval is determined, the vertical retrace signal is generated each time the horizontal synchronizing pulse count reaches 262.5 tor 525). If, by reason of the processing technique disclosed in the aforementioned patent, the number of line intervals included in a frame is greater than 525, this type of digital vertical synchronizing circuit will generate a vertical retrace signal before an entire field has been received and displayed.
Similarly, if less than 525 line intervals are included in a frame of processed video signals, this digital vertical synchronizing circuit will generate a vertical retrace slgnal some time after the next field has been received. As a result, picture n jumping"
will be observed.
But, this type of digital vertical synchronizing circuit has been designed to account for the possibility that a non-standard frame containing more or less than 525 line intervals is received. Vertical retrace is initiated when a 262.5 horizontal sync pulse count is reached only if a predetermined number of frames are received in succession having frame intervals that contain precisely 525 line intervals. Typically, such digital 20~2922 vertical synchronizing circuitry examines two successive frames to verify that each contains 525 lines. If not, the horizontal sync pulse counting operation is not initiated and, thus, a vertical retrace signal is not generated after 262.5 line intervals have been counted. Instead, the vertical retrace signal is produced when the vertical pulses included in the vertical synchronizing interval are detected.
To avoid vertical perturbations in the video picture which may be produced when thls type of digital vertical synchronizing circuit is used, the profile which controls the processing of the video signal, as disclosed in the aforementioned patent, makes certain that two successive frames do not contain 525 line intervals. Thus, this type of digital vertical synchronizing circuit is unable to "lock" onto the received video signal and the horizontal sync pulse counting operation cannot be carried out. Consequently, this type of digital vertical synchronizing circuit is prevented Z03;~9~,'Z

PATENT

1 from generating vertical retrace signals at constant, fixed

2 periods when the field periods of the received video signal are

3 varying.

4 Another type of digital vertical synchronizing circuit likewise initiates a horizontal sync pulse counting operation, 6 but this is done once a "standard" vertical synchronizing 7 interval is detected. The standard vertical synchronizing 8 interval included in the NTSC signal contains six pre-equalizing g pulses in the first three line intervals of a field, followed by six vertical pulses in the next three line intervals, followed by 11 six post-equalizing pulses in the next-following three line 12 intervals. If this "standard" vertical synchronizing interval is 13 sufficiently distorted, the digital vertical synchronizing 14 circuit will be unable to detect it and, thus, the horizontal sync pulse counting operation will be inhibited.
16 This type of digital vertical synchronizing circuit, 17 which senses a standard vertical synchronizing interval, operates 18 to detect when nine pulses of the twelve vertical and post-19 equalizing pulses are present. If the vertical and post-equalizing pulses are distorted such that no more than eight of 21 these twelve pulses are present, the "standard" vertical 22 synchronizing interval will not be sensed and vertical retrace 23 signals will not be generated at standard, fixed intervals.
24 Thus, the digital vertical synchronizing circuit will be defeated _5_ Z03~9~Z
PATENT

1 and a vertical retrace signal-wIll be~generated at the end of 2 each variable length field interval and not at fixed periods.
3 It also has been found that, even when analog vertical 4 synchronizing circuits are used to generate vertical retrace signals, brief vertical perturbations may be introduced into the 6 video picture in response to an increase or decrease in a field 7 interval. That is, when the length of a field interval is 8 changed, as by increasing or decreasing the number of line 9 intervals included therein, a brief vertical shift in the displayed video picture occurs; and this appears as a momentary ll reduction in interlace accuracy. However, this shift generally 12 is not observable and, moreover, disappears within one or two 13 field intervals thereafter. It is believed that this shift is 14 due to a change in the duty cycle of deflection current flowing through the vertical deflection coils of a typical television 16 receiver. The average DC level of the deflection current 17 establishes the center of the video picture. However, when the 18 duty cycle of the deflection current changes, as will occur when 19 the vertical pulses in the received video signal recur at greater or lesser intervals (due to increasing or decreasing frame 21 lengths), the average DC level of the deflection current will 22 change abruptly but soon thereafter will return to the middle of 23 the picture area. This change results in a corresponding 24 vertical movement of the video picture.

2 0 3 2 9 2 ~60939-1520 OBJECTS OF THE INVENTION
Therefore, it is an object of the present invention to provide an improvement to the video signal processing technique disclosed in the aforementioned patent which prevents digital vertical synchronizihg circuits from locking onto a standard frame repetition rate when, in fact, the video signal supplied thereto does not exhibit such a standard rate.
Another object of this invention is to improve the video signal processing technique disclosed in the aforementioned patent to prevent or at least minimize vertical perturbations which may be present in the video picture reproduced from a video signal having variable field and frame intervals.
A further object of this invention is to modify the standard vertical synchronizing interval included in a video signal to prevent that vertical synchronizing interval from being detected and used to generate periodic vertical control signals when, in fact, the video signal itself does not exhibit a fixed field or frame period.
An additional object of this invention is to modify the vertical pulses included in the vertical synchronizing interval of a video signal having a changing field and frame repetition rate so as to eliminate or at least minimize vertical perturbations in the video picture reproduced therefrom.

A~ ~

Z03;29ZZ

PATENT

1 Various other objects, advantages and features of the 2 present invention will become readily apparent from the ensuing 3 detailed description, and the novel features will be particularly 4 pointed out in the appended claims.
SUMMARY OF THE I~v~ ON
6 In accordance with this invention, the counting 7 circuitry included in the vertical synchronizing circuit of some 8 video receivers is prevented from generating vertical control 9 signals, such as vertical retrace pulses, at a fixed, standard periodicity when the video signal transmitted thereto exhibits a 11 changing field interval which varies above and below that 12 standard period. At least one of the vertical pulses in the 13 vertical period and some of the equalizing pulses in the post-14 equalizing period of each field interval are deleted.
Advantageously, the vertical pulses which are deleted are those 16 that commence at substantially the midpoint of a line interval.
17 Desirably, the last vertical pulse to commence at a line interval 18 midpoint is deleted. Accordingly, the deleted vertical pulse is 19 the last vertical pulse in each odd field interval and is the penultimate vertical pulse in each even field interval. The 21 post-equalizing pulses which are deleted preferably are those 22 which commence at the midpoint of a line interval.
23 As a feature of this invention, the line intervals in a 24 field interval are counted, and those vertical and equalizing pulses which occur at predetermined line interval counts are deleted.
As another aspect of this invention, the time of occurrence of the first vertical pulse in selected field intervals is shlfted. Advantageously, the first vertical pulse is advanced when the field interval of the video signal is increased, and the first vertical pulse is delayed when the field interval is delayed. Preferably, this shifting in the time of occurrence of the first vertical pulse is on the order of about one-third of a horizontal line interval.
BRIEF DESCRIPTION OF THE DRAWINGS
The following detailed description, given by way of example and not intended to limit the present invention solely thereto, will best be understood in conjunction with the accompanying drawings in which:
FIG. 1 is a block diagram representing the manner in which the vertical periods (i.e. frame lengths) of a television signal are adjusted in accordance with the invention of U.S.
Patent 4,914,694;
FIGS. 2A and 2B are graphical representations of profile patterns used by the lnvention of the aforementioned patent;
FIGS. 3A-3C are graphical representations of the manner in which vertical compensation in the video picture is attained when using the invention of the aforementioned patent;
FIGS. 4A and 4B are diagrammatical representations which are useful in understanding the manner in which frame lengths are ~.

adjusted in accordance with the invention of the aforementioned patent;
FIG. 5 is a block diagram representing one manner in which geometric compensation is achieved when using the invention of the aforementioned patent;
FIG. 6 is a block diagram of the electronics used to generate various timing signals for controlling frame length adjustments;
FIGS. 7A-7F are waveform diagrams which are useful in understanding the operation of the electronics shown in FIG. 6;
FIG. 8 is a block diagram of electronics used to adjust frame lengths in accordance with another embodiment of the invention of the aforementioned patent;
FIG. 9 is a block diagram of an overall television subscription system in which the invention of the aforementioned patent finds ready application;
FIG. 10 is a loglc diagra~ representing the manner in which "fingerprint" information may be provided in the system shown in FIG. 9 to detect misappropriation of the television signal transmitted via the subscription system;
FIGS. llA-llG are waveform diagrams which are useful in understanding the operation of FIG. 10;
FIG. 12 is a block diagram showing in greater detail a portion of the system shown in FIG. 9;
FIGS. 13A-13C are waveform diagrams which are useful in understanding one aspect of the subscription system shown in FIG.

9;

9a ~,;-FIG. 14 is a block diagram showing in greater detail another portion of the system illustrated in FIG. 9;
FIG. lS represents the manner in which the present invention may be used in the system shown in FIG. 9;
FIG. 16 is a block diagram showing in greater detail yet another portion of the system shown in FIG. 9; and FIG. 17 is a block diagram showing in greater detail the manner in which video signals are written into and read from a memory to provide both descrambling and vertical period adjustment;
FIG. 18 is a block diagram illustrating the use of the present invention in conjunction with apparatus of the type disclosed in the aforementioned patent;
FIG. 19 is a block diagram of one embodiment of a synchronizing signal generator which carries out the present invention;

9b Z0329i~Z

PATENT

1 FIGS. 2OA-2OH., 2lA-2lH, 22A-22H and 23A-23I are 2 waveform diagrams which are useful in understanding the operation 3 of the synchronizing signal generator shown in FIG. 19; and 4 FIGS. 24A and 24B are waveform diagrams which are useful in understanding the manner in which the present invention 6 minimizes vertical perturbations in the video picture reproduced 7 from a video signal having a changing field repetition rate.

9 The Parent A~plication Referring now to the drawings, wherein like reference 11 numerals are used throughout, and in particular to FIG. 1, there 12 is illustrated a block diagram of one embodiment of the present 13 invention. The apparatus illustrated in FIG. l is adapted to 14 modify the vertical period of a television signal so as to increase or decrease the vertical period with respect to nominal 16 field intervals of 16.683 milliseconds, thereby defeating the 17 ability of virtually all commercially available VTR's to record 18 and satisfactorily reproduce a video picture from the modified 19 television signal. By adjusting the vertical period, either by maintaining a constant number of horizontal line intervals but 21 varying the duration of groups of those line intervals, or by 22 adding or deleting line intervals while maintaining a constant 23 duration of each line interval, the capstan and drum servo 24 circuits normally provided in VTR's are inhibited from operating ~03Z9Z'~

PATENT

1 satisfactorily.However, this vertical period adjustment does not 2 prevent the vertical sync detecting circuitry normally provided 3 in most television receivers, including those television 4 receivers recently introduced having digital synchronizing circuitry, from displaying satisfactory video pictures. Thus, 6 the modified television signal cannot be adequately recorded and 7 reproduced, but nevertheless can be satisfactorily received for 8 video picture display on a conventional television receiver.
g The system shown in FIG. 1 includes an analog-to-digital converter 102 (referred to hereafter for convenience as 11 an A/D converter), a memory device 104, memory write and read 12 controls 106 and 108, a central processor 110, a digital-to-13 analog converter 112 (referred to hereafter simply as a D/A
14 converter), a profile library 118 and a scene change detector 120. A/D converter 102 is adapted to digitize a received 16 television signal such that pixels having respective pixel values 17 are produced to represent each horizontal line interval included 18 in the received television signal. As will become apparent, it 19 may not be necessary to digitize the synchronizing information included in the composite television signal and, therefore, A/D
21 converter 102 may be adapted simply to digitize only the useful 22 video information. For example, suitable timing signals may be 23 generated and supplied to the A/D converter such that it operates 24 only during those intervals that useful video information (also Z03~9~2 PATENT

1 referred to herein as ~activeU-video inrormation) is present. As 2 an alternative, a synchronizing signal separator circuit (not 3 shown) may be provided to strip the usual horizontal 4 synchronizing signals (including the usual color burst subcarrier signal) from the composite television signal, thereby supplying 6 A/D converter 102 only with useful video information.
7 The A/D converter is coupled to memory 104 which, 8 preferably, comprises an addressable memory adapted to store the 9 pixels included in at least each active horizontal line interval that has been digitized by A/D converter 102. For convenience, 11 memory 104 may be thought of as being formed of addressable rows, 12 with each row being adapted to store the pixels which constitute 13 an active horizontal line interval (e.g. line intervals 21 to 241 14 of a field). Write control circuit 106 and read control circuit 108 are coupled to memory 104 and serve to generate write and 16 read addresses, respectively, as well as timing and other control 17 signals, whereby each line interval may be written into and read 18 from a row of memory 104. As illustrated, write and read control 19 circuits 106 and 108 are coupled to processor 110 and receive address and other control signals from the processor. Thus, the 21 processor is adapted to determine the particular addresses of 22 memory 104 in which digitized horizontal line intervals are 23 stored and from which those digitized line intervals are read.As 24 will be described, each line interval, and preferably each active Z0329Z~2 PATENT

1 line inter~al, ~s written into memory 1~4 at a substant~ally 2 constant, standard write-in rate synchronized with the usual 3 horizontal line frequency fN of 15.735 KHz; and in one 4 embodiment, read control circuit 108 is adapted to read out from memory 104 each digitized active line interval at a variable 6 read-out rate within a predetermined range determined by 7 processor 110. In one embodiment, the read-out rate may vary 8 from approximately 15.370 KHz to approximately 16.110 KHz. These 9 ranges are not intended to be limitations but, rather, should be viewed merely as illustrative and explanatory of the present 11 invention.
12 Since each frame of television signals is comprised of 13 alternating field intervals, one being designated an "odd" field 14 and the other being designated an "even" field, it is preferable that memory 104 be thought of as including two field memories, 16 one for the odd field and one for the even.Thus, when pixels are 17 written into the odd memory, the pixels which are stored in the 18 even memory may be read out therefrom. Conversely, after pixels 19 have been read from the even memory, the line intervals contained within the next even field are written into this even memory, and 21 the pixels now stored in the odd memory are read out.
22 As a further refinement, it is appreciated that, since 23 the rate at which line intervals are read out from memory 104 24 differs from the rate at wh~ch line intervals are written in, it ~13-PATENT

1 is possible that a field of line intervals may not have been 2 fully read from the field memory at the time that the next field 3 is to be written therein. To accommodate this possibility, 4 memory 104 may be formed of an array of eight memories, such as four memory storage devices to accommodate four odd fields and 6 four memory storage devices to accommodate four even fields. It 7 should be recognized that these numerical examples merely are 8 illustrative and are not intended to limit the present invention g solely thereto. Any desired number of odd and even field memories may be used to carry out the present invention. With 11 multiple field memories, it is appreciated that the write and 12 read address signals generated by write and read control circuits 13 106 and 108 in response to processor 110 include memory select 14 signals such that the appropriate but different field memories lS are selected for concurrent write-in and read-out operations, as 16 determined by the processor. By using multiple field memories, 17 the possibility of data "collisions" caused by 18 overwriting data into a field memory which has not been fully 19 read out is minimized.
As a still further refinement of memory 104, this 21 memory may be thought of as three separate but substantially 22 identical memory devices, one for each color component normally 23 included in the composite television signal. More particularly, 24 since a composite television signal is comprised of red (R), PATENT

1 green (G) and blue (B) components, memory 104 may be thought of - 2 as being formed of R, G and B memory devices, each memory device 3 being comprised of multiple (e. g. eight) field memories.
4 Consistent with this concept of R, G and B memories, A/D
converter 102 may be thought of as being comprised of R, G and B
6 A/D converters. Since the television signal supplied to the A/D
7 converter typically is in NTSC format, an NTSC-to-RGB decoder may 8 be provided (not shown) to separate the received composite g television signal into its three color components and to supply these color components to the R, G and B A/D converters, 11 respectively. The output of memory 104, which is understood to 12 comprise the outputs of the field memories and, if separate RGB
13 memory devices are used, the outputs of the field memories 14 included in each of the RGB memory devices, is coupled to D/A
converter 112. For the embodiment wherein separate RGB memory 16 devices are used, D/A converter 112 may be thought of as being 17 comprised of separate R, G and B D/A converters.
18 The D/A converter is adapted to convert the digitized 19 pixel values to an analog signal, thus effectively recovering the original useful information contained in the original television 21 signal, with new vertical timing determined by the read-out rate 22 provided by read control circuit 108. ThUs, the D/A converter 23 reconstructs the original television signal, but with increased -lS-PATE~T

1 or decreased horizontal line interval durations, as will be 2 further described.
3 D/A converter 112 i8 coupled to a mixer 114 which also 4 is coupled to a synchronizing signal generator 116. The mixer functions to insert the usual horizontal and vertical 6 synchronizing signals, burst signals and equalizing pulses 7 conventionally used in NTSC format, as well as the "non- active"
8 line intervals (e.g. lines 1 to 20 and 242 to 262 of a field).
9 The output of the mixer thus comprises the modified television signal containing the original video information but with 11 lengthened or shortened vertical periods, depending upon whether 12 the horizontal line intervals in the respective fields have been 13 increased or decreased. This modified television signal then may 14 be transmitted to conventional television receivers which, notwithstanding the changed vertical periods, reproduce an 16 accurate video picture. However, if this modified television 17 signal is supplied to a conventional VTR, the changed vertical 18 periods inhibit that VTR from recording and accurately 19 reproducing an acceptable video picture. Hence, unauthorized production of video tapes is effectively prevented.
21 Processor 110 is coupled to profile library 118 which 22 comprises a storage device, such as a read only memory (ROM) that 23 stores profile data representing the manner in which the vertical 24 periods are lengthened or shortened over a period of time.

PATENT

1 Profile data corresponding to several different profiles are 2 stored in profile library 118, and processor 110 is adapted to 3 select a desired one of those profiles for controlling the 4 operation of read control circuit 108. As an example, the S profile data establishes the duration of each line interval in a 6 particular frame. For instance, the profile data may establish 7 the duration of the horizontal line intervals for the first frame 8 to be 63.56 microseconds, whereas the duration of the horizontal 9 line intervals in, for example, frame #16 may be 65.03 microseconds. Likewise, the profile data may establish the 11 duration of the line intervals included in frame #78 to be 62.10 12 microseconds. Of course, the line durations of the various 13 frames therebetween and thereafter also are established by this 14 profile data. Thus, when a particular frame of the television lS signal is received, the read-out rate associated with that frame 16 is determined by the selected profile, and the duration of the 17 line intervals included in that frame is set accordingly.
18 Processor 110 also is coupled to time code 19 reader/generator 122. In one application of the present invention, the source of the television signal supplied to the 21 illustrated apparatus comprises a video recorder which, as is 22 known, includes a time code reader for reading the time code 23 normally recorded on the video tape. Thus, when a video recorder 24 is used as the source of the television signal, a time code 20329~2 PATENT

1 identification of each reproduced frame may be provided to 2 accompany that frame. However, if the source of the television 3 signal is other than a video recorder, or if the time code is not 4 present, it is desirable to identify each frame of that television signal. Consequently, a time code frame 6 identification for each frame is generated by time code 7 reader/gene~ator 122. It is appreciated, therefore, that the 8 time code reader/generator serves to supply processor 110 with an 9 identification of each frame in the received television signal.
This frame identification information is used by processor 110 in 11 conjunction with the profile data retrieved from profile library 12 118 to control the reading out of line intervals from memory 104.
13 The present invention serves to increase and decrease 14 the lengths of frames included in the television picture over a period of time. As will be described, the frame lengths are 16 changed either by changing the durations in the line intervals 17 included in each frame, thus increasing or decreasing the overall 18 time duration of the frame, or by adding or deleting line 19 intervals to the frame. From observation and experimentation, when either embodiment is adopted, visual perturbations and 21 interference in the video picture which eventually i5 displayed 22 will be minimized if changes in the lengths of frames pass 23 through "standard" lengths (e. g. 16.683 milliseconds) when (or 24 just after) changes in the televised scene are detected. For 203292~

PATENT

this reason, and as will be described in greater detail below, 2 scene change detector 120 is coupled to processor 110 to apprise 3 the processor of the particular frame in which a scene change is 4 detected.
The detection of a scene change may be carried out by 6 using conventional devices, such as Oak Electronics video scene 7 change detector Model CTV 0725, or other circuitry which may 8 detect, for example, a significant difference in the overall 9 luminance level of one field or frame relative to that of a 10 preceding field or frame. Other techniques known to those of 11 ordinary skill in the art may be used to detect a scene change.
12 From experience, it has been found that, in a typical program 13 created specifically for television broadcasting, a scene change 14 occurs on the average of once every five seconds.
It is desirable to provide a supervisory override to a 16 programmed change in the vertical period at certain 17 conditions. For example, if the video picture corresponding to 18 the television signal to be modified includes a pattern of 19 horizontal lines, such as a video picture wherein venetian blinds 20 constitute a prominent portion, changes in the vertical period 21 during such frames may result in a noticeable disturbance in the 22 video picture. In those instances, it is preferred to reduce 23 deviations in the vertical period from the standard 16.683 24 milliseconds until a frame is reached that is substantially free PATENT

of such horizontal lines. Thereafter,~the programmed vertical period changes may continue. However, the standard vertical period is retained for only a relatively few frames to prevent those television receivers having digitized synchronizing circuitry from "locking" onto the standard vertical period, and 6 thereby becoming unable to "follow" subsequent changes in the 7 vertical period.
8 In this regard, a monitor 126 is coupled to receive and g display the television signal and a supervisory control 128 is coupled to processor 110 to permit a supervisor to supply a 11 signal to the processor for halting continued changes in the 12 vertical period. The supervisory control may include a keyboard 13 or other input device by which an appropriate signal may be 14 supplied through the processor. ~t is appreciated that other characteristics of the video picture may result in noticeable 16 interference if the vertical period corresponding to that picture 17 is changed. Supervisory control 128 thus provides a manual 18 override to vertical period changes when the supervisor observes 19 such picture content.
The operation of the television signal modifying 21 apparatus shown in FIG. 1 now will be described with reference to 22 two embodiments: one wherein the vertical period is changed by 23 varying the durations of the line intervals included in each 24 frame; and the other wherein the vertical period is changed by PATENT

adding or de~eting line intervals to or from the ~rame. ~n ~he 2 first embodiment, although the horizontal timing is changed, the 3 number of line intervals included in each frame is fixed. In the 4 other embodiment, the number of line intervals included in each

5 frame is varied, but the duration of each line interval remains

6 fixed.

7 Both embodiments operate in conjunction with the

8 profile data stored in profile library 118. As mentioned above, g the profile data represents the manner in which the vertical 10 period changes over a period of time. A graphical representation 11 of the profile pattern corresponding to the profile data stored 12 in profile library 118 is represented by the waveforms shown in 13 FIG. 2A. Merely as an example, four separate profile patterns 14 202, 204, 206 and 208 are illustrated, and each of these patterns 15 broadly resembles a trapezoidal waveform, although other 16 waveforms, such as sinusoidal or rectangular, may be used. The 17 ordinate of FIG. 2A represents the vertical period, either in 18 terms of the total number of lines included in a frame or the 19 average duration of each line interval within that frame, and the 20 abscissa represents time. It will be appreciated that the 21 abscissa also represents the particular frame of the television 22 signal, such as identified by time code reader/generator 122.
23 Thus, the profile patterns shown in FIG. 2A represent the length 24 of each frame and further indicate that the frame lengths vary 20329~2 PATENT

1 relative to the standard length of 525 lines (or the standard 2 horizontal line interval of 63.53 microseconds).
3 From profile pattern 202, it is seen that the vertical 4 period of the modified television signal increases from the s standard length to a length equal to 537 lines (or a length 6 formed of 525 lines, each having an average line interval 7 duration of 65.01 microseconds). Thereafter, the vertical period 8 remains at this maximum level for a predetermined number of

9 frames, whereafter the vertical period decreases toward the standard length and then is reduced below that length toward a 11 minimum vertical period shown as 513 lines (or a minimum length 12 formed of 525 lines each having an average line interval duration 13 of 62.10 microseconds). The vertical period then remains 14 constant for another predetermined number of frames, whereafter the vertical period increases from its minimum length (513 lines) 16 towards its standard length. Profile patterns 204, 206 and 208 17 are similar but, as is readily apparent, exhibit markedly 18 different characteristics. In the examples shown, the profile 19 patterns may vary, one from the other, with respect to the rate at which the vertical period increases or decreases with respect 21 to time, the total number of frames having greater than standard 22 length, the total number of frames having less than standard 23 length and the maximum and minimum frame lengths. The 24 illustrated profile patterns are comprised of positive and 20329~2 PATENT

1 negative portions, the positive portion of each representing 2 those frames having greater than standard vertical period and the 3 negative portion of each representing those frames having less 4 than standard vertical period. It has been found that if the area under the curve corresponding to the positive portion, shown 6 as area A, is equal to the area under the curve of the negative 7 portion, shown as area B, there is no net increase or decrease in 8 vertical period and, therefore, there is no net delay or advance 9 in the overall vertical period. Furthermore, it is preferred that the area A (as well as the area B) be such that the capacity 11 of memory 104 is not exceeded, i.e. the accumulated delay between 12 read-out and write-in does not exceed the storage space of the 13 memory, so that a frame of video information is not dropped.
14 In profile pattern 204, although the total number of frames having increased vertical period is seen to be less than 16 the total number of frames having decreased vertical period, and 17 although the maximum increase in the vertical period is seen to 18 be greater than the maximum decrease in vertical period, 19 nevertheless the area A' under the positive portion of profile pattern 204 is substantially equal to the area B' under the 21 negative portion of this profile pattern.Likewise, the area A"
22 under the positive portion of profile pattern 206 is equal to the 23 area B" under the negative portion of this profile pattern. Also, 24 the area A''' under the positive portion of profile pattern 208 PATENT

1 is equal to the area B " ' under the negative portion of this 2 profile pattern. That is the integral of the increased vertical 3 period over those frames having greater than standard frame 4 length is substantially equal to the integral of the decreased vertical period over those frames having less than standard frame 6 length. Thus, notwithstanding the marked differences in the 7 illustrated profile patterns, by reason of these equal positive 8 and negative areas (or integrals), the overall timing of the 9 vertical period, averaged over time, is approximately "standard", thereby minimizing accumulated delays and avoiding sound/video 11 mis-synchronization.
12 Deslr~bly, the 5elected pro~ile pattern should cross 13 the abscissa at the time of occurrence of a scene change in the 14 video picture. This is because maximum perturbation in the video picture generally will occur during this transition between 16 maximum and minimum levels in the profile pattern but such 17 perturbation will not be noticed by a typical television viewer 18 if a scene change also occurs at (or just prior to) that time.
19 By providing an inventory of profile patterns in profile library 118, the particular pattern providing a "best fit" to accommodate 21 detected scene changes may be selected to control the manner in 22 which the vertical period is changed.It is expected that scen~
23 changes of a television program may occur with varying frequency;
24 and processor 110, upon detecting changes in the frequency of 2~329~

PATENT

1 occurrence of scene changes, selects a more appropriate profile 2 pattern to satisfy the "best fit" objective. Furthermore, some 3 television receivers may exhibit instability if the maximum or 4 minimum vertical period is maintained for more than a few (e.g.
100-200) frames, and the processor selects profile patterns that 6 reduce the possibility of such instability yet defeat the 7 satisfactory operation of conventional VTR's. It is appreciated, 8 therefore, that the selection of the profile pattern to be~used 9 to control changes in the vertical period may vary while processing the television signal.
11 Additionally, in the event that some VTR's nevertheless 12 operate adeguately while the vertical period varies under the 13 control of a particular profile pattern, a pattern may be 14 selected from profile library 118 which, from experience, is known to defeat the successful operation of even those VTR's.
16 Hence, from time to time, processor 110 selects that profile 17 pattern for controlling the vertical period adjustment operation;
18 thereby minimizing perturbations in video picture display while 19 maximizing nonrecordability of the television signal.
Still further, if the present invention is used in 21 conjunction with a subscription television distribution network, 22 such as shown in the system diagram of FIG. 9, certain 23 constraints and restrictions may be imposed upon the selection of 24 the profile pattern, depending upon the operating characteristics 203;~9~2 PATENT

of the television distribution network. For example, the 2 subscription encoding/scrambling circuitry may limit the minimum 3 number of line intervals included in a frame. If this minimum 4 number is greater than the minimum number of lines established by, for example, profile pattern 202, then profile pattern 204 or 6 profile pattern 208 may be substituted. Profile library 118 thus 7 accommodates the constraints imposed by the particulars of the 8 television subscription network with which the present invention 9 may be used.
Another technique for accommodating the aforementioned 11 constraint which may limit the minimum (or maximum) number of 12 line intervals included in a frame is represented by offset 13 adjustment control 124, and is depicted in FIG. 2B. The offset 14 adjustment control serves to add an offset to the profile data, 15 thereby effectively raising or lowering the profile pattern with 16 respect to the abscissa.FIG. 2B represents profile pattern 202 17 with a negative offset added thereto, thereby resulting in an 18 effective "lifting" of the profile pattern. This offset may be 19 achieved by, for example, adding a predetermined number of lines 20 (e. g. 2, 4, 6, etc. lines) to the profile data included in a 21 selected profile.
22 Although the profile patterns shown in FIGS. 2A and 2B
23 are illustrated as relatively smooth curves having progressively 24 increasing and decreasing leading and trailing edges, it is 2032922 6og39-l520 contemplated that abrupt changes ~e.g. splkes) may be provlded ln the patterns, whether lntentlonal or lnadvertent.
Brlefly, ln operatlon, a recelved televlslon slgnal, whlch may be supplled from a vldeo recorder or from conventlonal televlslon slgnal generatlng or transmlttlng apparatus, ls dlgltlzed by A/D converter 102 to produce plxels havlng respec-tlve plxel values over the active vldeo portlon of each llne lnterval. Successlve llnes of plxels ln each recelved vldeo fleld are wrltten lnto a fleld memory lncluded ln memory 104 under the control of wrlte control clrcult 106. As mentloned above, the plxels are wrltten lnto the memory at a standard, flxed rate synchronlzed wlth the normal horlzontal synchronlzlng frequency fH. As one fleld of plxels ls wrltten lnto memory 104, a precedlng fleld of plxels ls read from the memory under the control of read control clrcult 108. In one embodlment, the rate at whlch the plxels are read from the memory ls varled, as represented by the proflle patterns shown ln FIG. 2A, under the control of processor 110. A proflle pattern stored ln proflle llbrary 118 ls selected as aforesald, and thls selected proflle pattern thus controls the lncrease and decrease ln the rate at whlch the llnes of pixels are read from memory 104. It ls seen that, as the read-out rate increases, the duratlon of the llne lnterval of plxels read from a row of memory 104 ls reduced.

.. ~ i ~032922 PATENT

1 Conversely, as the read-out rate decreases, the duration of this 2 line interval increases.
3 Preferably, the read-out rate and, thus, the duration 4 of each line interval is not changed. Rather, the read-out rate is changed once every twenty-five line intervals. Furthermore, 6 this read-out rate is increased or decreased by about 8 7 nanoseconds for each change in the read- out rate. As a result, 8 the duration of the line intervals included in a field changes by 9 approximately 100 nanoseconds from the beginning to the end of that field. It has been found that a change in the line duration 11 of 100 nanoseconds over a video field interval will not disturb 12 or interfere with the normal video display of a television 13 receiver. Thus, the length of each frame may increase or 14 decrease by approximately 200 nanoseconds from its preceding frame.
16 Time code reader/generator 122 identifies for processor 17 110 each frame that is received. By comparing the actual frame 18 count of the received television signal with the frame count 19 included in the profile pattern selected from profile library 118, processor 110 supplies read control circuit 108 with read-21 out data which establishes the proper read- out rates for the 22 line intervals included in that frame. Thus, each line of pixels 23 is read from memory 104 with a line duration determined by the 24 selected profile pattern; and these pixels are reconverted into PATENT

1 an analog video signal by D/A converter 112. Nevertheless, these 2 analog video signals now exhibit the line durations which have 3 been determined by the selected profile.
4 Mixer 114 adds to the active video signals supplied by D/A converter 112 the usual horizontal synchronizing signals, 6 burst signals, e~ualizing pulses, vertical synchronizing pulses 7 and non-active horizontal line intervals. The reconstituted but 8 modified television signal then is transmitted from the mixer.
g As scene changes in the received television signal are detected by scene change detector 120, processor 110 determines 11 which of the profile patterns stored in profile library 118 12 constitute the "best fit" to the occurrences of those scene 13 changes. Should a different profile pattern be found to provide 14 this best fit, processor 110 selects that new profile pattern for controlling the operation of read control circuit 108.
16 Furthermore, the processor periodically selects a profile pattern 17 known to defeat the operability of virtually all conventional 18 VTR's, as well as a profile pattern that will not result in the 19 "lock up" of television receivers having digital synchronizing circuitry, as mentioned above.
21 The received television signal also is displayed on 22 monitor 126. If a supervisor observes that the video picture 23 contains components which will result in visual interference if 24 the vertical period corresponding to that video picture is ~0329Z2 PATENT

1 changed, the supervisor may override the aforedescribed vertical 2 period adjustment operation. In that event, no deviations from 3 "standard" are made to the vertical period, that is, no changes 4 are made in the read-out rate, until the supervisor determines that such interference in the video picture no longer will be 6 present. Changes in the read-out rate then may resume.
7 In the alternative embodiment, the rate at which line 8 intervals of pixels are read from memory 104 remains constant.
g However, the number of lines included in a frame is increased or decreased, as represented by the profile patterns shown in FIGS.
11 2A and 2B. The particular address of memory 104 which is 12 selected for a read-out operation is, of course, determined by 13 read control circuit 108 under control of processor 110. The 14 profile pattern establishes the number of the lines included in each frame read from memory 104, and processor 110 advantageously 16 varies the start time at which the first line of active video 17 information is read from memory 104 by read control circuit 108.
18 In the event that the profile pattern calls for the 19 number of lines included in a frame to be greater than the standard number (e. g. greater than 525 lines), processor 110 21 commands synchronizing signal generator 116 to continue to 22 generate non-active (or "black") horizontal line intervals which 23 are supplied by mixer 114 as the output TV signal; and the 24 processor also commands read control circuit 108 to delay the ;~03X9~2 PATENT

1 time at which the stored lines of active video information are 2 read from the memory. Hence, although the same number of active 3 lines are included in the output TV signal, the total number of 4 lines therein is greater than the standard number because synchronizing signal generator 116 supplies "extra" black lines.
6 Alternatively, if less than the standard number of lines is to be 7 included in a frame, thereby reducing the frame length, processor 8 110 interrupts the generation of black horizontal line intervals g by synchronizing signal generator 116, and concurrently advances the time at which read control circuit 108 reads the stored lines 11 of active video information from memory 104.
12 It will be appreciated that as the period of each field 13 interval increases and decreases, whether by changing the number 14 of lines included in a frame or by changing the duration of the line intervals in a frame, a vertical shift is imparted into the 16 video picture which is displayed from the modified television 17 signal. For example, and with reference to the embodiment 18 wherein the vertical period is changed by changing the number of 19 lines included in the frame, the line interval which typically is displayed as the first raster line of the video picture, that is, 21 the line interval which constitutes the top of the video picture, 22 usually is line interval #21. If the vertical period is 23 increased (i. e. if the frame length is increased), line interval 24 #21, if read out at the same time as normally read in a vertical 203292~

PATENT

1 period of st~n~Ard len~th, will not be displayed as the first 2 raster line (i.e. as the top line). Rather, a later line 3 interval, for example, line interval #22, now would constitute 4 the first raster line of the displayed video picture.
Conversely, if the vertical period is decreased, line interval 6 #21, if read out at the same time as normally read in a vertical 7 period of standard length, may constitute the second or third 8 raster line of the video picture; and a preceding line interval, 9 such as line interval ~20 now would constitute the first raster line of the video picture. The foregoing is graphically 11 represented in FIGS. 3A-3C.
12To compensate for this vertical shift in the position 13 of the top line of the video picture, processor 110 controls read 14 control circuit 108 to advance or delay the time at which it 15addresses the row of memory 104 in which line interval ~21, the 16 first active line of the video picture, is stored. Thus, when 17 the vertical period is increased, as shown in FIG. 3B, read 18control circuit 108 addresses memory 104 to read out at a later 19 time ( t) the row in which the pixels of line interval #21 are stored. Conversely, if the vertical period is decreased, as 21shown in FIG. 3C, read control circuit 108 addresses memory 104 22 to read out at an earlier time ( t) the row in which the pixels 23 of line interval #21 are stored. Thus, the read address is 24 controlled such that the row read from memory 104 which contains ~O;~Z92~

PATENT

1 the first ras~r Li~e ~n ~he Yideo picture is dçlayed or advanced 2 depending upon whether the vertical period is increased or 3 decreased, respectively. As a numerical example, line interval 4 #21 may read from the memory at the time when line interval ~24 normally is read, in the event that the vertical period is 6 increased (Fig. 3B); and line interval t21 may be read from the 7 memory at the time when line interval #18 normally is read, in 8 the event that the vertical period is decreased (~IG. 3C).
g In describing the operation of the apparatus illustrated in FIG. 1, it has been assumed that memory 104 is 11 comprised of several field memory devices. As represented 12 diagrammatically in FIGS. 4A and 4B, lines of pixels are written 13 into the field memories during a time duration T and are read 14 from those field memories over another time duration T'. It is recognized that these time durations T and T' normally are not 16 equal because the read-out duration is increased or decreased to 17 change the vertical period, as discussed above.
18 In the representation of FIGS. 4A and 4B, it is assumed 19 that immediately after a field memory is filled, or loaded, it is unloaded. However, a delay in the unloading of a memory may be 21 provided, for example, four field memories may be loaded before 22 the first field memory is unloaded.Processor 110 is adapted to 23 determine when a particular field memory selected for a loading 24 operation has not yet been fully unloaded. When that occurs, the PATENT

1 incoming field, and more particularly, the incoming frame, simply 2 is discarded. If FIG. 4A represents the field memories which are 3 loaded and FIG. 4B represents the field memories which are 4 unloaded, it is seen that the nth unload cycle of field memory A
ends just as, or slightly later than, the time at which this very 6 same field memory i5 to be loaded for the (n + l)th time. This 7 overlapping of the loading and unloading of the very same field 8 memory could result in interference and, therefore, processor llO
g simply discards the fields which otherwise would have been loaded into field memories A and B during this (n + l)th cycle.
11 The number of memory load (and unload) cycles which can 12 be executed before a data collision occurs, that is, before the 13 very same field memory is selected for loading before it has been 14 fully unloaded, may be determined as follows: Let N be the number of such memory load cycles that may be carried out before 16 a data collision occurs. That is, N is the number of memory load 17 cycles which may be carried out before an incoming frame of video 18 information must be dropped. Then:
19 T = the duration needed to load a field memory.
T' = the duration needed to unload a field memory.
21 P = T/T'.
22 M ~ the number of field memory devices (in the present 23 example, M = 8).
24 N = (P + l)/M(P - 1) - l/(P - 1).

PATENT

1 A modification in the apparatus illustrated in FIG. 1 2 is contemplated. As described above, scene change detector 120 3 operates concurrently with the loading of memory 104; and as 4 mentioned above with respect to FIGS. 4A and 4B, a field memory is unloaded immediately after it has been loaded. Processor 110 6 selects a profile pattern from profile library 118 to best fit 7 the scene changes detected by scene change detector 120. In the 8 event that additional time is needed for processor 110 to select 9 the appropriate profile pattern, suitable delays may be imparted, where necessary. For example, several field memories may be 11 loaded before the first field memory is unloaded. As a further 12 alternative, the television signal may be supplied to scene 13 change detector 120 while it concurrently is recorded. Then, the 14 recorded television signal may be played back to A/D converter 102 for loading into memory 104. The inherent delay provided in 16 recording and then reproducing the television signal should 17 accommodate any time delays needed to detect scene changes and 18 select the appropriate profile patterns for controlling the frame 19 length of the modified television signal.
For the embodiment wherein the vertical period is 21 changed by changing the line interval durations therein, both 22 horizontal and vertical geometric distortions in the video 23 picture may result. This is because the vertical distance 24 traversed by the slight slant of each horizontal raster line ~03X92;~
PATENT

1 varies if the horizontal line duration varies. As the line 2 duration increases so too does the vertical distance traversed by 3 this raster line. Conversely, as the line duration decreases, 4 the vertical distance covered by the slight slant of this line also decreases. It has been found that geometric correction 6 generally is not needed for those fields in which the ratio P
7 (discussed above with reference to FIGS. 4A and 4B) is 8 approximately unity. However, as P increasingly deviates from 9 unity, that is, as the profile pattern approaches its maximum and lo minimum levels, distortion compensation is appropriate.
11 FIG. 5 is a block diagram representing one embodiment 12 by which geometric compensation is effected for the embodiment 13 wherein the vertical period is varied by changing the durations 14 of the horizontal line intervals. This compensation arrangement is comprised of field memories 402 and 404, field memories 416 16 and 418, look up tables 410 and 412, a table address generator 17 408 and an adder 414. Field memories 402, 404, 416 and 418 may 18 be viewed collectively as an embodiment of memory 104 (FIG. 1).
19 Field memories 402 and 404 are adapted to receive the line intervals of pixels produced by the A/D converter, and the 21 addresses in which these lines of pixels are stored are 22 determined by memory read/write control circuit 406. As an 23 example, field memory 402 is adapted to store the line intervals 24 of an odd field and field memory 404 is adapted to store the line 20;~292~

PATENT

1 intervals of an even field. The output of field memory 402 is 2 coupled to look up table 410 and the output of field memory 404 3 is coupled to look up table 412.
4 Each of the look up tables stores data representing different proportions of pixel values. To provide geometric 6 compensation, a portion of a pixel in one line interval is added 7 to another portion of a pixel in the next adjacent line interval 8 ti. e. the line interval adjacent thereto in the video display), 9 and the resultant reconstituted pixel is used as a replacement for the original. Depending upon the particular location in the 11 profile pattern, these proportions vary. The particular pixel 12 read from field memory 402 constitutes a portion of the address 13 for look up table 410, and the particular present location in the 14 profile is used to generate another portion of this look up table address. Table address generator 408 is coupled to receive 16 profile data from processor 110 and to generate address data 17 corresponding to the present location on the profile pattern. In 18 response to the addresses represented by table address generator 19 408 and the pixel values supplied by field memory 402, the proport~on of the pixel value stored in the addressed location of 21 look up table 410 is read out and supplied to adder 414.
22 Similarly, look up table 412 is coupled to field memory 23 404 and to table address generator 408 and serves to supply to 24 adder 414 the proportion stored in the location then being ~032~22 PATENT

1 addressed. It is appreciated~that the look up tables may 2 comprise read only memory devices.
3 Adder 414 is adapted to combine the proportions of 4 pixel values supplied thereto by look up tables 410 and 412 to produce a re-valued pixel. The adder is coupled to field 6 memories 416 and 418 which function as odd and even field 7 memories, respectively, to store the re-valued pixels therein.
8 Although not shown, it will be appreciated that the line 9 intervals of re- valued pixels stored in field memories 416 and 418 are read out under the control of read control circuit 108 in 11 the manner discussed above. Hence, memories 416 and 418 may be 12 thought of as arrays of memories similar to the arrays described 13 above for memory 104 (FIG. 1). The outputs of field memories 416 14 and 418 are coupled to D/A converter 422 which reconstructs a compensated analog video signal whose vertical interval has been 16 increased or decreased in accordance with the selected profile 17 pattern.
18 A start read control circuit 420 also has been provided 19 for the purpose of adjusting the start time at which a line of pixels stored in memory 416 or 418 is read out. Start control 21 circuit 420 is coupled to field memories 416 and 418 and is 22 responsive to the profile data supplied thereto by processor 110 23 to determine the start time at which the respective line 24 intervals are read from these field memories. As will be 203~922 PATENT

1 appreciated, the s~rt time is adv~nced (i. e. it is generated 2 earlier in the read cycle) when the durations of the line 3 intervals are increased and the start time is delayed when the 4 durations of the line intervals are decreased.
In operation, digitized line intervals of the 6 television signal, more particularly, the pixels which constitute 7 the active video portion of each line interval, are supplied to 8 field memories 402 and 404. Memory read/write control 406 9 selects one of the field memories to store successive line intervals during the reception of one field, and then the other 11 field memory is selected to store the line intervals included in 12 the next-following field. For example, an odd field of line 13 intervals is stored in field memory 402 and then the next-14 following even field of line intervals is stored in field memory 404. Althouqh only two field memories are illustrated, it will 16 be appreciated that eight field memories may be used to 17 accommodate the eight fields included in four successive frames.
18 After field memories 402 and 404 are loaded, they are 19 unloaded by reading out the line intervals stored therein.
Preferably, each pixel in the line interval is read out in 21 succession. Of course, the particular location on the profile 22 pattern at the time a field memory is unloaded is known from the 23 profile pattern supplied to table address generator 408.
24 Depending upon the profile data supplied to the table address 20329~22 PATENT

1 generator, an address signal is generated and applied to look up 2 tables 410 and 412. In addition, as a pixel is read out of field 3 memory 402, its pixel value is supplied to look up table 410 and 4 constitutes another portion of the table address. Thus, the combination of the pixel value and profile data is used to 6 address look up table 410 which, in turn, supplies to adder 414 7 data representing a particular portion, or percentage, of the 8 pixel value read out from field memory 402.
g At the same time that a line interval is read out of field memory 402, a line interval which would be displayed as the 11 next adjacent line in the video picture produced in response to 12 the contents of field memories 402 and 404 is read from field 13 memory 404. The read out timing of the field memories is such 14 that, when a particular pixel is read from field memory 402, the pixel in the next adjacent line interval which lies, for example, 16 directly below this pixel, is read from field memory 404. This 17 pixel value read from field memory 404 constitutes a portion of 18 the address of look up table 412, and the table address which had 19 been generated by table address generator 408 in response to the profile data supplied thereto is used as another portion of the 21 address for look up table 412. Hence, data is supplied from look 22 up table 412 to adder 414 which represents that portion or 23 percentage of the pixel value read from field memory 404 as 24 determined by the present location along the profile pattern as 203Z~2 PATENT

1 represented by the profile data supplied to table address 2 generator 408.
3 Adder 414 adds that portion of the pixel data read from 4 field memory 402 to that portion of the pixel data read from field memory 404 to produce a "corrected" value of the pixel read 6 from field memory 402. This corrected value is stored in field 7 memory 416 in the same location as the original pixel occupied in 8 field memory 402. Thus, the original pixel value is replaced by 9 the corrected pixel value.
This same operation is carried out when the next pixels 11 are read from field memories 402 and 404 until field memory 416 12 is supplied with a line interval of corrected pixel values.
13 Then, the next line interval stored in field memory 402 is read 14 out, and a portion of each pixel value in that line interval is added to a determined portion of each pixel value in the line 16 interval re-read from field memory 404. As a result, adder 414 17 produces "corrected" pixel values for the line interval now read 18 from field memory 404; and these corrected pixel values now are 19 stored in field memory 418 in the same location as the original pixels occupied in field memory 404.
21 As a numerical explanation, let it be assumed that line 22 55 of field memory 402 and line 56 of field memory 404 are read 23 out (it is recognized that the lines of the odd and even fields 24 are interlaced). Let it be further assumed that each line PATENT

1 interval contains approximately 900 pixels. Now, as an example, 2 when pixel 150 of line 55 is read from field memory 402, pixel 3 150 is read from line 56 of field memory 404. Look up table 410 4 supplies a percentage of the value of pixel 150 from line 55 and look up table 412 supplies a percentage of the value of pixel 150 6 from line 56. Adder 414 adds the percentage of the value of 7 pixel 150 from line 55 to the percentage of the value of pixel 8 150 from line 56 to produce a "corrected" value for pixel 150 of 9 line 55. This corrected value of pixel 150 in line 55 is written lo into field memory 416 at the proper location in the row in which 11 line 55 is stored. This operation continues until field memory 12 416 stores a "corrected" field of pixels.
13 Next, line interval 57 is read from field memory 402 14 and line 56 is re-read from field memory 404. When, for example, pixel 150 of line 57 is read from field memory 402, look up ta~le 16 410 is addressed to supply to adder 414 a percentage of the value 17 of pixel 150. Likewise, when pixel 150 of line 56 is read from 18 field memory 404, look up table 412 is addressed to supply to 19 adder 414 a percentage of the value of this pixel. Adder 414 com~ines the percentages of the values of pixel 150 from lines 57 21 and 56, respectively, to produce a "corrected" pixel value. This 22 corrected value of pixel 150 is stored in field memory 418 at 23 line 56 and, thus, replaces the original value of pixel 150 from 24 line 56 read from field memory 404.

~0;~9~2 PATENT

1 From the foregoing, it is seen that corrected odd and 2 even fields are stored in field memories 416 and 418, 3 respectively, thereby providing geometric compensation to 4 distortions which otherwise may arise when the vertical period is increased or decreased by increasing or decreasing the durations 6 of the line intervals included therein.
7 It is recognized that, as the duration of a line 8 interval increases beyond standard, that is, a line interval g greater than 63.56 microseconds, the first pixel which corresponds to the left edge of the video picture corresponding 11 - to that line interval is effectively "shifted" to the right. To 12 place this first pixel at the left edge of the video picture, the 13 start time at which this line interval is read from field memory 14 416 (or field memory 418) should be shifted to the left. Stated otherwise, the start time at which the line interval begins to be 16 read out of the field memory should be advanced relative to a 17 "standard" start time. Conversely, if the duration of the line 18 interval is decreased below standard, the first pixel in the 19 displayed portion of this line interval is effectively shifted to the left. To reposition this pixel of the shortened line 21 interval at the left edge of the video picture, the start time at 22 which this line interval is read out from the field memory should 23 be delayed relative to the standard start time. Horizontal start 24 control circuit 420 is responsive to the profile data supplied ~032922 PATENT

1 from processor llO to advance or delay the start time for reading 2 out each line interval stored in the field memories. As the 3 profile pattern increases, that i8, as the time durations of the 4 line intervals are increased, horizontal start control circuit 420 advances the start time for reading from the field memories 6 by a corresponding amount.Conversely, when the profile pattern 7 decreases, thereby reducing the durations of the horizontal line 8 intervals, 'he horizontal start control circuit delays the start 9 time for reading from the field memories. Consequently, distortions that otherwise might appear in the video picture are 11 compensated, particularly distortions that would be most visible 12 in displayed vertical lines.
13 In the embodiment shown in FIG. 5, it has been 14 preferred to utilize look up tables 410 and 412 to determine percentages of pixel values in accordance with the present 16 location of the profile pattern during the vertical period 17 adjustment operation. As an alternative, a multiplier circuit 18 can be used, wherein the value of a pixel read from field memory 19 402 (or field memory 404) is multiplied by a factor which varies as the profile pattern varies. As a result, a percentage of the 21 pixel value is produced; and this percentage may be combined with 22 the percentage of the value of an adjacent pixel in the next line 23 to provide a corrected pixel value.

20~2922 60939-1520 Referrlng now to FIG. 6, there ls lllustrated a block dlagram of apparatus used to control the readlng out of memory 104 (or the readlng out of fleld memorles 416 and 418) by whlch the vertlcal perlod ls adiusted by changlng the duratlons of the horlzontal llne lntervals lncluded ln the frames. The apparatus lncludes a latch clrcult 602, a counter 604, latch clrcults 610 and 612, a counter 614, a comparator 608, latch clrcults 618 and 620 and a comparator 616. Latch clrcult 602 ls adapted to recelve data representlng the duratlon of a llne lnterval, as determlned by the proflle pattern. Thls data may be derlved dlrectly from the proflle data and, as an example, may represent a llne duratlon wlthln the range of 62.10 mlcroseconds to 65.03 mlcroseconds. Latch clrcult 602 ls coupled to counter 604 and ls adapted to preset the counter to a count representlng the proflle-determlned duratlon of the llne lnterval.
Counter 604 ls coupled to a clock clrcult 606 whlch, as a numerlcal example, may generate clock pulses of a frequency 120 MHz. Counter 604 ls adapted to be decremented ln response to the clock pulses to produce an output pulse HCLR, represent-lng the end of the llne lnterval whose duratlon ls representedby the count to whlch the counter has been preset. The output of counter 604 ls coupled to counter 614, and the pulses HCLR
are supplled to counter 614 as clock pulses.

V '~
~ 1 ..... ~

~03292Z

PATENT

1 Latch circuit 610 is adapted to store therein the 2 number of the first line interval whose duration is t. Latch 3 circuit 612 is adapted to store the number of the last line 4 interval having this duration t. It will be appreciated that the duration t is equal to the duration supplied to latch circuit 6 602. The outputs of latch circuits 610 and 612 are coupled to 7 one input of comparator 608, and the comparator includes another 8 input coupled to the output of counter 614. An output of g comparator 608 is coupled to lat:ch circuit 602 and functions as an enable, or load, input.
11 Latch circuit 618 is adapted to receive and store data 12 representing the delay or advance ( t) for reading out the line 13 interval which constitutes the first viewable line of the video 14 picture (e.g. line #21). From the foregoing discussion of FIGS.
3A-3C, it is appreciated that, depending upon the increase or 16 decrease in the vertical period, the read-out time of the line 17 (e.g. line #21) which constitutes the top of the video picture 18 may vary. In the above-discussed example, the first line of the 19 video picture has been assumed to be line 21 for "standard"
vertical periods, and the read-out time of line #21 is delayed 21 for increased vertical periods and is advanced for decreased 22 vertical periods.
23 Latch circuit 620 is adapted to receive data 24 representing the number of the bottom-most viewable line of the ~0;~922 PATENT

1 video picture, typically line #241. The latch circuits are 2 coupled to one input of comparator 616, and this comparator 3 includes another input coupled to counter 614. The output of 4 comparator 616 is coupled to a flip-flop circuit 622 which, as will be described, toggles between set and reset states in 6 response to the output of the comparator. The output of flip-7 flop circuit 622, for example, the S~T output thereof, is coupled 8 to one input of an AND gate 624 whose other input is coupled to a 9 flip-flop circuit 630 to receive a rectangular signal, designated HDSP, which coincides with the active portion of a horizontal 11 line interval.
12 A look up table 626 is coupled to latch circuit 602 to 13 receive as an address the data representing the duration of a 14 line interval, as determined by the profile pattern. Look up table 626 stores count numbers representing different line 16 interval durations. A particular duration count is read from the 17 look up table to a counter 628 to preset that counter.Counter 620 18 is coupled to clock circuit 606 and, in accordance with one 19 example described herein, is adapted to decrement its count in response to each clock pulse supplied thereto. The counter 21 includes "count A" and "count B" outputs coupled to the set and 22 reset inputs, respectively, of flip-flop circuit 630.
23 The manner in which the timing circuit illustrated in 24 FIG. 6 operates now will be described in conjunction with the ~032922 PATENT

1 waveforms shown in FIGS. 7A-7F. FIG. 7A represents the 2 horizontal line intervals of a typical television signal, 3 including a horizontal synchronizing pulse, a burst signal and 4 active video information. It is app~eciated that the separation S of the horizontal synchronizing pulses increases if the duration 6 of the line interval increases and, conversely, the separation 7 between horizontal synchronizing pulses decreases as the duration 8 of the line interval decreases.
g The duration of the line interval being read from memory 104 (or from field memories 416 and 418) is supplied to 11 and stored in latch circuit 602. The data supplied to all of the 12 illustrated latch circuits may be provided by processor 110 13 (FIG. 1).
14 Counter 604 is preset to a count corresponding to this profile-determined duration, and the count is decremented in 16 response to the clock pulses supplied to counter 604 by clock 17 circuit 606. As an example, counter 604 may be preset to a count 18 of 7625 when the duration of the line interval being read from 19 the memory is the standard duration (e. g. approximately 63.56 microseconds). The counter may be preset to a count of 7450 when 21 the duration of the line interval is to be, for example, 62.10 22 microseconds, and the counter may be preset to a count of 7800 23 when the duration of the line interval is to be, for example, 24 65.03 microseconds. It is appreciated that, as the preset count -- 203Z9~2 PATENT

1 of counter 604 increases, the period required for the counter to 2 be fully decremented likewise increases.
3 Counter 604 produces the pulse HCLR, shown in FIG. 7B, 4 when it is fully decremented. At that time, the HCLR pulse is used as a load pulse to load the counter with a preset count 6 received from latch circuit 602 and representing the duration of 7 the next line interval to be read from the memory. This HCLR
8 pulse also is supplied to counter 614 whereat it is counted, and g the HCLR pulse also functions as a load pulse to load counter 628 with a count read from look up table 626 in response to data 11 representin~ the duration of the next line interval, as received 12 from latch circuit 602.
13 Counter 614 initially is reset by a pulse UNEND which, 14 as one example, may be generated upon detecting the first set of equalizing pulses normally included in a field of the television 16 signal. FIG. 7D represents these equalizing pulses, together 17 with the usual set of vertical synchronizing pulses, followed by 18 another set of equalizing pulses and horizontal blanking pulses 19 normally provided in the vertical blanking interval of a television signal. FIG. 7D also illustrates typical horizontal 21 synchronizing pulses included in, for example, line intervals 20-22 262 of a typical field. FIG. 7E represents the UNEND pulses 23 which generally coincide with the beginning of the first set of 24 equalizing pulses included in a field. As an alternative, it 20329~Z
PATENT

1 will be appreciated that the UNEND pulses may be generated by 2 counter 614 after a predetermined number of HCLR pulses (e. g.
3 262 or 263 HCLR pulses) have been counted.
4 The count of counter 614 represents the number of the line interval being read from the memory. Stated otherwise, the 6 count of counter 614 represents the vertical line count. This 7 vertical line count is compared by comparator 608 to a count 8 stored in latch circuit 610 representing the number of the first 9 line interval having the duration represented by the data stored lo in latch circuit 602.It is recalled that, preferably, a set of 11 twenty-five line intervals is provided with the same duration, 12 and the number of the twenty-fifth line interval is supplied to 13 latch circuit 612. When this last line interval having the 14 duration represented by the data stored in latch circuit 602 is reached, comparator 608 produces an output to enable latch 16 circuit 602 to store data representing the duration of each line 17 interval included in the next set of twenty-five line intervals.
18 From the foregoing discussion, it is appreciated that the 19 duration t changes from one set of twenty-five line intervals to the next set by approximately 8 nanoseconds. Thus, the data 21 stored in latch circuit 602 will increase or decrease by 8 22 nanoseconds at each latch-load cycle.
23 The vertical line count produced by counter 614 is 24 compared by comparator 616 to a count representing the top ~`
- ~0329Z2 PATENT

1 viewable line of the video picture~ as stored ln latch circuit 2 618 (e.g. line ~21~, and also to a count representing the bottom 3 viewable line of that video picture, as stored in latch circuit 4 620 (e.g. line t241). When the vertical line is equal to the top line, for example, when the vertical line count is equal to line 6 21, comparator 616 sets flip-flop circuit 622 which subsequently 7 is reset when the vertical line count is equal to the last line 8 of the video picture, for example, when it is equal to line 241.
9 FIG. 7F represents the output of flip-flop circuit 622. The negative portion of the illustrated rectangular waveform 11 coincides with the vertical synchronizing interval included in a 12 field of the television signal, and the positive portion of this 13 rectangular waveform represents the viewable portion of the 14 television signal.
Counter 628 is preset in response to each HCLR pulse to 16 a count read from look up table 626 which, in turn, is determined 17 by the duration of the line interval being read from the memory, 18 as represented by the data stored in latch circuit 602. Counter 19 628 counts the clock pulses supplied by clock generator 606, and when a first count, identified as count A, is reached, counter 21 628 applies a signal to flip-flop circuit 630 to set this flip-22 flop circuit. As a result, the flip-flop circuit produces the 23 output signal HDSP, shown in FIG. 7C. Counter 628 continues to 24 count the clock pulses supplied thereto; and when count B is PATENT

1 reached, flip-flop circuit 630 is reset. From FIG. 7C, it is 2 seen that signal HDSP is of a rectangular waveform whose positive 3 portion coincides with the useful video information provided in a 4 horizontal line interval. The delay between pulse HCLR and the positive portion of signal HDSP is a function of the count to 6 which counter 628 is preset; and this, in turn, corresponds to 7 the start read time and is determined by the profile pattern.
8 Signal HDSP is combined with the output VID from flip-g flop circuit 622 in AND gate 624. The AND gate produces a series of pulses each of a width equal to the positive portion of the 11 signal HDSP, and the period of the output signal UNDSP from AND
12 gate 624 is defined by the positive portion of the signal VID
13 (FIG. 7F). The signal UNDSP is used to enable the read-out cycle 14 of the memory.
Whereas FIG. 6 is a block diagram of timing circuitry 16 used to enable the read-out operation of the memory when the 17 vertical period is changed by varying the durations of the 18 horizontal line intervals, FIG. 8 is a block diagram of timing 19 circuitry used to enable the memory read operation when the vertical period is ad~usted by adding or deleting lines from a 21 field. The timing circuitry illustrated in FIG. 8 includes latch 22 circuits 802, 804 and 814, comparators 806 and 816, counter 808, 23 flip-flop circuit 810 and an AND gate 812. Latch circuits 802 24 and 804 are similar to latch circuits 618 and 620 and are adapted Z0329~2 PATENT

1 to store the line counts identifying the top line and bottom 2 line, respectively, of the displayed video picture.
3 Latch circuits 802 and 804 are coupled to comparator 4 806 which, in turn, is coupled to counter 808, the latter being adapted to count HCLR pulses of the type shown in FIG. 7B. The 6 output of comparator 806 is coupled to flip-flop circuit 810 7 whose output is, in turn, coupled to AND gate 812. It is 8 appreciated that the combination of latch circuits 802 and 804, g comparator 806, counter 808, flip-flop circuit 810 and AND gate 812 are similar to and perform substantially the same function as 11 latch circuits 618 and 620, comparator 616, counter 614, flip-12 flop circuit 622 and AND gate 624, described above in connection 13 with FIG. 6.
14 The output of counter 808 also is coupled to comparator 816 which is adapted to compare the count of this counter with a 16 line number count stored in latch circuit 814. This line number 17 count identifies the last raster line in a video picture read out 18 from the memory (e.g. line #241). It is appreciated that the 19 same number of active video lines (e.g. 220 lines) is read from the memory, whether the vertical period is increased or 21 decreased. Of course, the number of "black" line intervals that 22 precede and follow the active line intervals is modified, as 23 determined by processor 110 which controls synchronizing signal 24 generator 116 accordingly, (FIG. 1).

~032922 PATENT

1 The HCLR pulses supplied to counter 808 may be derived 2 from the actual horizontal synchronizing pulses included in the 3 video signal or, alternatively, a counter similar to counter 604 4 may be used to generate the HCLR pulse periodically. In this instance, since the duration of each line interval is fixed at 6 the standard duration of 63.56 microseconds, there is no need to 7 modify the count to which the counter would be preset.
8 Counter 808 is similar to counter 614 in that the count ~ produced thereby represents the vertical line count. As successive line intervals are read from the memory, counter 808 11 is incremented. When the vertical line count reaches the number 12 of the last active line included in the field, comparator 816 13 produces an UNEND output to reset the counter.
14 Comparator 806 toggles flip-flop circuit 810 to produce the VID signal shown in FIG. 7F, and this V~D signal is combined 16 with the HDSP signal (FIG. 7C) to produce the UNDSP signal. As 17 mentioned above, signal UNDSP enables the read operation of the 18 memory.
19 As described herein, the present invention controls the vertical period of a television signal either by adjusting the 21 duration of the horizontal line intervals included in each field 22 of the television signal or by adding or deleting line intervals 23 from the field. The modified television signal whose vertical 24 period thus is changed may be transmitted directly via ~03292Z

PATE~T

1 conventional "over-the-air~ broadcasting techniques, by cable 2 techniques or by subscription television techniques. A
3 television receiver which is supplied with this modified 4 television signal nevertheless is able to display an adequate video picture in response thereto. However, if this modified 6 television signal is recorded by conventional VTR's, the change 7 in vertical period inhibits those VTR's from accurately recording 8 and reproducing the television signal, thus preventing an 9 adequate video picture from being reproduced. The modified television signal thus may be thought of as a viewable but non-11 recordable video signal.
12 The present invention also may be used in a 13 subscription television distribution network of the type shown in 14 FIG. 9. Typically, television signals are distributed to subscribers by way of, for example, cable, in an encoded or 16 scrambled format. When such a subscription television 17 distribution network is used with the present invention, it is 18 preferred to supply to the cable distribution site, also known as 19 the head end, a television signal having standard vertical intervals but including data which represents the profile pattern 21 to be used at the head end for changing the vertical intervals in 22 the manner described above. of course, if desired, the 23 television signal supplied to the head end may be modified by 24 having its vertical period varied in the manner discussed above ~03292~

PATENT

l (i.e. the television signal w~ll exhibit non-standard vertical 2 intervals).
3 In addition, it is desirable that so-called 4 "fingerprint" indicia be added to the television signal at the head end so that if an unauthorized copy somehow is made, that 6 copy will include the "fingerprint~ which, typically, identifies 7 the time of transmission, the cable distribution site and the 8 operator of that site. Of course, final encoding or scrambling of 9 the television signal is effected at the cable distribution site.
11 When the present invention is used in the subscription 12 television network shown in FIG. 9, the source of the television 13 signal, that is, the television programming, preferably is 14 reproduced from a prepared video tape by a VTR 902. The television signal reproduced from the VTR is supplied to a scene 16 change detector and a fingerprint location detector 904. The 17 scene change detector has been described above; and the 18 fingerprint location detector is adapted to sense a location in 19 the television signal at which fingerprint data should be inserted prior to distribution to subscribers. One embodiment of 21 a fingerprint location detector which may be included in 22 subsystem 904 is illustrated in FIG. lo. Essentially, the 23 fingerprint location detector senses a substantial modification 24 in the video signal of one line with respect to the next-2 0 3 2 9 2 2 60939-l520 following line in a fleld. It has been found that if flnger-prlnt data, typlcally, a slngle bit, ls lnserted lnto the actlve vldeo slgnal at thls locatlon, lts presence ls not percelved ln the vldeo plcture. The flngerprlnt locatlon detector functlons to determlne thls locatlon.
Scene change detector and flngerprlnt locatlon detector 904 supply slgnals to produce a vldeo and tlme code record 906. The vldeo and tlme code record may comprlse a vldeo recordlng ln whlch both the composlte televlslon slgnals and the tlme codes whlch ldentlfy the respectlve frames ln the composlte televlslon slgnals are recorded.
In addltlon, a record, such as a magnetlc dlsk, ls made of the partlcular frames ln whlch scene changes are detec-ted and proper locatlons for lnsertlon of flngerprlnt data are found. Thls record preferably ls comprlsed of tlme code data to ldentlfy the frame ln whlch a scene change occurs, and also a numerlcal count to ldentlfy the particular horlzontal llne lnterval and segment of that llne lnterval ln whlch flngerprlnt data may be lnserted.
A controller 910 responds to the vldeo tlme code record 906 and also to the scene change tlme code and flnger-prlnt locatlon 908 to select a proflle pattern, as dlscussed above. In addltlon, any geometrlc correctlon that may be needed ln the vldeo slgnal, such as the geometrlc correctlon dlscussed wlth ~`
..~, . . .. .

2032~22 PATENT

1 reference to FIG. 5, also is made by controller 910. Still 2 further, the composite television signal, which has not yet been 3 subjected to vertical period adjustments, may be transmitted to 4 the aforementioned head end at the cable distribution site in scrambled format. Such scrambling provides security against 6 unauthorized reception of the composite television signal which, 7 but for the scrambling, would be in condition to be recorded and 8 reproduced. One preferred technique for scrambling the composite g television signal is to rearrange the line intervals in each field. Of course, information identifying the rearrangement, 11 that is, a so-called "scramble map" is produced; and this 12 scramble map, together with profile data representing the 13 selected profile pattern and fingerprint location data are 14 inserted into any suitable location of the television signal, such as the vertical blanking interval (VBI). It is recognized 16 that several line intervals included in the VBI are not used for 17 useful information; and it is convenient to insert the profile 18 data, scramble map and fingerprint location data in one or more 19 of these VBI line intervals. Preferably, the profile data, scramble map and fingerprint location data (referred to, for 21 simplification, merely as VBI data) are encrypted prior to 22 insertion. In one embodiment, a conventional DES encryption 23 technique may be used. Finally, controller 910 scrambles the 24 television signal in accordance with the scramble map inserted ~03Z9~;~

PATENT

1 into the VBI. Of course, this data may be inserted into other 2 locations of the television signal, such as is the horizontal 3 blanking intervals, one bit of data at a time.
4 The output of controller 910 is represented as video, VBI data and time code 912. The time code information represents 6 the location of each frame in the scrambled television signal;
7 and at this stage in the signal processing, the VBI data is 8 comprised of the aforementioned encrypted profile data, scramble 9 map and fingerprint location data. In one embodiment, a scrambled master distribution tape containing video, time code 11 and VBI data is prepared. This master video tape may be 12 physically delivered to a VTR 918 located at the head end of the 13 cable distribution site or, alternatively, information recorded 14 on the scrambled master distribution tape simply may be reproduced and transmitted, such as via satellite transmission, 16 from the location of controller 910 to the head end at the cable 17 distribution site. Conventional uplink 914 and downlink 916 are 18 provided to accommodate such satellite transmission.
19 At head end 920, vertical period adjustments to the composite television signal are made, in accordance with the 21 present invention. Of course, as mentioned previously, such 22 vertical period adjustments may be made prior to receipt of the 23 television signal by the head end. In addition, the scrambled 24 video signal is descrambled in accordance with the scramble data PATENT

1 map which, in turn, is decrypted and used to control the 2 descrambling operation. Furthermore, the fingerprint location 3 data encrypted prior to insertion into the television signal, 4 also is decrypted and used to identify the proper locations in the video signal in which suitable fingerprint data may be 6 inserted. It is expected that the resultant, modified television 7 signal (i. e. the television signal whose vertical period has 8 been changed in accordance with the present invention) then is 9 encoded in accordance with the encoding technique adopted by the cable distribution network. The encoded television signal, ll containing fingerprint data and having its vertical period 12 mod~fied as aforementioned then i8 transmitted via the cable 13 distribution network. Alternatively, the encoded, modified 14 composite television signal may be transmitted by other means to an electronic theater.
16 Referring to FIG. 10, a logic diagram representing the 17 manner in which the fingerprint location is detected is 18 illustrated. As mentioned above, fingerprint data is inserted l9 into the active video portion of a television signal at a location in a field whereat a sudden change in video 21 characteristics from one line to the next occurs. Comparator 22 1002 and delay circuit 1004 detects a sudden increase in, for 23 example, luminance level. The comparator is supplied with the 24 incoming video signal at one input thereof and also ~s supplied 20329~:2 PATENT

1 with the pr~ce~ng line of that video signal via delay circuit 2 1004, identified as a lH delay circuit. It is seen that delay 3 circuit 1004 delays the incoming video signal by a duration equal 4 to a horizonal line interval. Although not shown, an attenuator may be used to supply the incoming video signal to comparator 6 1002 such that an output is produced by the comparator only if 7 the incoming video signal exceeds the delayed version of that 8 video signal by a factor equal to the attenuation factor. In one g embodiment, this attenuation factor is on the order of about 4.
Alternatively an amplifier may be used to amplify the delayed 11 video signal supplied to the comparator. In any event, the video 12 and delayed video signals supplied to the comparator may be as 13 illustrated in FIGS. llA and llB, wherein FIG. llA represents a 14 sudden increase in the luminance level in the field interval presently being received. FIG. llC illustrates the output of 16 comparator 1002.
17 Preferably, only one location in a field interval has 18 fingerprint data inserted thereinto. AND gate 1006 is coupled to 19 comparator 1002 to make certain that the output of the comparator is gated only once during a field interval. As will be 21 explained, a flip-flop circuit 1020 is reset by a strobe pulse 22 STB2, produced by, for example, a microprocessor, at the end of a 23 field interval. The flip-flop circuit thus remains reset only 24 until comparator 1002 produces its output (Fig. llC) and then the PATENT

1 flip-flop circuit is set at a suitable delayed time thereafter.
2 AND gate 1006 is conditioned to pass the output of comparator 3 1002 when flip-flop circuit 1020 exhibits its reset state.
4 Another constraint on detecting the location at which S fingerprint data is to be inserted is that this location should 6 not be present during the horizontal blanking interval.
7 Accordingly, end gate 1006 is provided with an inverted version 8 of a horizontal blanking pulse such that the AND gate is 9 inhibited during horizontal blanking intervals.
The output of comparator 1002 is used to initially 11 reset a flip-flop circuit 1008, and the output of AND gate 1006 12 triggers this flip-flop circuit to its set state in coincidence 13 with a clock pulse supplied to a clock input of the flip-flop 14 circuit by a suitable clock generator. In the illustrated embodiment, clock pulses on the order of 250 KHz are supplied to 16 flip-flop circuit 1008. As is also shown, this flip-flop circuit 17 preferably comprises a D-type flip-flop, with the output of AND
18 gate 1006 coupled to the data input D thereof. It is recognized 19 that, by reason of the timing of the 250 KHz clock pulses, flip-flop circuit 1008 always will be reset in response to the output 21 of comparator 1002 just slightly in advance of being set by this 22 same output as passed through AND gate 1006. The output signal, 23 designated DIFF, produced by flip-flop circuit 1008 24 is illustrated in FIG. llD.

~032922 PATENT

1 This DIFF signal is supplied to a flip-flop circuit 2 1010 which normally is in its reset state awaiting this DIFF
3 signal. In the illustrated embodiment, flip-flop circuit 1010 4 comprises a D-type flip-flop, with the DIFF signal supplied to the data input D and with 250 KHz clock pulses supplied to the 6 clock input thereof. FIG. llE illustrates the output of flip-7 flop circuit 1010, and it is seen that the output signal 8 produced by this flip-flop circuit, designated fingerprint g location ~PINT, is delayed relative to the DIFF signal. It will be appreciated that this delay is equal to a cycle of the 250 KHz 11 clock pulse.
12 Also not shown, the FPINT signal is supplied to the 13 microprocessor mentioned above, and in response to this FPINT
14 signal, the microprocessor returns a strobe signal STB1 to reset the flip-flop circuit. FIG. llF illustrates the relative timing 16 of this strobe signal STBl, and in one embodiment, the 17 microprocessor returns the strobe signal STBl at the completion 18 of the line interval in which the FPINT signal is produced.
19 Thus, flip-flop circuit 1010 will be reset to await the occurrence of the next DIFF signal.
21 As also shown in FIG. 10, the FPINT signal æets flip-22 flop circuit 1020, thereby inhibiting AND gate 1006 until the 23 flip-flop circuit next is reset. Consequently, one and only one 24 output of comparator 1002 is passed by the AND gate, PATENT

notwithstanding the possibility that several successive outputs 2 may be produced by the comparator during a field interval. Of 3 course, and as mentioned above, flip-flop circuit 1020 is reset 4 by the STB2 pulse produced by the microprocessor at the end of 5 the field interval in which the FPINT signal had been produced.
6 Thus, flip-flop circuit 1020 may be set once and only once during 7 a field interval.
8 The FPINT signal produced by flip-flop circuit 1010 is 9 coupled to the load input of a latch circuit 1012 to enable the

10 latch circuit to receive and store the contents of counter 1014

11 coupled thereto. Counter 1014 counts horizontal blanking pulses

12 HZBLNK and, thus, the count of this counter identifies the number

13 of the horizontal line interval then being received. As

14 illustrated, the counter is cleared, or reset, in response to the

15 vertical blanking pulse normally produced once during each field

16 interval. Accordingly, latch circuit 1012 stores therein the

17 number of the horizontal line interval in which the FPINT signal

18 is produced. This is used to identify the number of the line

19 interval in which fingerprint data is to be inserted. This line

20 number is supplied to the microprocessor, and the microprocessor

21 clears the latch circuit by supplying signal STBl thereto,

22 thereby conditioning the latch circuit to store the line number

23 of the horizontal line interval in the next field interval at

24 which fingerprint data is to be inserted.

Slmllarly, the FPINT slgnal ls supplled to the load lnput of latch clrcult 1016 to enable thls latch clrcult to store thereln the count then reached by counter 1018. Counter 1018 ls cleared, or reset, at the beglnnlng of each horlzontal llne lnterval ln response to the horlzontal blanklng pulse HZBLNK. The counter then counts the 250 KHz clock pulses to provlde a count representlng a partlcular locatlon or segment of a llne lnterval. As an example, flfteen of these clock pulses may be produced durlng each horlzontal llne lnterval, and the count reached by counter 1018 at the tlme that the FPINT slgnal is produced represents that segmented locatlon ln the llne interval (whose number was ldentlfled by the count now stored ln latch clrcult 1012) at whlch flngerprlnt data may be lnserted.
Thus, the counts stored ln latch clrcults 1012 and 1016 ldentlfy the partlcular llne lnterval ln a fleld lnterval and also the segment ln that llne lnterval at whlch flngerprlnt data ls to be lnserted. As shown ln FIG. 9, thls data representlng the lnsert locatlon for flngerprlnt data ls stored for subsequent lntroduc-tlon lnto the VBI data.
FIG. 12 ls a functlonal block dlagram of controller 910 shown ln FIG. 9. The apparatus of FIG. 12 lncludes a VTR
1201 for reproduclng the vldeo slgnal whose vertlcal perlod ls to be modlfled ln accordance wlth the present lnventlon and whlch wlll be scrambled prlor to transmlsslon or other dellvery ,_ . . ~5.

PATENT

1 to the cable distribution site. The locations in each vertical 2 interval of this video signal at which fingerprint data is to be 3 inserted also i8 identified.
4 The video signal is played back by VTR 1201 while being re- recorded on VTR 1211 and monitored on a video monitor 6 1209 by a supervisor 1213. This playback and monitoring 7 operation is used to select appropriate profile patterns which 8 best fit this video signal (as discussed above), and profile 9 data representing such profile patterns is inserted into the VBI
data. Accordingly, as a video signal is played back by VTR 1201, 11 time code reader 1203 supplies to a computer 1207 time codes 12 representing each of the played back frames. Also, a 13 synchronizing signal separator 1205 detects the vertical 14 interval and supplies data to the computer corresponding thereto. It is recalled that the particular frames in which 16 scene changes occurred had been determined by scene change 17 detector 904 (Fig. 9), and the location in each field in which 18 fingerprint data may be inserted also have been detected. Such l9 frame identifications of scene change and fingerprint locations are stored on, for example, a magnetic disk 1219, and this stored 21 information is supplied by a disk interface 1217 to computer 22 1207. The computer now utilizes the previously obtained scene 23 chanqe and fingerprint location data with the time code 24 information supplied by time code reader 1203 to produce a record PATE~T

1 for every vertical blanking interval. This record identifies the 2 particular location of the profile pattern for each frame 3 reproduced by VTR 1201 (and identified by time code reader 12033 4 and also identifies the number of the line interval in the field interval and segment of that line in which fingerprint data may 6 be inserted. Still further, computer 1207 generates a scramble 7 map (discussed above) to identify the particular scramble 8 rearrangement that will be used for a field. Thus, computer 1207 g generates for each field of the video signal, the following information profile data representing the vertical period for 11 that field in accordance with the present location along the 12 profile pattern, fingerprint location data and scramble mapping 13 data. This information is stored in suitable data record format 14 and is arranged as a VBI data record for insertion into predetermined locations of the television signal (such as the 16 vertical blanking interval in each field). Advantageously, all 17 of this VBI data is encrypted such as in accordance with a DES
18 encryption code, described above, and the encrypted VBI data is 19 inserted into the video signal. This video signal containing the encrypted ~3I data is recorded on VTR 1211 and distributed, 21 either by physically transporting the recorded tape to the cable 22 network distribution site or playing back this recorded tape for 23 reception at the cable network distribution site.

~O~Z922 PATENT

1 FIGS. 13A-13C represent the vertical blanXing interval 2 and VBI data inserted thereinto, in accordance with a preferred 3 embodiment. As mentioned previously, one technigue that may be 4 used to scramble the video data is to randomly rearrange groups of lines of a field interval. For example, if 240 active lines 6 in a field are contained in the viewable portion, or raster, of 7 the video picture, these 240 lines are broken up into, for 8 example, 4 different blocks, each block of a different length.
g As a numerical example, one block may be formed of 8 line lo intervals, another block may be formed of 150 line intervals, yet 11 another may be formed of 45 line intervals and the last block may 12 be formed of 37 line intervals. These blocks of different 13 lengths are rearranged, thus resulting in a scrambled television 14 signal. Continuing with this numerical example, let it be assumed that a field memory is formed of at least 256 rows, each 16 row being adapted to store a line followed by line intervals 17 containing active video information. Two available line 18 intervals included in the vertical blanking interval are used to 19 store the VBI data. FIGS. 13B and 13C represent these two line intervals which, as an example, may be any desired line intervals 21 between lines 10 and 20 in the field interval.
22 FIG. 13B represents six bytes of VBI data representing 23 the scramble map, and FIG. 13C represents six bytes of VBI data, 24 two bytes being associated with the remainder of the scramble 20329~2 PATENT

1 map, two bytes identifying the location in which fingerprint data 2 may be inserted, one byte containing profile data and a "spare"
3 byte. The scramble map identifies the number of line intervals 4 included in each of the aforementioned four blocks and also the number of the first line included in each block. Stated 6 otherwise, the scramble map identifies the number of memory rows 7 used to store each block of scrambled line intervals, and also 8 the number of the first row in each block. Thus, in FIG. 13B
9 byte 0 identifies a count of 8 line intervals included in the first block, and byte 1 identifies memory row 141 as the first 11 row in which 8 line block is stored. Byte 2 represents a count 12 of 150 line intervals included in the second block, and byte 3 13 identifies memory row 186 as the first row in which this block 14 is stored. Byte 4 represents a count of 45 line intervals, and byte 5 identifies memory row 95 as the first row in which this 16 block is stored.
17 Continuing with FIG. 13C, byte 0 represents a count of 18 37 line intervals and byte 1 identifies memory row 149 as the 19 first row in which this block of line intervals is stored. Byte 2 identifies the line in this field interval in which fingerprint 21 data may be inserted, and byte 3 identifies the particular 22 segrnent of this line interval in which that fingerprint data is 23 inserted. Byte 4 contains profile data and, in accordance with 24 the two embodiments of the present invention described herein, 203Z9~2 PATENT

1 this byte may represent the d~ation of the first 20 line . 2 intervals included in this vertical field, or the byte may 3 represent the number of lines included in the field. As byte 4 4 changes, the vertical period of the field interval correspondingly changes.
6 In one embodiment, each vertical blanking interval in 7 each fiel~ may be provided with the VBI data shown in FIGS. 13B
8 and 13C. In an alternative, the VBI data may be inserted into 9 the vertical blanking interval of only the first (i.e. the odd) field of each frame. Those of ordinary in the art will 11 appreciate other variations which may be used to accommodate the 12 VBI data shown in FIGS. 13B and 13C.
13 The manner in which the VBI data that is generated by 14 computer 1207 (FIG. 12) having the format discussed above (FIGS.
13B and 13C) is inserted into a vertical blanking interval now 16 will be described with reference to FIG. 14. As illustrated, VBI
17 data is inserted into a television signal by VBI data insertion 18 circuit 1402. This circuit is supplied with a signal from VBI
19 timing circuit 1404 to indicate the presence of the vertical blanking interval in the incoming television signal. The VBI
21 timing circuit is supplied with horizontal synchronizing pulses, 22 as may be recovered from the incoming television signal, to 23 determine when the vertical blanking interval occurs. For - 20329~2 PATENT

1 example, ~he VBI timing circuit may include a simple counter ~or 2 counting the horizontal synchronizing pulses.
3 VBI data insertion circuit 1402 is supplied with the 4 fingerprint location data from, for example, the circuit shown in FIG. 10, profile data as may be produced by processor 110 6 (FIG. 1) or as may be produced by controller 910 (FlG. 9), and 7 the scramble map as may be produced by, for example, computer 8 1207 ~FIG. 12) and represented by the various bytes discussed 9 above with respect to FIGS. 13B and 13C. In the embodiment shown in FIG. 14, the fingerprint location data, profile data 11 and scramble map are extracted from data written into a field 12 data buffer 1408 by computer 1406. Computer 1406 may be the 13 same computer as aforementioned computer 1207 (FIG. 12) and is 14 adapted to derive from magnetic disk 1221 the data which had been compiled previously. For example, computer 1406 may read 16 from magnetic disk 1221 and store in field data buffer 1408 the 17 following information: the number of each field interval (or 18 frame), as may be determined from the time code data supplied to 19 computer 1207 as each frame is reproduced from VTR 1201, the fingerprint location data produced by the circuitry shown in FIG.
21 10, a profile data corresponding to the desired profile pattern 22 selected from profile library 118 (FIG. 1) and the scramble map 23 consistent with a desired scramble format (e.g. the number and 24 size of each block of line intervals to be scrambled).

~03Z92Z

PATENT

1 The aforementioned data stored in field data buffer 2 1408 is compiled for each field interval of the incoming 3 television signal. In the embodiment shown in FIG. 12, the 4 incoming television signal is reproduced by VTR 1201, and the field data buffer thus contains the time code data, fingerprint 6 location data, profile data and scramble map for each reproduced 7 field (or frame).
8 For convenience, the fingerprint location data stored g in field data buffer 1408 is supplied to a fingerprint location data buffer 1410. Also, the profile data stored in field data 11 buffer 1408 is supplied to profile data buffer 1412. Finally, 12 each scramble map stored in field data buffer 1408 is supplied to 13 scramble map buffer 1414. These respective buffers supply the 14 data stored therein to VBI data insertion circuit 1402 whereat the data is assembled in the format shown in FIGS. 13B and 13C
16 and inserted into the proper line intervals included in the 17 vertical blanking interval of the incoming television signal.
18 In one embodiment, a new accumulation of data is 19 loaded into field data buffer 1408 with each new field interval read from the VTR. In an alternative embodiment, field data 21 buffer 1408 may include several stages adapted to store the time 22 code data, fingerprint location data, profile data and scramble 23 map for several field intervals, and computer 1406 may load into 20329~Z

PATENT

1 the field data buffer this information associated with each of - 2 those respective field intervals.
3 A decoder 1416 functions to separate the active video 4 information from the incoming television signal and supplies this information to A/D converter 1418 which digitizes the video 6 information. As an example, 900 pixels for each line interval 7 may be produced by the A/D converter and supplied to memory 1420 8 for storage therein. In one embodiment, memory 1420 comprises a 9 dual memory adapted to store odd and even fields, and thus designated a "dual" memory. As one field of digitized video 11 information is loaded into memory 1420, a previously stored field 12 therein may be unloaded and supplied to a D/A converter 1424 for 13 combination in mixer 1426 with the synchronizing pulses, vertical 14 blanking interval, black inactive line intervals and VBI data supplied by VBI data insertion circuit 1402. Memory address 16 control 1422 selects the appropriate memory included in dual 17 memory 1420 into which digitized line intervals are written and 18 from which those digitized line intervals are read. Memory 19 address control 1422 also determines the write- in and read-out rates for the dual memory which, for the embodiment shown in 21 FIG. 14, are synchronized with the "standard" horizontal 22 synchronizing signal. The memory address control also 23 determines the particular rows in which the line intervals are 24 stored, as determined by the scramble map read from scramble map ~9ZZ

PATENT

1 buffer 1414. The output from mixer 1426, which comprises the 2 scrambled composite television signal containing the VBI data 3 discussed above, is recorded on VTR 1428.
4 VBI data insertion circuit 1402 additionally functions to encrypt the fingerprint, profile and scramble map data prior 6 to insertion in the television signal (such as in the vertical 7 blanking interval). As mentioned above, it is preferred to use a 8 DES encryption ~ey for such encoding.
9 In the embodiment shown in FIG. 14, the television signal recorded by VTR 1428 corresponds to the television signal 11 provided by circuit 912 (FIG. 9). It is appreciated, therefore, 12 that the vertical period of this television signal constitutes 13 the standard vertical period of 16.683 milliseconds. Changes in 14 the vertical period, that is, modification of the television signal to prevent it from being accurately reproduced if it 16 subsequently is recorded on a conventional VTR, is carried out by 17 the apparatus shown in FIG. 15 which, it will be appreciated, 18 incorporates the present invention discussed previously with 19 respect to FIGS. 1 and 5.
The apparatus shown in FIG. 15 is located at the head 21 end, or cable network distribution site. The purpose of this 22 apparatus is to modify the vertical period of the television 23 signal, as discussed in detail hereinabove, and to permit 24 fingerprint data to be inserted into the identified location of 203Z9Z~

PATENT

1 the active video signal. An incoming television signa} whose 2 vertical blanking interval has been prepared in accordance with 3 the apparatus shown in FIG. 14 and which has been scrambled, is 4 received either by means of, for example, satellite transmission, or by reproducing same from a video tape (as represented by VTR
6 1503). In either event, the scrambled and VBI-encoded television 7 signal is assumed to be present in NTSC format and is converted 8 by NTSC-to-RGB decoder 1505 to separate red, green and blue video 9 components, each component being scrambled as aforesaid.
The usual 3.58 MHz color subcarrier burst signal and 11 horizontal synchronizing signals are recovered from the incoming 12 television signal, and the subcarrier and horizontal 13 synchronizing signals are supplied to timing generator 1507 14 whereat suitable timing pulses are generated to control the timing of portions of the remaining illustrated circuitry. As 16 an example, a timing signal frequency of six times the color 17 subcarrier frequency f, is generated, as is a timing signal 18 whose frequency is 3fs~
19 These timing signals are supplied to memory load control circuit 1511 and to memory unload circuit 1513 which 21 operate to load memory 1519 with digitized line intervals of the 22 separated R, G and B components of the television signal, and 23 also to unload the memory so as to adjust the vertical period 203Z~22 PATENT

1 thereof in accordance with the present invention, and to -2 descramble the incoming television signal.
3 A vertical interval detector 1518 detects the presence 4 of the vertical blanking interval in each field of incoming television signal; and this detector may be located either 6 upstream or downstream of the NTSC- to-RBG decoder. In any 7 event, the vertical interval detector serves to strip the 8 vertical blanking interval from the incoming television signal 9 and supply it to VBI data detector 1509. The VBI data detector receives timing pulses from timing generator 1507 for 11 the purpose of separating from the incoming vertical blanking 12 interval the encrypted fingerprint, profile and scramble map 13 data. This separated VBI data is 5upplied to a central 14 processing unit (CPU) 1515, together with a suitable DES
decryption key. It is recognized that, of course, the purpose 16 of the DES decryption key is to permit the proper decoding of 17 the encrypted VBI data.
18 CPU 1515 also is coupled to memory load control 19 circuit 1511 and to memory unload control circuit 1513 to select the particular field memory included in memory 1519 for loading, 21 to select the particular field memory for unloading, to 22 descramble the incoming line intervals so as to restore the 23 proper order thereto, and to control the manner in which 24 television data is read out from the selected field memory. It PATENT

1 is this la~er ~eature which results ln a modificatlon ~ the 2 television signal by adjusting the vertical period thereof.
3 Thus, CPU 1515 controls memory unload control circuit 1513 so as 4 to determine the read-out rate for each line interval read from memory 1519. In the other embodiment described herein, CPU 1515 6 controls memory unload control circuit 1513 so as to determine 7 the read-out time of line intervals read from memory 1519 and the 8 number of black line intervals to be added to the active lines g read from the memory, as described above. By changing the read-out rate of memory 1519, the duration of the line intervals read 11 therefrom likewise is changed. Also, by changing the number of 12 line intervals included in each field, the duration of each field 13 and, thus, the duration of each frame may be ad~usted.
14 Of course, the particular read-out rate used to unload memory 1519, or the number of inactive lines to be included in a 16 field, is determined by the profile data included in the vertical 17 blanking interval of the incoming television signal. The manner 18 in which CPU 1515 operates to control the vertical period in 19 accordance with the selected profile pattern has been discussed in detail hereinabove and need not be repeated here.
21 The separated R, G and B video components are 22 digitized by separate R, G and B A/D converters 1517. Thus, and 23 in the manner discussed above, each A/D converter produces a line 24 interval of pixels, each pixel having a value representing the PATENT

1 chrominance level of that component. A/D converters 1517 supply -2 the ~, G and B digitized line intervals to separate R, G and B
3 field memory devices 1519. It is preferred that each field 4 memory device be comprised of eight separate field memories, four field memories to accommodate four odd fields and four field 6 memories to accommodate four even fields. Memory 1519 thus may 7 be formed of twenty- four separate memory units, eight memory 8 units for each of the R, G and B components, with each set of 9 eight memory units being adapted to accommodate four frames, each frame being formed of two interlaced odd and even field 11 intervals.
12 The scramble map received in a vertical blanking 13 interval is decrypted, and each such scramble map represents the 14 scrambled order of the line intervals included in the next-following field. Consistent with the example described above, 16 the first block of line intervals is stored in rows 141-148, and 17 these rows are read out from memory 1519, line-by-line, first.
18 Then, rows 186-335 are read out, line-by-line, constituting the 19 second block of line intervals. Following row 335, rows 95-140 are read from the memory 1519, and it is recalled that these rows 21 constitute the third block of line intervals. Finally, rows 149-22 185 of memory 1519 are read out, and these rows comprise the 23 fourth block of line intervals. Thus, notwithstanding the 24 receipt of a scrambled field interval, the scramble map recovered 20329~

~ATENT

1 from the vertical blanking interval and stored in CPU 1515 serves 2 to descramble the vertical field intervals, thereby recovering 3 the video signal in proper order.
4 As each line interval of pixels is read from a field memory included in memory 1519, the pixels are converted into 6 analog form by D/A converter 1521. In the preferred embodiment 7 wherein separate R, G and B memory devices are used as memory 8 1519, D/A converter 1521 likewise is formed of separate R, G and 9 B, D/A converters. Thus, each chrominance component is recovered in analog form, and these recovered analog signals, having their 11 vertical periods modified in accordance with the present 12 invention, are supplied to RGB-to-NTSC encoder lS25 for combining 13 the R, G and B components into an NTSC color video signal.
14 The output of the RGB-to-NTSC encoder is supplied to a cable distribution head end unit 1527 for mixing with the usual 16 horizontal synchronizing pulses, vertical blanking pulses and 17 color subcarrier bursts.
18 As a result, a conventional NTSC composite television 19 signal, having the usual synchronizing and color bursts added thereto, but having modified vertical periods is supplied to the 21 cable network.
22 FIG. 16 illustrates in somewhat greater detail the 23 manner in which timing generator 1507 and memory load control 24 circuit 1511 operate to load memory 1519 wlth received, ;~0~2922 PATENT

1 scrambled video signals. As before, the incoming video signal 2 is supplied to NTSC-to-RGB decoder 1505 which, in turn, supplies 3 separated R, G and B video components to A/D converters 1517. It 4 is recalled from FIG. 15 that the A/D converters supply memory 1519 with digitized line intervals for each of the R, G and B
6 components.
7 The incoming video signal also is supplied to a 8 synchronizing signal separator 1602 which separates from the 9 incoming video signal the horizontal synchronizing pulses. A
color subcarrier recovery circuit 1604 also is supplied with the 11 incoming video signal and recovers therefrom the usual color 12 subcarrier o~ frequency fs. A ~requency multiplier 1606 13 multiplies the recovered color subcarrier by factors of 3 and 6, 14 respectively, thereby producing timing signals of frequencies 3fs and 6f5, respectively. These timing signals, together with the 16 separated horizontal synchronizing pulses, are supplied to a 17 phase generator 1608 which, in turn, generates the HCLR pulses 18 (such as discussed above with respect to FIG. 7B) together with 19 three phased timing signals identified as PHA, PHB and PHC, respectively, the frequency of each of these timing signals being 21 equal to 3f~, but these signals exhibiting relative phase shifts 22 of 120 with respect to each other. The HCLR signal, which 23 coincides approximately with the recovered horizontal 24 synchronizing pulses, is counted by a counter 1612, the count of ~03Z9Z2 PATENT

1 which represents the vertical line count. Thus, the count of 2 counter 1612 indicates the raster line number then being received 3 by the illustrated apparatus.
4 The recovered horizontal synchronizing signals also are supplied to a line analyzer 1610 together with a horizontal 6 count signal, the latter being represented as an 8-bit digital 7 signal. This HCNT signal represents the present horizontal 8 position of the line interval included in the vidéo signal then 9 being received. Line analyzer 1610 generates a LDEND signal which occurs generally at the first equalizing pulse included in 11 a vertical field. Thus, the LDEND signal may be used to indicate 12 the start of a field interval and serves to reset counter 1612, 13 thus resetting the vertical line count at the beginning of the 14 line intervals commencing in the vertical blanking interval.
Counter 1612 thus accurately tracks the line intervals as they 16 are received.
17 The HCNT signal produced by counter 1614 is supplied 18~ to a decoder 1616 which utilizes the HCNT signal to produce a 19 horizontal display signal HDSP. This HDSP signal is similar to that shown in FIG. 7C, and represents that portion of each line 21 interval wherein active video information is present. It will be 22 recognized that this HDSP signal is used to control memory 1519 23 so as to effectively "open" the memory to receive digitized line PATENT

1 interval information only during the active portion of that 2 interval.
3VBI detector 1620 is coupled to A/D converter 1517 and 4 is adapted to detect and pass the VBI data to serial-to-parallel converter 1624. The VBl detector is enabled by VBI line decoder 6 1622 which, in turn, responds to the vertical line count 7 generated by counter 1612. Thus, during those line intervals in 8 which VBI data has been inserted, for example, during the g selected line intervals between lines 10 and 20 of a field 10interval, decoder 1622 enables VBI detector 1620 to pass the VBI
11 data which is present in those line intervals. As a result, 12 fingerprint location, profile and scramble map data are converted 13 from serial form (i. e. the form in which they are present in the 14 vertical blanking interval) to parallel form, and this data then is stored in latch circuit 1626 to be supplied thereafter to CPU
16 1515. If desired, the latch circuit may include separate stages, 17 each stage storing a respective one of the fingerprint location 18 data, the profile data and the scramble map. As determined by 19 CPU 1515, this data may be transferred thereto as called for by the CPU.
21As mentioned above, the scramble map data present in a 22 verti~al blanking interval represents the scramble map for the 23 next-following field interval. Of course, this scramble map data 24 is transferred to CPU 1515 by latch circuit 1626, and then, prior 20:~2!~22 PATENT

1 to the re~ipt of the ~ext-followinq field interval, the CPU
2 supplies latch circuit 1630 with a count representing the number 3 of lines included in the first block of scrambled video data that 4 will be received in the next-following field interval. At the same time, the CPU supplies to latch circuit 1634 a count 6 representing the address of the first row in memory 1519 in which 7 the first line interval of the first block of scrambled video 8 data is to be stored, or loaded. Thus, the starting row in which 9 the first block of scrambled video information is to be stored, lo as well as the size of that block are loaded into latch circuits 11 1634 and 1630, respectively. The counts stored in these 12 latch circuits then preset counters which, in turn, supply 13 addresses to memory 1519 to address the proper rows therein into 14 which the received and digitized line intervals are loaded. As shown, counter 1632 is coupled to latch circuit 1630 and counter 16 1636 is coupled to latch circuit 1634. Both of these counters 17 count the HCLR pulses generated by phase generator 1608 so as to 18 provide current, updated addresses for the memory. In one 19 embodiment, counter 1632 is decremented such that the instantaneous count thereof indicates the number of line 21 intervals remaining in the block of scrambled line intervals 22 being received. Preferably, counter 1636 is incremented so as to 23 address successive rows in memory 1519 into which each received 24 line of digitized video information is stored. In the numerical ~0329X2 PATENT

1 example discussed above, the video information is received in the 2 following order: block 3, consisting of 4S line intervals, 3 followed by block 1, consisting of 8 line intervals, followed by 4 block 4 consisting of 37 line intervals, followed by block 2 consisting of 150 line intervals. CPU lS15 utilizes the scramble 6 map supplied thereto by latch circuit 1626 such that, when block 7 3 is received, counter 1632 is preset to a count of 45 and 8 counter 1636 is preset to a count of, for example, 178. When 9 counter 1632 is decremented tc a count of 0, counter 1636 will be incremented to a count of 222. Then, counter 1632 is 11 preset to a count of 8 and counter 1636 is preset to a count of 12 20. Block 1 next is received, and this block is stored in rows 13 20-27, respectively, of memory 1519. When all rows of this 14 block is received, counter 1632 will have been decremented to a count of 0, whereafter this counter is preset to a count of 37 16 and counter 1636 is preset to a count of 223. Block 4 next is 17 received and is stored at rows 223-259, respectively, in memory 18 1519. When the last row of this block is received, counter 1632 19 will have been decremented to a count of 0, and the CPU then presets counter 1632, via latch circuit 1630, to a count of 150.
21 At this time, counter 1636 is preset to a count of 28; and block 22 2 is stored, line-by-line, at rows 28-177, respectively, in 23 memory 1519. Thus, the scrambled video information is 24 descrambled and stored, in order, at the proper row addresses of Z0329~2 PATENT

1 memory 1519. The contents of this memory then may be read out in 2 the manner discussed above so as to change the vertical period of 3 each field interval, in accordance with the present invention.
4 In one embodiment of this invention, memory 1519 is s comprised of dynamic random access memories (DRAM~ which, as is 6 known to those of ordinary skill in the art, are relatively 7 inexpensive but operate at a relatively slow rate. Moreover, a 8 DRAM must be refreshed periodically to accurately retain the 9 digital information stored therein. In one embodiment, the operating cycle of a typical DRAM may be too slow to accommodate 11 the sampling rate at which the A/D converters operate. For 12 example, if the A/D converter samples the incoming R, G and B
13 components at a rate equal to the color subcarrier frequency f5~
14 or at a rate equal to 3 times this frequency, the operating speed of a typical DRAM may not be sufficient to accommodate this 16 sampling rate. It is for this purpose that phase generator 1608 17 (FIG. 16) generates the three phased timing pulses PHA, PHB and 18 PHC, respectively. One embodiment of one field memory using such 19 a DRAM, but timed to load and unload R, G and B components, respectively, is illustrated in FIG. 17. This embodiment 21 represents a compromise, whereby the operations of the D~AM are 22 divided into three phases so that the speed limitations of the 23 individual DRAM devices are overcome by phase overlapping. The 24 illustrated one field of memory actually is comprised of nine 203Z9~2 PATENT

1 DRAM devices, one for each phase and one for each of the R, G and 2 B color components.
3 The illustrated DRAM devices 1711-1731 are known as 4 "single port" devices wherein the same terminal, or pin, functions both as an input and an output. Memory devices 6 1711, 1713 and 1715 are used to store one field of the red 7 component, memory devices 1719, 1721 and 1723 are used to store 8 one field of the green component, and memory devices 1727, 1729 9 and 1731 are used to store one field of the blue component. The R, G and B color components are derived from the incoming 11 television signal by NTSC-to-RGB decoder 1701. Separate R, G and 12 B A/D converters 1703, 1705 and 1707 digitize each line interval 13 of the respective color components, and 8-bit pixel values are 14 supplied to the R, G and B latch circuits 1709, 1717 and 1725, respectively. The timing signal 3f, produced by multiplier 1606 16 (FIG. 16) is used to load successive pixels into their respective 17 latch circuits. Each memory device is addressed by a row and 18 column address technique. Stated otherwise, each memory device 19 may be thought of as having rows of storage locations for storing respective line intervals, and each storage location in a row may 21 be addressed as a column address to store therein a pixel 22 produced by A/D converter 1703 (or 1705 or 1707). In addition to 23 addressing a row and column of the memory device, each memory 24 device also is provided with a write enable input which, when ~03Z9~2 PATENT

1 supplied with a write control signal enables a pixel to be 2 written into the location addressed by the row and column 3 addresses. A clock generator 1735 generates row and column 4 addresses, together with a write control signal, all supplied to memory device 1711. Similarly, clock generator 1737 generates 6 row and column addresses and a write control signal for memory 7 device 1713. Finally, clock generator 1739 generates row and 8 column addresses together with a write control signal for memory 9 device 1715. If memory devices 1711, 1713 and 1715 are ~hought of as phases A, B and C for the red field memory, clock 11 generators 1735, 1737 and 1739 may be thought of as the phase A, 12 phase B and phase C clock generators, respectively. These clock 13 generators are driven by a decoder matrix 1733 which supplies the 14 respective clock generators with timing pulses derived from the PHA, PHB and PHC signals produced by phase generator 1606 (FIG.
16 16), together with load and unload signals (which select the 17 write and read memory functions, respectively) and a select 18 signal (supplied by CPU 1515 (of FIG. 15) for selecting the 19 particular field memory which is to be loaded and unloaded.
Column address counters 1741, 1743 and 1745 are 21 supplied with timing pulses of a frequency 3fs and are used to 22 address successive columns in each addressed row of a 23 corresponding phase of the memory devices. As a numerical 24 example, about 680 columns are addressed successively for each ;~03Z9~2 PATENT

1 row. It is recognized that column address counter 1741 -2 addresses the columns of phase A memory device 1711 las well as 3 the columns of phase A memory device 1719 and phase A memory 4 device 1727). Column address counter 1743 addresses the columns of phase B memory device 1713 (as well as the columns of phase B
6 memory device 1721 and phase B memory device 1729). Finally, 7 column address counter 1745 addresses the columns of phase C
8 memory device 1715 (as well as the columns of phase C memory g device 1723 and phase C memory device 1731).
Row address counters 1747, 1749 and 1751 are supplied 11 with the HC1R signal and are used to address successive rows of 12 the phase A, phase B and phase C memory devices, respectively.
13 Thus, when a row is addressed in phase A memory device 1711 (or 14 phase A memory device 1719 or phase A memory device 1727), 680 successive columns in that row are addressed by column address 16 counter 1741. A similar cooperative relationship exists between 17 row address counter 1749 and column address counter 1743, and 18 between row address counter 1751 and column address counter 19 1745.
During a load operation, the select and load signals 21 supplied to decoder matrix 1733 are used to select the field 22 memory into which the digitized video signals are to be written, 23 as determined by CPU 1515, and latch circuits 1709, 1717 and 1725 24 are enabled to ~upply to the selected field memory the 8-bit ~0~29~2 PATENT

1 pixels stored in each ~atch cIrcuit. The write con~roI s~g-~a~ -2 generated by clock generators 1735, 1737 and 1739 enable the 3 pixels to be written into the selected field memory, and the 4 column address signals generated by these clock generators serve to "clock" each pixel into the row and column location determined 6 by the row and column address counters at the particular time 7 esta~lished by the column address signal. Thus, at the phase A
8 clock time, the pixels stored in latch circuits 1709, 1717 and 9 1725 are written into the addressed row and column location of lo phase A memory devices 1711, 1719 and 1727; at the phase B clock }1 time, the pixels then stored in latch circuits 1709, 1717 and 12 1725 are written into the addressed row and column locations of 13 phase B memory devices 1713, 1721 and 1729; and at the phase C
14 clock time, the pixels stored in latch circuits 1709, 1717 and 1725 are written into the addressed row and column locations of 16 phase C memory devices 1715, 1723 and 1731.
17 During an unload, or read operation, a similar 18 operation is carried out, except that now the unload signal 19 supplied to decoder matrix 1733 serves to enable read-out latch circuits 1755, 1757 and 1759 to receive the pixels read from the 21 addressed row and column locations of the phase A, phase B and 22 phase C memory devices, at the phase A, phase B and phase C clock 23 times determined by the column control signals generated by clock 24 generators 1735, 1737 an~ 1739, respectively. The contents then 20329~Z

PATENT

1 stored in these read-out latch circuits are supplied to D/A
2 converts 1761, 1763 and 1765, respectively, at an output timing 3 rate equal to 3f5. From FIG. 17, it is seen that the converted 4 analog R, G and B components are combined in NTSC encoder 1767 and supplied as a composite video signal whose vertical period is 6 adjusted in accordance with the memory read-out timing that has 7 been discussed above in conjunction with FIGS. 1 and 5.
8 Although not shown herein, the timing of the row and g address control signals produced by each of clock generators 1735, 1737 and 1739 functions to permit the contents of each of 11 the phase A, phase B and phase C memory devices to be refreshed 12 periodically, to be loaded, and to be unloaded. Since a refresh 13 operation occurs at times other than when a particular row of 14 memory is loaded or unloaded, each row address counter includes a register to store temporarily the address of the particular row 16 which is in the process of being refreshed. In one embodiment, 17 the refresh operation serves to refresh 32 rows of a memory 18 device during each horizontal blanking interval. Since active 19 video information is not present during the horizontal blanking interval, this refresh operation does not interfere with the 21 loading and unloading cycles of the field memories. It is 22 appreciated, therefore, that eight horizontal blanking intervals 23 are needed to refresh 256 rows of video information stored in 24 each of the phase A, phase ~ and phase C memory devices.

~03Z9Z2 PATENT

1 The Improvements 2 Referring now to FIG. 18, there is illustrated another 3 block diagram of apparatus similar to that of FIG. 1 for 4 processing a video signal to prevent it from being copied on a conventional video recorder but permitting it to be displayed by 6 a conventional television receiver, which apparatus incorporates 7 the present invention. The signal processing apparatus includes 8 an analog-to-digital (A/D) converter 12, N field memories 14 and 9 a digital-to-analog (D/A) converter 20. An input video signal to be processed is supplied to a video input 11 to which A/D
11 converter 12 is coupled. The A/D converter functions to digitize 12 each line interval of the video signal, thereby generating pixels 13 in each such interval. A/D converter 12 is coupled to N field 14 memories 14, each memory being adapted to store a field of useful video information. A write circuit 16 is coupled to memories 14 16 and, under the control of a memory controller (not shown) 17 determines the appropriate storage locations in which each line 18 of pixels is stored.
19 Once a field of useful video information is stored in a field memory, it is read out therefrom under the control of a 21 read circuit 18. The read circuit determines which line of pixel 22 elements are to be read; and here too, the read circuit is 23 controlled by the memory controller. The pixels read from a 24 field memory are supplied to D/A converter 20 where they are PATENT

1 converted back to analog form. The reconverted, analog video 2 signal then is supplied to a combining circuit 22 whereat it is 3 combined with synchronizing signals, including the usual 4 horizontal synchronizing signals as well as those signals normally included in a vertical synchronizing interval. ln 6 accordance with the conventional NTSC st~n~rd, the vertical 7 synchronizing interval includes three line intervals, each 8 containing two pre-equalizing pulses, followed by three line 9 intervals each containing two vertical pulses, followed by three line intervals each containing two post-equalizing pulses.
11 Additional "blank" line intervals, that is, line intervals which 12 do not contain useful video information, also are supplied to 13 combining circuit 22 to reconstitute a composite video signal.
14 As described above, a field interval is increased or decreased by adding a greater or lesser number of "blank" line intervals.
16 The present invention modifies the pulses normally 17 provided in the conventional vertical synchronizing interval so 18 as to prevent digital vertical synchronizing circuits from 19 locking onto a standard field repetition rate when the video signal produced at the output of combining circuit 22 contains a 21 variable field repetition rate. This modification of the 22 conventional vertical synchronizing interval is achieved by a 23 sync separator 24, a horizontal sync leading edge generator 30, a 24 subcarrier regenerator 28, a frequency multiplier 32, an output ~03Z~;2Z

PATE~T

1 synchronizing signal generator 34, an output line counter 36 and 2 a comparator 38. Sync separator 24 is coupled to video input 11 3 and is adapted to separate the usual horizontal and vertical 4 synchronizing signals normally included in a composite input video signal. It is expected that the illustrated apparatus is 6 used with color television signals and, thus, sync separator 24 7 also functions to remove the usual chrominance subcarrier burst 8 signal normally included in the composite video signal.
9 Sync separator 24 is provided with a horizontal synchronizing signal output and a chrominance subcarrier output.
11 The horizontal synchronizing signal output is coupled to a 12 horizontal sync detector 26 and the chrominance subcarrier output 13 is coupled to a chrominance subcarrier regenerator 28.
14 Horizontal sync detector 26 may be a conventional device adapted to detect the usual horizontal synchronizing pulses which are 16 present in the composite video signal and which have been 17 separated therefrom by sync separator 24. The output of the 18 horizontal sync detector is coupled to horizontal sync leading 19 edge generator 30 which is adapted to generate a narrow pulse in response to the leading edge of each separated horizontal 21 synchronizing pulse. This leading edge pulse is identified 22 herein as an HCLR pulse and represents the beginning of a line 23 interval. The HCLR pulse is supplied to output synchronizing 24 signal generator 34, as shown.

~0329~2Z

PATENT

1 Chrominance subcarrier regenerator 28 may include a 2 phase locked loop adapted to regenerate a substantially 3 undistorted, noise-free signal with frequencies e~ual to the 4 usual chrominance subcarrier freguency f,c. The regenerated chrominance subcarrier is coupled to freguency multiplier 32 6 which is adapted to multiply this chrominance subcarrier 7 frequency by a factor of, for example, four. Multiplier 32 is a 8 conventional circuit and need not be described in detail. The g frequency-multiplied chrominance subcarrier is utilized as a clock signal having the fre~uency, or repetition rate, 4f~c. As 11 shown in ~IG. 18, this clock signal 4fsc is supplied to output 12 synchronizing signal generator 34.
13 An output of horizontal sync leading edge generator 30, 14 such as, but not necessarily, the HCLR signal, is supplied to output line counter 36 which is adapted to count that signal, 16 thus providing a count representing numbers of horizontal line 17 intervals. As will be apparent, the count of output line counter 18 36 represents the number of the line intervals provided at the 19 video output of combining circuit 22.
The count of output line counter 36 is coupled to 21 comparator 38 whereat it is compared to a preset count supplied 22 to another input of the comparator by a last line register 40.
23 The last line register is coupled to a preset input 39 to receive 24 a pre-loaded count representing the number of line intervals 20~2922 60939-1520 included ln the fleld of the processed vldeo slgnal produced at the video output of comblnlng clrcult 22. It ls appreclated that when the count of output llne counter 36 ls equal to the pre-loaded count stored ln last llne reglster 40, the comparator produces an end-of-fleld slgnal representlng the end of a fleld lnterval contalnlng the preset number of llne lntervals. Thls end-of-fleld slgnal ls used to reset output llne counter 36 and also ls supplled to output synchronlzlng slgnal generator 34 for a purpose descrlbed below.
In operatlon, let lt be assumed that a fleld lnterval of the output vldeo slgnal ls to contaln 264 llne lntervals.
Let lt be further assumed that output llne counter 36 has been reset after the lmmedlately precedlng fleld lnterval has been produced. Accordlngly, as each actlve and lnactive llne lnterval ls provlded at the vldeo output of comblnlng clrcult 22, the count of output llne counter 36 ls lncremented ln response to, for example, each HCLR pulse. Conslstent wlth the present assumptlon, last llne reglster 40 ls preset wlth a count of 264. Thus, lt ls seen that, once 264 llne lntervals have been provlded at the output vldeo slgnal, the count of output llne counter 36 ls equal to the count stored ln last llne reglster 40, resultlng ln the end-of-fleld slgnal produced by comparator 38. Accordlngly, output llne counter 36 ls reset and the aforementioned process ls carrled out once agaln. Of course, the ., 9S
:.
. .
~., s ._, . , ~ .

PATENT

1 line count to which last line register 40 is preset may be equal 2 to any other suitable count, described above; and once output 3 line counter 36 has been incremented to this count, another end-4 of-field signal is produced. It is recognized, therefore, that the end-of-field signal represents the end of a field interval 6 whose length is, of course, variable and determined by the pre-7 loaded count stored in last line register 40, which is derived 8 from the selected profile by the memory controller.
g Output synchronizing signal generator 34 responds to the end-of-field signal to produce the vertical synchronizing 11 interval containing modified vertical and equalizing pulses which 12 prevent digital vertical synchronizing circuits included in some 13 television receivers from generating vertical control signals at 14 a fixed periodicity when, in fact, the field intervals of the output video signal produced by combining circuit 22 vary.
16 Although not shown and described herein, it will be 17 appreciated that the write and read operations by which pixels 18 are written into and read from field memories 14 are synchronized 19 with the horizontal synchronizing signals and chrominance subcarrier bursts separated from the input video signal. Thus, 21 the output synchronizing signals generated by output 22 synchronizing signal generator 34 are in synchronism with the 23 memory read-out operation.

= 60939-1520 A more detalled descrlptlon of the output synchronl-zlng slgnal generator now wlll be provlded ln con~unctlon wlth the block dlagram shown ln FIG. 19. As lllustrated, output synchronlzlng slgnal generator 34 ls comprlsed of a horlzontal counter 52, an output llne counter 54, a decoder 56, a loglc gate array 58, latch clrcults 60, 62 and 64, a loglc gate array 66, a counter 68 and a decoder 70. Horlzontal counter 52 ls to be dlstlngulshed from a horlzontal llne counter. The horlzontal counter ls adapted to count the 4fSC clock pulses generated by frequency multlplier 32 (FIG. 18), of whlch approxlmately 900 are produced durlng a standard horlzontal Ilne lnterval. The horizontal counter ls supplled wlth these 4fSC clock pulses by way of a clock slgnal lnput 51; and the counter lncludes a reset lnput coupled to a horlzontal sync leadlng edge lnput 53 to whlch the HCLR pulses are supplled. It wlll be appreclated, then, that the changlng count of horlzontal counter 52 repre-sents a changlng locatlon ln a horlzontal llne lnterval.
The count of the horlzontal counter ls coupled to a decoder 56 whlch functlons to decode predetermlned counts attalned by the horlzontal counter correspondlng to the begln-nlng of a horlzontal llne lnterval, the mldpolnt of a horlzontal llne lnterval, a polnt located at approxlmately one-slxth of a horlzontal llne lnterval and a polnt located at approxlmately flve-slxths of a horlzontal llne lnterval. These decoded counts ; 97 X' ... , " _ --PATENT

1 result in the following pulses: an HSTART pulse, representing 2 the beginning of a horizontal line interval; an HMID pulse 3 representing the midpoint of a horizontal line interval, a 1/6H
4 pulse, representing the one-sixth point along a horizontal line interval and a 5/6H pulse representing a point five-sixths along 6 the horizontal line interval. The HSTART, HMID, 1/6H and 5/6H
7 pulses all are supplied tc gate array 58, for a purpose to be 8 described.
9 Output line counter 54 is adapted to count the HCLR
pulses supplied to horizontal sync leading edge input 53.
ll Counter 54 includes a reset input coupled to an end-of-field 12 input to which the end-of-field signal produced by comparator 38 13 (FIG. 18) is supplied. It is appreciated, then, that the count 14 of output line counter 54 represents the particular line interval provided at the video output of combining circuit 22 (FIG. 18).
16 This line count together with the end-of-field signal are 17 supplied to gate array 58.
18 In one embodiment, gate array 58 is comprised of 19 conventional logic gates, flip-flop circuits and a line count decoder. The function of the gate array is to determine the 21 beginning of each equalizing pulse, the beginning of each 22 vertical pulse and the duration of the vertical synchronizing 23 interval for each field interval of the video signal. The 24 particular construction of the gate array forms no part of the PATENT

1 present invention per se; and those of ordinary skill in the art - 2 are readily enabled to construct a suitable gate array circuit.
3 In addition to the HSTART, HMID, 1/6H, 5/6H, line count and end-4 of-field signals produced by decoder 56 and output line counter 54, gate array 58 also receives a FIELD I/FIELD II field 6 indication identifying the field interval as being odd (i. e. the 7 first field) or even (i. e. the second field) in a frame. For 8 example, the memory controller mentioned in conjunction with FIG.
9 18 may produce a binary "0" when the FIELD I interval is read from memories 14 and a binary "1" when the FIELD IT interval is 11 read. Furthermore, gate array 58 is connected to receive an 12 "advance" signal adv as well as a delay signal del which, as will 13 be described, are used to shift the time of occurrence of the 14 beginning of the first vertical pulse produced by the gate array.
More particularly, when the vertical period of the video signal 16 produced at the video output of combining circuit 22 is 17 increasing, the memory controller tnot shown3 supplies the adv 18 signal to the gate array to advance the time of occurrence of the 19 first vertical pulse. Conversely, when the field interval of the video signal is decreasing, the memory controller supplies the 21 del signal to the gate array to delay the time of occurrence of 22 the first vertical pulse. As will be described below, this 23 shifting of the time of occurrence of the vertical pulse 20:~Z9;22 PATENT

1 minimizes interlace perturbations in the video picture derived 2 from the pro~es~^d video signal.
3 Depending upon whether a field interval is FIELD I or 4 FIELD II, gate array 58 is adapted to delete a predetermined vertical pulse and to delete selected post-equalizing pulses from 6 the vertical synchronizing interval. Each pre-equalizing and 7 post-equalizing pulse is generated in response to a start 8 equalizing pulse STARTEQ which, as will be described, is produced 9 in response to each HSTART and HMID signal during selected line intervals, that is, when output line counter 54 reached ll predetermined counts. An equalizing pulse is deleted by 12 inhibiting the STARTEQ pulse. In accordance with the NTSC
13 standard, post-equalizing pulses are generated at the beginning 14 and at the midpoint of the seventh, eighth and ninth horizontal line intervals, respectively, for FIELD I, and at the midpoint of 16 the sixth line interval, the beginning and midpoint of each of 17 the seventh and eighth line intervals, and the beginning of the 18 ninth line interval, respectively, for FIELD II. Gate array 58 19 generates the STARTEQ pulse at each of these locations. However, in accordance with the preferred embodiment of the present 21 invention, the STARTEQ pulse is not generated at the midpoint of 22 each of the sixth line interval in FIELD I, and the seventh, 23 eighth and ninth line intervals in FIELDS I and II. Hence, post-24 equalizing pulses are not produced at those times.

PATENT

1 Likewise, during FIELD I intervals, gate array 58 2 generates a STARTVER pulse at the beginning and midpoint of each 3 of the fourth and fifth line intervals and at the beginning of 4 the sixth line intervals. During FIELD II intervals, the gate array generates the STARTVER pulses at the midpoint of the third 6 line interval, the beginning and midpoint of the fourth line 7 interval and the beginning of the fifth and sixth line intervals.
8 However, in accordance with this invention, the last STARTVER
9 pulse which i5 produced at the midpoint of a line interval is inhibited. Thus, during the FIELD I and FIELD II field 11 intervals, the STARTVER pulse which otherwise is generated at the 12 midpoint of the sixth and fifth line intervals, respectively, is 13 inhibited.
14 The gate array also generates a pulse whose duration is equal to the vertical synchronizing interval. During FIELD I
16 intervals, this VSYNCINT pulse commences in response to the end-17 of-field signal and terminates after the midpoint of the ninth 18 line interval. During FIELD II intervals, this VSYNCINT pulse 19 commences at the midpoint of the line interval preceding the first line interval and terminates before the beginning of the 21 tenth line interval.
22 Latch circuits 60 and 62 are coupled to gate array 58 23 to receive the STARTEQ and STARTVER pulses, respectively. Latch 24 circuit 6~ is coupled to decoder 56 to receive the HSTART signal;

~03Z~Z2 PATENT

1 and this latch circuit additionally includes an inhibit input -2 coupled to the gate array to receive the VSYNCINT pulse. Each 3 latch circuit also includes a reset input and operates to latch 4 the signal supplied thereto until reset by a reset signal, to be described. It will be appreciated that latch circuit 64 is 6 inhibited from latching, or storing, the HSTART signal for so 7 long as the VSYNCINT pulse is present. Thus, during the vertical 8 synchronizing interval, latch circuit 64 is inhibited from g storing the HSTART signal.
The latch circuits are coupled to gate array 66 which 11 may be comprised of logic gates and bistate devices for 12 generating an output signal when a latch circuit has been 13 triggered, or set. This output signal is supplied as an enable 14 signal to counter 68 which responds thereto to count the 4fsc clock pulses produced by frequency multiplier 32 (FIG. 18). The 16 count of counter 68 is coupled to decoder 70 together with an 17 output of gate array 66. Depending upon the particular latch 18 circuit which has been triggered, gate array 66 sets decoder 70 19 to detect a respective count of counter 68. The output of the decoder is fed back to clear counter 68 and is coupled to the 21 reset inputs of latch circuits 60, 62 and 64 which, when reset, 22 clears gate array 66 to turn off the output signal.
23 It will be appreciated that the combination of gate 24 array 66, counter 68 and decoder 70 functions to generate output ~03~922 PATENT

1 pulses w~ose aura~lon ls aeter~ed by the pa~ cula~ c~u~t t~
2 which decoder 70 is set to detect. Accordingly, this combination 3 generates relatively narrow egualizing pulses and relatively wide 4 vertical pulses, as well as horizontal synchronizing pulses whose duration is greater than that of an equalizing pulse but less 6 than that of a vertical pulse. Still further, this combination 7 of gate array 66, counter 68 and decoder 70 operates to generate 8 a wider vertical pulse when the STARTVER pulse is advanced and to g generate a narrower vertical pulse when the STARTVER pulse is delayed.
11 The manner in which the output synchronizing signal 12 generator shown in FIG. 19 operates now will be described in 13 conjunction with the waveform diagrams of FIGS. 20A-20H. Let it 14 be assumed that the field interval of pixels read from memory 14 is FIELD I. Accordingly, a "0" field signal is supplied to gate 16 array 58. When the immediately preceding FIELD II terminates, 17 whether that field interval is greater than, equal to or less 18 than a standard field interval, comparator 38 (FIG. 18) generates 19 the end-of-field signal shown in FIG. 20A. Conseguently, output line counter 54 is reset; and this count is incremented, as shown 21 in FIG. 20B in response to each HCLR signal produced by 22 horizontal sync leading edge generator 30.
23 The HCLR signal also resets horizontal counter 52 24 which, in turn, counts the clock signal 4f~c. The instantaneous f~O3~92Z

PATENT

1 count of counter 52 is decoded by decoder 56 which generates the 2 HSTART signal at the beginning of each line interval, as shown in 3 FIG. 20C, as well as the HMID signal at the midpoint of each line 4 interval, as shown in FIG. 20D. Although decoder 56 also generates the 1/6H and 5/6H pulses, the operation presently 6 described does not utilize these pulses.
7 Depending upon the count of output line counter 54, 8 gate array 58 generates the STARTEQ pulses shown in FIG. 2OE, the 9 STARTVER pulses shown in FIG. 2OF and the VSYNCINT pulse sho~n in FIG. 20G. Thus, for an odd field interval, all of the STARTEQ
11 pulses in the pre-equalizing interval are generated, and all but 12 the last STARTVER pulse are generated, as shown in FIG. 20F.
13 From FIG. 20E, it is seen that gate array S8 generates those 14 STARTEQ pulses which occur at the beginning of each line interval included in the post-equalizing interval, but the STARTEQ pulses 16 which otherwise would be produced at the midpoints of those line 17 intervals are inhibited. An "x" in FIGS. 20E and 20F represents 18 the omitted STARTEQ and STARTVER pulses.
19 In a manner described in conjunction with FIGS. 22A and 22B, each STARTEQ pulse shown in FIG. 20E and each STARTVER pulse 21 shown in FIG. 20F triggers an e~ualizing or vertical pulse which 22 is produced at the output of counter 68, as shown in FIG. 20H.
23 It is seen that the last vertical pulse to be produced at the 24 midpoint of a line interval included in the vertical period is ~)3Z~

PATENT

1 deleted and each post-equalizing pulse which would be produced at 2 the midpoint of those line intervals included in the post-3 equalizing period are deleted. Consequently, digital vertical 4 synchronizing circuits which rely on a standard number of equalizing and vertical pulses included in the video signal will 6 be unable to "lock" onto the vertical synchronizing interval that 7 appears as shown in FIG. 20H. Therefore, as the field interval 8 of the video signal processed by the apparatus shown in FIG. 18 9 varies, the television receiver which includes a digital vertical synchronizing circuit will, nevertheless, generate vertical 11 control signals in synchronism therewith. Vertical control 12 signals of fixed period~city thus will not be produced and the 13 television receiver will display a video picture with minimal 14 perturbations.
When a FIELD II interval is read from field memories 16 14, the STARTEQ, STARTVER and VSYNCINT pulses are produced as 17 shown in FIGS. 21A-21G, respectively. Thus, the pre-equalizing 18 interval commences at the midpoint of the line interval preceding 19 the first line interval and not at the beginning of the first line interval as is the case when FIELD I video signals are read 21 from the field memories. Stated otherwise, the STARTEQ, STARTVER
22 and VSYNCINT pulses all are delayed by a half line interval, as 23 shown. It is appreciated that gate array 58 thus responds to the 24 odd/even field indication to produce the STARTEQ, STARTVER and ;~0329Z2 PATENT

1 VSYNCINT pulses at the times shown in FIGS. 2OE-2OG or at the 2 times shown in FIGS. 2lE-2lG.
3 In accordance with one embodiment of this invention, 4 irrespective of whether the vertical synchronizing interval commences at the beginning of the first line interval or at the 6 midpoint of the preceding line interval, gate array 58 deletes 7 the last STARTVER pulse otherwise generated at the midpoint of 8 the sixth line interval, in FIELD I and at the midpoint of the 9 fifth line interval in FIELD II; and also deletes the STARTEQ
pulses wh~ch otherwise are generated at the midpoints of the post ll equalizing line intervals. Stated otherwise, the last midpoint-12 occurring STARTVER pulse as well as each of the midpoint-13 occurring STARTEQ pulses (in the~post-equalizing interval) are 14 deleted. As a result, the vertical synchronizing interval generated for an even field is as shown in FIG. 21H. Here too, 16 the modified pulses prevent digital vertical synchronizing 17 circuitry from "locking" onto the vertical synchronizing interval 18 of the received video signal and thus prevent uniformly periodic l9 vertical control signals from being generated. Thus, vertical perturbations which otherwise would be present in the displayed 21 video picture because of such uniformly periodic vertical 22 synchronizing signals are avoided.
23 FIG. 21F illustrates the selected advance or delay in 24 the first STARTVER pulse generated during a FIE~D II interval.

- ~03Z922 PATENT

1 An advanced STARTVER pulse is represented as "a" and a delayed 2 STARTVER pulse is represented as "d". Whether this STARTVER
3 pulse is advanced or delayed is dependent upon whether the adv or 4 del signal is supplied to gate array 58 by the memory controller (not shown). It is recalled that the adv signal is produced when 6 the field interval of the video signal is increasing; and the,del 7 signal is produced when the field interval of that video signal 8 is decreasing. By advancing or delaying the first STARTVER
9 puise, the time of occurrence of the first vertical pulse likewise is advanced or delayed. This advance or delay in the 11 beginning of the vertical pulses prevents the first line of the 12 next-following field (FIELD I) from being scanned directly over 13 the first line of the present field (FIELD II). That is, by 14 shifting the beginning of the vertical pulses, the vertical scanning circuitry in a video receiver will shift the location of 16 the displayed field upwardly or downwardly. Hence, if the next 17 FIELD I contains the same number of lines as the present FIETD
18 II, as may occur in response to the profile control described 19 above (and shown in FIG. 2), the proper interlace relationship of FIELD I with respect to FIELD II is maintained.
21 Before explaining the i~proved results achieved by 22 selectively shifting the beginning of the vertical pulses in an 23 even field of the video signal, a discussion is presented as to 24 the manner in which this shifting ~s obtained. Let ~t be assumed 203Z9~2 PATENT

1 that the beginning of the vertical pulses is to be advanced.
2 Accordingly, the adv signal is supplied to gate array 58. FIGS.
3 22B-22E illustrate the relative locations in each line interval 4 of the HSTART, HMID, 1/6H and S/6H pulses produced by decoder 56.
For convenience, FIG. 22A illustrates only some of the line 6 counts which have been discussed above in conjunction with FIGS.
7 20 and 21. Thus, FIG. 22 illustrates various pulses that are 8 produced during line counts 2, 3, 4, 5, 6, 8, 9 and 10. It is g seen from FIG. 22D that the 1/6H pulse is generated after a delay lo of approximately one-sixth of a line interval. Similarly, 11 FIG.22E illustrates that the 5/6H pulse is produced after a delay 12 on the order of five-sixths of a line interval. As will be 13 described below, the 1/6H and 5/6H pulses are used to produce the 14 advance or delayed STARTVER pulse.
FIG. 22F illustrates the STARTEQ pulses which are 16 generated by gate array 58 during the second line interval of the 17 pre-equalization period. In the interest of brevity, those 18 STARTEQ pulses which are generated during the zeroth and first 19 line intervals are omitted. As was discussed above, no STARTEQ
pulses are generated during the vertical period (i. e. the third, 21 fourth and fifth line intervals) of an even field. From FIG.
22 21E, it is recalled that the STARTEQ pulses normally are 23 generated in the post-equalization interval of an even field 24 commencing with the midpoint of the sixth line interval. Of 203292;~

PATENT

1 course, in accordance with the present invention, and as has been 2 described above, those post-equalizing pulses and, thus, the 3 STARTEQ pulses, which occur at the midpoints of line intervals 4 included in the post-equalization period are deleted. FIG. 22F
designates by an "x", the deleted STARTEQ pulse which otherwise 6 would be generated at the midpoint of the sixth line interval.
7 Similar to FIG. 21F, FIG. 22G illustrates the STARTVER
8 pulses which, normally, are generated at the midpoint of the g third line interval of the vertical period, the beginning and midpoint of the fourth and fifth line intervals and the beginning 11 of the sixth line interval. Of course, and consistent with one 12 aspect of the present invention, the last STARTVER pulse to be 13 generated at the midpoint of a line interval, that is, the 14 STARTVER pulse to be generated at the midpoint of the fifth line lS interval, is deleted. This deleted pulse is represented by the 16 "x" in FIG. 22G.
17 FIG. 22G also illustrates a shift in the time of 18 occurrence of the first STARTVER pulse, that is, the STARTVER
19 pulse which normally is produced at the midpoint of the third line interval. Gate array 58 responds to the adv signal, which 21 may be supplied by the memory controller, to advance the time of 22 occurrence of the first STARTVER pulse. More particularly, when 23 the adv signal is present, the STARTVER pulse is generated in 24 response to the 1/6H pulse rather than in response to the HMID

;~03Z9Z;~

PATENT

1 pulse. Hence, and as clearly shown in FIG. 22G the first 2 STARTVER pulse produced during the vertical period coincides with 3 the 1/6H pulse.
4 Gate array 66 responds to the latching of the STARTEQ
pulse in latch circuit 60 to enable counter 68 and to set decoder 6 70 to detect when the counter reaches a preselected count of, for 7 example, A. Once count A is reached, decoder 70 resets the gate 8 array and also resets latch circuit 60. ThUs, in response to g each STARTEQ pulse, counter 68 counts A clock signals. FIG. 22H
represents the output of gate array 66 which is a logic high 11 signal when a latch circuit is triggered and is a logic low 12 signal when decoder 70 senses a particular count (for example, 13 count A) of counter 68. Thus, an output pulse of duration equal 14 to a count of A is generated in response to each STARTEQ pulse, as shown. FIG. 22A illustrates the clearing of the counter by 16 decoder 70.
17 Gate array 66 responds to the latching of the advanced 18 STARTVER pulse to enable counter 68 and also to set decoder 70.
19 The decoder responds to the adv signal supplied thereto to detect when the counter reaches another predetermined count B. Of 21 course, when count B is reached, counter 68, latch circuit 62 and 22 gate array 66 are reset (which resets the gate array output 23 signal). FIG. 22H illustrates the output of gate array 66 in 24 response to the advanced STARTVER pulse.

~03~9;2Z

PATENT

l As also shown in FIG. 22H, when the advance signal is 2 not present, decoder 70 is set by gate array 66, which responds 3 to the latching of the STARTVER pulse in latch 62, to detect yet 4 another preset count C reached by counter 68. Thus, when latch circuit 62 is triggered, the gate array enables counter 68 to 6 count the 4f5c clock pulses; and when the counter reaches the 7 count of C, decoder 70 clears coun~er 68 and resets latch circuit 8 62 and gate array 66. Hence, the output of the gate array 9 exhibits its logic high level for a duration equal to C clock pulses.
11 It will be recognized that, in response to each 12 STARTVER pulse, latch circuit 62 stores that pulse and, in 13 response thereto, gate array 66 enables counter 68 and presets 14 decoder 70 to detect when the counter reaches a count of C.
Consequently, the stream of vertical pulses shown in FIG. 22H is 16 generated and, of course, the vertical pulse which otherwise 17 would be produced at the midpoint of line interval 5 is deleted.
18 Likewise, each STARTEQ pulse included in the post-equalization 19 period is stored by latch circuit 60; and gate array 66 responds thereto to enable counter 68 and to preset decoder 70 to sense 21 when the counter reaches a count of A. As a result, gate array 22 66 generates the post-equalization pulses shown in FIG. 22H, 23 which figure, of course, indicates that those equalizing pulses 203Z~2 PATENT

1 that would otherwise be generated at the midpoints of line 2 intervals included in the post-equali2ation period are deleted.
3 Finally, latch circuit 64 remains inhibited during the 4 VSYNCINT pulse duration. When the VSYNCINT pulse terminates, as shown in FIG. 21G, latch circuit 64 is enabled to store the next 6 HSTART pulse produced by decoder 56. Gate array 66 responds to 7 the setting of latch circuit 64 by the HSTART pulse to enable 8 counter 68 and to set decoder 70 to detect when the counter g reaches a count of D. After D clock pulses ha~e been counted, decoder 70 resets counter 68 and also resets latch circuit 64.
11 Consequently, gate array 66 generates horizontal synchronizing 12 pulses having durations equal to D clock pulses, as shown in FIG.
13 22H.
14 The foregoing has described the operation by which pre-equalizing, vertical, post-equalizing and horizontal 16 synchronizing pulses are generated when the STARTVER pulse is 17 advanced, as when the adv signal is produced. Reference now is 18 made to FIGS. 23A-23I, which are substantially identical to FIGS.
19 22A-22I, to explain how these pulses are generated when the STARTVER pulse is delayed, as when the del signal is produced.
21 It is appreciated that gate array 58 produces the first STARTVER
22 pulse shown in FIG. 23G in time coincidence with the 5/6H pulse 23 (FIG. 23E) when the del signal is present. As a result, the 24 first STARTVER pulse is delayed by one-third of a line interval - ;~03Z9~'~

PATENT

1 relative to the time at which it normally is produced. That is, 2 the first STARTVER pulse is delayed by a one-third line interval 3 from the midpoint of the third line interval included in the 4 vertical synchronizing period. Of course, the 5/6H pulse is seen to be delayed by a one-third line interval from the HMID pulse 6 produced during the third line interval.
7 Decoder 70 is preset by gate array 66 (which responds 8 to the setting of latch circuit 62) and to the del signal to 9 detect when counter 68 reaches a count of E clock pulses.
Accordingly, gate array 66 responds to the setting of latch 11 circuit 62 to enable counter 68; and when the clock pulse count 12 reaches E, decoder 70 resets the counter and also resets latch 13 circuit 62. Hence, as shown in FIG. 23H, the first vertical 14 pulse produced during the vertical period is relatively narrow, as compared to the normal vertical pulse whose duration is equal 16 to a count of C clock pulses.
17 As a numerical example, the counts A-E may be as 18 follows:
19 A = 33 clock pulses = 2.30 microseconds B = 698 clock pulses = 48.7 microseconds 21 C = 387 clock pulses = 27.03 microseconds 22 D = 67 clock pulses = 4.68 microseconds 23 E = 86 clock pulses = 6.01 microseconds Z03Z9~2 PATENT

Of course, other clock pulse counts may be used, if desired.
2 Likewise, the durations of the equalizing, vertical and 3 horizontal pulses need not be limited precisely to the foregoing 4 numerical examples, provided that such pulse durations are within 5 the tolerance limits of the appropriate television standard 6 (e. g. the NTSC standard).
7 The manner in which the advanced and delayed vertical 8 pulses minimize perturbations in the video picture reproduced g from the video signal provided at the video output of combining 10 circuit 22 now will be described in conjunction with FIGS. 24A
11 and 24B. FIG. 24A is a schematic waveform representation of the 12 vertical control signals normally produced by the vertical 13 synchronizing circuit of a conventional video receiver. The 14 diagonal lines shown in FIG. 24A represent the deflection signal 15 supplied to the vertical deflection circuit to achieve a top-to-16 bottom scanning of the electron beam. The vertical lines shown 17 in FIG. 24A represent the retrace signal supplied to the 18 deflection circuit to return the electron beam to its starting 19 position. It is seen that the vertical intervals V1, V2, etc.
20 represent the field intervals; and it is assumed, for purposes of 21 the present discussion, that field intervals V1 and V2 are of 22 standard duration.
23 Let it be assumed that field interval V3 is increased 24 above the standard duration. Consequently, current flows throu~h ~03Z9Z2 PATENT

1 the vertical deflec~ion circuit ~or a longer than stan~ard 2 period. It is seen that the DC level of the deflection current 3 during field interval V3 is reduced; and this reduction in the DC
4 current produces a downward drift in the video picture. Whereas the peak-to-peak value of the deflection current during a 6 standard field interval is shown as A1, the peak-to-peak value of 7 the deflection current during an enlarged field interval now is, 8 for example A2, which is greater than Al and, furthermore, g includes a negat$ve DC shift.
During the next-following field interval V4, the DC
11 level of the deflection current still is shifted downwardly 12 relative to the center display level; and it is not until field 13 interval V5 at this DC level of the vertical deflection current 14 is restored to its center level. This restoration of the DC
current results in an upward shift in the video picture. Thus, 16 the combination of the negative and positive shifts in the DC
17 level of the deflection current may be perceived as a vertical 18 perturbation in the video picture. The peak-to-peak amplitude of 19 the vertical deflection current during enlarged field intervals is seen to be A2.
21 Let it be assumed that field interval Vr is reduced.
22 Thus, as shown in FIG. 24A, the vertical retrace signal is 23 generated at an earlier than expected time, resulting in a 24 positive shift of the average DC deflection current. During ~0;~29~2 PATENT

1 field intervals V8 and V9, the DC level of the deflection current 2 tends to return to its center picture level which is reached at 3 field interval V10. It is appreciated that the upward shift in 4 the DC level of the deflection current followed by its downward shift results in a vertical "jump" or perturbation in the 6 displayed video picture.
7 FIG. 24B illustrates the manner in which this shifting 8 in the DC level of the vertical deflection current is minimized.
9 As discussed above, and as shown in FIG. 22H, when the field lo interval of the video signal provided at the video output of 11 combining circuit 22 is enlarged, as during field interval V4, 12 the time of occurrence of the ~irst vertical pulse included in 13 the vertical period of the vertical synchronizing interval is 14 advanced. By advancing this time of occurrence, the lowermost level of the deflection current at the end of field interval V3, 16 as shown in FIG.-24A, is not reached. Nevertheless, the vertical 17 retrace signal is of the same peak-to-peak level, thus returning 18 the electron beam to a position higher than that shown at the 19 beginning of field interval V4 in FIG. 24A. Therefore, as seen in FIG. 7B, although a reduced negative shift in the DC level of 21 the vertical deflection current occurs during field interval V3, 22 the DC level is returned to its center picture level in field 23 interval V4. Therefore, any perturbation in the video picture is 24 reduced, is abrupt and is generally unnoticeable.

'~03Z922 PATENT

1 Similarly, when the fiQld interval of the video signal 2 is reduced, as represented by field interval V~, the time of 3 occurrence of the first vertical pulse included in the vertical 4 period of the vertical synchronizing interval is delayed, as shown in FIG. 23H. Consequently, the vertical deflection current 6 flows through the deflection circuitry for a greater period of 7 time during the interval V7, as may be seen by comparing FIG. 24B
8 with FIG. 24A, and the electron beam is returned at the beginning 9 of field interval V8 to a position relatively lower in the video display than that to which the electron beam would be returned if 11 the first vertical pulse is not delayed. Here too, the shift in 12 the DC level o~ the vertical deflection current is substantially 13 reduced, thus reducing any perturbation in the displayed video 14 picture and rendering it substantially unnoticeable.
Thus, by advancing the time of occurrence of the 16 vertical period included in the vertical synchronizing interval 17 when the field interval of the video signal is increased, the 18 amount of overshoot in the vertical deflection current, as shown 19 at the end of field interval V3 in FIG. 24A, is reduced.
Conversely, by delaying the onset of the vertical period included 21 in the vertical synchronizing interval when the field interval is 22 decreasing, the amount of undershoot in the vertical deflection 23 current, as shown at field interval V7 of FIG. 24A, also is 24 reduced. It has been found that a shift on the order of one-~0329~;2 PATENT

1 third of a horizontal line interval to advance or delay the time 2 of occurrence of the vertical period produces no noticeable 3 degradation of the displayed video picture, yet substantially 4 eliminates, or at least minimizes, vertical perturbations.
While the present invention has been particularly shown 6 and described with reference to a preferred embodiment, it will 7 be readily appreciated by those of ordinary skill in the art that 8 various changes and modifications may be made without departing g from the spirit and scope of the invention. For example, those vertical and post-equalizing pulses which are deleted need not be 11 limited solely to the particular pulses which have been described 12 above. For instance, those post-equalizing pulses which are 13 produced at the beginning of line intervals may be deleted rather 14 than those which occur at the midpoint. Similarly, the last vertical pulse included in the vertical period for both odd and 16 even fields may be deleted, rather than deleting only the last 17 vertical pulse which is produced at the midpoint of a line 18 interval. Still further, any other vertical pulse may be deleted 19 from the vertical period.
In addition, it should be pointed out that the profile 21 patterns illustrated in FIGS. 2A and 2B need not be repeated 22 continuously and, in a preferred embodiment after one full cycle 23 of a selected profile pattern is completed, the next profile 24 pattern which may be selected from library 118 (FIG. 1) need not PATENT

1 be initiated immediately. Improved performance has been 2 observed, particularly in preventing digital vertical 3 synchronizing circuits of television receivers from locking onto 4 a standard (525 line) frame length, when a substantial delay is provided between successive profile patterns, such as on the 6 order of hundreds of frame periods, and the length of each video 7 frame during this delay period is, for example, 523 lines.
8 It is intended that the appended claims be interpreted g as covering the embodiment described herein, the foregoing changes and all other equivalents thereto.

Claims (58)

WHAT IS CLAIMED IS:

1. A method of preventing counting circuitry included in the vertical synchronizing circuit of a video receiver from generating vertical control signals at a fixed, standard rate when a video signal transmitted to said video receiver exhibits a changing field interval which varies above and below a fixed, standard period, said method comprising the steps of deleting at least one of the vertical pulses in the vertical period of each field interval of said transmitted video signal; and deleting plural equalizing pulses in the post equalizing period following said vertical pulses in said field interval.

2. The method of Claim 1 wherein the step of deleting at least one of the vertical pulses in the vertical period comprises deleting a vertical pulse that commences at substantially the midpoint of a line interval included in said vertical period.

3. The method of Claim 2 wherein the deleted vertical pulse is the last vertical pulse that commences at substantially the midpoint of a line interval.

4. The method of Claim 3 wherein the deleted vertical pulse is the last vertical pulse in each FIELD I interval and is the penultimate vertical pulse in each FIELD II interval.

5. The method of Claim 1 wherein the step of deleting plural equalizing pulses comprises deleting a selected number of those equalizing pulses in the post equalizing period following said vertical pulses and commencing at substantially the midpoint of a line interval in said post equalizing period.

6. The method of Claim 5 wherein the selected number of equalizing pulses that are deleted comprises all of the equalizing pulses that commence at substantially the midpoints of line intervals in said post equalizing period.

7. The method of Claim 1 further comprising the step of identifying the last line interval in the changing vertical period of the transmitted video signal, and detecting the vertical period in the next-following field interval of said transmitted video signal, whereby the vertical and equalizing pulses to be deleted are determined.

8. The method of Claim 7 wherein the step of determining the vertical and equalizing pulses to be deleted comprises counting line intervals in said next-following field interval, and deleting selected vertical and equalizing pulses in pre-determined line intervals.

9. The method of Claim 1 further comprising the step of shifting the time of occurrence of the first vertical pulse in the vertical period of selected field intervals.

10. The method of Claim 9 wherein the step of shifting the time of occurrence of the first vertical pulse comprises advan-cing the time of occurrence of said first vertical pulse.

when the field interval of the transmitted video signal is increased and delaying the time of occurrence of said first vertical pulse when the field interval of the transmitted video signal is decreased.

11. The method of Claim 9 wherein the shift of the time of occurrence of the first vertical pulse is on the order of about one-third of a horizontal line interval.

12. A method of controlling vertical and equalizing pulses in the vertical synchronizing interval of a video signal transmitted with a changing frame period which varies above and below a fixed standard period to enable a video picture to be displayed therefrom on a conventional television receiver but prevent that video signal from being copied on a conventional video recorder, said method comprising the steps of generating less than a standard number of vertical pulses in each vertical period of the vertical synchronizing interval; selectively shifting the beginning of selected vertical periods; generating less than a standard number of post equalizing pulses in each vertical synchronizing interval; and combining the video signal with the generated vertical and post equalizing pulses, whereby a vertical synchronizing circuit of a television receiver is inhibited from locking onto the vertical synchronizing interval of said video signal and thereby generate vertical control signals at said fixed, standard period, and whereby perturbations in the displayed video picture attributed to a change in the frame period of the video signal are minimized.

13. The method of Claim 12 wherein the step of generating less than a standard number of vertical pulses comprises generating a series of vertical pulses, and inhibiting at least one of the vertical pulses in said series.

14. The method of Claim 13 wherein the vertical pulses in said series are generated at the beginning and at the midpoint of predetermined line intervals, and said step of inhibiting comprises inhibiting the last midpoint-generated vertical pulse in said series.

15. The method of Claim 12 wherein the step of generating less than a standard number of post equalizing pulses comprises generating a series of post equalizing pulses, and inhibiting selected post equalizing pulses in said series.

16. The method of Claim 15 wherein the post equalizing pulses in said series are generated at the beginning and at the midpoint of predetermined line intervals, and said step of inhibiting comprises inhibiting the midpoint-generated post equalizing pulses in said series.

17. The method of Claim 12 wherein the step of selectively shifting the beginning of selected vertical periods comprises shifting the time of occurrence of the first vertical pulse in selected vertical periods.

18. The method of Claim 17 wherein said selected vertical periods comprise the vertical periods in FIELD II
intervals of the video signal.

19. The method of Claim 17 wherein the time of occurrence of the first vertical pulse is shifted by no more than half a line interval.

20. The method of Claim 17 wherein the step of shifting the time of occurrence of the first vertical pulse comprises advancing said time of occurrence when the frame period of the video signal increases and delaying said time of occurrence when the frame period of said video signal decreases.

21. The method of Claim 20 wherein said first vertical pulse is produced by generating a start vertical pulse at a predetermined location in said vertical synchronizing interval, commencing the count of clock pulses in response to said start vertical pulse, and generating a vertical pulse commencing with said start vertical pulse and ending when said count reaches a predetermined count.

22. The method of Claim 21 wherein said first vertical pulse is advanced by advancing the location in the vertical synchronizing interval at which said start vertical pulse is generated, and said first vertical pulse is delayed by delaying the location in the vertical synchronizing interval at which said start vertical pulse is generated.

23. The method of Claim 22 wherein said steps of advancing and delaying the location in the vertical synchronizing interval at which said start vertical pulse is generated comprises generating advanced and delayed start pulses at respective, predetermined locations in said vertical synchronizing interval and selecting said advanced or delayed start pulse from which the start vertical pulse commences.

24. A method of generating pre-equalizing, post-equalizing and vertical pulses for insertion into the vertical synchronizing interval of a video signal, comprising the steps of counting horizontal line intervals in each field of the video signal; generating start equalizing representations representing the start of respective pre-equalizing and post-equalizing pulses at predetermined line counts and omitting selected ones of the start equalizing representations at preselected line counts;
generating start vertical representations representing the start of respective vertical pulses at other predetermined line counts and omitting selected ones of the start vertical representations at preselected ones of said other line counts; counting clock signals in response to each start equalizing representation and each start vertical representation to produce clock counts;
sensing when the clock count reaches a first count following a start equalizing representation and a second count following a start vertical representation; generating equalizing pulses of durations determined by said first count; and generating vertical pulses of durations determined by said second count, whereby equalizing and vertical pulses are not generated when start equalizing and start vertical representations are omitted.

25. The method of Claim 24 wherein the step of generating start equalizing representations comprises generating a start equalizing representation at the beginning and at the midpoint of those horizontal line intervals corresponding to said predetermined line counts; and the step of omitting selected start egualizing representations comprises omitting the start equalizing representations at the midpoint of the line intervals corresponding to at least some post-equalizing line counts.

26. The method of Claim 24 wherein the step of generating start vertical representations comprises generating a start vertical representation at the beginning and at the midpoint of those horizontal line intervals corresponding to said other predetermined line counts; and the step of omitting selected start vertical representations comprises omitting the start vertical representation at the midpoint of the line interval corresponding to at least one of said other predetermined counts.

27. The method of Claim 26 wherein the video signal exhibits a changing frame period which varies above and below a fixed standard period, and wherein the step of generating a start vertical representation at the beginning and at the midpoint of horizontal line intervals further comprises advancing the location of the first start vertical representation when the frame period increases and delaying the location of the first start vertical representation when the frame period decreases.

28. The method of Claim 27 wherein the first start vertical representation is respectively advanced or delayed on the order of about one-third the duration of a horizontal line interval.

29. The method of Claim 28 further comprising the steps of sensing when the clock count reaches a third count following an advanced first start vertical representation;
sensing when the clock count reaches a fourth count following a delayed first start vertical representation; and generating a first vertical pulse of duration determined by the third or fourth count.

30. Apparatus for preventing counting circuitry included in the vertical synchronizing circuit of a video receiver from generating vertical control signals at a fixed, standard rate when a video signal transmitted to said video receiver exhibits a changing field interval which varies above and below a fixed, standard period, said apparatus comprising synchronizing signal generating means for controlling the synchronizing signals included in the transmitted video signal, including vertical pulse control means for deleting at least one of the vertical pulses in the vertical period of each field interval of said transmitted video signal; and equalizing pulse control means for deleting plural equalizing pulses in the post equalizing period following said vertical pulses in said field interval.

31. The apparatus of Claim 30 wherein said vertical pulse control means comprises means for deleting a vertical pulse that commences at substantially the midpoint of a line interval included in said vertical period.

32. The apparatus of Claim 31 wherein said means for deleting deletes the last vertical pulse that commences at substantially the midpoint of a line interval.

33. The apparatus of Claim 32 wherein the deleted vertical pulse is the last vertical pulse in each FIELD I
interval and is the penultimate vertical pulse in each FIELD II
interval.

34. The apparatus of Claim 30 wherein said equalizing pulse control means comprises means for deleting a selected number of those equalizing pulses in the post equalizing period following said vertical pulses and commencing at substantially the midpoint of a line interval in said post equalizing period.

35. The apparatus of Claim 34 wherein the last-mentioned means for deleting deletes all of the equalizing pulses that commence at substantially the midpoints of line intervals in said post equalizing period.

36. The apparatus of Claim 30 wherein the synchronizing signal generating means further includes line identifying means for identifying the last line interval in the changing vertical period of the transmitted video signal, and means responsive to said last line interval for detecting the vertical period in the next-following field interval of said transmitted video signal to determine the vertical and equalizing pulses to be deleted.

37. The apparatus of Claim 36 wherein the means to determine the vertical and equalizing pulses to be deleted comprises line counting means for counting line intervals in said next-following field interval, and means for deleting selected vertical and equalizing pulses at predetermined line counts.

38. The apparatus of Claim 30 wherein the synchronizing signal generating means further includes shift means for shifting the time of occurrence of the first vertical pulse in the vertical period of selected field intervals.

39. The apparatus of Claim 38 wherein the shift means comprises advance means for advancing the time of occurrence of said first vertical pulse when the field interval of the transmitted video signal is increased and delay means for delaying the time of occurrence of said first vertical pulse when the field interval of the transmitted video signal is decreased.

40. The apparatus of Claim 38 wherein the shift of the time of occurrence of the first vertical pulse is on the order of about one-third of a horizontal line interval.

41. Apparatus for generating vertical and equalizing pulses inserted into the vertical synchronizing interval of a video signal transmitted with a changing frame period which varies above and below a fixed standard period to enable a video picture to be displayed therefrom on a conventional television receiver but prevent that video signal from being copied on a conventional video recorder, said apparatus comprising vertical pulse generating means for generating less than a standard number of vertical pulses in each vertical period of the vertical synchronizing interval; shift means for selectively shifting the beginning of selected vertical periods; equalizing pulse generating means for generating less than a standard number of post equalizing pulses in each vertical synchronizing interval;
and combining means for combining the video signal with the generated vertical and post equalizing pulses, whereby a vertical synchronizing circuit of a television receiver is inhibited from locking onto the vertical synchronizing interval of said video signal and thereby generate vertical control signals at said fixed, standard period, and whereby perturbations in the displayed video picture attributed to a change in the frame period of the video signal are minimized.

42. The method of Claim 41 wherein the vertical pulse generating means comprises means for generating a series of vertical pulses, and inhibit means for inhibiting at least one of the vertical pulses in said series.

43. The apparatus of Claim 42 wherein the vertical pulses in said series are generated at the beginning and at the midpoint of predetermined line intervals, and said inhibiting means comprises means for inhibiting the last midpoint-generated vertical pulse in said series.

44. The apparatus of Claim 41 wherein the equalizing pulse generating means comprises means for generating a series of post equalizing pulses, and inhibit means for inhibiting selected post equalizing pulses in said series.

45. The apparatus of Claim 44 wherein the post equalizing pulses in said series are generated at the beginning and at the midpoint of predetermined line intervals, and said inhibit means comprises means for inhibiting the midpoint-generated post egualizing pulses in said series.

46. The apparatus of Claim 41 wherein the shift means comprises means for shifting the time of occurrence of the first vertical pulse in selected vertical periods.

47. The apparatus of Claim 46 wherein said selected vertical periods comprise the vertical periods in FIELD II
intervals of the video signal.

48. The method of Claim 46 wherein the means for shifting shifts the time of occurrence of the first vertical pulse by no more than half a line interval.

49. The apparatus of Claim 46 wherein the means for shifting the time of occurrence of the first vertical pulse comprises advance means for advancing said time of occurrence when the frame period of the video signal increases and delay means for delaying said time of occurrence when the frame period of said video signal decreases.

50. The apparatus of Claim 49 wherein said vertical pulse generating means comprises means for generating a start vertical pulse at a predetermined location in said vertical synchronizing interval; a source of clock pulses; count means for commencing the count of said clock pulses in response to said start vertical pulse; means for sensing when the clock pulse count reaches a predetermined count; and means for generating a vertical pulse commencing with said start vertical pulse and ending when said predetermined count is reached.

51. The apparatus of Claim 50 wherein said advance means comprises means for advancing the location in the vertical synchronizing interval at which said start vertical pulse is generated, and said delay means comprises means for delaying the location in the vertical synchronizing interval at which said start vertical pulse is generated.

52. Apparatus for generating pre-equalizing, post-equalizing and vertical pulses for insertion into the vertical synchronizing interval of a video signal, comprising line count means for counting horizontal line intervals in each field of the video signal; start equalizing means for generating start equalizing representations representing the start of respective pre-equalizing and post-equalizing pulses at predetermined line counts and for omitting selected ones of the start equalizing representations at preselected line counts; start vertical means for generating start vertical representations representing the start of respective vertical pulses at other predetermined line counts and for omitting selected ones of the start vertical representations at preselected ones of said other line counts; a source of clock signals; clock counting means for counting clock signals in response to each start equalizing representation and each start vertical representation to produce clock counts;
sense means for sensing when the clock count reaches a first count following a start equalizing representation and a second count following a start vertical representation; equalizing pulse generating means for generating equalizing pulses of durations determined by said first count; and vertical pulse generating means for generating vertical pulses of durations determined by said second count, whereby equalizing and vertical pulses are not generated when start equalizing and start vertical representations are omitted.

53. The apparatus of Claim 52 wherein said start equalizing means comprises means for generating a start equalizing representation at the beginning and at the midpoint of those horizontal line intervals corresponding to said predetermined line counts and means for omitting the start equalizing representations at the midpoint of the line intervals corresponding to at least some post-equalizing line counts.

54. The apparatus of Claim 52 wherein said start vertical means comprises means for generating a start vertical representation at the beginning and at the midpoint of those horizontal line intervals corresponding to said other predetermined line counts and means for omitting the start vertical representation at the midpoint of the line interval corresponding to at least one of said other predetermined counts.

55. The apparatus of Claim 54 wherein the video signal exhibits a changing frame period which varies above and below a fixed standard period, and wherein said start vertical means further comprises means for advancing the location of the first start vertical representation when the frame period increases and means for delaying the location of the first start vertical representation when the frame period decreases.

56. The apparatus of Claim 55 wherein the first start vertical representation is respectively advanced or delayed on the order of about one-third the duration of a horizontal line interval.

57. The apparatus of Claim 56 wherein said sense means further comprises means for sensing when the clock count reaches a third count following an advanced first start vertical representation and a fourth count following a delayed first start vertical representation; and wherein said vertical pulse generating means includes means for generating a first vertical pulse of duration determined by the third or fourth count.

58. Apparatus for preventing counting circuitry included in the vertical synchronizing circuit of a video receiver from generating vertical control signals at a fixed, standard rate when a video signal transmitted to said video receiver exhibits a changing field interval which varies above and below a fixed, standard period, said apparatus comprising profile generating means for generating a profile representing the characteristics of said changing field interval, including the rate at which said field interval changes and the maximum and minimum periods of said field interval; control means for varying said field interval in accordance with said profile such that said field interval is equal to said standard period for no more than a limited number of successive field intervals; and means for transmitting the varying field interval.