CA2015392A1 - Scrambler with self calibration - Google Patents
Scrambler with self calibrationInfo
- Publication number
- CA2015392A1 CA2015392A1 CA002015392A CA2015392A CA2015392A1 CA 2015392 A1 CA2015392 A1 CA 2015392A1 CA 002015392 A CA002015392 A CA 002015392A CA 2015392 A CA2015392 A CA 2015392A CA 2015392 A1 CA2015392 A1 CA 2015392A1
- Authority
- CA
- Canada
- Prior art keywords
- signal
- scrambler
- signals
- inverted
- video
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/16—Analogue secrecy systems; Analogue subscription systems
- H04N7/167—Systems rendering the television signal unintelligible and subsequently intelligible
- H04N7/171—Systems operating in the amplitude domain of the television signal
- H04N7/1713—Systems operating in the amplitude domain of the television signal by modifying synchronisation signals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/16—Analogue secrecy systems; Analogue subscription systems
- H04N7/167—Systems rendering the television signal unintelligible and subsequently intelligible
- H04N7/171—Systems operating in the amplitude domain of the television signal
- H04N7/1716—Systems operating in the amplitude domain of the television signal by inverting the polarity of active picture signal portions
Abstract
AN IMPROVED SCRAMBLER WITH SELF CALIBRATION
ABSTRACT OF THE DISCLOSURE
The invention is directed to an improved scrambler capable of self-calibrating output signals. In one embodiment, the scrambler provides an encoded signal along separate signal pulses. A portion of one signal is made to correspond to a portion of another signal to thereby self-calibrate the signals. Also, portions of the incoming video signal are forced to cor-respond with internally generated voltage level signals.
ABSTRACT OF THE DISCLOSURE
The invention is directed to an improved scrambler capable of self-calibrating output signals. In one embodiment, the scrambler provides an encoded signal along separate signal pulses. A portion of one signal is made to correspond to a portion of another signal to thereby self-calibrate the signals. Also, portions of the incoming video signal are forced to cor-respond with internally generated voltage level signals.
Description
~13 AN IMPROVED SCRAMBLEP~ WITH SELF CALIBRATION
R~LATED APPLICATIONS
This applicatlon Is related to commonly owne~ copending app~-cation Serial No. l88,480, filed April 29, 1988 which is hereby Inco~
porated in Its entirety by this re~erence thereto~
BACKGROUNDQF T~E INVENl'ION
This invention relates generally to an improved scrambllng apparatus or en~oder ~or self calibra~ing a selectlvely scrambled or encoded video slgnal. Currently, several techniques are known tor scrambling a video signal. These tPchniques include, but are not lim-ited to, selective inversion o~ at least a portion o the vi~eo signal, selective syochronization (sync) suppresslon and/or generation o~ spl~t sync pulses. Typlcally, th~ syn~ pulse comprises a single pulse between the front and back porch charactelized by a single voltage level ~or substantially the entire sync interv~. A split sync pulse generally r~Iers to a sync lnterval comprising two or more pulses, i.e"
two or more voltage levels between the front and back porch. The desirability o2 providing split sync pulses and the advantages derived thereîrom are ~ully describ~ in the above re~erenced copending application. For purposes ot ~llustration, an exampl~ Or a video signal havlng a split sync pulse is shown In Flgure l. It is to be understQod 3 9 ~
that many other embocllments ot a split sync signal will be readlly apparent to one o~ ordinary sklll ln the art.
As shown ~n Figure 1, the horizontal sync Interval o~ the video sigs~al comprises two signal portlons. The tirst portion is prererably a pulse having a level at substantially -40 IRE corresponding to the sync tip level. The second portion of the sync interval preterably com-prlses a pulse having a level of substantially ~lOû IRE corresponding to the peak whlte level of the signal. Many other formats ~or spllt sync pulses are described in the referenced copending application and it is to be understood that split sync pulses may ~e used with sel~c-tively inverted vid~ or non-inverted video signaL~ and the spllt sync pulses may themselves ~e selectively inverted or non-inverted.
As more ~uLly described in the referenced application, a signal transmltted with such a spllt sync signal has many advantages. For example, if it Is de~ired to scramble the signal by inverting the video portion of the signal, the signal mu~t be reinverted at the rec iver and significantly, thls inversion and reinverslon mu~t occur around the same a~s of inversion in both the transmitter (scram~ler) and receiver ~descrambler). Il it is desired to establish an a~s of inver-sion substantially mldway between the peak white level (e.g., +100 IRE) and the sync tip level (e.g.~ -40 IRE), it will be apparent that the axl~ o~ inversion should be +30 IRE. This axis o~ inversion can be cal-culated In the receiver by averaging the peak level and sync tip level.
One way ot selectively inverting signals or portions thereot is to pr~
du~e substantially parallel signal paths in a scrambler comprislng, e.g., a non-inverted signal path and an inverted signal path. Since 20~3~2 there will ~e dilferent ~omponen~s in the dif~erent signal paths which may introduce an of ~set of the signal in one path with respect to the signal in another path, it is important to ensure that the selected pu~se levels o~ both the inverted and non-inverted signals produced in the scrambler are accurately calibrated, i.e., at least a portion o~ one of the signals substantially corresponds to at least a portion Or another of the signals. Plural paths may be used in other scrambling applieations as well. For example, they may be used to provide var~-ous levels of sync suppression.
In the pa~t, scramblers were manufactured and subsequently calibrated in the tactory using external calibration instrumen~s known to those o~ ordinary skill 11~ the art. This calibration was necessary to ensure that corresponding portions of the signals in each o~ the signal paths occurred at desired levels, e.g., in the case of split sync pulses it may be desired to have the low sync tip and high sync tip leveLs correspond to -40 IRE and +100 IRE levels respectively. This c~ibra-tion step adds additional ex~nse and time to the manufacture o~
scramblers which Is obviously undesirable. To carry out th~s external calibration, the video signal in a non-inverted signal path might ~e sampled and compared to a video signal ~rom an inverted path and any ditference between a predetermined portion of the signals woul~
be corrected.
As wlll be explalned more fully below, the present lnvention re~es on sel~-callbration. Self-callbratior3 is dlstinguished from exter-nal calibratlon in that sel~-callbration is pertormed by circuitry within the scrambler itsel~ and automatically ad~usts at least a ~J'~
portion o~ one signal to correspond to a portlsn o~ another signal without the use of external calibration equipment.
As described in the cross-referenced application, video slgnals comprislng a split sync pulse may be generated by using Internally generated voltage levels that are multiplexed with a standard video signal to replace the normally occurring sync signal with an Internally generated split sync signal. According to a preferred embodiment or the copending application, the spllt sync signal mag comprise a puse corresponding to the sync tip level (-40 IRE~. It is a~so disclosed that it is desirable to perform the ~unctions o~ D.C. clamplag and aut~
matic gain control (ACC). It is preferr~d that the sync tip level b~3 clamped to the -40 IRE voltage level and then the gain be ad~usted so that the back porch level corresponds to the O IRE level. It clamping and gain control do not occur prior to insertlon of internally gener-ated split sync pu~ses, errors can occur if, e.gc the clamped sync tip level is not substantially the same as the internally generated low sync tip leYel portion o~ the sync pulse.
SUM~ARY OF TH~ INVEN~ON
In order to overcome these and other drawbacks o~ prior ar~
seramblers, it is an o~ect o~ the present lnvention to provide a seU-calibrating scrambler which avoids the need for ~actory calibration.
It is another obJect o~ this invention to provide ~ncoded and non-encoded signals along plural paths, s~lectively output one oi the signals and seU-calibrate the signals along the plural paths.
R~LATED APPLICATIONS
This applicatlon Is related to commonly owne~ copending app~-cation Serial No. l88,480, filed April 29, 1988 which is hereby Inco~
porated in Its entirety by this re~erence thereto~
BACKGROUNDQF T~E INVENl'ION
This invention relates generally to an improved scrambllng apparatus or en~oder ~or self calibra~ing a selectlvely scrambled or encoded video slgnal. Currently, several techniques are known tor scrambling a video signal. These tPchniques include, but are not lim-ited to, selective inversion o~ at least a portion o the vi~eo signal, selective syochronization (sync) suppresslon and/or generation o~ spl~t sync pulses. Typlcally, th~ syn~ pulse comprises a single pulse between the front and back porch charactelized by a single voltage level ~or substantially the entire sync interv~. A split sync pulse generally r~Iers to a sync lnterval comprising two or more pulses, i.e"
two or more voltage levels between the front and back porch. The desirability o2 providing split sync pulses and the advantages derived thereîrom are ~ully describ~ in the above re~erenced copending application. For purposes ot ~llustration, an exampl~ Or a video signal havlng a split sync pulse is shown In Flgure l. It is to be understQod 3 9 ~
that many other embocllments ot a split sync signal will be readlly apparent to one o~ ordinary sklll ln the art.
As shown ~n Figure 1, the horizontal sync Interval o~ the video sigs~al comprises two signal portlons. The tirst portion is prererably a pulse having a level at substantially -40 IRE corresponding to the sync tip level. The second portion of the sync interval preterably com-prlses a pulse having a level of substantially ~lOû IRE corresponding to the peak whlte level of the signal. Many other formats ~or spllt sync pulses are described in the referenced copending application and it is to be understood that split sync pulses may ~e used with sel~c-tively inverted vid~ or non-inverted video signaL~ and the spllt sync pulses may themselves ~e selectively inverted or non-inverted.
As more ~uLly described in the referenced application, a signal transmltted with such a spllt sync signal has many advantages. For example, if it Is de~ired to scramble the signal by inverting the video portion of the signal, the signal mu~t be reinverted at the rec iver and significantly, thls inversion and reinverslon mu~t occur around the same a~s of inversion in both the transmitter (scram~ler) and receiver ~descrambler). Il it is desired to establish an a~s of inver-sion substantially mldway between the peak white level (e.g., +100 IRE) and the sync tip level (e.g.~ -40 IRE), it will be apparent that the axl~ o~ inversion should be +30 IRE. This axis o~ inversion can be cal-culated In the receiver by averaging the peak level and sync tip level.
One way ot selectively inverting signals or portions thereot is to pr~
du~e substantially parallel signal paths in a scrambler comprislng, e.g., a non-inverted signal path and an inverted signal path. Since 20~3~2 there will ~e dilferent ~omponen~s in the dif~erent signal paths which may introduce an of ~set of the signal in one path with respect to the signal in another path, it is important to ensure that the selected pu~se levels o~ both the inverted and non-inverted signals produced in the scrambler are accurately calibrated, i.e., at least a portion o~ one of the signals substantially corresponds to at least a portion Or another of the signals. Plural paths may be used in other scrambling applieations as well. For example, they may be used to provide var~-ous levels of sync suppression.
In the pa~t, scramblers were manufactured and subsequently calibrated in the tactory using external calibration instrumen~s known to those o~ ordinary skill 11~ the art. This calibration was necessary to ensure that corresponding portions of the signals in each o~ the signal paths occurred at desired levels, e.g., in the case of split sync pulses it may be desired to have the low sync tip and high sync tip leveLs correspond to -40 IRE and +100 IRE levels respectively. This c~ibra-tion step adds additional ex~nse and time to the manufacture o~
scramblers which Is obviously undesirable. To carry out th~s external calibration, the video signal in a non-inverted signal path might ~e sampled and compared to a video signal ~rom an inverted path and any ditference between a predetermined portion of the signals woul~
be corrected.
As wlll be explalned more fully below, the present lnvention re~es on sel~-callbration. Self-callbratior3 is dlstinguished from exter-nal calibratlon in that sel~-callbration is pertormed by circuitry within the scrambler itsel~ and automatically ad~usts at least a ~J'~
portion o~ one signal to correspond to a portlsn o~ another signal without the use of external calibration equipment.
As described in the cross-referenced application, video slgnals comprislng a split sync pulse may be generated by using Internally generated voltage levels that are multiplexed with a standard video signal to replace the normally occurring sync signal with an Internally generated split sync signal. According to a preferred embodiment or the copending application, the spllt sync signal mag comprise a puse corresponding to the sync tip level (-40 IRE~. It is a~so disclosed that it is desirable to perform the ~unctions o~ D.C. clamplag and aut~
matic gain control (ACC). It is preferr~d that the sync tip level b~3 clamped to the -40 IRE voltage level and then the gain be ad~usted so that the back porch level corresponds to the O IRE level. It clamping and gain control do not occur prior to insertlon of internally gener-ated split sync pu~ses, errors can occur if, e.gc the clamped sync tip level is not substantially the same as the internally generated low sync tip leYel portion o~ the sync pulse.
SUM~ARY OF TH~ INVEN~ON
In order to overcome these and other drawbacks o~ prior ar~
seramblers, it is an o~ect o~ the present lnvention to provide a seU-calibrating scrambler which avoids the need for ~actory calibration.
It is another obJect o~ this invention to provide ~ncoded and non-encoded signals along plural paths, s~lectively output one oi the signals and seU-calibrate the signals along the plural paths.
2~ 3~
More specl~lcally, lt is an ob~ect ot this invention to obviate the need for tactory calibratlon o~ scramblers that are used tor pro-duclng vldeo slgnals with split sync pulses.
It ls a rurther ob~ect o~ this Invention to provide an Improved scrambler for use In produclng video signals w1th spllt sync pulses that may be scrambled by a variety of known scrambling techniques.
It is a ~urther ob~ect of this inventlon to provide a more ef~
cient scrambler.
It is a turther ob,~ect oS this invention to provide a scrambler that may ~e produced more economically.
It is a further ob~ect of this invention to minimize signal errors in a scrambler capable o~ generating split sync pu~ses.
It is a further ob~ect o~ this Invention to minimize discrepancy between clamped signal levels of signa~ portions and corresponding Internally generated slgnal portiors that are ir~ierted into a scrambled video signal.
Generally speaking, one asp~t ot the present Invention relates to self calibrating a scrambler wherein, e.g., plural signal paths are used to generate various types of signals. For example, if selective inversion of a part of a video signal is desired, there may be a non-inverted signal path and an inverted signal path. The ssll cali-bration re~erred to i~ the proce~s whereby at least a portion ~ a slg-nal rrom one ~ the plural paths is made to correspond with a ~orr~
sponding portion o~ a signal from another of th~ plural paths. For example, the sync tip level o~ a first slgnal on a firs~ path may be made equal to the sync tip level of a second signal on a second path.
More specl~lcally, lt is an ob~ect ot this invention to obviate the need for tactory calibratlon o~ scramblers that are used tor pro-duclng vldeo slgnals with split sync pulses.
It ls a rurther ob~ect o~ this Invention to provide an Improved scrambler for use In produclng video signals w1th spllt sync pulses that may be scrambled by a variety of known scrambling techniques.
It is a ~urther ob~ect of this inventlon to provide a more ef~
cient scrambler.
It is a turther ob,~ect oS this invention to provide a scrambler that may ~e produced more economically.
It is a further ob~ect of this invention to minimize signal errors in a scrambler capable o~ generating split sync pu~ses.
It is a further ob~ect o~ this Invention to minimize discrepancy between clamped signal levels of signa~ portions and corresponding Internally generated slgnal portiors that are ir~ierted into a scrambled video signal.
Generally speaking, one asp~t ot the present Invention relates to self calibrating a scrambler wherein, e.g., plural signal paths are used to generate various types of signals. For example, if selective inversion of a part of a video signal is desired, there may be a non-inverted signal path and an inverted signal path. The ssll cali-bration re~erred to i~ the proce~s whereby at least a portion ~ a slg-nal rrom one ~ the plural paths is made to correspond with a ~orr~
sponding portion o~ a signal from another of th~ plural paths. For example, the sync tip level o~ a first slgnal on a firs~ path may be made equal to the sync tip level of a second signal on a second path.
3 ~ ~
Additionally, the gain ot a rirst signal may be made equal tO the gain ot a second signal to s~ calibrate the slgna~s.
This sell calibration may be Implemented in a number of ways whlch may Include comparing corresponding slgnal portions and using a feedback signal to make one signal correspond to the other signal, clamplng a portion o~ a signal to a corresponding portion of another signal, clamping signals ~rom two separate paths to the same re~e~
ence level and other techniques that will be readily apparent to one o~ ordinary skill in the 'art.
According to another ~eature of the invention, an incomlng video signal may be clamped and gain controlled based on InternaLly generated levels, which levels are also used to generate scrambled video signals including split sync signals.
BRn~F DESCRIP~ON OF THE DR~WINGS
Figure 1 ~s a diagrammatic representation o~ a video signal having a split sync slgnal.
Figures 2 and 3 are a block diagram of a scrambler according to a pre~erred embodiment o~ the present invention.
Figures 4 and 5 are block diagrams o~ the High and Low syn~
comparators of the present invention.
Flgures 6, 7 and 8 are a schematic representation o~ the scram-bler according to a pre~rred embodiment o~ the present invention.
Figure 9 is a timing diagram illustratlng varisus timin~ signals that con~r~l portions o~ the circuits o~ Figs. S-8.
~ lgure 10 a diagrammatlc representation o a noninverted and inverted video signal including spllt sync pu~;es.
Flgures 11 and 12 are block diagrams illustrating alternative ways ol sel~-calibrating signals on plural signal paths according to the teachings of the present lnvention.
Figure 13 is an alternative voltage divider clrcult.
Figures 14 and 15 show alternative sel~-calibration circuitry.
DETAILED DESC~IPTION OF THE P~EFER~EI~ EMBODD~l~NT
The present inventlon is not limited to the partlcular ~mbo~-ments that wlU be described below. Rather, one aspect oi the inven-tion is broadly detined as self-calibrating si~nals on plural signals paths ot a scrambler. This technlque may be implemented ln a num-ber o~ ways and may be used with various ty~es Or scrambling (encod ing) techniques. For example, the plural si~nal paths could generate inverted/non-lnverted signal5; suppressecl/non~uppressed signals or various levels ot suppression; or broadly speaking encoded/
non-encoded signals.
For the sake o~ clarity, all of these permutations wlll not ~e discussed herein. However, the preferred embodin ent Or using sele~
tive inversion/non-lnversion o~ a signal having split sync pulses will be discussed. It wlll be readily apparent to one of ordinary sklll ln the art, ~rom a description ot the preferred embodiment, how to impl~
ment the various other permutations of the present lnvention.
Figure 2 ls a block diagram o~ a scrambler according $o the present Invention. The encircl~d numbers in Fig. 2 indicate varlous nodes of the cireu~t to aid the reader in understanding this em~di-ment. At node 1, a standard NTSC video signal is input to a scram-bler. This signal may be passed through the appropriate signal - 8 - ~ 9 ~
condItloning clrcuits and is applled at node 2 to an input ot an opera-tional ampll~ler 21. A portion or the output ot oFerational amplltler is provided along a feedback path 22 and is ~ed back to an input o~ the operational amp~fier 21. The output or the operational amplifier is indicated by node 3. Another portion o~ the output of operational amplifier 21 is provided along feedback path 23 to a DC clamp circuit 24. This DC clamp circuit locks the sync tip level to 0 volts. The DC
clamp circuit 24 also receives as inputs, a 0 volt signal and a control signal designated as "A-40" which corresponds to a clamp enable sig-nal. The output ot the DC clamp is provided along path 25 to an input o~ operational ampli~ier 21. Another portiorl of the output of opera-tional amplifier 21 is provided along feedback path 26 to AGC circuit 270 This A~C circuit perfor~s automatic gain control and provides an output signal to light dependent resistor 28 which ls connected between node 2 and ground. The AGC circuit 27 receives an input indicated by BURST WINI:~OW and an Input from node 6 which corr~
sponds to the 0 IRE level of the video signal. The AGC circuit loeks the portions of the video signal (at node 3) that are to occur at the 0 IRE level to the voltage at node 6. Node 3 is connected to node 4 through a resistor. Node 4 is conneeted to a peak ~lip clrcuit 29 which performs the funcffon of clipping the video signals or portions thereo~ that exceed a predetermined reference leveL Typically, this reference level may corre~pond to the 100 IRE level. An input to the peak clip circuit ~s a voltage tapped froml node 5 corresponding to the 100 IRE level o~ the video signal. The output of node 4 which is a conditioned video signal in NTSC ~ormat, is applied as one input ~o 2~1~392 g multiplexer 30. Another input to multiplexer 30 is a signal corre-sponding to the lOO IRE level. Addltionally, the multiplexer 30 recelves inputs corresponding to a O IRE level and a -40 IRE leYel.
The 100 IRE and O IRE levels may be generated by a voltage divider network consisting o~ a voltage source connected to node S via a resistor, a second resistor connected between node S and node 6, and a third resistor connected between nocie 6 and ground. (Lt additional voltage levels are desired, a voltage divider such as the one shown in Figure 13 may be used to generate any number o~ voltages at any volt-age levels.) The -40 lRE level is pre~erably a signal corresponding to ground. Multiplexer 30 also receives ~nputs corresp~nding to SYNC A
and SYNC B timing signaJs which wlll be described more ~ully below.
Based on these inputs, there may be produced at node 7 a video slgnal with spli~ sync pulses simllar to the signal shown in Figure l.
A more detailed description ot how this video signal with split sync pulses is produce~ is provided in the cross-reference application.
However, a brieI descriptlon will be provided here ~or clarity. In essence, the output 7 is normally connected to the video signal input.
However, during the horizontal blanking interval, e.g., multiplexer 30 conne~ts the output node 7 to either the 100 IRE, O IRE or -40 lRE
inputs. For example, the output node 7 may be connected thro~gh multiplexer 30 to the video Input during the portion corresponding to the vîdeo Interval o~ the signal. During a blanking interval or refe~
ence level, the output may ~ connected to the Q IRE leYel input si~-naL This may correspond to the breez~way or 2ront porch interval o~ the video signal. To generate the synchronizatlon interval, the 2 ~ 2 output 7 may tisst be connected to the -40 IRE Input signal ~or a period og tlme corresponding to on~hal~ of the synchronization Inte~
val pel-iod and ~or the second hal~ of the synchronization interval perisd, the output 7 may be connected to the 100 IRE input slgnal. At the end of the synchronlzation Interval the output node 7 may then again be connected to the 0 IRE input tor the back porch interval and then again to the video signal input. By repeating this pattern, video signals wlth split sync pulses can be internally generates'.
The output of mu~tiplexer 30 indicated by node 7 !s then applied to the input ot emitter follower buf~er 31. The output o~
emitter lollower buffer 31 as indicated at node 8 is provided along two ~gnal paths to generate an ~verted and a non-inverted video signal.
One portion of the output is provided to the positive input ot a non-inverting UDity gain operaffonal amplifier 32 to generate the non-inverted video signal. The output of this non-inv rting ampli~ler 32 Is indicated as node 11. The other portion sf the output of emitter follswer buffer 31 is provided through a resistor to the negative Input or inverting ampli-ier 33 to generate the inverted video signal. The output ot amplitler 33 indicated as node 12 ~ fed back to a tesdback path ~omprising a reslstor connected in parallel to a light dependent resistor indicated by LDR3~ For the r easons noted above, it is impo~
tant thati e.g., the sync levels ot the inverted and non-inverted vldeo signaL~ be substantially identical. Thereore, the positive input ot ampli~ier 33 is provided as a reedback signal from node 10 correspond-ing to the output ot a low syn~ compare circuit 34 which will be descri~d more full~ below. A portion ol the output ot amplirler 33 is also provlded as an input to each of a low sync compare clrcuit 34 and a high sync compare clrcuit 35. Each of the low sync compare ~ircult and high sync compare circuit 34 and 35 respectively, also receives an input trom no~e ll corresponding to the output Or amplitler 32. The output ot high sync compare circuit 35, indicated by node 9, ls pro-vided as an lnput to the light dependent resistor lndicated by LDR3.
As w~ be explalned more fully below, this arrangement causes the sync tip levels o~ the inverted video signal to traclc the sync tip levels of the non inverted video signa~t.
The non-lnverted video slgnal ~rom the output Or node 11 is provid~d as an input to mode select switch 36. Another input to mode select switch 36 is the inverted video signal provided trom node 12 correxponding to an output of amplifier 33. Mode select switch 36 also receives a signal indicated as t~INVERT" which is used to selec~ an inverted or non-lnverted mode of operation to thereby provide an output signal at node 13 corresponding to a video signal having split sync pu~s wherein portions of the video signal may be selectively inverted or non-inverted according to a desired operation. A descri~
tion of the INVERT signal will be provided below.
With reference to Flgure ~, it can be seen that the output ot mode select switch 36 lndicated by node 13 is provided as an input ~o emltter follower buffer 37~ The output o~ buffer 37 indicated by node 14 is provided a~ong two signa~ paths. A portion ~ the output o~
buf~er 37 Is provided along a path comprising voltage divider network 38. The output of th~ voltage divider network 38 is prov~ded as an input to switch 40. Another portion o~ the output of ampll~ier 371~
2~53~2 pro-,rided to a SIN2 tilter 39 and other circult components including reslstors as shown. The output o~ tilter 39 is provided as another input to switch 40. Additlonally, switch 40 receives a timlng slgnal indicated ~y "/AREL," which corresponds to a ring sliminating timing slgnal. The output o~ swltch 40 ls AC couple~ through capacitor ~1 to afl output buffer 42 and is provided as a video output signal.
With reference to Figur~s 4 and 5, the low sync compare cir-cuit 34 and high sync compare circuit 35 of Figure 2 wi~ now be described. Figure 4 Illustrates a preferred embodiment Or a high Syllc compare circuit comprlsing a gated integrator. As shown, the high sync compare circuit has two inputs, an inverted lnput and a non-inverted input ~rom no~es 12 and 11, respectiYely, Th~
non-inverted input corresponcls to the output o~ ampll~ier 32 o~ Figure 2. The inverted input corresponds to the output of ampli~ier 33 shown ln Figure 2. Each o~ these inputs is connected through a switch and resistor to an input terminal of operational amplifier 43. The inverted input is applied through a switch which is controlled accor~
ing to a timing signal corresponcling to "/A-40" while the non-inverted input is applied through a switch controlled by a timing signal corr~
sp~nding ~o ~/A100.
This circuit samples both the re~erence and the signal to b~
locked. The dl~erence between them i~ integrated during the gate window~
Attention ts now directed to Flgure 5 and the following description o~ th~ low sync compar~ circuit 34 of Fig. 2. The lo~v sync compare circuit has two inputs, a non-inverted input and an 3 ~ ~
~nverted input. The non-lnverted input corresponds to the output ot ampl~ler 32 ot Figure 2 whlle the inverted Input corresponds to an output of amplltler 33 o~ Figure 2. Each o~ these inputs is connected through a switch and reSistor to an input terminal ot amp~ier 44.
The switch through which the non-lnverted input is connected to amplifier 44 is controlled by a timlng signal corresponding to "/A-40.~
The switch through which the inverted lnput is connected to amplifier 44 is controlled based on a timing slgnal corresponding to "/AlO0."
Amplifiers 43 and 44 are cor~lgured ln a known manner as comparators to compar~ the sync levels o~ the inverted and non-inverted sync signals. Since the output of these comparators are connected to the feedba~k paths of amplifier 33 as described above, the inverted video signal with split sync pulses is made to track the non-inverted video signal with spllt sync puises thereby sell calibrat-ing the system. This circuit operates in a simllar manner as that of the high sync compare circuit. Alternatives to the gated integrator approach are disclosed in Figures 14 and 15 and the descrip~ion thereo~.
~ hat h~ b~en described above is a blcck ~iagram illustrating th~ mapr components o~ lhe present invention presented in a simpli-fied manner to enhance the clarity of the description of ~he novel features o~ the present invention. Schemati~ diagrams of a preferred Implementatlon of the present invention are provided in Figures B, '~
and 8.
In Figure ~, op amp U1 correspon~s to op amp 21 of Figure 2.
DC CLAMP LOOP ~orresponds to D.C. Clamp 24 and AGC LOOP
2~3.~32 corresponds to AGC circuit 27. The /A~UR signal correspond~ to "BIJRST WINDOW." Q3 and Q4 comprise the PEAK CLIP clrcuit 29.
U6 corresponcs to multiplexer 30. Nodes 1, 2~ 3, 49 5t 6 and 7 of Fl~
ure 6 correspond to the respectlve nodes Or Figure 2.
In Figure 7, Q5 and the associated clrcuitry corresponds to bufrer amp 31 ot Figure 2. U7 and U8 correspond to non-lnverting ampli~ler 32 and Inverting ampllfier 33, respectively. U9 and Ulû
correspond to the HIGH SYNC COMPARE cir~uit 35 and LOW SYNC
COMPARE circuit, respectively. Node~ 8, 9, l0, ll and 12 of Flgure 7 correspond to th~ respectlve nodes ot Figure 2.
ID FigUre 8, Q9 and Q8 correspond to node select switch 36.
/AINV corresponds to the lNVERT signal applied to switch 36. Ql0 corresponds to bu~fer 37. R38 and R37 comprise resistor network 38 of Figure 3~ Ll-L3 and C35-C40 compr~se SIN2 ilter 39. Qll and Ql2 compr1se switch 40 of Figure 3. Ul2 correspoads to ampllIier ~2.
Nodes 13, l4, lS, 16 and 17 correspond to the respective nodes o~ Fig-ure 3.
The operation of the schematically illustrated circuitry will b~
readily apparerlt to one of ordinary skill in the art in view o~ ~he dis-cussion o the block diagram of Figures 2-5 presented above.
However, the Hi~h and Low sync compare circuits Will be further described.
Figure l0, repre3ent~ a non inverted video signal as would b~
~ollnd on pin ll o~ IJ7, labeled NONINVERTEI) VIDEO, in Fig. 7. Th~s signal has already had the split sync signal added in swltch U6 (Fig. 6~.
However, the selective video inversion has not yet be~n 2~ 2 accomplished. Indeed lt iS the runction ot the High and Low sync compare circuits to conditlon the video signal so selectlve portlons or it can be inverted. One ob~ct Q~ the clrcuitry of Fig. 7 is to generate both non inverted and Inverted video (pres~nt on pin ll ot U7 and U8 respectively) havlng substantlally ldentlcal amplltudes and ori'sets, though o~ opposite polarity. rnverslon is ~hen accomplished by switching ~etween the two video signals at the appropriate times.
The switchlng is accomplished in transistors Q9 and Q8 (Fig. 8). Tlm-ing of the switehing action is governed by some or the waveforms on ~he timlng diagram, which will ~e explalned below. The object of the High and Low sync compare sample and hold clrcuits (Fig. 2), is to ensur~ that the video appearing on the two ampli~ier outputs are lndeed identical in gain and offset, though of opposlte polarity. The LOW sync oomparator governs the operation o~ the DC matching.
Flg. 10 helps cla~y the operation of this loop. The LOW ~omparator seeks to maintain the -~0 IRE level o~ the two video slgnals at the same D.C. reference, regardless of oIfsets ln the two vldeo opera-tional ampliflers, U7 and U8. This is accomplishe~ by sampling the -40 IRE level o~ the two signals, and applying a eorrection, i~
required, to one input of ampllfier U8. This correction is supplied to pin 6 Or U8 through resistor R~4. As shown in Fig. 10, ~he /'-40 IRE
REF~ signal ~ontrols operation o~ two sampling gates, though we only address ol~e o~ them now. This "A-~0 ~RE REF" s~gnal is so armotate~
on the timing dlagram o~ Flg. 9, and is referred to on the schematic by its circui~ de~ignation /A-40.
With reference agaln to Fig. 7, the -40 IRE F~EF (a.k.a. ~tA-~13n) ~5 supplied to switch Ull pin 9, whlch is closed while the non inverted sync is at the -40 IRE level. Thls -40 IRE level is stored on capacitor C67. During the last halt' o~ the spllt sync, signal "100 IRE REF~
~a.k.a. ~'/A100") is active. It causes switch Ull pln 16 to close. This connects a -40 IRE level signal from the inverted video, to capacitor C70, which stores that voltage level. Operational ampll~ier U10 com-pares the voltage stored on C67, representlng -40 IRE ol' the non inverted video, with that stored on C70, representing~ -40 IRE o~' the invert~ vi~eo. Ideally the two voltages are equal. 1~' not the output from Ula changes. This changes the voltas~e on pin 6 ol' inver~
operational amplilier U8~ in turn changing the output voltage (~
the -40 IRE portion of split sync) until it ls the same as the -40 IRE
voltage ol' the non inverted video.
In a like manner, the ~100 IRE levels oi' the non inverte~ an~
inverted video are sampled respectively by Ull pin 1 and Ull pin 8.
Timing ol' the two samples is ~ontrolled again by ~he -~0 IRE REF and 100 IRE REF logic levels, operating on the video at the proper times to recover the ~100 IRE level. The two voltages repres~nting the +100 IRE portion ol' the two video signals, are stored on capacitors C29 and C30 and compared in comparator U9. The output ~rom U9 controls a light dependent re~;istor, I DR3, which controls the gaill oî
the inverting video ampli~er, U8.
To summarize, the amplitude and gain of the inverted and non-inverted vid~ signals are made equal by first ad~ustlng the ofræa (DC) voltage o~ one ~ignal until the two match at the lowest voltage ~Q~92 level. Then the g in o~ one signal ls ad~usted unt31 the two slgnaLs ar~
o~ egual magnl~ude, determlned by measuring their respective peak ampUtudes. A2ter it hæ been assured that the two slgnals are of iden-tical DC level and galn, they are consldered ~eLt-cal~brated and the self calibrated selectlvely inverted signal can be composed by switch-ing between these two signals.
It wlll ~e readily apparent that the "LOW" circuit operates taster than the "HIGH" clrcuit, based on the value of the holding capacitors in the tws circuits. In the "LOW" circult, the value of holdinOE capacitors C67 and C70 is 0.01 uF. The value of the holding capacitors ln the "HIGH" circuit, C29 and C30, are 0.47 uF, i.e., 47 tlmes larger. Siwe all lour capacitors are charged through like resis-tances (R 29, 30, 32, 60), ~he smaller capacitors will charge ~aster, resulting in ~aster operation oI th~ "LOW" sampling clrcuit. For loop stability reasons a signifi¢antly faster "LOW" loop than "HIGH" loop is d~;ired. Since the "HIGH" value of the video signal is a~ected by the "LOW" amplitude, it the two loops operated at about the same speed, the "HIGH" loop could wind up "ehasing'l the "LOW" loop, resulting ln an unstable circult.
The ~LOW" circuit acts as a DC level ad~ust by changing the voltage on pin 6 oî U8, in respnnse to the difference between the -40 IRE level voltag~; oS the two video signals. The voltage output OI this ampl~ier can be shown to be equal to:
YOUT - VPIN6(RF~R83)-VVIDEO(RF/R83)~
where ~ = Rss in parallel with R54 + LDP~3.
, 2 ~
- 18^
Thus, by ad3ustlng the input voltage on pin 6 ot U8, its output volt-age ls correspondin~ly ad~usted. Similarly, the gain is adjusted by chang-lng the value o~ llght dependent resistor LDR3. This can also ~e seen rrom the equation.
Figure 9 is a timing diagram which shows relative timing between various signals shown in the schematic and block diagrams. The upper portion of Figure 9 depicts a portion o~ a video signal having a split syn~
pulse. Above the video signal, there are various symbols which are def~ned as ~o~lows.
1~ ENWS - ENable Window Start. At this time the video being proces~d through the scrambler is switched to go through the ring eliminator SIN2 filter to eliminate Gibbs finging cau3ed by sharp transitions of video inversion processing.
2. INVS - INverting Window Start. At this time the video being proce~ised by the scrambler is brought to O IRE to prepare it for proce~sing. Failure to do so will under certain conditions resul~ in an improperly descrambled video signal. Also, at this time the video inversion starts 3f the syn~ invert mode is selected. I~ video Invert ls selected, this is ~he time at whlch the inversion stops. For both of the above cases, this condition will continue until INVE. If either sync suppres-sion or invert all modes is seleeted, nothing happens at this time.
3. SYWS - SYnc Window Start. This is the time at which the syn~ pulse starts on the incomlng video. It is also the time , ~ J~
that the reconstructed sync starts (reoornstructed sync ~s used to generate the split sync signal).
. 300N (first ocf~urrence) - 300 nanoseconds. This is the tlme required rOr the sync to transition rrom 0 IRE to -40 IRE. It is determined by the ring eliminator filter of Flg. 8. This filter Is added to restrict the trequencies involved in the spllt sync pulse otherwise the phenomenon of ~'Gibbs ringing~
may occur. Sampling of the -40 IRE pu~e is delayed to make it insensitive to any transients which may exist on the edge of the sync pulse at the sampling poin~.
5. SPLT - SPI,iT. Th~s defines the beginning o~ the split sync pulse, which is generated by controlllng switch IC U6 ~top right OI Fig. 6).
6. 300N (second occurrence~ - 300 nanoseconds. This is the time required to allow the split sync to reach 100 IRE. It is controlled as above. Sampling o~ the 100 IRE level is delayed with the ~100 IRE~' signal supra, again to eliminate any sampling errors caused by ringing in the internal circuits.
. SYWE - SYnc Window End. This ~ the time at which the sp~t sync signal is ended, and samp~ng the 100 IRE level is ended.
8. 300N (third occurrence) - 300 nanoseconds (again). Th~s is the time requlred for the sync signal to reach 0 IRE. Noth-ing Is done at this time.
3 ~ ~
9. BUP~S - BURSt. At this time the circuit is preparing to transmit the lncoming color burst to the output. During most of the horizontal blanking lnterval we are reconstruct-ing the video waveform, but it is desirable to pass the in~oming burst to the output unaffected. So the output, whlch has been swltched to internally generated signals since time ENWS, ~ switched back to the input. (The output video is connected to internally generated si~nals whenev~r either SYNCA or SYNC:B is high - see the ri~ht slde of the timing diagram.) Also, the ring element invert is,switched of i during this time.
10. CBUR - Cclor BURst. Thls designates the time for the oolor burst on the incoming signal. Nothing is done during th~s time.
11. BURE - BURst End. At this time, the video is 5witched back to internally generated signa~s In preparation for ending the blanking mode and returr~ng to the activ~ video mode.
1~. INVE - INYert End. At this time, the output is switched back to the input video9 and depending on the scrambling mode, inversion is either begun or ended at this tim~.
13. ENWE - ENable Window End. At this time, the ring elimina-tsr f~ter is swit~hed off and the active line b~gins.
The tin~ling signals o~ figure 9 are de~cribed as follows.
1. SUPPRESSION WINDOW. Controls operation o~ the switched sync suppression part of the scrambler.
2. INYERSION WINDC)W. Controls inversion ot all or part o~
the video (actlve or blanking), depending sn the mode ot scrambllng. This signal appears on Fig. ~ as /AINV, (bottom le2t). 1t controls the two transistors swltches Q8 and Q9, which select Inverted or non inverted video.
3. SYNCB. When hlgh, switch U6 connects the outgoing video to signals generated internally in the scrambler. When low, the ~ncoming vides is pa~d to the output (unless overridd~n by SYNCA). This signal appear~ on Fig. 6 (top right).
Additionally, the gain ot a rirst signal may be made equal tO the gain ot a second signal to s~ calibrate the slgna~s.
This sell calibration may be Implemented in a number of ways whlch may Include comparing corresponding slgnal portions and using a feedback signal to make one signal correspond to the other signal, clamplng a portion o~ a signal to a corresponding portion of another signal, clamping signals ~rom two separate paths to the same re~e~
ence level and other techniques that will be readily apparent to one o~ ordinary skill in the 'art.
According to another ~eature of the invention, an incomlng video signal may be clamped and gain controlled based on InternaLly generated levels, which levels are also used to generate scrambled video signals including split sync signals.
BRn~F DESCRIP~ON OF THE DR~WINGS
Figure 1 ~s a diagrammatic representation o~ a video signal having a split sync slgnal.
Figures 2 and 3 are a block diagram of a scrambler according to a pre~erred embodiment o~ the present invention.
Figures 4 and 5 are block diagrams o~ the High and Low syn~
comparators of the present invention.
Flgures 6, 7 and 8 are a schematic representation o~ the scram-bler according to a pre~rred embodiment o~ the present invention.
Figure 9 is a timing diagram illustratlng varisus timin~ signals that con~r~l portions o~ the circuits o~ Figs. S-8.
~ lgure 10 a diagrammatlc representation o a noninverted and inverted video signal including spllt sync pu~;es.
Flgures 11 and 12 are block diagrams illustrating alternative ways ol sel~-calibrating signals on plural signal paths according to the teachings of the present lnvention.
Figure 13 is an alternative voltage divider clrcult.
Figures 14 and 15 show alternative sel~-calibration circuitry.
DETAILED DESC~IPTION OF THE P~EFER~EI~ EMBODD~l~NT
The present inventlon is not limited to the partlcular ~mbo~-ments that wlU be described below. Rather, one aspect oi the inven-tion is broadly detined as self-calibrating si~nals on plural signals paths ot a scrambler. This technlque may be implemented ln a num-ber o~ ways and may be used with various ty~es Or scrambling (encod ing) techniques. For example, the plural si~nal paths could generate inverted/non-lnverted signal5; suppressecl/non~uppressed signals or various levels ot suppression; or broadly speaking encoded/
non-encoded signals.
For the sake o~ clarity, all of these permutations wlll not ~e discussed herein. However, the preferred embodin ent Or using sele~
tive inversion/non-lnversion o~ a signal having split sync pulses will be discussed. It wlll be readily apparent to one of ordinary sklll ln the art, ~rom a description ot the preferred embodiment, how to impl~
ment the various other permutations of the present lnvention.
Figure 2 ls a block diagram o~ a scrambler according $o the present Invention. The encircl~d numbers in Fig. 2 indicate varlous nodes of the cireu~t to aid the reader in understanding this em~di-ment. At node 1, a standard NTSC video signal is input to a scram-bler. This signal may be passed through the appropriate signal - 8 - ~ 9 ~
condItloning clrcuits and is applled at node 2 to an input ot an opera-tional ampll~ler 21. A portion or the output ot oFerational amplltler is provided along a feedback path 22 and is ~ed back to an input o~ the operational amp~fier 21. The output or the operational amplifier is indicated by node 3. Another portion o~ the output of operational amplifier 21 is provided along feedback path 23 to a DC clamp circuit 24. This DC clamp circuit locks the sync tip level to 0 volts. The DC
clamp circuit 24 also receives as inputs, a 0 volt signal and a control signal designated as "A-40" which corresponds to a clamp enable sig-nal. The output ot the DC clamp is provided along path 25 to an input o~ operational ampli~ier 21. Another portiorl of the output of opera-tional amplifier 21 is provided along feedback path 26 to AGC circuit 270 This A~C circuit perfor~s automatic gain control and provides an output signal to light dependent resistor 28 which ls connected between node 2 and ground. The AGC circuit 27 receives an input indicated by BURST WINI:~OW and an Input from node 6 which corr~
sponds to the 0 IRE level of the video signal. The AGC circuit loeks the portions of the video signal (at node 3) that are to occur at the 0 IRE level to the voltage at node 6. Node 3 is connected to node 4 through a resistor. Node 4 is conneeted to a peak ~lip clrcuit 29 which performs the funcffon of clipping the video signals or portions thereo~ that exceed a predetermined reference leveL Typically, this reference level may corre~pond to the 100 IRE level. An input to the peak clip circuit ~s a voltage tapped froml node 5 corresponding to the 100 IRE level o~ the video signal. The output of node 4 which is a conditioned video signal in NTSC ~ormat, is applied as one input ~o 2~1~392 g multiplexer 30. Another input to multiplexer 30 is a signal corre-sponding to the lOO IRE level. Addltionally, the multiplexer 30 recelves inputs corresponding to a O IRE level and a -40 IRE leYel.
The 100 IRE and O IRE levels may be generated by a voltage divider network consisting o~ a voltage source connected to node S via a resistor, a second resistor connected between node S and node 6, and a third resistor connected between nocie 6 and ground. (Lt additional voltage levels are desired, a voltage divider such as the one shown in Figure 13 may be used to generate any number o~ voltages at any volt-age levels.) The -40 lRE level is pre~erably a signal corresponding to ground. Multiplexer 30 also receives ~nputs corresp~nding to SYNC A
and SYNC B timing signaJs which wlll be described more ~ully below.
Based on these inputs, there may be produced at node 7 a video slgnal with spli~ sync pulses simllar to the signal shown in Figure l.
A more detailed description ot how this video signal with split sync pulses is produce~ is provided in the cross-reference application.
However, a brieI descriptlon will be provided here ~or clarity. In essence, the output 7 is normally connected to the video signal input.
However, during the horizontal blanking interval, e.g., multiplexer 30 conne~ts the output node 7 to either the 100 IRE, O IRE or -40 lRE
inputs. For example, the output node 7 may be connected thro~gh multiplexer 30 to the video Input during the portion corresponding to the vîdeo Interval o~ the signal. During a blanking interval or refe~
ence level, the output may ~ connected to the Q IRE leYel input si~-naL This may correspond to the breez~way or 2ront porch interval o~ the video signal. To generate the synchronizatlon interval, the 2 ~ 2 output 7 may tisst be connected to the -40 IRE Input signal ~or a period og tlme corresponding to on~hal~ of the synchronization Inte~
val pel-iod and ~or the second hal~ of the synchronization interval perisd, the output 7 may be connected to the 100 IRE input slgnal. At the end of the synchronlzation Interval the output node 7 may then again be connected to the 0 IRE input tor the back porch interval and then again to the video signal input. By repeating this pattern, video signals wlth split sync pulses can be internally generates'.
The output of mu~tiplexer 30 indicated by node 7 !s then applied to the input ot emitter follower buf~er 31. The output o~
emitter lollower buffer 31 as indicated at node 8 is provided along two ~gnal paths to generate an ~verted and a non-inverted video signal.
One portion of the output is provided to the positive input ot a non-inverting UDity gain operaffonal amplifier 32 to generate the non-inverted video signal. The output of this non-inv rting ampli~ler 32 Is indicated as node 11. The other portion sf the output of emitter follswer buffer 31 is provided through a resistor to the negative Input or inverting ampli-ier 33 to generate the inverted video signal. The output ot amplitler 33 indicated as node 12 ~ fed back to a tesdback path ~omprising a reslstor connected in parallel to a light dependent resistor indicated by LDR3~ For the r easons noted above, it is impo~
tant thati e.g., the sync levels ot the inverted and non-inverted vldeo signaL~ be substantially identical. Thereore, the positive input ot ampli~ier 33 is provided as a reedback signal from node 10 correspond-ing to the output ot a low syn~ compare circuit 34 which will be descri~d more full~ below. A portion ol the output ot amplirler 33 is also provlded as an input to each of a low sync compare clrcuit 34 and a high sync compare clrcuit 35. Each of the low sync compare ~ircult and high sync compare circuit 34 and 35 respectively, also receives an input trom no~e ll corresponding to the output Or amplitler 32. The output ot high sync compare circuit 35, indicated by node 9, ls pro-vided as an lnput to the light dependent resistor lndicated by LDR3.
As w~ be explalned more fully below, this arrangement causes the sync tip levels o~ the inverted video signal to traclc the sync tip levels of the non inverted video signa~t.
The non-lnverted video slgnal ~rom the output Or node 11 is provid~d as an input to mode select switch 36. Another input to mode select switch 36 is the inverted video signal provided trom node 12 correxponding to an output of amplifier 33. Mode select switch 36 also receives a signal indicated as t~INVERT" which is used to selec~ an inverted or non-lnverted mode of operation to thereby provide an output signal at node 13 corresponding to a video signal having split sync pu~s wherein portions of the video signal may be selectively inverted or non-inverted according to a desired operation. A descri~
tion of the INVERT signal will be provided below.
With reference to Flgure ~, it can be seen that the output ot mode select switch 36 lndicated by node 13 is provided as an input ~o emltter follower buffer 37~ The output o~ buffer 37 indicated by node 14 is provided a~ong two signa~ paths. A portion ~ the output o~
buf~er 37 Is provided along a path comprising voltage divider network 38. The output of th~ voltage divider network 38 is prov~ded as an input to switch 40. Another portion o~ the output of ampll~ier 371~
2~53~2 pro-,rided to a SIN2 tilter 39 and other circult components including reslstors as shown. The output o~ tilter 39 is provided as another input to switch 40. Additlonally, switch 40 receives a timlng slgnal indicated ~y "/AREL," which corresponds to a ring sliminating timing slgnal. The output o~ swltch 40 ls AC couple~ through capacitor ~1 to afl output buffer 42 and is provided as a video output signal.
With reference to Figur~s 4 and 5, the low sync compare cir-cuit 34 and high sync compare circuit 35 of Figure 2 wi~ now be described. Figure 4 Illustrates a preferred embodiment Or a high Syllc compare circuit comprlsing a gated integrator. As shown, the high sync compare circuit has two inputs, an inverted lnput and a non-inverted input ~rom no~es 12 and 11, respectiYely, Th~
non-inverted input corresponcls to the output o~ ampll~ier 32 o~ Figure 2. The inverted input corresponds to the output of ampli~ier 33 shown ln Figure 2. Each o~ these inputs is connected through a switch and resistor to an input terminal of operational amplifier 43. The inverted input is applied through a switch which is controlled accor~
ing to a timing signal corresponcling to "/A-40" while the non-inverted input is applied through a switch controlled by a timing signal corr~
sp~nding ~o ~/A100.
This circuit samples both the re~erence and the signal to b~
locked. The dl~erence between them i~ integrated during the gate window~
Attention ts now directed to Flgure 5 and the following description o~ th~ low sync compar~ circuit 34 of Fig. 2. The lo~v sync compare circuit has two inputs, a non-inverted input and an 3 ~ ~
~nverted input. The non-lnverted input corresponds to the output ot ampl~ler 32 ot Figure 2 whlle the inverted Input corresponds to an output of amplltler 33 o~ Figure 2. Each o~ these inputs is connected through a switch and reSistor to an input terminal ot amp~ier 44.
The switch through which the non-lnverted input is connected to amplifier 44 is controlled by a timlng signal corresponding to "/A-40.~
The switch through which the inverted lnput is connected to amplifier 44 is controlled based on a timing slgnal corresponding to "/AlO0."
Amplifiers 43 and 44 are cor~lgured ln a known manner as comparators to compar~ the sync levels o~ the inverted and non-inverted sync signals. Since the output of these comparators are connected to the feedba~k paths of amplifier 33 as described above, the inverted video signal with split sync pulses is made to track the non-inverted video signal with spllt sync puises thereby sell calibrat-ing the system. This circuit operates in a simllar manner as that of the high sync compare circuit. Alternatives to the gated integrator approach are disclosed in Figures 14 and 15 and the descrip~ion thereo~.
~ hat h~ b~en described above is a blcck ~iagram illustrating th~ mapr components o~ lhe present invention presented in a simpli-fied manner to enhance the clarity of the description of ~he novel features o~ the present invention. Schemati~ diagrams of a preferred Implementatlon of the present invention are provided in Figures B, '~
and 8.
In Figure ~, op amp U1 correspon~s to op amp 21 of Figure 2.
DC CLAMP LOOP ~orresponds to D.C. Clamp 24 and AGC LOOP
2~3.~32 corresponds to AGC circuit 27. The /A~UR signal correspond~ to "BIJRST WINDOW." Q3 and Q4 comprise the PEAK CLIP clrcuit 29.
U6 corresponcs to multiplexer 30. Nodes 1, 2~ 3, 49 5t 6 and 7 of Fl~
ure 6 correspond to the respectlve nodes Or Figure 2.
In Figure 7, Q5 and the associated clrcuitry corresponds to bufrer amp 31 ot Figure 2. U7 and U8 correspond to non-lnverting ampli~ler 32 and Inverting ampllfier 33, respectively. U9 and Ulû
correspond to the HIGH SYNC COMPARE cir~uit 35 and LOW SYNC
COMPARE circuit, respectively. Node~ 8, 9, l0, ll and 12 of Flgure 7 correspond to th~ respectlve nodes ot Figure 2.
ID FigUre 8, Q9 and Q8 correspond to node select switch 36.
/AINV corresponds to the lNVERT signal applied to switch 36. Ql0 corresponds to bu~fer 37. R38 and R37 comprise resistor network 38 of Figure 3~ Ll-L3 and C35-C40 compr~se SIN2 ilter 39. Qll and Ql2 compr1se switch 40 of Figure 3. Ul2 correspoads to ampllIier ~2.
Nodes 13, l4, lS, 16 and 17 correspond to the respective nodes o~ Fig-ure 3.
The operation of the schematically illustrated circuitry will b~
readily apparerlt to one of ordinary skill in the art in view o~ ~he dis-cussion o the block diagram of Figures 2-5 presented above.
However, the Hi~h and Low sync compare circuits Will be further described.
Figure l0, repre3ent~ a non inverted video signal as would b~
~ollnd on pin ll o~ IJ7, labeled NONINVERTEI) VIDEO, in Fig. 7. Th~s signal has already had the split sync signal added in swltch U6 (Fig. 6~.
However, the selective video inversion has not yet be~n 2~ 2 accomplished. Indeed lt iS the runction ot the High and Low sync compare circuits to conditlon the video signal so selectlve portlons or it can be inverted. One ob~ct Q~ the clrcuitry of Fig. 7 is to generate both non inverted and Inverted video (pres~nt on pin ll ot U7 and U8 respectively) havlng substantlally ldentlcal amplltudes and ori'sets, though o~ opposite polarity. rnverslon is ~hen accomplished by switching ~etween the two video signals at the appropriate times.
The switchlng is accomplished in transistors Q9 and Q8 (Fig. 8). Tlm-ing of the switehing action is governed by some or the waveforms on ~he timlng diagram, which will ~e explalned below. The object of the High and Low sync compare sample and hold clrcuits (Fig. 2), is to ensur~ that the video appearing on the two ampli~ier outputs are lndeed identical in gain and offset, though of opposlte polarity. The LOW sync oomparator governs the operation o~ the DC matching.
Flg. 10 helps cla~y the operation of this loop. The LOW ~omparator seeks to maintain the -~0 IRE level o~ the two video slgnals at the same D.C. reference, regardless of oIfsets ln the two vldeo opera-tional ampliflers, U7 and U8. This is accomplishe~ by sampling the -40 IRE level o~ the two signals, and applying a eorrection, i~
required, to one input of ampllfier U8. This correction is supplied to pin 6 Or U8 through resistor R~4. As shown in Fig. 10, ~he /'-40 IRE
REF~ signal ~ontrols operation o~ two sampling gates, though we only address ol~e o~ them now. This "A-~0 ~RE REF" s~gnal is so armotate~
on the timing dlagram o~ Flg. 9, and is referred to on the schematic by its circui~ de~ignation /A-40.
With reference agaln to Fig. 7, the -40 IRE F~EF (a.k.a. ~tA-~13n) ~5 supplied to switch Ull pin 9, whlch is closed while the non inverted sync is at the -40 IRE level. Thls -40 IRE level is stored on capacitor C67. During the last halt' o~ the spllt sync, signal "100 IRE REF~
~a.k.a. ~'/A100") is active. It causes switch Ull pln 16 to close. This connects a -40 IRE level signal from the inverted video, to capacitor C70, which stores that voltage level. Operational ampll~ier U10 com-pares the voltage stored on C67, representlng -40 IRE ol' the non inverted video, with that stored on C70, representing~ -40 IRE o~' the invert~ vi~eo. Ideally the two voltages are equal. 1~' not the output from Ula changes. This changes the voltas~e on pin 6 ol' inver~
operational amplilier U8~ in turn changing the output voltage (~
the -40 IRE portion of split sync) until it ls the same as the -40 IRE
voltage ol' the non inverted video.
In a like manner, the ~100 IRE levels oi' the non inverte~ an~
inverted video are sampled respectively by Ull pin 1 and Ull pin 8.
Timing ol' the two samples is ~ontrolled again by ~he -~0 IRE REF and 100 IRE REF logic levels, operating on the video at the proper times to recover the ~100 IRE level. The two voltages repres~nting the +100 IRE portion ol' the two video signals, are stored on capacitors C29 and C30 and compared in comparator U9. The output ~rom U9 controls a light dependent re~;istor, I DR3, which controls the gaill oî
the inverting video ampli~er, U8.
To summarize, the amplitude and gain of the inverted and non-inverted vid~ signals are made equal by first ad~ustlng the ofræa (DC) voltage o~ one ~ignal until the two match at the lowest voltage ~Q~92 level. Then the g in o~ one signal ls ad~usted unt31 the two slgnaLs ar~
o~ egual magnl~ude, determlned by measuring their respective peak ampUtudes. A2ter it hæ been assured that the two slgnals are of iden-tical DC level and galn, they are consldered ~eLt-cal~brated and the self calibrated selectlvely inverted signal can be composed by switch-ing between these two signals.
It wlll ~e readily apparent that the "LOW" circuit operates taster than the "HIGH" clrcuit, based on the value of the holding capacitors in the tws circuits. In the "LOW" circult, the value of holdinOE capacitors C67 and C70 is 0.01 uF. The value of the holding capacitors ln the "HIGH" circuit, C29 and C30, are 0.47 uF, i.e., 47 tlmes larger. Siwe all lour capacitors are charged through like resis-tances (R 29, 30, 32, 60), ~he smaller capacitors will charge ~aster, resulting in ~aster operation oI th~ "LOW" sampling clrcuit. For loop stability reasons a signifi¢antly faster "LOW" loop than "HIGH" loop is d~;ired. Since the "HIGH" value of the video signal is a~ected by the "LOW" amplitude, it the two loops operated at about the same speed, the "HIGH" loop could wind up "ehasing'l the "LOW" loop, resulting ln an unstable circult.
The ~LOW" circuit acts as a DC level ad~ust by changing the voltage on pin 6 oî U8, in respnnse to the difference between the -40 IRE level voltag~; oS the two video signals. The voltage output OI this ampl~ier can be shown to be equal to:
YOUT - VPIN6(RF~R83)-VVIDEO(RF/R83)~
where ~ = Rss in parallel with R54 + LDP~3.
, 2 ~
- 18^
Thus, by ad3ustlng the input voltage on pin 6 ot U8, its output volt-age ls correspondin~ly ad~usted. Similarly, the gain is adjusted by chang-lng the value o~ llght dependent resistor LDR3. This can also ~e seen rrom the equation.
Figure 9 is a timing diagram which shows relative timing between various signals shown in the schematic and block diagrams. The upper portion of Figure 9 depicts a portion o~ a video signal having a split syn~
pulse. Above the video signal, there are various symbols which are def~ned as ~o~lows.
1~ ENWS - ENable Window Start. At this time the video being proces~d through the scrambler is switched to go through the ring eliminator SIN2 filter to eliminate Gibbs finging cau3ed by sharp transitions of video inversion processing.
2. INVS - INverting Window Start. At this time the video being proce~ised by the scrambler is brought to O IRE to prepare it for proce~sing. Failure to do so will under certain conditions resul~ in an improperly descrambled video signal. Also, at this time the video inversion starts 3f the syn~ invert mode is selected. I~ video Invert ls selected, this is ~he time at whlch the inversion stops. For both of the above cases, this condition will continue until INVE. If either sync suppres-sion or invert all modes is seleeted, nothing happens at this time.
3. SYWS - SYnc Window Start. This is the time at which the syn~ pulse starts on the incomlng video. It is also the time , ~ J~
that the reconstructed sync starts (reoornstructed sync ~s used to generate the split sync signal).
. 300N (first ocf~urrence) - 300 nanoseconds. This is the tlme required rOr the sync to transition rrom 0 IRE to -40 IRE. It is determined by the ring eliminator filter of Flg. 8. This filter Is added to restrict the trequencies involved in the spllt sync pulse otherwise the phenomenon of ~'Gibbs ringing~
may occur. Sampling of the -40 IRE pu~e is delayed to make it insensitive to any transients which may exist on the edge of the sync pulse at the sampling poin~.
5. SPLT - SPI,iT. Th~s defines the beginning o~ the split sync pulse, which is generated by controlllng switch IC U6 ~top right OI Fig. 6).
6. 300N (second occurrence~ - 300 nanoseconds. This is the time required to allow the split sync to reach 100 IRE. It is controlled as above. Sampling o~ the 100 IRE level is delayed with the ~100 IRE~' signal supra, again to eliminate any sampling errors caused by ringing in the internal circuits.
. SYWE - SYnc Window End. This ~ the time at which the sp~t sync signal is ended, and samp~ng the 100 IRE level is ended.
8. 300N (third occurrence) - 300 nanoseconds (again). Th~s is the time requlred for the sync signal to reach 0 IRE. Noth-ing Is done at this time.
3 ~ ~
9. BUP~S - BURSt. At this time the circuit is preparing to transmit the lncoming color burst to the output. During most of the horizontal blanking lnterval we are reconstruct-ing the video waveform, but it is desirable to pass the in~oming burst to the output unaffected. So the output, whlch has been swltched to internally generated signals since time ENWS, ~ switched back to the input. (The output video is connected to internally generated si~nals whenev~r either SYNCA or SYNC:B is high - see the ri~ht slde of the timing diagram.) Also, the ring element invert is,switched of i during this time.
10. CBUR - Cclor BURst. Thls designates the time for the oolor burst on the incoming signal. Nothing is done during th~s time.
11. BURE - BURst End. At this time, the video is 5witched back to internally generated signa~s In preparation for ending the blanking mode and returr~ng to the activ~ video mode.
1~. INVE - INYert End. At this time, the output is switched back to the input video9 and depending on the scrambling mode, inversion is either begun or ended at this tim~.
13. ENWE - ENable Window End. At this time, the ring elimina-tsr f~ter is swit~hed off and the active line b~gins.
The tin~ling signals o~ figure 9 are de~cribed as follows.
1. SUPPRESSION WINDOW. Controls operation o~ the switched sync suppression part of the scrambler.
2. INYERSION WINDC)W. Controls inversion ot all or part o~
the video (actlve or blanking), depending sn the mode ot scrambllng. This signal appears on Fig. ~ as /AINV, (bottom le2t). 1t controls the two transistors swltches Q8 and Q9, which select Inverted or non inverted video.
3. SYNCB. When hlgh, switch U6 connects the outgoing video to signals generated internally in the scrambler. When low, the ~ncoming vides is pa~d to the output (unless overridd~n by SYNCA). This signal appear~ on Fig. 6 (top right).
4. SYNCA. High during the sync tip. Tl~ls stgnal appears at the top right ot Fig. 6.
5. SPLIT. This s1gnal is part of the 10gl~ that makes up SYNC B (Figo 6~ top right). SPLIT controls selection o~ the 100 IRE level or -g0 IRE (ground), ælected in U6 6. BURST WINDOW. This signal is used as a sample window ~or the AGC Loop which comes before the video inve~sion cir cu~try. The signal i~ also involved in calculating /AREL and SYNC (Fig. 8, lower left), in order to trar~;mit the incoming color burst to the output. ThiS signa~ appears in the middle o~ Fig. 6.
7. -40 IRE REF(iA-4û). Described above ~or vldeo Inversion, this signal is a~so used as a sample window for the DC clamp loop. It is Yound in the middle of Fig. ~.
8. 1001RE REF. Described above~
9. Ring ellminator. Swltches in the ring eliminator ~ilter (FiB~ 8~ wherl we generate a transitioa, for which Gibbs ~ 22 -rin~lng must be suppre~sed. Thls ~s shown at /AREL, In th~
lower lef t o~ Fig. 8.
lower lef t o~ Fig. 8.
10. ENABLE WINDOW. De~lnes the times when we substitute internaLly generated slgnals tor the Incoming video (except for the burst time). This signal is part Or the make-up of SYNCB.
Flgures 11 and 12 show block diagrams o~ circuits capable oi use ln the present invention to sel- calibrate output signals o plural signal patts. In Figures 11 and 12, there is shown at least two signal paths. One path represents an encoded slgnal path and another path represents a non~ncoded path. The nonencoded path contains "non-encoding ci~
cuitry" whi~h may comprise for example a unity gain ampl~ler. ThQ
encoded path contains "encoding circuitry" which may comprise circuitry for modlfylng at least a portion o~ a signal to thereby ef~ect at least one type of scrambling of the signal provided to the encoded path. Portions or the outputs of the non-encoding and encodlng cireuitry may ~e provided to seL~ calibraeion circuitry to sel~ calibrate the signals.
The encoding may comprise one or more o~ a num~r or 3~nown encoding techniques including, but not limlted to, video inversinn, syn~
inversion, sync suppression including one or mor~ levels o~ suppr~ssion or other encod~ng techniques that will be readily apparent to one oî ordinary sklll in ~he art.
For example, the sel~ callbration circuitry may comprise gated in~egrators, gated s~mple and hold devices and/or peak detectors to com-pare corr~spondlng portions o~ sign~l~ in the plural paths. Outputs ot the se~-r~lbration circultry may ~ ted back to either or both oi the - 2~ -encoding/non-enCOding circuitry to sel~ calibrate the signals. Outputs o~
the encodlng/non-encoding circultry are also provlded to a mode select switch to manua~ly or automatlcally select a desired mode, eg., non-encoded video out or enc~ed video out.
In Figure 12, there is shown an example o~ self calibration circuitry that may be used in accordance with the present invention. There ~s shown plural signal paths and appropriate circuitry for each path. Here the selt calibratlon ctrcuitry is shown in the torm o~ clamping and gain control circuitry ~or clamping a portion o~ one signal to a value corre-sponding to a portlon of another signal. Alterna~vely, or in addition to clamplng, a gain control operation may be per~ormed to make the gain or a portion o one signal corresporld to the ~aln of a portion o~ another signal.
For any of the embodiQIents described herein, it may ~e desirable ~o use other Internally generated levels. This may be accomplished acco~ding to the voltage divider Or Fig. 13 which shows levels may be generated above, below, or between 100 IRE and O IRE. In thi~s Fi~, X, Y and Z are variables such that (lOO+X), ~100-Y) and (-40+Z) are desired voltage leveLs.
Figure 14 shows a gated sample and hold device which drives an integrator. In this case, the inte~rator would be operable substantially all o~ the time, not ~ust during the sample window.
Figure 15 shows a peak detector to per~orm the self-calibration. In this embodiment, no gate signal is required but the circuit operates when the "periodic voltages'l ar~ at the extremes (e.g., sync tip levels).
- 2 ~ 2 Shown ln Figure 15 is a positive peak detector. For a negat~ve peak detector, the diode is reversed.
What has ~een descrlbed is the preferred embodiments oi' the pre-sent inventlon. Other embodiments will be appar~nt to one of ordinary skill in the art. For example, even through the prererred embodiment utllizes parallel paths ~or the encoded/non encoded signals, the present inventlon could be applied to serial path systems. Thls invention is not limi~ed to the embodlments described herein but is only limited by the clalms appended here~o.
Flgures 11 and 12 show block diagrams o~ circuits capable oi use ln the present invention to sel- calibrate output signals o plural signal patts. In Figures 11 and 12, there is shown at least two signal paths. One path represents an encoded slgnal path and another path represents a non~ncoded path. The nonencoded path contains "non-encoding ci~
cuitry" whi~h may comprise for example a unity gain ampl~ler. ThQ
encoded path contains "encoding circuitry" which may comprise circuitry for modlfylng at least a portion o~ a signal to thereby ef~ect at least one type of scrambling of the signal provided to the encoded path. Portions or the outputs of the non-encoding and encodlng cireuitry may ~e provided to seL~ calibraeion circuitry to sel~ calibrate the signals.
The encoding may comprise one or more o~ a num~r or 3~nown encoding techniques including, but not limlted to, video inversinn, syn~
inversion, sync suppression including one or mor~ levels o~ suppr~ssion or other encod~ng techniques that will be readily apparent to one oî ordinary sklll in ~he art.
For example, the sel~ callbration circuitry may comprise gated in~egrators, gated s~mple and hold devices and/or peak detectors to com-pare corr~spondlng portions o~ sign~l~ in the plural paths. Outputs ot the se~-r~lbration circultry may ~ ted back to either or both oi the - 2~ -encoding/non-enCOding circuitry to sel~ calibrate the signals. Outputs o~
the encodlng/non-encoding circultry are also provlded to a mode select switch to manua~ly or automatlcally select a desired mode, eg., non-encoded video out or enc~ed video out.
In Figure 12, there is shown an example o~ self calibration circuitry that may be used in accordance with the present invention. There ~s shown plural signal paths and appropriate circuitry for each path. Here the selt calibratlon ctrcuitry is shown in the torm o~ clamping and gain control circuitry ~or clamping a portion o~ one signal to a value corre-sponding to a portlon of another signal. Alterna~vely, or in addition to clamplng, a gain control operation may be per~ormed to make the gain or a portion o one signal corresporld to the ~aln of a portion o~ another signal.
For any of the embodiQIents described herein, it may ~e desirable ~o use other Internally generated levels. This may be accomplished acco~ding to the voltage divider Or Fig. 13 which shows levels may be generated above, below, or between 100 IRE and O IRE. In thi~s Fi~, X, Y and Z are variables such that (lOO+X), ~100-Y) and (-40+Z) are desired voltage leveLs.
Figure 14 shows a gated sample and hold device which drives an integrator. In this case, the inte~rator would be operable substantially all o~ the time, not ~ust during the sample window.
Figure 15 shows a peak detector to per~orm the self-calibration. In this embodiment, no gate signal is required but the circuit operates when the "periodic voltages'l ar~ at the extremes (e.g., sync tip levels).
- 2 ~ 2 Shown ln Figure 15 is a positive peak detector. For a negat~ve peak detector, the diode is reversed.
What has ~een descrlbed is the preferred embodiments oi' the pre-sent inventlon. Other embodiments will be appar~nt to one of ordinary skill in the art. For example, even through the prererred embodiment utllizes parallel paths ~or the encoded/non encoded signals, the present inventlon could be applied to serial path systems. Thls invention is not limi~ed to the embodlments described herein but is only limited by the clalms appended here~o.
Claims (16)
1. A scrambler for use in a video system employing synchroni-zation pulses comprising:
means for generating a video signal having a video portion and a synchronization portion; and means for self-calibrating an output of the scrambler based on a predetermined operation involving the synchronization pulses.
means for generating a video signal having a video portion and a synchronization portion; and means for self-calibrating an output of the scrambler based on a predetermined operation involving the synchronization pulses.
2. The apparatus of claim 1 wherein the synchronization por-tion of the video signal comprises a low sync pulse and high sync pulse and the means for self-calibrating uses the low sync pulse and the high sync pulse to self-calibrate the output of the scrambler.
3. A self-calibrating scrambler for use in a video system, wherein the video system comprises video signals having at least a video signal portion and a synchronization signal portion, the scrambler comprising:
means for generating an inverted video signal having at least a portion of the video signal inverted and for generating a non-inverted video signal;
means for comparing a corresponding portion of the inverted and non-inverted video signals; and means responsive to the comparing means for modifying one of the inverted or non-inverted video signals to thereby self-calibrate an output of the scrambler.
means for generating an inverted video signal having at least a portion of the video signal inverted and for generating a non-inverted video signal;
means for comparing a corresponding portion of the inverted and non-inverted video signals; and means responsive to the comparing means for modifying one of the inverted or non-inverted video signals to thereby self-calibrate an output of the scrambler.
4. The scrambler of claim 3 wherein the synchronization signal portion comprises a low sync portion and a high sync portion and the means for comparing compares the low sync portion of the inverted video signal with the low sync portion of the non-inverted video signal.
5. The scrambler of claim 4 wherein the means for comparing compares the high sync portion of the inverted video signal and the high sync portion of the non-inverted video signal.
6. A self-calibrating scrambler for use in a video system wherein the scrambler is capable of producing and selectively outputting inverted and non-inverted video signals said signals including synchroniza-tion signals comprising a low synchronization pulse and a high synchroni-zation pulse, said scrambler comprising:
means for sampling and holding signals corresponding to the low synchronization pulses of the inverted and non-inverted video signals;
first comparator means for comparing said low synchroniza-tion pulses;
means responsive to said first comparator means for adjust-ing a DC level of one of the low synchronization pulses;
means for sampling and holding signals corresponding to the high synchronization pulses of the inverted and non-inverted video signals;
second comparator means for comparing said high synchro-nization pulses; and means responsive to said second comparator means for adjusting the gain of one of said video signals.
means for sampling and holding signals corresponding to the low synchronization pulses of the inverted and non-inverted video signals;
first comparator means for comparing said low synchroniza-tion pulses;
means responsive to said first comparator means for adjust-ing a DC level of one of the low synchronization pulses;
means for sampling and holding signals corresponding to the high synchronization pulses of the inverted and non-inverted video signals;
second comparator means for comparing said high synchro-nization pulses; and means responsive to said second comparator means for adjusting the gain of one of said video signals.
7. An encoder capable of selectively outputting an encoded or non-encoded signal from one of a plurality of signal paths, comprising:
means for providing an encoded signal along a first or said plurality of signal paths;
means for providing an non-encoded signal along a second or said plurality of signal paths; and means for making at least a portion of one of said non-encoded or encoded signals correspond to a respective portion of the other of said non-encoded or encoded signals.
means for providing an encoded signal along a first or said plurality of signal paths;
means for providing an non-encoded signal along a second or said plurality of signal paths; and means for making at least a portion of one of said non-encoded or encoded signals correspond to a respective portion of the other of said non-encoded or encoded signals.
8. A scrambler for selectively outputting one of a plurality of signals comprising:
means for generating a plurality of signals comprising at least a first signal having a first characteristic and a second signal having a second characteristic; and means for self-calibrating said first and second signals.
means for generating a plurality of signals comprising at least a first signal having a first characteristic and a second signal having a second characteristic; and means for self-calibrating said first and second signals.
9. The scrambler of claim 8 wherein said means for self-calibrating comprises means for making a portion of said first signal correspond to a portion of said second signal.
10. The scrambler of claim 8 wherein said means for self-calibrating comprises:
sample and hold means for sampling and holding portions of said first and second signals;
comparator means for comparing corresponding portions of said first and second signals; and means responsive to said comparator means for modifying one of said first or second signals.
sample and hold means for sampling and holding portions of said first and second signals;
comparator means for comparing corresponding portions of said first and second signals; and means responsive to said comparator means for modifying one of said first or second signals.
11. The scrambler of claim 8 wherein said self-calibrating means comprises:
clamping means for clamping at least a portion of at least one of said first or second signals to a reference level.
clamping means for clamping at least a portion of at least one of said first or second signals to a reference level.
12. The scrambler of claim 11 wherein said reference level is generated from a portion of one of said first or second signals.
13. The scrambler of claim 8 wherein said self-calibrating means comprises:
clamping means for clamping a portion of said first signal to a value corresponding to a portion of said second signal.
clamping means for clamping a portion of said first signal to a value corresponding to a portion of said second signal.
14. The scrambler of claim 13 further comprising:
gain control means for controlling the gain of a portion of said first signal.
gain control means for controlling the gain of a portion of said first signal.
15. The scrambler of claim 14 wherein said gain control means controls the gain of said first signal to correspond to the gain of a corre-sponding portion of said second signal.
16. The scrambler of claim 8 wherein said self-calibrating means comprises a gated integrator.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US34524089A | 1989-05-01 | 1989-05-01 | |
| US345,240 | 1989-05-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2015392A1 true CA2015392A1 (en) | 1990-11-01 |
Family
ID=23354174
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002015392A Abandoned CA2015392A1 (en) | 1989-05-01 | 1990-04-25 | Scrambler with self calibration |
Country Status (6)
| Country | Link |
|---|---|
| CN (1) | CN1024622C (en) |
| AU (1) | AU5534790A (en) |
| CA (1) | CA2015392A1 (en) |
| GB (1) | GB2247808B (en) |
| MX (1) | MX171988B (en) |
| WO (1) | WO1990013973A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998042130A1 (en) * | 1997-03-17 | 1998-09-24 | Macrovision Corporation | Method and apparatus for adaptively enhancing a scrambled television signal |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4075660A (en) * | 1972-02-18 | 1978-02-21 | Teleglobe Pay-Tv System, Inc. | Pay television system with synchronization suppression |
| CA1016647A (en) * | 1975-07-07 | 1977-08-30 | Edward T. Ball | Apparatus for scrambling and unscrambling an amplitude modulated signal |
| US4257065A (en) * | 1979-12-17 | 1981-03-17 | Pay Television Corporation | Video clamp and inverter circuit |
| US4599648A (en) * | 1983-05-24 | 1986-07-08 | Nec Corporation | Video signal transmission systems |
-
1990
- 1990-04-25 CA CA002015392A patent/CA2015392A1/en not_active Abandoned
- 1990-04-27 WO PCT/US1990/002245 patent/WO1990013973A1/en unknown
- 1990-04-27 AU AU55347/90A patent/AU5534790A/en not_active Abandoned
- 1990-04-30 MX MX2051890A patent/MX171988B/en unknown
- 1990-05-01 CN CN 90104116 patent/CN1024622C/en not_active Expired - Fee Related
-
1991
- 1991-11-01 GB GB9123261A patent/GB2247808B/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1049259A (en) | 1991-02-13 |
| CN1024622C (en) | 1994-05-18 |
| GB2247808B (en) | 1994-05-18 |
| GB9123261D0 (en) | 1991-12-18 |
| MX171988B (en) | 1993-11-26 |
| WO1990013973A1 (en) | 1990-11-15 |
| AU5534790A (en) | 1990-11-29 |
| GB2247808A (en) | 1992-03-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| FZDE | Discontinued | ||
| FZDE | Discontinued |
Effective date: 19980427 |