CA2013446A1 - Interface module - Google Patents
Interface moduleInfo
- Publication number
- CA2013446A1 CA2013446A1 CA 2013446 CA2013446A CA2013446A1 CA 2013446 A1 CA2013446 A1 CA 2013446A1 CA 2013446 CA2013446 CA 2013446 CA 2013446 A CA2013446 A CA 2013446A CA 2013446 A1 CA2013446 A1 CA 2013446A1
- Authority
- CA
- Canada
- Prior art keywords
- interface
- microprocessor
- interface module
- host
- bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
Abstract
ABSTRACT OF THE DISCLOSURE
An adaptable host interface which is controlled by the host microprocessor is provided between a bus and an arbitrary host microprocessor. An interface module having a programmable microprocessor that controls the data interchange between the bus and the processing module serves this purpose. The interface module of the present invention can be applied in every kind of coupling between a bus and an apparatus such as a programmable control system.
An adaptable host interface which is controlled by the host microprocessor is provided between a bus and an arbitrary host microprocessor. An interface module having a programmable microprocessor that controls the data interchange between the bus and the processing module serves this purpose. The interface module of the present invention can be applied in every kind of coupling between a bus and an apparatus such as a programmable control system.
Description
2013~
INTERFACE MODULE
Fiel~ f The InventiQ~
This invention pertains to an arrangement for coupling a processing module to a bus by an interface.
Background Of n~he Invention Pxesently, known interfaces for transferring data between a bus and a processing module can be either parallel or serial. Therefore, the proces~ing module needs an adapter which is tailored to the bus mode æo that data can be transferred to the bus. Such an adapter needs to:be~designed in different ways depending on the host microprocessor being: usad~ in the~ processing module.
Having :the adapters for each of the various processing modules is expensive. Therefore,~there is a naed for an adaptable intsrface for the :transfer o~ data between a data~ bus and a processing modulé.
Sum~ary Of The Invent.~Qn ~This and other needs are satisfied by the present : invention for an interface module for the transPer o~ data between a data bus and a processing module. ~he interface module comprises a microprocessor, a bus interface for coupling the in~erface module to a bus, and a host ~ .
,~ j 20134~6 ~2-interface for couplinq the interface ~odule to a processing module. A program is provided for operating the microprocessor. The program makes possible a data interchange between the bu~ and the intsrface module as well as the processing module. Such an interface module can be made having small dimensions and is unlversally applicable. If the interface module is designed as a plug-in unit, then it can easily be coupled and replaced.
A data interchange is possible between the interface module and a host microprocessor having a parallel interface. A fir~t user-specific circuit having several operation parameters is provided in the interface module.
This first user-specific circuit adapts the data interchangQ between the microprocessor of the interface module and the host microprocessor of the processing module during the write/read function of the processing module. Because the first user-specific circuit provides several operational modes, a maximization of the data signalling rate is possible. Changing the parameters of the first user-specific circuit is easily performed by the input ~ of a first code into the program of the microprocessor.
Since some host microprocessors have a serial host interface, the interface ~odule can operate with such a miaroprocessor with relatively few connections which reduces costs. If the host interface of the interface module has both a serial and a parallel transfer part, then the coupling between the interface module and the processing module can be carried out selectively according to the existing interfaae~of the host microprocessor. The data interchange between the microprocessor of the interface module and the bus is adaptable by the input of a second code into the program of the microprocessor.
This allows the interface module to be flexible in working with busses having different bus protocols.
2013~6 Brief~ Qxi~tion Of The ~r~
The single Figure is a block diagram of an inter~ace module constructed according to the present invention.
Detailed pesc~iPtio~
Referring to the Figure, an interface module 4 i5 shown. The interfac~ module 4 adapts a standardized buR
1, having a maximum of two 8et8 of bus lin~s laJ lb, to a host microprocessor 6 of a processing module 2. The standardized bu~ 1 has a bus protocol which is processed in the interface module 4. ~ccording to its type, the host microprocessor 6 has a parallel interface 14 and/or a serial interface 13 as ~ts host interface 3.
Furthermore, the host microprocessor 6 may execute varied write/read functions. The interface ~odule 4 needs to adapt for the particular wr~te/read ~unction executed by : the host microprocessor.
The interface module 4 has a memory 7 and a first user-specific circuit 8 for transmitting the data received by the microprocessor S from the bus 1 through a parallel host interface 14 to the host microprocessor 6. The data is stored in the memory 7 after being received by the microprocessor 5. The storing of data in tbe memory 7 must be controlled according to the write/read function of the respective host microprocessor 6. The first user-25 'specific circuit 8 serves this purpose. The first user-specific circuit 8 supports the data interchange between the microprocessor 5 and the host micropro~essor 6.
Adapting to the various write/read functions of different types of host microprocessors 6, (e.g., different acknowledgement functions and different archite~ture) is accomplished by changing parameters in the interface module 4. Chilnging parameters in the interface module 4 ., ..... ~ : ~
:, ;' "' - ' ' : :
:' . ............................................ : i " .
.--` 20134~6 comprises the input of a first code to the microprocessor S by its program. This first code correspond~ to speci~ic dat~ that c~ncerns the wrlte and read ~unction of the respective host microprocessor 6. This specific data is then stored in the microprocessor 5. Parallel host interfaces 14 are usually quite wide and have a nu~ber of data and address lines which correspond to those of the host microprocessor 6.
In the event that the host microprocessor 6 has a serial interface 13, the user-specific circuit 8 can be dispensed with in the interfaca module 4. The adaptation for th~ serial interface 13 is accomplished primarily by the miaroprocessor 5 with the aid of appropriate firmware.
The expense of an interPace module 4 with a serial host interface 13 can be considerably less compared to an interface module 4 with a parallel host inter~ace 14, since only a few connec~ions are required.
In a development of the present invention, the bus 1 can be standardized, (i.e., it can operate using a specific bus protocol). An operation using different buses ~. which operate using different bus protocols, is also concaiYable. For this purpo~e, it is possible to provide the program of the microprocessor 5 with processing routines which correspond to the bus protocols.
These processing routines make possible the data interchange between the microprocessor 5 and the bus 1.
Also, these processing routines can be selected by the input o~ a second code into the program.
I
The interface modules are provided with plug-in connections sc~ that the electrical connections of the interface are easily detachakle. Thus, a replacement of the interface ~odule 4 is possible without a great degree of complexity. The unlversal applicability and possible i ~0~3446 small dimensions in design represent considerable advantages of such interface modules.
The interface module 4 which has changeable operating parameter presents an asynchronou~ UART~
interface (universal asynchronous ~ecei~e transmit) by its serial host interface 13.
The parallel host interface 14 operates according to the HOLD/HOLD ACKNOWLEDGE principle (HLD/HLDA). On HOLD, the inter~ace module 4 logs on the request to communicate with the host processor 6. In principle, the interface module 4 can wait as long as needed. The bus interface 9 and the host interface 3 are thus chronologically balanced. If the parallel host inter~ace 14 i8 assigned HOLD A~KNOWLEDGE, then a bus access is actuated. The host microprocessor 6 has full control over the host interface 3 and can block the interface module 4 by re~using the HLDA signal.
The first user-specific circuit 8 presents three operational modes. In the first operational mode, a fully autonomous, conqecutive block transfer (DMA) from the memory 7 to the host 6 ta~es place. In the second operational mode the first user-specific circuit 8 operates in an ~TN mode (STM = single transfer mode) where any arbitrary memory address in the host microprocessor 6 can be accessed. In the third operational mode, a storaga area can automatically be reserved ~or executing the ~semaphore mode (SEM). The host access can also take place under Lock by changing operation parameters (i.e. the host interface 3 is reserved over a longer period of time).
The host: interface 3 allows a byte or woxd mode (16 bit) by changing operation parameters. In this operation, an input of the interface module 4 switches this module into the transparent mode (i.e. the interface module 4 can .^..... ...... . .
, . . ...
.... .
... I
. :: ~. ....
. - ~ -, . ,.. , - , , 201~4~6 be installed as a single processor system with an externally available address and data bus).
The parallel interfalce 14 makes high data throughput possible. The program for the microprocessor 5 is stored in the microprocessor 5 itself or in a memory 13 and controls th~a bus interface 9 after a second code is input in the microprocessor 5. The interface module 4 can process various serial data protocols by means of the variable second code.
A second usQr-speci~ic clrcuit 10 psrmits the setting of variable baud rates and the controlling of single channel or dual channel modes. In the dual channel mode, a redundant system can be implemented or two bus interfaàes 9 with di~ferent baud rates can be operated. A built-in transmission monitoring device prevents the blocking of the bus 1 by an inoperable participant. The second user-specific circuit 10 presents the possibility of modulating the serial channel by its modulator and demodulator. The modulator and demodulator generate a serial bus ~ignal without d.c. voltage components and thereby mak~s a trans~ormer coupling po~sible.
The bus interface 9 is set up in galvanic separation while making;available an external voltage ~or supplying the bus.~ An optocoupler 11 i8 provided which separates the interface 9 from th~ microprocessor 5 and the processing module 2. By this configuration a transformative isolation of the bus participants can be achleved. Driver circuits 12 are coupl~d between the optocoupler 11 and the bus lines la,lb. These driver circuits 12 can bo drivers ~or an ~S 485 interface~
!
, . . . . . ... . . . . . . . . ... . . . .
INTERFACE MODULE
Fiel~ f The InventiQ~
This invention pertains to an arrangement for coupling a processing module to a bus by an interface.
Background Of n~he Invention Pxesently, known interfaces for transferring data between a bus and a processing module can be either parallel or serial. Therefore, the proces~ing module needs an adapter which is tailored to the bus mode æo that data can be transferred to the bus. Such an adapter needs to:be~designed in different ways depending on the host microprocessor being: usad~ in the~ processing module.
Having :the adapters for each of the various processing modules is expensive. Therefore,~there is a naed for an adaptable intsrface for the :transfer o~ data between a data~ bus and a processing modulé.
Sum~ary Of The Invent.~Qn ~This and other needs are satisfied by the present : invention for an interface module for the transPer o~ data between a data bus and a processing module. ~he interface module comprises a microprocessor, a bus interface for coupling the in~erface module to a bus, and a host ~ .
,~ j 20134~6 ~2-interface for couplinq the interface ~odule to a processing module. A program is provided for operating the microprocessor. The program makes possible a data interchange between the bu~ and the intsrface module as well as the processing module. Such an interface module can be made having small dimensions and is unlversally applicable. If the interface module is designed as a plug-in unit, then it can easily be coupled and replaced.
A data interchange is possible between the interface module and a host microprocessor having a parallel interface. A fir~t user-specific circuit having several operation parameters is provided in the interface module.
This first user-specific circuit adapts the data interchangQ between the microprocessor of the interface module and the host microprocessor of the processing module during the write/read function of the processing module. Because the first user-specific circuit provides several operational modes, a maximization of the data signalling rate is possible. Changing the parameters of the first user-specific circuit is easily performed by the input ~ of a first code into the program of the microprocessor.
Since some host microprocessors have a serial host interface, the interface ~odule can operate with such a miaroprocessor with relatively few connections which reduces costs. If the host interface of the interface module has both a serial and a parallel transfer part, then the coupling between the interface module and the processing module can be carried out selectively according to the existing interfaae~of the host microprocessor. The data interchange between the microprocessor of the interface module and the bus is adaptable by the input of a second code into the program of the microprocessor.
This allows the interface module to be flexible in working with busses having different bus protocols.
2013~6 Brief~ Qxi~tion Of The ~r~
The single Figure is a block diagram of an inter~ace module constructed according to the present invention.
Detailed pesc~iPtio~
Referring to the Figure, an interface module 4 i5 shown. The interfac~ module 4 adapts a standardized buR
1, having a maximum of two 8et8 of bus lin~s laJ lb, to a host microprocessor 6 of a processing module 2. The standardized bu~ 1 has a bus protocol which is processed in the interface module 4. ~ccording to its type, the host microprocessor 6 has a parallel interface 14 and/or a serial interface 13 as ~ts host interface 3.
Furthermore, the host microprocessor 6 may execute varied write/read functions. The interface ~odule 4 needs to adapt for the particular wr~te/read ~unction executed by : the host microprocessor.
The interface module 4 has a memory 7 and a first user-specific circuit 8 for transmitting the data received by the microprocessor S from the bus 1 through a parallel host interface 14 to the host microprocessor 6. The data is stored in the memory 7 after being received by the microprocessor 5. The storing of data in tbe memory 7 must be controlled according to the write/read function of the respective host microprocessor 6. The first user-25 'specific circuit 8 serves this purpose. The first user-specific circuit 8 supports the data interchange between the microprocessor 5 and the host micropro~essor 6.
Adapting to the various write/read functions of different types of host microprocessors 6, (e.g., different acknowledgement functions and different archite~ture) is accomplished by changing parameters in the interface module 4. Chilnging parameters in the interface module 4 ., ..... ~ : ~
:, ;' "' - ' ' : :
:' . ............................................ : i " .
.--` 20134~6 comprises the input of a first code to the microprocessor S by its program. This first code correspond~ to speci~ic dat~ that c~ncerns the wrlte and read ~unction of the respective host microprocessor 6. This specific data is then stored in the microprocessor 5. Parallel host interfaces 14 are usually quite wide and have a nu~ber of data and address lines which correspond to those of the host microprocessor 6.
In the event that the host microprocessor 6 has a serial interface 13, the user-specific circuit 8 can be dispensed with in the interfaca module 4. The adaptation for th~ serial interface 13 is accomplished primarily by the miaroprocessor 5 with the aid of appropriate firmware.
The expense of an interPace module 4 with a serial host interface 13 can be considerably less compared to an interface module 4 with a parallel host inter~ace 14, since only a few connec~ions are required.
In a development of the present invention, the bus 1 can be standardized, (i.e., it can operate using a specific bus protocol). An operation using different buses ~. which operate using different bus protocols, is also concaiYable. For this purpo~e, it is possible to provide the program of the microprocessor 5 with processing routines which correspond to the bus protocols.
These processing routines make possible the data interchange between the microprocessor 5 and the bus 1.
Also, these processing routines can be selected by the input o~ a second code into the program.
I
The interface modules are provided with plug-in connections sc~ that the electrical connections of the interface are easily detachakle. Thus, a replacement of the interface ~odule 4 is possible without a great degree of complexity. The unlversal applicability and possible i ~0~3446 small dimensions in design represent considerable advantages of such interface modules.
The interface module 4 which has changeable operating parameter presents an asynchronou~ UART~
interface (universal asynchronous ~ecei~e transmit) by its serial host interface 13.
The parallel host interface 14 operates according to the HOLD/HOLD ACKNOWLEDGE principle (HLD/HLDA). On HOLD, the inter~ace module 4 logs on the request to communicate with the host processor 6. In principle, the interface module 4 can wait as long as needed. The bus interface 9 and the host interface 3 are thus chronologically balanced. If the parallel host inter~ace 14 i8 assigned HOLD A~KNOWLEDGE, then a bus access is actuated. The host microprocessor 6 has full control over the host interface 3 and can block the interface module 4 by re~using the HLDA signal.
The first user-specific circuit 8 presents three operational modes. In the first operational mode, a fully autonomous, conqecutive block transfer (DMA) from the memory 7 to the host 6 ta~es place. In the second operational mode the first user-specific circuit 8 operates in an ~TN mode (STM = single transfer mode) where any arbitrary memory address in the host microprocessor 6 can be accessed. In the third operational mode, a storaga area can automatically be reserved ~or executing the ~semaphore mode (SEM). The host access can also take place under Lock by changing operation parameters (i.e. the host interface 3 is reserved over a longer period of time).
The host: interface 3 allows a byte or woxd mode (16 bit) by changing operation parameters. In this operation, an input of the interface module 4 switches this module into the transparent mode (i.e. the interface module 4 can .^..... ...... . .
, . . ...
.... .
... I
. :: ~. ....
. - ~ -, . ,.. , - , , 201~4~6 be installed as a single processor system with an externally available address and data bus).
The parallel interfalce 14 makes high data throughput possible. The program for the microprocessor 5 is stored in the microprocessor 5 itself or in a memory 13 and controls th~a bus interface 9 after a second code is input in the microprocessor 5. The interface module 4 can process various serial data protocols by means of the variable second code.
A second usQr-speci~ic clrcuit 10 psrmits the setting of variable baud rates and the controlling of single channel or dual channel modes. In the dual channel mode, a redundant system can be implemented or two bus interfaàes 9 with di~ferent baud rates can be operated. A built-in transmission monitoring device prevents the blocking of the bus 1 by an inoperable participant. The second user-specific circuit 10 presents the possibility of modulating the serial channel by its modulator and demodulator. The modulator and demodulator generate a serial bus ~ignal without d.c. voltage components and thereby mak~s a trans~ormer coupling po~sible.
The bus interface 9 is set up in galvanic separation while making;available an external voltage ~or supplying the bus.~ An optocoupler 11 i8 provided which separates the interface 9 from th~ microprocessor 5 and the processing module 2. By this configuration a transformative isolation of the bus participants can be achleved. Driver circuits 12 are coupl~d between the optocoupler 11 and the bus lines la,lb. These driver circuits 12 can bo drivers ~or an ~S 485 interface~
!
, . . . . . ... . . . . . . . . ... . . . .
Claims (16)
1. A circuit configuration for an interface that couples a processing module to a bus, wherein said interface is designed as an interface module, and said interface module comprising:
a microprocessor;
a bus interface which couples the bus to the interface module;
a host interface which couples the processing module to the interface module; and a digital program, which is executed in said microprocessor, the execution of said program controlling the transfer of data between the bus and the interface module and between the bus and the processing module.
a microprocessor;
a bus interface which couples the bus to the interface module;
a host interface which couples the processing module to the interface module; and a digital program, which is executed in said microprocessor, the execution of said program controlling the transfer of data between the bus and the interface module and between the bus and the processing module.
2. The interface module of claim 1 wherein the interface module is a plug-in unit.
3. The interface module of claim 1 wherein the host interface of the interface module is a parallel interface and the processing module includes a host microprocessor which executes write/read functions, and further comprising:
a first user-specific circuit having variable operating parameters, said first user-specific circuit adapting the transfer of data between the microprocessor and the host microprocessor during the execution of a write/read function in the host microprocessor.
a first user-specific circuit having variable operating parameters, said first user-specific circuit adapting the transfer of data between the microprocessor and the host microprocessor during the execution of a write/read function in the host microprocessor.
4. The interface module of claim 2 wherein the host interface of the interface module is a parallel interface and the processing module includes a host microprocessor which executes write/read functions, and further comprising:
a first user-specific circuit having variable operating parameters, said first user-specific circuit adapting the transfer of data between the microprocessor and the host microprocessor during the execution of a write/read function in the host microprocessor.
a first user-specific circuit having variable operating parameters, said first user-specific circuit adapting the transfer of data between the microprocessor and the host microprocessor during the execution of a write/read function in the host microprocessor.
5. The interface module of claim 3 wherein the first user-specific circuit has several operational modes.
6. The interface module of claim 4 wherein the first user-specific circuit has several operational modes.
7. The interface module of claim 3 wherein the microprocessor computes the parameters of said first user-specific circuit depending on a first code which is input into the microprocessor.
8. The interface module of claim 4 wherein the microprocessor computes the parameters of said first user-specific circuit depending on a first code which is input into the microprocessor.
9. The interface module of claim 1 wherein the host interface is serial.
10. The interface module of claim 1 wherein the host interface has both a serial and a parallel transfer component.
11. The interface module of claim 1 wherein the data transfer between the microprocessor and the bus is controlled by various bus protocols, and said data transfer is adapted by the input of a second code into the microprocessor and the execution of a program in the microprocessor that has the second code as an input.
12. The interface module of claim 1 wherein the modulation and demodulation of the data appearing at the serial bus interface is controlled by a second user-specific circuit which has several operation parameters.
13. The interface module of claim 1 wherein the serial bus interface has a single or dual channel.
14. The interface module of claim 11, further comprising a second user-specific circuit which includes a transmission monitor as a protocol-supporting element.
15. The interface module of claim 12 wherein the second user-specific circuit includes a transmission monitor as a protocol-supporting element.
16. The interface module of claim 1 wherein the bus interface is galvanically isolated from the microprocessor and the processing module by an optocoupler and an external interface voltage.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE3910719 | 1989-04-03 | ||
| DEP3910719.1 | 1989-04-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2013446A1 true CA2013446A1 (en) | 1990-10-03 |
Family
ID=6377721
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA 2013446 Abandoned CA2013446A1 (en) | 1989-04-03 | 1990-03-30 | Interface module |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP0391157A3 (en) |
| JP (1) | JPH02287665A (en) |
| AU (1) | AU5252390A (en) |
| BR (1) | BR9001505A (en) |
| CA (1) | CA2013446A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9189437B2 (en) | 1997-03-04 | 2015-11-17 | Papst Licensing Gmbh & Co. Kg | Analog data generating and processing device having a multi-use automatic processor |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4008667A1 (en) * | 1990-03-17 | 1991-09-19 | Telefonbau & Normalzeit Gmbh | CIRCUIT ARRANGEMENT FOR CONNECTING A COMPUTER TO A DIGITAL TELEPHONE |
| GB2264374A (en) * | 1992-02-24 | 1993-08-25 | Systems Limited Kk | Programmable protocol converter. |
| DE29603064U1 (en) * | 1996-02-12 | 1996-05-09 | Eukontroll Energiesysteme Mikr | Modular module system as process computer interface with free bus adaptation and expansion bus interface |
| BE1026569B1 (en) | 2018-08-27 | 2020-03-23 | Phoenix Contact Gmbh & Co | Control and data transmission system to support various communication protocols and an adapter module |
| DE102018120823B3 (en) | 2018-08-27 | 2019-12-19 | Phoenix Contact Gmbh & Co. Kg | Control and data transmission system to support various communication protocols and an adapter module |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4293909A (en) * | 1979-06-27 | 1981-10-06 | Burroughs Corporation | Digital system for data transfer using universal input-output microprocessor |
| AU606854B2 (en) * | 1986-01-10 | 1991-02-21 | Wyse Technology, Inc. | Virtual peripheral controller |
-
1990
- 1990-03-22 EP EP19900105458 patent/EP0391157A3/en not_active Withdrawn
- 1990-03-30 CA CA 2013446 patent/CA2013446A1/en not_active Abandoned
- 1990-04-02 JP JP8810290A patent/JPH02287665A/en active Pending
- 1990-04-02 BR BR9001505A patent/BR9001505A/en unknown
- 1990-04-02 AU AU52523/90A patent/AU5252390A/en not_active Abandoned
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9189437B2 (en) | 1997-03-04 | 2015-11-17 | Papst Licensing Gmbh & Co. Kg | Analog data generating and processing device having a multi-use automatic processor |
Also Published As
| Publication number | Publication date |
|---|---|
| EP0391157A3 (en) | 1991-09-18 |
| EP0391157A2 (en) | 1990-10-10 |
| AU5252390A (en) | 1990-10-04 |
| BR9001505A (en) | 1991-04-16 |
| JPH02287665A (en) | 1990-11-27 |
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