CA2011227A1 - Electronic meter digital phase compensation - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

An electronic watthour meter for metering the consumption of electrical energy on power lines includes phase compensation means for compensating for leading and lagging phase differences between line current and voltage, whereby sampling times of the current and voltage are shifted to compensate for phase errors between the current and voltage by controlling timing signals provided to current and voltage analog to digital converters. Digital output signals from the analog to digital converters proportional to current and voltage are multiplied to provide an accurate representation of energy consumption as a result of the compensation.

Description

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l ll-ME-223 ELECTRONIC METER DIGITAL PHASE COMPENSATION

BACKGROUND OF THE INYE~TION

The present invention relates to electronic power metering utilizing digital signal processing and, more particularly, to simpli~ied means to improve the accuracy o~ such meters by compensating for undesired differences or errors in the phase o~
the voltage and current signals.
Electronic watthour me~ers are disclosed, for example9 in United States Patents 4,535,287 - Milkovic; 4,556,843 - Milkovic and Bogacki; 4,682,102 - MiIkovic; and 4,761,605 - Jochum; all o~ which are assignzd to the same assisnee as the present invention. In the present inven~iony an electronic watthour meter converts the analog signals proportional to current and voltage in the circuit being metered to digital signals ~or digital signal processing. Tne current signals are ~irst converted to voltage signals by a current to voltage converter for compatibility with the analog to digital converters which provide digital signal~ based on samples ~ the current and voltage input signals. The conversion of such signals to binary . :~
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to binary form is based on the amplitude o~ the current and voltage signals. The digital signals can then be readily multiplied and the product o~ the multiplication is added to an accumulator which generates pulses proportional to the power use on the power lines being metered. The accuracy o~ such electronic watthour meters re,~uires that the voltage and current signals be in the correct phase relationship before each is provided to its analog to digital converter. That is, the phase relationship should accurately represent that in the power lines. However, the voltage and current scaling and isolation is accomplished through circuitry including instrument transformers and other circuit elements which may introduce phase di~ferences or errors between them.
In order to obtain the required accuracy, and to compensate ~or manu~acturing tolerances, errors in the instrument transformers and changes in circuit elements with ~ime and/or environmental exposure, it becomes necessary to provide phase ad~usting or compensating means for the electronic watthour meter~ However, it is important tha~ such conpensating means be simple, inexpensive, stable, and reliableO Power meter users~

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~ ME~223 such as powar companies and electrical utilities are used to simple adjustments in present rotat:ing ele~ent magnetic watthour meters which require tools no more complex than a screwdriver.
The phase adjustment requires effet:tively compensating for, or shifting the phase of, the voltage signal from the secondary winding of the voltage transformer relakive to the current signal from the current sensor the amount of their error phase di~erence. However, in three phase power meters there are separate current and voltage isolation and scaling trans~ormers for each of the three phases. Conventional phase shifters utilizing a variable resistor and/or variable capacitor for each o~ the three phases would increase the material cost and complexity (and hence reduce reliability), and would require additional cost and complexity for a technician to perform each adjustment individually, particularly in the field when recalibration may be undertaken by a customer. Moreover, variable RC network phase shifting is not applicable to multiplexed signals in three phase electronic power meters.

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4 11--ME~22 OBJECTS AND SUMMARY OF INVENTION

It is an object of the present invention to provide a si~pli~ied phase adjustmen~ for an el~ctronic power me~er;
It is another object of the present invention to provide a phase adjustment ~or an electronic power meter which requires but a single adjustment ~or multi-phase power circuits; and It is yet another object o~ the present invention to provide a phase adjustment for an electronic power meter which is inexpensive, reliable and stable.
In practicing the invention, an electronic solid state power meter is provided ~or polyphase power lines utilizing a current multiplexer to combine the signals from individual line currents in each phase, a voltage multiplexer to combine the individual line voltage signals ~or each phase, current and voltase analog to digital converters ~or converting each multiplexed signal to a digital. signal9 and a multiplier to multiply the dig.ital signals as an indicatisn o~ power use on the polyphase power lines. Phase shift compensation means are provided to adjust the timing o~ the sampling o~ one multiplexed .
, ;'~' ' signal relative to the other to compensate for phase shifts in the system, and provide a more accurate indication of power use on the power lines. The phase shift compensation allows adjustment for either lead or lag phase error dif~erences. The invention also has application in single phase power line systems, in which case multiplexing is not required.

aRIEF OESCRIPTION OF THE DRAWING

FIG. 1 is a block diagram of an electronic watthour meter in accordance with the present invention;
FIG. 2 is a plot o~ in phase current and voltage signals;
and FIG~ 3 is a plot of current and voltage signals illustrating a delayed current signal and phase compensation in accordance ~ith the present invention;
FIG. 4 is a diagram o~ a phase shi~ting network in accordance with thc present invention;
FIG~ 5 is a table illustrating the e~ects of the binary code switching on the phase compensation; and FIG. 6 is a diagram of a phase locked loop arrangement useful in one embodiment 3~ the present invention.

DESCRIPTION OF THE PREFERRED EM3ODII~ENT

Referring to fIG. 1, there is shown a three phase electronic watthour meter in which three current scaling and isolation means 1, 2 and 3 provicie output current signals 4, 5, and 6 respectively, which are proportional to the line currents in power lines 11, 12 and 13 respectively. In order to obtain the desired scaling and isolation, the current scaling and isolation circuits 1, 2, and 3 include current transformers (not shown) which, with the proper turns ratio between the primary and secondary windings, in part provide the desired scaling. In addition, the trans~ormers isolate the solid state circuitry of the electronic power meter ~rom the power lines. The structure and operation o~ current scaling and isolation means 1, 2 and are described in more detail in copending paten~ application serial numher 259,2~4, ~iled October 18, 1988 by ~onald F.
Bullock, entitled "Current Sensors", and assigned to the same assignee as the present inventionO Current scaling ratios of 100,000-to-one and 10,000-to-one have been selected ~or selt-containecl power meters wi~h ~ull scales o~ 200 amperes and 20 amperes (transformer ra~ed) meters respectively. Full-scale . . .

' ç~ rl secondary currents or output signals 4, 5 and 6 are then 2.0 milliamps root means square (rms). In order to minimiz~ the complexity o~the eleotronic circuit:ry, the scaled output current signals 4, 5 and 6 are provided to current multiplexer 15 where they are sequentially sampled to provide separate ~ime separated sample signals which are proportional to each of the current signals 4, 5, and 6. The multiplexer enables the use o~ a single data processing channel (described below) ~or time-sharing all three of the multiplexed and hence time separated current signals 4, 5 and 6 as multiplexed current signal 16. Multiplexed current signal 16 is provided to the input o~ the current to voltage converter 17, which passes the multiplexed current signal 16 through a current to voltage converter 18 to generate a voltage signal 18 propo~tional to the multiplexed current signal 16 which is compatible with the analog to digital converker 24 to be described below. The scaling of the current ~o voltage converter 17 is one volt output signal 18 per one milliamp input signal 16. The voltage signal 18 is ~ed to the gain adjust circuit 19 which utilizes gain adjust con~rol or poten~iome~er 20 to vary the gain o~ an operational ampli~ier (not shown) and provide the desired .
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am4litude ~or signal 18 be~ore the gain adjusted current analog signal 23 is fed to the current analog to di3ital converter or current A/D converter 24. The A/D converter 24 also receives the current or I clock signal 25 and voltage re~erence signal ?6. The I clock signal 25 is a precision timing signal provided by a crystal controlled oscillator or clock 30 which is fed through a shift sample timc circuit ~2 which includes a phase adjustment means 33 and which is described in more detail beluw in connection with FIGs. 2, 3, 4 and 5. The voltage re~erence slgnal 26 is a stable precision voltage re~erence provided by a temperature-compensated zener diode in the precision voltage reference circuit 36 and which may be an integrated circuit o~
the type manufactured by National Semiconductor and identi~ied as their type LM 129.
The phase 1 voltage 41, phase 2 voltage 42 and pnase 3 v~ltage 43 are ~ed through the voltage scaling and isola~ion circuits or trans~ormer circuits 44, 45 and 4S, respectively, to provide voltage scaled and isolated signals 51, 5~ and 5~
respectively to the voltage multiplexer 56 which provides a voltage multiplexed analog signal 57 to the voltage analog to ~ , .,.- ,.:
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9 11-M~-223 digital converter, or voltage A/D converter, 58. It is important that the voltage scaling and isolation circui~s 44, 45, and 46 be matched such that their phase delay characteristics are equal. Similarly, it is important that the current scaling and isolation circui~s 1, 2 and 3 be matched to one another such that their phase delay characteristics are also equal. The voltage A/D converter 58 also receives a voltage re~erence signal 26 ~rom the precision voltage re~erence circuit 36 and the voltage clock or V clock signal 60 which is provided by shift sample time circuit 32. In the FIG. 1 embodiment both, A/D converters 24 and 58 have a ~ull-scale range of approximately + 3.45 volts DC as determined by the voltage re~erence signal 2~. The clock 30 provides precision time base clock signals 27 to oontroL the functioning o~ the A~D
converters 24 and 58 and th~ shi~ted time sample clock si~nals 25 and 60 are at a rate which is one twelfth of the ~requency o~
cloc~ signals 27 as described below in connec~ion with fIG. 4.
Signals 25 and 60 establish a constant sample rate at which the A/D converters 24 and 58 "sample" the current and voltage inputs 23 and 57 and convert their amplitudes to binary words.

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10 ll-ME-223 The current and voltage signals 23 and 57 are sampled every twelfth cycle of the clock signal 27. Sample rates in excess of several kilohertz are desired to obtain good per~ormance for harmonics in the input signals 23 and 57. The current A/D
converter 24 and the voltage A/D converter 58 provide output signals, namely a digital current signal 63 and a digital voltage signal 64, respectively, which are digital words representative of, and prooortional to, their analog inputs, nameiy the gain adjusted current signal 23 and the voltage multiplexed signal 57, respectively. In the cu~rent and voltage A/D converters 24 and 58, upon application of the I clock or timing signal 25 and the V clock or timing signal 60 to the A/D
converters respectively, the analog input signals 23 and 57 respectively, are sampled and held with their ~agnitudes converted into binary ~orm with the voltage re~erence signal 26 de~ining the binary magnitudes o~ the current and voltage signals 23 and 57.

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The digital current signal 63 and the digital voltage signal 64 are in the form o~ binary coded signals or words, such that digital logic or digital signal processing techniques can be used to acco~plish the remainder of the metering function. The digital current signal 63 and the digital voltage signal 64 provide the inputs to the multiplier 65 which multiplies each binary coded current sample, with that of its corresponding voltage sample, to provide a digital input signal 68 to the accumulator 69, which input represent~ their product and which is proportiGnal to power. Samples o~ the line current 11 of line 1 as it is carried ~y the multiplexed current signal 16, and samples o~ phase voltage 41 of phase 1 as it is carrie~ by the multiplaxed voltage signal 57 of the power being measured in line 1 are thus multiplied; as are the current and voltage sampl~s o~ lines 2 and 3. In the case o~ line 2, it is samples o~ the line current 12 and the voltage 4~ which are multiplied, while in the case of line 3, it is samples o~ the line current I3 and the voltage 43 which are multiplied.
Each time the accumulated swm o~ the multiplied voltage and current samples or input 68 reaches a preset threshold value, proportional to the meter watthour constant, an output pulse is , . ~

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generated by the accumulator 69. In one embodiment of the present invention, the rate of output pulse 70 was selected to be twelve times the rate of one disk revolution ~or an equivalent electromechanical watthour meter. A typical threshold value is 144 (10 6) volt-ampere-seconds ~or a one element meter for two-wire single phase applications, and 864 (10 6) volt-ampere-seconds for three phase applications. The register 71 counts, stores and displays energy information based on the number o~ pulses 70 that it receivss. The registPr 71, could include a digital display, such as a liquid crystal display (not shown)9 to display the line power consumption in kilowatt ho~rs.
The accuracy o~ the energy reading provided ~y the register 71 is dependent on the current and voltage signals 63 and 649 which are derived from the analog current and voltage signals 23 and 57 respectiYely, being o~ the correct phase when multiplied in mu Niplier 65. Referring to FIG. 2, an ideal phase relationship is shown where the current signal 23 and voltage signal 57 are in phase. As such, no phase shift compensation is required. As a result the A/D conversions o~ the in phase current and voltage signals 23 and 57 are simul~aneously carried .

; - , ~J~2~rl out by converters 24 and 58 respecti.vely This simultaneous conversion is illustrated in FIG. 2 where the I clock 25 and the V clock 60 are coincident with the i.n phase co~ponents o~
signals 23 amd 57. At ~he end of t~e two A/D conversions, the binary outputs 63 and 64 from converters 24 and 57 are thus, each true in phase representations of the in phase analog current and voltage signals 23 and 57 respectively~ As a result, when the current signal 63 and voltage signal 64 are multiplied by multiplier 65 an accurate representation o~ the power consumed by power lines 11, 12 and 13 will be manifested in the binary digital signals 68 ~rom the multiplier 65.
Referring to FIG. ~, it is to be now noted that the current signal 23 has suffsred a phase delay in the current circuits, for example, in the curren~ sensors of current scaling and isolation circuits 1, 2 and 3. While the delays encountered in actual use are some~hat exaggerated in FIG. 3, there is a time delay or td 74 such that if the I clock and V clock signals 25 and 60 were simultaneously generated (as in FIG. 2) th~ ourrent signal 23 would be negative while the voltage signal 57 is positive, thus providing a multiplier output signal 68 which would not be an accurate representation of the real power in : . ' .

lines 11, 12 and 13. The shi~t sa~lple time circuit 32 can be and is adjusted as described in more detail below in connection with FIGS~ 4 and 5 such that the I clock 25 is delayed ~y the clock delay or td 75 an amount equal to the time delay 74 relative to the V clock 60 such that their timing is corrected relative to the phases of the current and voltage signal~ 23 and 57. Thus, the time shi~ted I clock signal 25 and the V clock signal 60 both begin to sample their respective signals, ~or example, at the inctant when both the curr0nt signal 23 and voltage signal 57 start positive. In this manner~ the sampling period is adjusted to begin at a precise point in time when the current and voltage signals 23 and 57 are in phase. The operation and details o~ the shi~t sample time circuit are best discussed with re~erence to fIGs. 4 and 5.
FIG. 4 shows the details o~ the digital phase adjustment circuitry. RePerring to fIG. 4, the clock 30 provides a 414.6 kilonertz clock signal 31 to counter or divider 83 of shi~t sample tlme 32 which divides the signal 31 by twelve providing an output signal 84 which is approximately 34.5 kiloher~z. The signal 84 drives the and/or select lu~ic circuit 106 which provides the voltage clock signal 60 at approximately 34.5 . . , -~

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kilonertz to the voltage analog to digital converter 58; and also provides a current clock signal 25 at approximately 34.5 kilohertz to the current analog to digital converter 24. The vol~age clock signal 60 and the current clock signal 25 are control signals which control when the analog to digital ;.
converters 5B and 24 respectively, sample the mul~ipl~xed analog input signals, 57 and 23, respectively, and convert the magnitudes of the conver~er analog input signals 57 and 23 to binary coded ou~puts, 64 and 63 respectively. Basically, the voltage clock signal 60 and ~he current clock signal 25 determine the sampling rate, and each conversion process in analog to digital converters, 58 and 24 respectiY~ly, is clocked to completion within the twelve clock times or pulses allotted before the next voltage clock signal 60 and the current clock signal 25, respectively.
The phase or timing shi~t ~etween the vol~age clock signal 60 and the current clock signal 25 is set by shi~t sample time circuit 32. This timing shift is controlled by a phase shi~t control 88 which is pre~era~ly a sixteen position binary-coded switch such as that sold by EEC0, Inc., as their model 33C035GS. The four bi~ ~inary input shown as aIT 0, aIT 19 BIT

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2, and BIT 3 provides a four bit signal via inputs 90, 91, 92 and 9~ to the decode logic circuit 95. FIG. 5 shows the possible input states (in Hex code and Binary code) for BITS
0-3. FIG. 5 also shows the allocation o~ which states o~ BITS
5 0-3 provide prescribed degrees (given as TAU) o~ phase delay between the voltage and current clock signals 60 and 25. It should be noted that state 0 (Hex) proYides no delay between clock signals 60 and 25, which means that these signals are coincidental in time or phase under that conditionO The four 10 bit output of the decode logic circuit 95 is provided to the compare or comparison circuit 103 via outputs 97, 98, 99 and 100. The decode logic circuit 95 decodes BITS 0-3 ~rom the binary switch 88 inputs and provides decoded outpu~s n~ 97-100, representative of delay as shown in FIG. 5. That is, outputs 15 971 98, 99 and 100 de~ine how many steps or states frnm 0 (Hex) the phase separation (in degrees) should be. Decode logic 95 also decodes BITS 0-3 ~o develop a Late signal 107 ~rom ~he -decodes shown in FIG~ 5. The Late signal 107 determines the direction o~ the phase correction or campensation (ie9 whether 20 the current signal 2} ls leading or lagging the voltage signal 57). When the counter 83 reaches the state de~ined by 97, 98, 99 and 100, t~le output INl 105 takes .. . . . . .
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?, @~ 7 17 ll~ME 223 place from the compars 10. When the counter 83 reaches its full count, the output IN2 ta~es place. The output INl or clock signal 105 and the output IN2 or clock signal 84 are both approximately 34.5 kilohertz. The output signals 105 and 84 are the input signals to the ~ld~or select logic circuit 106 which also receives the Late signal 107. The Late signal serves as a switching signal to cross switch the INl and IN2 signals at the outputs 25 and 60 of the and/or logic 106 to control the sampling start times o~ the converters 24 and 57. The two clock signals 84 and 105 are logically combined with ~he Late signal 107 in the and~or select logic circuit 106. When the Late signal 107 is equal to 1, the INl signal 105 controls the current or I clock signal 25f and the IN2 signal 84 controls the voltage or V clock signal 60. The V clock signal will be delayed as determined by ~IT 0-3 switch se~tings as shawn in FIG. 5. When the Late signal 107 is equal to zero, the INl signal 105 is switched in logic 106 ~o control the vol~age or V
clock signal 60 and th~ I~2 signal 84 is switched to control the I clock 25. Thus~ ~he sampling of the curren~ signal 25 in converter 24 is delayed by the amount (in degrees) specified by the time of occurrence of the INl signal now applied to the voltage converter 57 (see fIG. 5 for La~e = 0).

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The details o~ the time delay or phase shi~t provided by the shi~t sample time circuit ~2 is explained in ~urther detail in connection with FIG. 5.
Re~erring to FIG. 5, the ta~le shows the ~inary codes ~or the sixteen step, ~our bit hex-coded rotary switch 88. The zero or 0 delay provides ~or the situation when there is no delay between the analog input current and voltage signals 23 and 57 to converters 24 and 58 respectively. The 11 switch positions abovc the zero delay represent steps in situations where the current analog input 23 to the converter 24 lag the analog volta~e signal 57 to the converter 58. The 4 switch positions below the 0 delay represent steps in situations where the input cusrent 23 le ds the input voltage 57~ The rotary switch 88 is conveniently screwdriver ac~uated to provide delays between the clock timing signals 60 and 25 to the voltage A~D converters o~
approximately 0.052 degrees per step ~or a total adjustment range o~ approximately three-~ourths o~ a degree. The small steps can be very precisely controlled discrete steps based on the ~requency o~ the clock signal 31 ~rom crys~al controlled clock 30. It is to be noted that those ~our s~eps below the no delay point o~ FIG~ 5 provide timing or clock signals in which ~ . :

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19 ll~ME-223 the current timing or clock signal 25 precedes the voltage timing or clock signal 60. That is, the sampling of the input current, initiated by the current clock signal 25, leads the sampling of the input voltage initiated by the voltage clock signal 60. Thus, the rotaxy switch 88 enables a leading or lagging timing or phase adjustment to compensate for phase di~erences which otherwise would introduce errors into the metering. The phas~ adjustment, oeing screwdriver actuated can readily be accomplished during manu~acture and also during any repair or recalibration undertaken by the customsr's service p~rsonnel. Moreover, a single adjustment ls all that is required to adjust the phases o~ a multiphase power meter.
The prescnt invention thus provides an ef~ective and simple adjustment to compensate for a number of situations which would otherwise introduce error into the power meter including manufacturing tolerances, changes o~ circuit parameters with tim~ and/or environ~ental exposure~ and to compensate for errors in other system compon~nts, such as the current transformers (not shown) included within the current scaling and isolation circuits 1,2 and 3. In addition,adjustment may be made to ccn~orm to dif~erent test oonditions, and/or with different s~ ~

re~erence standards. Also, a single screwdriver adjustment ef~ectively compensates for phase errors in single phase meters as well as compensation o~ such errors in all three phases of polyphase meters~
Since the ~requency of the power lines 11, 12 and 1~ o~
most commercial power systems is very stable because clocks and other timing devices depend on such accuracies, it may not be necessary to provide compensation for variations in the power line frequency. In the present invention, matching the phase of the input signals to the analog to digital converters 24 and 58 is accomplished by shi~ting the sampling time of the voltage signal 57 relative to the current signal 23. When the power line frequency changes, the fixed amounts shown in FIG. 5 represent a different amount of phase shift. Worst case line frequency variations seldom exceed 0.02 per cent. This typically occurs during periods o~ low power usagP sucn as nights or weekends when the electric utility is '~catching up" on cycles lost during high usage periods. Ameriean National Standards Institute (ANSI) standard C12.1 descrlbes a line frequency variation test in which the~requency is varied plus and minus 5 per cent with a power ~actor o~ 1Ø Even in the .
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, ' ~ ' -" 2 ~ 7,~.1 worst case test condition, the resultant variation in ~atthour meter calibration at a power factor of loO is probably nPgligible. In the present invention, errors due to line frequency variations do not appear to justi~y the complexity involved in making the time delays vary with power line frequency variations. However, to the extent such increased accuracy is required, the phase compensation accomplished by the present invention can be made insensitive to line ~requency variations by "slaving" the clock 30 to the line trequency through use o~ a phase locked loop.
FI~. 6 shows a phase loc~ed loop circuit which may be use~
with the present invention i~ the additional aocuracy i~
required or desired. A suitable phase-locked loop is disclosed in United States Patent 4,682,102 - Milkovic, assigned to the same assignee as the present invention. Re~erring to fIG. 6, the oscillator or clock 30 includes the phase locked loop 108.
The phase locked loop 108 includes a counter or N divider 109 in series with control circuit 111. The analog line voltage 112 from the p~wer lines is an input to the control circuit 111 along With the feedback signal 113. The dividing rate N o~ divider 109 and the frequency of clock 30 are selected such that the ?~ 2?rJ

~requency divided by the dividing rate N equals the ~requency of the line voltage 112. That is clock frequency : counter rate N
= power line ~requency. The control circuit 111 compares the phases of the line voLtage 112 and the feedback signal lL3 and applies a control signal to clock 30 to effectively lock the frequeney o~ the clock 30 to the desired muLtiple N of the power line frequency, ma~ing the frequency accuracy of the clock 30 equal to the frequency accuracy of the power line ~requency 112. It is desirable that N be a large number7 in the order of 7000 or more since it is desirable in a digital power meter that the nu~ber of output pulses per measurement be suf~iciently high to avoid any jitter on the output pulse rate.
While the present invention has been descri~ed with respect to certain preferred embodiments thereor7 it is to be understood that numerou~ variations in the details of cons~ruction, the OErangement and com~ination of parts, and the type of materials used may be made without departing from th spirit and scope of the invention.

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Claims (31)

1. In an electronic watthour meter for metering the consumption of electrical energy in polyphase power lines, the combination comprising:
a first analog to digital converter for providing a first digital signal in response to current flow in each line of said power lines;
a second analog to digital converter for providing a second digital signal in response to voltage applied to each of said power lines;
a multiplier for multiplying said first digital signal and said second digital signal to derive an indication of electrical energy consumption on said power lines; and compensation means for providing a first timing signal to said first analog to digital converter and a second timing signal to said second analog to digital converter, said compensation means including phase shifting means for shifting the timing of said first timing signal relative to that of said second timing signal, whereby said first and second digital signals provided to said multiplier are substantially in time phase for all current and voltage phases of said polyphase power lines.

2. The electronic watthour meter in accordance with claim 1 wherein said phase shifting means includes means for shifting the timing of one of said first and second timing signals to correspond with a shift in the phase of either one of said power line currents and voltages.

3. The electronic watthour meter of claim 2 wherein a current scaling and isolation circuit is adapted to be connected in circuit with each phase of said power lines; and a current multiplexer is provided to combine the outputs of each current scaling and isolation circuit for provision of a multiplexed analog current signal to said first analog to digital converter.

4. The electronic watthour meter of claim 3 wherein a voltage scaling and isolation circuit is adapted to be connected in circuit with each phase or said power lines; and a voltage multiplexer is provided to combine the outputs of each voltage scaling and isolation circuit for provision of a multiplexed analog voltage signal to said second analog to digital converter.

5. The electronic watthour meter of claim 4 wherein a current to voltage converter converts said multiplexed analog current signal to a voltage signal proportional to the multiplexed analog current before said multiplexed analog current signal is applied to said first analog to digital converter.

6. The electronic watthour meter of claim 5 wherein an adjustable gain circuit is provided to adjust the amplitude of the proportional voltage signal prior to the application thereof to said first analog to digital converter.

7. The electronic watthour meter of claim 6 wherein a precision voltage reference source provides a voltage reference signal to said first analog to digital converter and to said second analog to digital converter.

8. The electronic watthour meter of claim 7 wherein said precision voltage reference source includes a zener diode.

9. The electronic watthour meter of claim 8 wherein said first and second timing signals are derived from an oscillator.

10. The electronic watthour meter of claim 9 wherein said oscillator includes a phase locked loop which varies the frequency output of said oscillator in accordance with variations in the frequency of said power lines.

11. In an electronic watthour meter for metering the consumption of electrical energy in polyphase power lines the combination comprising:
means for providing a multiplexed current signal, in response to the current flow in each of the lines of said power lines;
means for providing a multiplexed voltage signal, in response to the voltage applied to each of the lines of said power lines;
a multiplier for multiplying said multiplexed current signal and said multiplexed voltage signal to provide a signal proportional to electrical energy consumption in said polyphase power lines;
means for sampling said multiplexed current signal and said multiplexed voltage signal prior to the multiplication thereof by said multiplier; and means to compensate for phase difference errors between said multiplexed current signal and said multiplexed voltage signal by adjusting the timing of the sampling of said multiplexed current and voltage signals.

12. The electronic watthour meter of claim 11 wherein said means for sampling includes a current analog to digital converter for converting said multiplexed current signal to a first digital signal prior to multiplication by said multiplier;
and a voltage analog to digital converter for converting said multiplexed voltage signal to a second digital signal prior to multiplication to said multiplier.

13. The electronic watthour meter of claim 12 wherein said means to compensate includes means for providing a separate timing signal to each of said first and second analog to digital converters; and means for adjusting the timing of one of said timing signals relative to the other of said timing signals.

14. The electronic watthour meter of claim 13 wherein said timing signals are derived from an oscillator.

15. The electronic watthour meter of claim 14 wherein said oscillator includes a phased locked loop whereby the accuracy of said oscillator is made equal to the frequency accuracy of the frequency of said power lines.

16. The electronic watthour meter of claim 15 wherein the timing signal provided to said current analog to digital converter may be adjusted relative to the timing signal provided to said voltage analog to digital converter; and said means to compensate further includes means for cross switching the timing signals provided to said analog to digital converters.

17. The electronic watthour meter of claim 16 wherein said oscillating is a high frequency oscillator.

18. The electronic watthour meter of claim 17 wherein the adjustment of the timing signal provided to said current analog to digital converter is performed by a binary coded switch.

19. The electronic watthour meter of claim 18 wherein a fixed timing offset between said timing signals is provided, which timing offset may then be modified by adjustment of said binary coded switch.

20. The electronic watthour meter of claim 19 wherein said binary coded switch provides at least a 4-bit binary code.

21. The electronic watthour meter of claim 20 wherein the frequency of said oscillator is very high compared to the frequency on said power lines, and includes;
means for providing high frequency pulses to each of said current and voltage analog to digital converters to provide high frequency sampling of the multiplexed current and voltage signals during the periods when the timing signals are provided to said current and voltage analog to digital converters.

22. The electronic watthour meter of claim 21 wherein said means to compensate includes means responsive to outputs from said binary coded switch to indicate whether said multiplexed current signal is leading or lagging said voltage multiplexed signal.

23. The electronic watthour meter of claim 22 wherein said binary coded switch may be actuated to change the timing of the sampling of said multiplexed current signal relative to said multiplexed voltage signal to compensate for the phase difference error therebetween.

24. The electronic watthour meter of claim 13 wherein a fixed offset is provided to the timing of said timing signals and said means for adjusting the timing is binary coded to enable adjustment for both lead and lag phase differences.

25. The electronic watthour meter of claim 24 wherein a fixed offset is provided to the timing of one of said timing signals and said means for adjusting the timing is a binary coded switch to enable adjustment for both lead and lag phase difference.

26. The electronic watthour meter of claim 14 wherein the frequency of said oscillator is divided by a counter circuit to provide said timing signals at a sub-multiple frequency of said oscillator, which sub-multiple frequency is much higher than the line frequency of said power lines.

27. The electronic watthour meter of claim 26 wherein a decoding logic circuit provides a signal to selectively control the application of said timing signals to said current and voltage analog to digital converters.

28. The electronic watthour meter of claim 27 wherein the contents of a counter in said counter circuit are compared with the binary coded outputs from said decoding logic circuit to provide the amount of delay and direction of change of at least one of said timing signals to compensate for phase differences between the multiplexed current and voltage signals.

29. The electronic watthour meter of claim 28 wherein the frequency of said oscillator is in excess of 400 kilohertz and said counter circuit divides said oscillator frequency by 12.

30. The electronic watthour meter of claim 19 wherein the rate of said timing signals are equal at said fixed timing offset.

31. In an electronic watthour meter for metering the consumption of electrical energy in a power line, the combination comprising:
a first analog to digital converter, responsive to current flowing in said power line; for generating a first digital output signal proportional to the magnitude of said current;
a second analog to digital converter, responsive to voltage on said power line, for generating a second digital output signal proportional to the magnitude of said voltage;

a multiplier, responsive to said first and second digital signals for generating a third digital output signal proportional to electrical energy consumption on said power line; and compensation means for selectively providing first and second sampling signals to said first and second analog to digital converters to compensate for leading and lagging phase differences between the current and voltage applied to said first and second analog to digital converters, whereby the timing of the generation of said first and second sampling signals with respect to one another enables said first and second analog to digital converters to sample said current and voltage in a substantially in phase relationship such that the third digital output signal from said multiplier is an accurate representation of the electrical energy in said power line.