CA2010491A1 - Microprocessor-controlled circuit breaker and system - Google Patents

Abstract

ABSTRACT

A circuit breaker system uses a microprocessor for calculating at least one function of a measured current flow. The microprocessor provides other functions such as serial data stream communications, the ability of many circuit breaker systems to communicate with a central computer, storage of trip information concerning the last trip, storage of historical trip information concerning a number of past trips, EEPROM memory for storing trip information, the microprocessor may inhibit tripping on a high current fault to permit storage of trip information into a memory, power is derived from current transformers drawing energy from current flow to a load and the electronics are protected from high voltage caused by heavy current flow to the load, optical isolators are used for the circuit breaker to communicate with external equipment, a multi-turn resistor adjusts an external test voltage for testing the circuit breaker system, in the event that there is no load or a load drawing insufficient current to provide power for the electronics the circuit breaker may be externally powered to provide readout of electrically erasable programmable read only memory, the microprocessor reads setting switches and a multiplier plug. Also the microprocessor is capable of digitizing selected quantities frequently and of digitizing other quantities less frequently. A second microprocessor permits one microprocessor to sample voltage and current rapidly for metering purposes, and the second microprocessor operates other functions.

Description

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E~Leld o~ the Invent~o~ , The lnvention relates to circuit breakers operated by a microprocessor, and.more particularly to a network having a plurality o~ circuit breakers communicat'ing with a computer.

Backaround of the Inventio~
A circuit breaker is used to disconnect an electrical circuit from a supply of electric energy in the event that too much electric current .~lows in the electrical circuit.
In applications such as the elect~ical distribution system of a ~actory it is necessary to utilize a co~plex system Oe main electrical feeder lines providing electrical energy for a large number of branch circuits. Each of the main electrical feeder lines must be ~rotected by a circuit breaker. Also each of the branch circuits ~ust be protected by a circuit . breaker. Additionally, it is convenient to provide tie lines between feeder circuits so that a feeder line which loses ... power ~ay be alternati~ly supplied by a different ~eeder - line which remains capable of supplying electrical power.
.20 And it is convenient to provide the tie connection with a .
protective circuit breaXer in order to protect the associated circuits from over current and short circuit conditions.

A microcomputer may be incorporated in a circuit breaker ; design ln order to give the circuit breaker 1n~elligence so ~ 25 that switching operations may be simplified~ ~owever, a problem not solved ~y present designs of microcomputer containin~ ci~uit breakers is that no provision has been made for a communications network having circuit breakers communicating with a central control point.

SummarY of the Invention The invention is a network of microprocessor operated circuit breakers capable of communications with a central computer and with digital meters. Each circuit breaker uses a microprocessor to control its operation. The network provides a means for convenient control of switching actions of the circuit breakers. Additionally, the network supplies information concerning each main feeder circuit, and each branch circuit for which information i5 desired, to the central computer. The information supplied about each circuit may include, current and voltage in each phase of a mult-iple phasa distribution system, electric power, vars, phase angle, trip settings o~ the circuit breaker, current reached during trip events, the number of trip events, and historical records o trip events, etc. Any information which can be sensed through current sensors or voltage sensors and then calculated from the quantities sensed may be supplied to the central computer. The invention uses both circuit breaXers and metering units to sense the required information and to ~ransmit ~he information to the central computar.
Additional objects of the invention are as set out hereinbelow.

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Object No. 1 To provide a switchgear system with computer intelligence capable of mon.itoring power circuits and taking actions based upon decisions made by the computer.
Object No. 2 To provide a circuit breaker and metering unit having serial data communications in addition to microprocessor operated restraint-in and restraint-out signals.
Object No. 3 To provide a circuit breaker system havin~ a plurality of - circuit breakers, a plurality o~ metering units, and a ring communications system for communications with a central rOmputer.
Object No. ~
lS To provide a circuit breaker transmitting a serial data stream to a receiving unit and havin~ pauses betwe~n BYTES.
Object No. 5 ---To provide a circuit breaker system having a metering unit capable of receiving serial data from a circuit breaker and capable of tran~mitting in~ormation on a transmission system.
Object No. 6 To provide a circuit breaker having a serial communications data stream to a receiving uni~ and including wait states to enhance data reception, and having more cri~ical data transmi~ted most of~en and less critical data transmitted less often, and having trip data transmitted upon occurrenca o~ a trip.

Object No, 7 2 ~ 9 ~
To provide a circuit breaker transmitting a serial data stream to a Remote Indicator Unit, and the Remote Indicator Unit having solid state latch memory to preserve information during a power outage.
Object No. 8 To provide a circuit breaker drawing power from current transformers and having a microprocessor placed in a low power state during loss of power.
Object No. 9 To provide a power down and reset control circuit for a circuit breaker.
Object No. 10 To provide a trip unit with po~er failure resistant memory for retention of former trip data.
Object No. 11 To provide a power supply using current transformers for powering a circuit ~reaker, and having means fox shorting the power supply to ground in order to prevent overvoltage during high current transients.
Object No. 12 : To provide a circuit breaker capable of external testing and having optical isolation.
Object No. 13 To provide a circuit breaker trip unit selective betwPen motor prot~ction curves and circuit breaker curves, and a circuit breaker offering phase unbalance protection.
Object No. 14 To provide a circuit break~r having a trip unit, and an external u~it ~or applying power ~o ~e trip unit to get data out of the trip unit.

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Object No. 15 - To provide a Circuit breaker having external test using multi-turn resistor fine adjustment of test parameters.
Object No. 16 To providP a circuit breaker indicator package having a switchable battery power supply and an oscillator that runs only when needed, for a trip unit or the like.
Object No. 11 To provide a circuit breaker using microprocessor and having operator accessible switch controls for trip characteristics and multiplier plug.
Object No. 18 To provide a circuit breaker having a metering unit with a display panel operating fro~ a menu.
lS Object No. 19 To provide a digital metering unit having two micr;oprocessors, where a first processor may sample current and voltage parameters, and a second processor may handle other functions including communications.

Object Nc. 20 To provide a circuit breaker having a microprocessor operated Metering Unit which has a software reset in the event that the microproce~or quits running.
Object No. 21 To provide a circuit breaker having a remotP indicator unit using latching relays to retain status after trip.
Object No. 22 To provide a circuit breaker having direct ~rip by a haavy current event, and microprocessor inhibition of the trip to pe~mit storage o~ data into memory.

Ob~ect No~ 23 To provide a microprocessor controlled circuit breaker capable of digitizing a plurality of input quantities, and capable of digitizing only selected ones of the quantities on a cyclical basis.
Object No. 24 To provide a Power Metering Unit using a microprocessor and sampling both voltage and current during the same time interval using an analog latch.

Other and further aspects of the present invention will become apparent during the course of the following description and by reference to the accompanying drawings.

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~5 3rief Description of the Drawinas Referring now to the drawings, in which like numerals represent like parts in the several views~
Fig. 1 is a drawing of a circuit breaker system mounted S in an equipment rac~, and including computer intellig~nce.
Fig. 2 is a close up of a computer operated circuit breaker.
Fig. 3 is a close up drawing of the control panel of a computer operated circuit breaker Trip Unit.
~ 1~ Fig. 4 is a close up drawing of a Local Managemen~ Unit, ,, , LMU.
Fig. 5a is a drawing of a programmable control~er.
Fig. 5b is a drawing of a system interface unit for a programmable controller.
lS Fig. 5c is a schematic for a system interface unit.
Fig. 6 is a drawing of a Display Unit.
Figs. 7A and 7B ccmprise a drawing of a Remote Indicat~r Unit.
~ ~Fig~ 8 is a schematic of a simple power distribution system.
Fig. 9 is a schematic of a more extensive power distribution system.
Fig. 10 is a partial schematic of a power distribution system.
Fig. 11 is a diagram of a power management system having Local Management Units connected in an optical fiber communications system.
Fig. 12 is a connection diagram for a Trip Unit and a Local Management Unit and having communications between the Trip Unit and a the ~ocal Management Unit, and between a plurality of Local Management Units.

.. .. ... , .. .. .. _ .. .. ~ . ~ . . . -2~
Fig. 13 is a connection diagram for a Trip Unit having communications to a Display Unit.
Fig. 14 is a partial schematic of a connection of a Trip Unit to a power distribution system.
~ig. 15-1 is a schematic of a Trip Unit, sheet 1 of 4.
Fig. 15-2 is a schematic of a Trip Unit, sheet 2 of 4.
Fig. 15-3 is a schematic of a Trip Unit, sheet 3 of 4.
Fig. 15-4 is a schematic of a Trip Unit, sheet 4 of 4.
Fig. 16 is a timing diagram of a Trip Unit.

Fig. 17 is a flow diagram for software oE a trip unit.
Fig. 18A is part of a flow chart for Trip Unit software.
Fig. 18~ is part of a flow chart for a Trip Unit software.
Fig. 18C is part of a flow chart for Trip Unit software.

Fig. 19 is part of a flow chart for Trip Unit software.
Fig. 20 is a schematic of a Display Unit.
Fig. 21 is a block diagram of a menu program for a Display Unit.
Fig. 22 is a schematic of a Remote Indicator Unit.
Fig. 23 is a block diagram of a Local Management Unit, s~leet 1 of 2.
Fig. 24 is a block diagram of a Local Management Unit, shaet 2 of 2.
Fig. ~5-1 is a schematic of a Local Management Unlt, 25sheet 1 of 13.
Fig. 25-2 is ~ schematic of a Local Management Unlt, shaet 2 of 13.
Flg. 25~3 is a schematic of a Local Management Unit, sheet 3 of 13~

Fig. 25-4 is a schematic o a Local Management Unit, sheet 4 of 13.

FigO 25-5 is a schematic of a Local Management Unit, - sheet 5 o~ 12.
Fig. 25-6 is a schematic of a Local Management Unit, sheet 6 o~ 12.
Fig. 2S-7 is a schematic of a Local Management Unit, sheet 7 of 12.
Fig. 25-8 is a sche~atic of a Loc~l Management Unit, she~t 8 of 12.
Fig. 25 9 is a schematic of a Local Management Unit, 10sheet 9 of 12.
Fig. 25-10 is a schematic o~ a Local Manaqement Unit, sheet 10 of 12.
Fig. 25-11 is a schematic o~ a Local Management Unit, sheet 11 of 12.
Fig. 25-12 is a schematic of a Local Management Unit, sheet 12 of 12.
Flg. 26 is a b~s timing diagram for a Local Management Unit.
Fig. 27 is a ~emory map for a ~ocal Management Un.it and a 20Syste~ Interfa~e Unit.
Flg~ ~8 i~ a drawing of a Local Management Unit control panel and display panel.
Fig. 29 is a dia~ram of a m~nu for an LXU, sheet 1 of 4.
Fig. 30 is a diagram o~ a menu for an LMU, sheet 2 of 4.
Fig. 31 i~ a diagra~ of a menu ~or an LMU, sheet 3 of ~.
Figr 32 is a diagram of a menu for an LMU, sheet 4 of 4.
Fig~ 33 i~ a diagram o~ an option tree for an LMU
display.
Fig. 34 is a blocX diagram of sof-twar~ for an LMU.
30Figv 35 is a schematic ~or a Sys~em Inter~ace Unit, SIU.

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DE~AILED DESCRIRTION
Overview Fig. 1 ~hows a circuit breaker equipment rack 100 having a system of microproc~ssor controlled circuit breakers mountèd therein. A variety of circuit breaker types may be controlled by programmable controller 101, including an iron ~rame circuit breaXer 102, a molded case circuit breaker 104, and a toggle operated molded case circuit breaker 105.
Local Management Unit 106 is mounted on the door of the compartments having a circuit breaker. Each Local Management Unit has a control panel 107. Each circuit breaker transmits data on a serial communications llnk to its Local Management Unit. The Local Management Units have two way serial communications with the programmable controller 101. Meter panel 108 may display measured quantities such as voltage, current, power; phase angle, or Xilowatt hours.
Fig. 2 i5 a detailed view o~ the front o~ a , microprocessor controlled circuit breaker. The circuit board for the Trip Unit (TU) i3 visibla through the panel opening.
Various switche~ visible through the panel opening are used to control s¢tting~ of the Trip Unit, such a~ the long time ampere rating and delay time, the short time ampere pickup rating and delay ti~e, the instantaneous ampere pickup rating, and tha ground ~ault ampere pickup rating and delay time. The actual amperes at which functions occur i deter~ined, additionally, by the choice o~ current transformers and by the cholce o~ a ra~ing plug ~or the unit. A control pan~l is shown for the Trip Unit in a projection from it~ place of mounting. Connection jacks for '10--2~04~
c~nnecting external equipment to the Trip Unit circuit board are shown. The external equipment may be a Local Management Unit (LMU), a Display Unit (DU), or a Remote Indicator Unit (RIU~.
~ig. 3 i~ a detailed view of the Trip Unit control panel. The statu of the Trip Unit may be read from the Trip Unit control panel display device.
A table gives the values o~ current in amperes selected by the variou~ position~ of the front panel ~witches for different s~nsor current transformers.
Fig. 4 shows a control panel 107 for a Local Management Unit ~LMU) }06, mounted on the door of the enclosure for the circuit breaker. The LMU receives data via a serial communication link ~rom the Trip unit. The Local Management Unit i~ a microprocessor controlled apparatu~ for performing severa~ functions, including measurement o~ electrical curr;ent and electrical power at sufficient accuracy ~or metering purposes, displayinq Trip Unit data, displaying LMU
data, and for communicating through a ring optical ~iber link to a program~ahl~ controller, through a System Interface Unit (SIU) along wi~h up to, for example, 64 other Local Management Units, in order to provide an intelligent electrical energy management system.
Fig. 5 shows a programmable ~ontroller 101. One o~ the module~ in th~ programmable controller may b2 a Systems Interfac~ Unit (SIU). The SIU is the transmitter and recaivar for tha ring type optical ~iber communication system, and ~h~ SIU may communicate with up to 64 ~ocal Management Units.

Fig. 6 shows a Display Unit ~DU~. The Display Unit provide~ a remot~ display of functions o~ the Trip Unit. The Display Unit is an optional feature used when the sophistication of a ~ocal Management Unit is not needed. A
Display Unit may mount, for example, on ~he door of the circuit breaker enclosure, as is shown for the Lscal ~anagement Unit in Fi~. 1. The Display Unit receives data ~ia the serial communications link from the TU.
7B illustrate front and bottom views of Figs. 7A and/ a Remote Indicator Unit. A ~emote Indicator Unit provides contact closures to indicate selected states of the Trip Unit. The Remote Indicator Unit is an optional feature which can be used independently with a Trip Unit or in conjunction with either a Local Management Unit or a ~isplay Unit. The contact closur~s of the relay may be used for remote signaling of the status of the Trip Unit. The Remotè Indicator Unit receive~ data via ~he serial c~mmunications link from the TU.
Fig. 8 is a schematic diagram of a typical three-phase AC
power distribution system. A main circuit breaker utilizes a Trip Unit and a Local Management Unit. A ~eeder bus supplied by th~ main circuit breaker feeds branch circuits, each of which i~ protected by a Trip Unit~ A~ shown, some of the Trip Units have a Display Unit connectad and the remaining TU
do not. The arrangement shown in Fig. 8 dqes not permit co~munications on a serial communication~ link ~etwe~n the varioua Trip Units. Howaver~ the Trip Unit~ co~unicate ~iractly by a "restraint-in and restraint-out" system~

.

- Restraint-In~ Rest~aint-Out The restraint-in and restraint-out system is indicated by the dashed line. Each Trip Unit contains its own microprocessor, and the restraint-in and res~raint-out ~ystem operate~ by logic level ~i~nals provided by the microprocessor. The purpose of the restraint in re~traint-out connection is for a branch circuit breaker to communicate to a main circuit breaker that a fault is occurring in its branch, and commands the main circuit breaker to utilize a higher current and longer time delay "look up table" in its trip routine. The higher current and longer tima delay "look up table" o~ the main breaker permits the branch brea~er to trip ~irst, thereby isolating a power los~ to that branch, and avoiding the loss o~ power to the othér branches by a premature trip of the main circuit br akèr.
The restraint-in and r~straint-out syste~ is a lPvel communications system in addition to communications between circuit breakers through the Trip Unit Serial Communications Link to the LMU, and co~munication of various LMU Units to a System Interface Unit, SIU. A Trip Unit may be arranged to communicate with another Trip Unit so that the process o~
occurrence oP a trip at the first Trip Unit changes the set~ings for ~ha occurrencQ o~ a ~rip at a s~cond Trip Unit.
For example, if a ~irst Trip Unit monitors a bus supply system and other Trip Units monitor loads deriving thsir source o~ electrical en~rgy Prom ths a~oramentioned bus, then it is desirable to ha~e the downs~rea~ Trip ~nit trip out first in ~he event o~ a ~ault on 1ts load. ~he Re~traint In, --~3--Restraint Out signal~ connected between a downstream circuit breaker and an upstream circuit breaker cause the downstream - circuit breaker to signal the upstream circuit breaker that a fault is occurring in the load of the downstream circuit break~r. R~ceipt of this signal by the,upstream circuit breaker causes the upstream circuit breaker to utilize different settings for developing a trip. The differen~
settingq cause thQ upstxea~ circuit breaXer to dalay its trip until t~e downstream circuit breaker has had a chance to lsolate the fault. The Restraint In, Restra:int Out signaling arrangement prevents the occurrence of a fau:Lt on one branch circuit from causing an upstream circuit breaker to trip thereby removing power from other branch circuits in which no ~ault is occurring.
;Some of the branch circuits shown in Fig. 8 are protected by a`Trip Unit only. A Trip Unit withou~ a Display Unit, a Local ~anagement Unit, or a Re~ote Indicator Unit does not have co~unications capability. However, the st~tus of the Trip Unit may be read fro~ the Trip Unit control panel as shown in Fiy. 3.
Fig. 9 shows a more complex electrical energy distribution sy~te~. Two main thres-phase AC power lines are capable of feeding a num~er of branch circuits. Each AC
power linQ is protected by a main circuit ~reak~r. Each main circuit breaker i~ controlled by a Trip Unit and a Local Manage~ent Unit. Restraint-in and restraint-out communications between the branch circuit breakers and the main circuit breakerare available, but is not shown in Fig. 9 for the sake of clarityO

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A power "link" is protected by a Trip Unit and a Display Unit. Alternatively, a Local Management Unit could be used with the link Trip Unit.
Branch circuits which are judged to ba "critical" are protected by both a Trip Unit and a Local Management Unit.
All Local Management Unit-~ are connected in an optical fiber ring com~unication system to a system interface unit (SIU).
The SIU is a board plugged into a programmable controller.
The SIU is mounted within the programmable controller as a receiver and transmitter for the optical fiber ring communication3 link.
Variou~ branch circuits may be protected by additional Trip Unit~ in combination with a Local Manaqement Unit, or by Trip Units in combination with a Display Unit, or by Trip Units with a Remote Indicator Unit, or by Trip Units standing alone.
Also shown in Fig~ 9 is a connection betwe~n tha programmable controiler and an optional host computer. The communications connection between the programmable controller and the ho~t computer may be by a standardized ~anufac~uring Automation Protocol, MAP link, or alternatively by any convenien~ da~a conn~ction.

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SYSTEM CONNECTIONS
Single Trip Unit and Local Manaqement Uni~
Fig. 10 shows the connection of a Trip Unit (TU) and a Local Management Unit (LMU). An AC power source ~upplies thr~e phase electrical energy to conduct~rs A, B, C.
Conductors A, B, C supply energy to the load. Current transformers CTA, CTB, and CTC provide signals to th~ Trip Unit proportional to current flow in their respective conductors. Contacts CA, CB, and CC interrupt current flow in their respective con~uctors when the trip coil is energized by the Trip Unit. The trip coil is energized ~y the Trip Unit whenever current flow in conductors A, B, C
exceeds predetermined valuqs. For example, if a short circuit develops in the load, the Trip Unit will energize the trip coil and open contacts CA, CB, CC. Al~o, if a ground fault occurs in the load the Trip Unit will open contacts CA, CB,.CC in order to isolate the fault.
The Local ~anagement Unit, LMU, has input signals from precision current transformers PCTR, PCTB, PCTC, from their 2~ respective phases A, B, C. Also, potential connactions ~A, PB, PC connect to the LMU. The LMU measures current flow, power, reactive power, and phase fa~tor in conductors A, B, C. The LMU measures these quantitie~ to an accuracy necessary for metering purpo~es a~, for example, 1% A read ou~ of th~ ~arious quantities measured and computed by the LMU may be observed by an operator at the read out block.
Tha Trip Unit communicates with the Local Manag2ment Unit through the Trip Unit Serial Communications Link, an electrical communications link. Tho Trip Unit transmits, on a predetermined protocol, informa~ton including the followinq: fault conditions including phase and balance pickup or trip, ground fault pickup or trip, short time pickup or trip, long time pickup or trip, 90~ of long time pickup, instantaneous pickup or trip, if a trip is occurring, a ground fault pickup condition, a short~time pickup condition, a long time pickup condition, an instantaneous pickup condition, whether a self-test trip occurred, current levels in phase A, phase B, and phase C, ground fault cuxrent, the option of trip unit or motor protection unit for which the trip unit is set, sensor and plug identifiars, positions of selector switches for long-time delay, long-time pickup, short time delay, short time pickup, ground fault delay, ground fault pickup, instantaneous pickup, phase and balance percent switch, long time trip memQry, the cause o~
the last trip, the current at the last trip, and other pertinent circuit breaker data. A 31 BYTE stream is cyclically transmitted. The individual bits of each BYTE are discussed hereinbelow.
Operating power for the Trip Unit i3 supplied by current derived ~rom the current transformer CTA, CTB, CTC. Power for operation o~ the Local ~anaqement Unit, L~U, is supplied by an external power source.
The information communicated from the ~rip Unit to the Local Management Uni~ may be observed by an opera~or at the readout o~ the Local Management Unit.
Alternati~ely, the serial communication~ port may communicate on a linear bu~, and alternatiYely, ~ay use RS232, RS422 or other standard communication~ method.

The Local Management Unit has a serial communications port for communicating on a ring optical link, along with up to 64 other Local Management Unit~, to a programmable controller or oth~r computer.

LMU Optical Rinq Communications System Figure 11 shows a drawing of individual Trip Units, TU, and Lacal Managsment Units, LMU, connected in a~ optical communications ring. Each individual Trip Unit m~asures current flow to its individual load. Each Trip Unit has its own Local Management Unit for measuring power flow. The Trip Unit communicates to its Local Management Unit on the Trip Unit electrical serial communications link.
The various Local Management Unit~ communicate with a Systém Interface Unit utilizing an optical r~ng serial communications system, or alternatively on a linear bus, or may use RS232, RS422 or other standard communications method. Up to 64 Loca} Management Units can communicate with a single SIU.

Each LMU co~municates with tha System Interface Unit according to a polling protocol. The SIU/LMU co~munications protocol is described hereinbelow.
The information communicated by an LMU to the System Interface Unit may includ~ all of the in~ormation transmitted from the Trip Unit ~o tha LMU, and also may include all o~

th~ infoxmation developed by th6 LMU in it~ ~easurement function.

SIU-5ystem Interface Unit The System Interface Unit may be a module mounted within a prog~ammable controller. For example, the Sy/Max brand of programmable controller sold by the Square D Company may satisfactorily serve a~ the programmable controller. The SIU module may fit into a slot in a register rack o~ the programmable controller. The programmable controller nor~ally receive information along a data highway connecting the SIU and the programmable controller. Also, the programmable controller may control the SIU and direct it to poll a particular Local Management Unit, LMU.

Central Computer Output from the progra~mable controller may be transmitted along a data highway to a central computer. The central computer may utilize inputs from the SIU along wi~h inputs from various other sensors in order to control processes in a manufacturing plant.

System Connection ~iaqra~
Fiy. 12 is a System Connection Diagram. An alternating current bus is shown in th~ upper left corner of Fig. 1~, and includes conductors for phase A, phase B, phase C and the neutral line. Main current transformers for circuit breaker #l arQ shown schematically, and are connected to Trip Unit #1 at connection TB3. Conductors passing through circuit breaker ~1 main current transform~r, conductors A, B, C, N, connact ~o contacts operated by ~he trip solenoid.
Energization of the trip solenoid by Trip Unit #l opens the contac~s.

~19-Conductors A, B, C, N connect from the downstream side of the contact ~o breaker #l precision current transformer, and continue on to the breaker #l load. The breaker #l precision current transformers connect at connection TB5 to Local Management Unit LYU #1. A serial communlcation link from Trip Unit #1 is connected to Local Management Unit LMU X1 at jack J5 o~ Trip Unit #1 and plug P5 of Local Management Unit LMU #1. Trip Unit #1 has a rating plug connected a~ jack J6. A Testing and Calibration Unit may be connected to Trip Unit #1 at ~ack J4. Step up current transformers connect into Trip Unit #1 at connection TB4, and accept current at connection TB3 from breaker #1 main current transformers.
Local Management Unit LMU #l is connected to control power at connection TB #6. Local Management Unit LMU unit #1 is -in a ~iber optical ring type "daisy chain" serial data communication ring. Other LMU units in the communications ring are indicated, and unit ~N is shown. There may be up to 64-L~U units connected in the optical ring "daisy chain". A
System Inter~ace Unit, SIU, i5 shown connected in the optical ring. Th~ SIU connect~ to a programmable controller. Data transmitted to the System Interface Unit from each of the Trip Units and the Local Management Units may be trans~rred to the programmable controller. Also, the programmable controller may command the SIU to poll a particular LMU.

Alternative Embodiment ~or Trip Unit Fig. 13 shows an alternative eMbodiment of a Trip Unit.
The alternative em~od~ment does not utilize a ~ocal Manag~ment Unit, LMn. Tho alternative em~odiment is a stand-alon2 circuit breaker utilizing a Trip Unit and a 9~
display unit. Rather than connecting an ~MU to the TU at jack J5, a Display Unit i5 connected to the TU at jack J5.
Also, a Remote Indicator Unit (RIU) i~ shown connected to the TU at connection TB4. The R~U is capable of operating a contact in order to signal a long time PiCk-UP or dry trip condition o~ the Trip Unit.
The Display Unit accepts the serial comMunications data stream output by the TU, just as the LMU accepts the serial data stream, and may display the data at a location remote from the Trip Unit. Internal operation of the Display Unit and the RIU will be described hereinbelow.

Trip Unit I~O connections Flg. 14 shows connections between a Trip Unit and a 3 phase AC line. Conductors A, B, C, and Neutral, are shown at the left of Fig. 14 in the connection between a switch gear bus and à load. Current flow in conductors A, B, C may be intérrupted by opening of the contacts. The trip solenoid, when energizsd, opens the contacts.
Main current transform~r CTA, CTB, CTC, and CTN are shown. Current transormer CTN develops a voltage proportional to the current ~low in the neutral line. The main current trans~ormers are connected to current trans~ormers SUA, SUB, SUC, and S~M. Trans~ormers SUA, SU~, and SUC have turn~ ratio of, fox example, 1 to 10. The SUM
current transformer has a turn~ ratio of, for example, 1 to 5, in order to provide a laxger output voltage for a smaller current flow in the nsutral l~ne.

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- T~IP_UNI~ HARDWARE
Throughout the hardware of the Trip Unit, a logical "high" re~ers to approximately 5.8 volts on a signal 1 ine . A
logical "low" refers to a signal line at approximately ground potential.

Tri~ Unit Current Transform~rs As shown in Fig. 14, power for the electronics of the Trip Unit (TU) is derived from current flow in the power . conductors of the circuit breaker. Current flow in phase A
induces a proportional current in current transformer (hereina~er abbreviated CT) secondary CTA. Current flow in phase B induces a proportional current in CT secondary CTB, current ~low in phase C induces a proportional current in CT
secondary CTC, and current flow in the neutral induces a proportional current in CT secondary CTN.
Thè currents in the CT secondari~s CTA, CTB and CTC also pass through the primaries of step-up trans~ormers SUA, SUB
and--SUC, respectively, which each have a turns ratio of 1 to 10. The turns ratio of 1 to 10 means that a curr~nt is induced in ~ach o~ their respectiv~ secondaries which is one-tenth of tha current in their primarie~. These current --~ source~ ha~e respective voltage complianca-~ approximately ten times greater than those of CT secondaries CTA, CTB and CTC, respectively, and for this reason they are called step-up instead o~ step-down transformers~ in spite of the fact that they produca a reducad current flow.
A ground f~ult is detected by a lack of balance between the phase current transformer~ and the neutral current transformer CTN. CTN return~ all loads conneoted between any o~ the three phase~ (A, B or C) and ~h~ neutral power conductor. Any phase current not balanced by th2 ~o~ 9 ~ase currents or by the neutral conductor current flow provides a net current flow ~hrough the ground fault summer, transformer SUM, primary. That is, if the sum of the ourrents flowing in CT secondaries CTA, CTB, CTC, and CTN is not zero, indicating a ground fault, the remainder flows through the primary of trans~ormer SUM. The su~mer transformer SUM has a turns ratio of 1 to 5, which results in a reduction in current flow from primary to secondary of a factor of five, as well as a voltage compliance increase o~ approximately 5.
Step-up trans~ormers SUA, SUB and SUC drive two full-wave bridge rectifiers, CR1 and CR2. One side of the secondary of SUA is connected via a current sense resi~tor, Rl, to one AC
terminal of bridge CR1 and the same side of SUB (in the sense of current flow in the main power conductors) is conne~ted via R2`to the other AC terminal of SUB. The same side of the secondary of SUC is connected via R3 to one AC ~erminal of CR2-. And the retur~ sides o~ SUA, SUB and SUC are connected together, and this junction is then connected via R5 to the other AC terminal o~ CR2. 80th o~ these bridges have their negatiYe terminals connected to the Trip Unit's circuit ground. The positive terminal of bridge CRl is connected to the positive terminal of bridge CR2 and this junction is connected via ~ense resistor R5 to the power supply. Current to supply the electronics o~ th~ Trip Unit ~lows through resistor R5 to point BRC.

T~iP Unit Schematic Diaqrams The Trip Unit schematic diagrams are on four shee~s designated Fig. 15-1 through FigO 15-4. The diagrams indicate continuations to sheet 1, sheet 2... etc.. A
continuation to sheet 2 can be read as to Fig. 15-2, etc.

TriP-unit Voltaqe Requlation As shown in Fig. 15-}, power i~ supplied to the Trip Unit S by the current trans~ormers, and input to the regulator circuits occurs at point 8RC.
The dynamic range of current flows in conductors A, B, and C make it difficult to design a power supply having a constant output voltage under all condition~ o~ current flow in conductors A, B, and C. The voltage at point BRC depends very strongly on current flow in conductors A, B, C. And the electronic circuits require a well regulated powex supply.
Particularly, a power supply that supplies sufficient voltage ~or;operation of the electronics when current flow in the conductors A, B, and C is a small fraction of P may have dif~iculty in limiting the output voltag~ when current flows are considerably .in excess of P. P i5 the plug ra ing and has defined values batween approximately 200 amperes to approxi~ately 4000 amperes. For example, the po~er supply may ba designed to provide a proper output voltage for ourrent ~low m conductors A, B, C of O.lP. T~e pow~r supply may then produce excessiv~ voltages if current flow should be as great a~ 16 P or even 32 P.
The invention uses two regulator circuits in order to achieve a regulated power supply output voltage, a3 shown in Fig. 15~1.

~2~- -. ... . . . ... . .

2~
The first regulator is a shunt regulator deriving current from point BRC through an equivalent Zaner diode to ground.
The equivalent Zener diode i~ made ~rom integrated circuit XQl. Circuit XQl hold~ point BRC slightly above 18 vslts.
Capacitor C3 is a filter capacitor. Cap~citor C3 may be a 350 microfarad capacitor, and is charged through diode CR6.
The 18 volt supply is obtained across capacitor C3, and the 18 volt supply provides current for the electronics of the Trip Unit.
The first regulator also provides a precision 2.5 Volt source across Zener diode U5. Capacitor C4 provides further regulation of the preci~ion 2.5 Volt source.
A difficulty ~ound in the first regulator is that current excursions in the conductors A, B, C far in excess of the P
rating of the circuit breaker may cause excessive voltages at the 18 volt point, and ~ay burn out electronics supplied by the pow~r supply. Alco~ exc2~sive voltage~ at points A, A', B,--B', C, C', D, E, F and G ~ay drive operational amplifiers Ul-A, U3-C, U2-A, U2-C, U2-D into saturation, particularly when the voltages to ground exceed the operational ampli~ier common moda rejection threshold. The oparatisnal amplifiers generate analog voltages in response to current flow in conductors A, B, C.
The second regulator is shown in Fig~ 15-1 and Fig.
15-3. Th~ sacond regulator is a shunt limiter, and is a circuit for driving the voltage at point BRC to zero for predetermined tim~ pexiods~ The second regulator incorporates a rslaxation oscillator to cyclically short cixcuit point BRC to ground. In Fig. $5-1, Point~ A, B, C, D, E, and F ar~ connected through diod~3 CR12~.. CR15, CR57, -~5-2~
CR58 to a common point COM1. Metal Oxide Varistor MOV, RVl provides some transient protection for point COM1.
As shown in Fig. 15~3, Zener diode VR2, which may be a 30 volt æener diode, charg~s capacitor C59 through diode CR62.
Resistor R23 provides a discharge path for capacitor C59, and diode CR62 prevents discharge of capacitor C59 back through points A, B, C, D, E, or F.
Resistor R131 and resistor R132 provide a voltage divider, and their junction point provides a signal to op-amp U30-A at its negative input terminal. A signal to the positive input t~rminal o~ op-amp U30-A is taken from the positive terminal of capacitor C59.
In operation, the voltage at the negative input terminal of op-amp U30-A i~ one-half the voltage at point COMl, with R131 and R132 being set equal, where R131 and R132 may be lOk ohm r~sistors. When the voltage at point COMl ex~eeds the 30 volt characteristic of th2 Zener diode VR2, then the voltaqe at-th2 positive input terminal of operational amplifier U30-A
will exceed the voltage at the negative input terminal, thereby turning op-a~p U30 A "off" and allowing output terminal 1 o~ U30-A to go to the voltagQ o~ point COMl.
Transi~tor Q13 provides current amplification and drives ~ase current into Darlington pair XQ5.
Darling~on pair XQ5 thereby turns "on" and goes into conduction saturation. Conducti~n of tran~istors Darlington pair XQ5 short circuits point COM1 to ground through small ~esistor R13~, and R136 may be 0.1 ohmO Shorting point COMl to ground pul 1 s the voltage at po intR A, B ~ C, D, E, and F to near ground, thereby li~iting the output voltag~ o~ the shunt requla~or XQl a~ poin~ BRC ~o much le~ an 1~ volts.

However, it is desirabl~ to maintain ourrerlt ~low to the el~ctronics of the apparatus by discharge of c~pacitor C22, C46, shown in Fig. 15-2. However, the load supplied to microprocessor U24 may vary between 100 milliamperes to as much as 900 milliamperes when the electronics activate the trip coil to trip th~ breaker to an "oPf" state. This current load far exce2ds the energy storage capacity of capacitors C22, C46. Accordingly, the shunt limiter permits periodic charging o~ capacitor~ C22, C46 while still limiting 10 the outpu~ voltage of the shunt regulator.
In order to permit the periodic charglng o~ capacitors C22, C46, the current limiter acts as a relaxation oscillator. Capacitor C59 and resistor R23 determine the of~-time of the relaxation os~illations.
Th~ initial voltage transient which drove point COMl to high voltage charged capacitor C59. Capacitor CS9 will dischaxge through rasistor R23 when Darlington pair XQ5 ~hor~s point-~ ~, B, C, D, E, F to ground. However, diode CR62 blocks a more rapid discharge of capacitor C59 bàckwards through the current transformers. For example, R23 may be a 5k ohm resistor and capacitor C59 may be a O.05 microfarad capacitor, thereby having a time constant of approximately 0.25 millisecond~. When capacitor C59 discharges to ~he point that the positive input ter~inal o~ op-amp U30-A
becomes of lesser potential than thQ negative input terminal of op-amp U30-A, then op-amp U30-A turns "on'i, stopping base driv~ into transis~or Q13. However, ~apacitor C51 was charged to approximately the voltage reached by point COMl during the tran~lent of op-a~p U30-A. Capacitor C51 slowly discharges through r~sistor R135, thereby allowing Darlington pair XQ5 to slowly go out of conduction, thereby allowing point CO~l to rise as the voltages of point~ A, B, C, D, E, - and F are pulled up by the current transformers. As the voltages at points A, B, C, D, E, and F rise, current flow is reestablished to charge capacitors C22, C46, Fig. 15-2.
The slow discharge of capacitor CSl through resistor R135 limits the rise time of the current flow into capacitors C22,C46. Capacitor C51 may be 0.01 microfarad and resistor Rl35 may be lOOk ohm, thereby giving a discharge time of capacitor C51 of approximateIy l.O millisecond~.
After the voltage at point COMl has risen sufficiently to develop 30 volts across tne Zen~r diode, then capacitor c59 reaches a voltage sufficient to drive the positive input terminal of op-amp U30-A in excess of the potential at the negative input terminal, thereby starting the relaxation oscill~tion cycle over again.

Trip Unit Catastrophic Event Trip A "catastrophic event" trip of the circuit breaker is shown in Fig. 15-3 and is provided by the voltage developed acros~ resistor R136. ~ voltage is developed across resistor R136, and thi~ voltage provide~ an output to drive the trip - solenoid driver ~ransistor Q12 through discrimlnator amplifier U30-B. Transi~tor Ql2 is shown in Fig. 15-3. The voltage developed across re3istor R136 t~us provides a very hig~ current, rapid trip o~ the ~ircuit brea~er.
An output signal from the microprocessor U2~ port PC7 pin 21 i~ connected to inhibi~ the cata~trophic event trip. The inhibit signal from the microprocessor provides an opportunity ~or the microprocessor, in th~ even~ o~ a heavy --2g--'~

current surge which is not of "catastrophic" magnitude, to initiate an ordarly trip of the circuit breaker. The orderly trip also permits the microprocessor to output information to the non-volatile memory in ordar to record parameters of the trip The voltage developed across R136 change~ capacitor C53 at point PT1. The voltage at point PTl is amplified by op-amp U30-B, and the output o~ op-amp U30-B drives transistor Q12 into conduction, thereby tripping the circuit breaker "off". When Ull pin 6 is "high", then transistor Q14 is conductive, thereby shorting out point PTl through the internal resistance o~ transistor Q14. In the event that a catastrophic event develops enough current ~low through resistor R136 to drive up the voltage at point PTl even though transistor Q14 is shorted, then op-amp U30-B will develop enough output to drive transistor Q12 into conduction and therèby trip the circuit breaker "off".
- The +13V ssurce from Fig. 15-1 connects to the junction of resistors R139, R142, and may, if the 18 volt source goes too high during a catastrophic event, drive through diode CR65 and drive transistor Q12 into conduction, thereby tripping th~ circuit breaker "off".

TRIP UNIT POWER-UP CO~T~
The 18 volt power source is shown in Fig. 15-1.
~5 operating power i~ obtained a~ poin~ B~C th~ough resistor R5. Zener diode VR1 and shunt regula~or QXl provide an 13 volt source at the positive terminal o~ fil~sr capacitor C3.
Zener diode U5 and resistox R13 provida a precision 2.5 volt source. External power may he applied to tha Trip Unit t~rough jack J5 at pin 5, or at jack J4 pin 1, A plu5 2 4 volt potential applied to either jack J4 or J5 provides a current flow through diode C~7 to the point ~RC in order to power th~ Trip Unit, and the internal impedance o~ the extern~al power source permits shunt regu}ator XQl to regulate point BRC to 18 volts.
Under ordinary ope_a~ing conditions, as current flow to the load begins to build up after a load i5 switched on, the output voltage of the shunt regulator at the 18 volt source will begin to increase from a zero potential toward the 18 volt value.
After the shunt regulator comes into regulation, the 18 volt SOUrCQ will stabilize at 18 volts. Before the 18 volt source reaches l~ volts, the preci~ion 2.5 volt source will stabili~e at 2.5 volts when the potential at point BRC
reaches approximately 3.0 volts.
As load current through conductors A, B, C is turn~d off and on, the voltag~ supplied to the electronics of the Trip Unit may vary. The microprocessor of the Trip Unit U-24 has a short time power supply provided by capaci~ors, C22, C46, and also the microprocessor ~st be properly reset.
Raferring to Fig. 15-2, op-amp UlO-A, transistor U6-A and transistor U6-B provid~ logic si~nals indicative of the status of the 18 volt power source.
The status of the voltage at point BRC, that i5 the 18 volt sourc~, is monitored by op-amp U10-A ~s shown in Fig.
15-2. The 18 volt supply is connected by voltaga divider R68, R69, to positive input pin 3 o~ op-amp U10-A. The precision +~.5 volt source i~ conn~c~ed to the input o~
op-amp UlO A at negative input pin 2. Op amp UlO-A is ;;~O~L9~
powered by th~ 18 volt source at pin 4 of op-amp U10-A. R68 and R69 provide a voltage divider which applie~ a fraction of the 18 volt source to input pin 3 of op-amp U10-A. When the 18 volt source reaches approximately 12.5 volts, then pin 3 o~ op-amp UlO A goes higher than 2.5 volts, and therefore higher than negative input pin 2 of op-amp U10-A, thereby turning op-amp U10-A "off". When op~amp UlO-A turns off, output pin l of op-amp U10-A switches to approximately the voltage supplied by the 18 volt source, and at "switch on"
time pin 1 o~ op-amp UlO-A goes to approximately 12.5 volts.
The 12.5 volts at pin 1 appears as signal PS, and after 2 diode drops, appears as signal PSD. Signals PS and PSD are used to control various chip~ in the Trip Unit. After the 18 volt souxce reaches 18 volts, signal PS reaches approximately 18 volts, and ~ignal PSD reaches approximately 17 volts.
As shown in Fig. 15-2~ the L5.8 volt voltage source i5 provided by transistor Q9. The left side of resistor R76 connects to the precision 2.5 volt source. The 18 v~lt source connects to collector pin 3 of transistor Q9. A
2~ voltage doubler circuit comprise~ op-amp U10-C, resistor R76, resistor R75, and resistor R77. As the power supply comes "on", and precision voltage source 2.5 vol~s reaches 2.5 volts, then op-amp U10-C i3 turned on and develops approximately 5 volts at its output pin B. Op-amp U10-C
turns on transistor Q9, and a~ long as the 18 volt source is above approximately 6 volts, emitter pin 1 o~ transistor Q9 lS at 5.~ volts. E~itter pin 1 of transistor Qg is the source of the voltage indica~ed as L~.8 volt eource. The L5.~ volt source i~ ~iltered by capacitor C31 The PS.8 volt source is provided by op-amp U10-D, transistor U6-D and associated rirCuitry. The L5,8 volt source control~ op amp U10-D to produce approximately 5.8 volts at ita output pin 14. The 18 volt source, through transistor U6~D, generates the P5.8 vo}t source, where the transistor U6-D amplifies the output of op-amp UlO-D.
The P5.8 volt source "switch on" time is controlled by signal PS. The P5.8 volt source switches "on" as the 18 volt sourca reaches approximately 12.5 volts, thereby driving signal PS high. Diode C~36 provides a clamp of the input of op-amp U10-D, where the clamp is controlled by a status circuit comprising op-amp U10-A. Before the power supply 18 volt source voltage rises above 12.5 volts, op-amp U10-A is turned "off" and signal PS is at gr.ound, thereby clamping the lS pos~tive input of op-amp U10-D at pin 12 to ground. After thc 18 volt source rises above 12.5 volts, op-amp U10-A
~ecomes non-conductive, thereby driving signal PS to the vol-tage being supplied by the 18 vo}t sourc~ at that point in time, that is 12.5 vo}ts at the time of transition, and thereby permitting input pin 12 of op-a~p U10-D to rise to the 18 volt source level. Input pin 12 of op-amp U10-D rises to the $5.8 volt value, and thereby switches l10nll the P5.8 volt sourca.
The P5.8 volt source is capable o~ providing oparating current at a voltagQ of 5.8 volts. Th~ P5 . 8 vo~ t source provides current to a number o~ circuit~ in the Trip Unit, including the microprocessor U-240 The L5.8 volt ~ource supplies power at 5.8 volt~ to many of the integrated circuits in the Trip Unit.

In summary, a~ the pow~r supply turns on, the 18 volt source slowly rises, the 2.5 volt precision source, at the positive terminal o~ capacitor C-4, becomes constant at 2.5 volts after point BRC reaches approximately 3 volts.
Final~y, as the 18 volt source value rises above 12.5 volts, op-amp U10-A switche~ to an "oPf~7 state, thereby permitting, through signal PS, op amp U10-D to switch state and begin supplying the P5.8 volt source to microprocessor U-24 and other cir~uits in the Trip Unit.

POWER SUPPLY LOGIC SIGNALS
Two logic signals, LPSL and LPSH, indica~iva of power supply status, are generated by transistors U6-A and U6-B.
Logic signal LPSL goes "low" when the 18 volt source rises above 12.5 volts. As the voltage at the 18 volt source risës from zero towards 12.5 volts, output pin 1 of op~amp UlO~A is-held at ground~ thereby grounding input pin 4 o~
transistor U6 A, thereby holding transistor U6-A "off".
Signal LPSL, taken at the collector of transistor Q2, is held at 5.8 volts by th~ L5.8 voltage sourc~. Logic signal LPSL
goes "low" when op amp ~lO-A turn~ "on" as a result of the 18 volt sourc2 rising above 12.5 volts. That i~, transistor - U6-A is turned "on" by its input pin 4 going "high~. Thus, the signal LPSL switches ~low" when the 1~ volt source goes above 12.5 volts.
Logic signal LPSH goe~ "high" after the power supply 18 vol~ source goes above ~2.5 volts. Signal LPSH is ~'low"
while the 18 volt source voltage is between zero and 12.5 volts, by pin 2 o~ transistor U6-B being held 'thigh" by voltage source L5. 8 volt~. When tran5istor U6-A becomes 2~4~
conducting and grounds signal LPSL, then transistor Q1 is turned "off", driving its collector high, and there~ore driving signal LPSH high by action of the L5.8 volt source.
Power is "good" and the microprocessor U-2~ can operate relia~ly when the 18 volt source reaches 12.5 volt5 . The fact that power is "good" is signaled by signal LPSL going "low'l and LPSH going "high." The 18 volt source goes "good"
after it reaches a potential of 12.5 volts. Fig. 16 is a timing diagram graph and shows logic signal LPSH going high at the time that tha 18 volt source goes "good", and signal LPSL going low at the time that the 18 volt sourc~ goes "good". Also the graph shows the P5.8 volt source switching "on" to 5.8 volts, wher~ the tran~ition is caused by signal PS at the time th~t the 18 volt source goes "good".

lS LPSH means Logic Power Supply High. LPSL means Logic Power Supply Low. LPSH goes high when the 18 volt source becomes "good", or equal to 12.5 volts. LPSL goes low when the-18 volt source becom~s 7'good".

MICRO~ROCESSOR_~ESE~
Microprocessor U-24 i5 reset under control o~ logic signal~ ~PSH, LPS~ and an additional signal 30SC, as shown in Fig. 15-20 Reset of microprocessor U-24 is controlled by op-amp U7-A, op-amp U7-B, op-amp U12-~, and FET transistor Q7. ~icroproc~ssor U-24 is resat by ~irst driving its pin l,RST, to ground ~or a time period of at laas~ 15 milliseconds, and then driving pin 1 "high" and holding pin 1 "high".

, . .

2~
The logic provided by op-amps U7-A, U7-B, U12-D, and the - a~sociated circui~ry, provide~ that microprocessor U-2~ i5 reset when the power is initially ~urned "on", and further that the reset is properly handled in the event that a dip occur-~ in the 18 volt source to a potential beneath 12.5 volts. The potential of the 18 volt source may dip below 12.5 volts as a result of a variety of occurrences, including: disconnection of the load from the power main, a trip of the circuit brea~er, etc... In the event of a trip o~ the circuit breaker, the circuit breaker may reclose within less than 30 seconds.
In the event that the circuit breaker is "out" for less than 30 second~, data stored in RAM of microprocessor U-24 must be preserved. It is desirable not to apply the reset "low" transition to RST at pin 1 until the power supply becomès 'Igood" in order to preserv~ the in~ormation held in microprocessor U-24 RAM. Power is maintained, in a trickle quantity, to Xeep microprocessor U-24 RAM ~alive" by capacitors C22, C46 puttiny microprocessor U-24 to sleep LPSH
at pin 22.
Undar normal operating conditions, power is supplied to operat~ microprocessor U-24 fro~ power supply P5.8 volt source at VDD pin 40 of microprocessor U-24. Power supplied by the P5.~ volt source al~o charge~ capacitor C22, C46 through resistor RSl. Under normal operating conditions, capacitors C22~ C46 are charqed to 5.8 volts. In the event o~ the loss o~ the P5.8 volt source, capacitor C22, C46 discharge through diode CR29 to supply a trickle current to microprocessor U-24 in order to keep the RAM o~
microprocessor U-2~ alive. In the eYent that power to the g~
P5.8 volt source is lost for less than 30 seconds, and then is turned on, the recently turned on P5.8 vol~ source will drive microprocessor U-24 through its pin 40, and will also provide a charging current for capacitors C22, C46. A more rapid charging o~ the capacitors is e~fected through the 18 volt source, the L5 8 V source, op-amp U12-A, and diode CR28.
The reset pulse to thQ microprocessor U24 is controlled by FET transistor Q7. The gate of FET transistor Q7, at its pin 2, is controlled by logic signals LPSL, L~SH, and 30SC.
Signal 30SC is the voltage across the 30 second timing capacitor C42, shown in Fig. 15-3~ The logia signals controlling the gate, pin 2, of transistor Q7 ensure that the proper reset puls~ sequence is applied to microprocessor U24 during both a l'cold" start and a "hot" start. A "cold" start is an application o~ power to the Trip Unit after the uni~
has had po~er removed for a time period exc~eding approximately 30 second~. A ~hot" start is an application of ~leetric power to the Trip Unit after less than 30 seconds have elapsed sinc~ power was last removed from the Trip Unit.

Cold Start A cold start will first be traced through tha logic signals. The ~ignal 30SC will be at ground potential because the 30 second tim.ing capacitor C42 will be discharged. As the 18 volt source rises from ground to 12.5 volts, logic signal LPSH i3 high, and logic signal LPSL gradually goes from low to high. A low value of logic signal LPSH prevents charging o~ timing capacitor C47, and also holds input pin 7 of op amp U7-B at ground po~ential, thereby holding op~amp U7-B '1on'l. With op-amp U7-B held "on~, it~ output pin 1 is ~10~
at ground potential, and thereby holds the gate, pin 2, of transistor Q7 at ground, thereby holding ~ran~istor Q7 "offn. With transistor Q7 off, it's pin 3 is then ~ree to risa to the P5.8 volt voltage source potential value, thereby bringing reset pin RST, pin 1, of microprocessor U-24 "high", that is, to the potential of the P5.8 volt source. The potential of the P5.8 volt ~ource starts at zero potential and gradually climbs until it reaches 5.8 volts as the 18 volt power source potential rises. Also, when signal 30SC is low, then op-amp U7-A is turned "on" as the 2.5 volt source rises in potential thereby drivin~ positive input pin 5 of op-amp U7-A positive. Ou~put pin 2 o~ op-amp U7-A tends to riso in potential, but is clamped by op-amp U12 D. Op-amp U12-D is "on" at the early initiation of electric power by signal LPSL rising positive and turning op-amp U12 D "on".
Op-amp U12-D then tends to drive its output pin 14, and therefore pin 2 o~ op-amp U7-A, to ground when signal L~SL is high.
After the 18 volt source crosses the 12.5 volt threshold, then signal LPSH go~s "high" and signal LPSL goes "low."
When ~ignal LPSH goes "high" capacitor C47 i~madiately charge~ and than tends ~o discharge through resistor R34.
The ti~e constant for capacitor C47 to discharge through resistor R34 is given by the values o~ capacitor C47 and 2~ resistor R34. Capacitor C47 may be 0.47 microfarad and resistor R34 may be 27~ ohms. The RC time constant is then (0.47 *~7) = 15 mllliseconds~ As cap~citor C47 discharges it holds pin 7 of op~amp U7-B "high, " ~hereby driving output pin 1 o~ op-a~p U7 B "~igh~. Pin 1 o~ op-amp U7~ drives gate pin 2 of transistor Q7 "high," ther~by turning transistor Q7 2~
"on." Output pin 3 of transistor Q7 is dxiYen to ground as transistor Q7 comes "on," thereby driving input pin 1, signal RST, o~ microprocessor U24 "low". Pin RST of microprocessor U24 is held 'tlow" for a time given by the discharge time constant o~ capacitor C47, R34. Input pin 1, ¢ignal RST of microprocessor U~4, is held "low" for approximately 15 millisecondæ. After capacitor C47 discharges to below the 2.5 volt precision voltage source connected to input pin 6 of op-amp U7-B, op-amp U7-B turns "on," thereby grounding output pin 1 of op-amp U7-B, and grounding input pin 2 of transistor Q7, thereby turning l-off'1 transistor Q7. Transistor Q7 turning "off" permits a transition o~ signal RST toward the P5.8 volt source, there~y driving signal RST "high."
M.icroprocessor U24 is initiated by tha sequence of driving its pin 1, signal RST, low for approximately 15 millis~conds and then driving it high and holding it high. Therefore, the sequence resets microprocessor U24, and starts it operating at its "start up" memory location.
Simultaneou~ly, with signal LPSH going high, signal LPSL
g~es low. A low value of siqna} LPSL applied to input pin 12 of op-amp U12-D turns "o~" op-amp U12-D thereby causing pin 14 to appaar aq an open circuit to the circuit to the right of re~istor R35.
Within approximately 0.5 seconds from reset of 2~ microprocessor U-24 si~nal 30SC, applied to input pin 4 of op-amp U7-A, will go hiqh. Thirty second timing capacitor C42, shown in Fig. 15-3, charge~ undar the control of the softwar~ in ~icroprocassor U24 ~rom ~he L5.8 volt power supply through electronic swi~ch U11. Electronic switch Ull, shown in FigO 1~-2 i~ driven by output port PC7 at pin 21 of 2~

microprocessor U24, as shown in Fig. 15-2. Charging current for both 30 second timing capacitor C42 and 5 minute timing capacitor C36 is controlled by switch U11l and capacitor c42 chargeR thro~gh signal MCS 1, and capacitor C36 charges through signal MCS 2. The chargin~ time constant for 30 second capacitor C42 is given by the capacitance of capacitor C42 and the resistance of resistor R98. The capacitance o~
C42 may be 47 microfarad and the resistance o~ R98 may be 10K
ohms giving a time constant of 0.47 seconds. Thus, in approximately one hal~ second, capacitor C42 will be charged to approximately 63~ of 5.8 volts and signal 30SC will go "high" in approximately 1 second to 2 seconds.

Hot Star~
The sequence of events in a "hoti' start will now ~e traced. A hot start is a situation in which power has been appliad to the apparatus for a period of time, and a power loss is suffered, where the 18 volt source is below 12.5 volts ~or less than 30 seconds. As the 18 volt source drops below 12.5 volts, op-amp U10-A has its positive input pin 3 driven below the 2.5 volt potential at which its negative input pin 2 is connected. Op-amp U10-A therefore undergoes a transition and b~comes conductive as tha 18 volt supply drops through 12.5 volts, there~y driving signal LPSL "high" and driving signal LPSH "low". How~ver, slgnal 30SC remains "high" for approximately 30 ~econd~, or for the time required for 30 second ti~ing capacitor C42 to discharge to less than th~ 2.5 volt potent~al applied to input pin 5 of op-amp U7-A. ~he discharg~ o~ capacitor C42 occur~ through resistor .....
~0 )4~
R108, and C42 ~ay be 47 microfarad and R108 may be 1.0 megohn~ giving a discharge time constant of 47 seconds.
Signal LPSH is low, and SQ op-amp.U7-B i5 "on," holding output pin 1 at ground. Signal LPSL is "high" and so turns "off" op-amp U12-D thereby driving output pin 14 of op~amp U12-D "high," and this condition attempts to drive transistor Q7 "on." However, signal 30SC prevents transistor Q7 from being driven "on" by the high v~lue o~ signal 30SC driving op-amp U7-A into conduction and thereby grounding output pin 2 of op-amp U7-A, thereby preventing the "high" value of signal LPSL from turning on transistor Q7.
In the event that power returns within 30 seconds, or before the internal RAM of microprocessor U24 goes "bad,"
then signal ~PS~ goes "low" and signal LPSH goes 'Ihigh".
When signal $PSH goe~ high, capacitor C47 charges quickly, and discharges slowly through resistor R34, and thereby applies an approximat~ly a 15 millisecond "on" pulse to turn transistor Q7 on for approximately lS milliseconds. There~y, sig~al RST at pin 1 o~ microprocessor U-24 is grounded for approxi~ately 15 milliseconds. At tha expiration o~ the approxi~ately 15 millisecond time period, input pin 2 o~
transi~tor Q7 goes low, thereby turn~ng "of~" transistor Q7 and~driving signal RST high and resetting microprocessor U24, and the microprocessor begins running at its "start up"
memory location.
Power ~oss_and Reset State of ~ic~oprocessox The microprocessor U24 is put into ~n " ~leep" state when ~he 18 volt power supply goes below 12.5 volts, as follows.

Siqnai LP~H goes "low" as the 18 volt source goes below 12.5 volts, and signal LPSH is connected to microprocessor U24 at : port PC6 pin 22. The microprocessor background code tests port PC6 periodically, for example, once each millisecond, and exscutes a "put to sleep" subroutine in the event that signal LPSH goes "low". The "put to sleep" subroutine stores critical data in the internal RAM o~ microprocessor U24, converts outputs to inputs in order to preven~ current drain through external peripheral deviceq, and then executes a STOP
instruction. The CPU of the microprocessor U24 then stops running. However~ the data stored into tha lnternal RAM is preserved by the power supplied by C22, C46. The external clock pulses applied to the microprocessor at port OSCl pin 39 are gated -off'l internally in the microprocessor. The ext~rnal clock may die from lack of power, but a sputtering dying of-the clock is immaterial to preservation of data stored in the internal RAM because the microprocessor U24 is halted and the clock pulses ar~ gated lloff".

Bus Disable - IBEL
-~ 20 The internal RAM of microprocessor U24 may be maintained "good~ by ~he trickle current supplied by capacitor C22, C46 connected to connection VDD, pin 40, of micr~processor U24.
However, it is necessary to di~able the bus D0...D7 from port PA0...PA7 o~ microprocessor U24, or load on the data bus will draw too much current from capacitors C22, C46/ thereby discharging the capacitors too quic~ly. A bu~ disable signal `

z~
is labeled IBEL. The I~EL signal is generated approximately 5 milliseconds after LPSL goes low. IBEL is generated by op-amp U27-D, resistor R33 and capacitor C18, a~ shown in the upper left corner of Fig. 15-2. Signal LPSL goes low when the power supply becomes "good", causing'capacitor C18 to discharge with an approximately ~ millisecond tim~ oonstant through resistor R33. After positive input terminal pin 11 of op-amp U27-D goes lower than the 2.5 volt potential which negative input terminal pin 10 is connected to, then op-amp U27-D beco~es conductive driving output pin 13 to ground.
Therefore, ~ignal IBEL taken from output pin :l3 of op-amp U27-~ is driven "low". A "low" IBEL signal enables the chips connected to the bus, including U21, and U22, on Fig. 15-2, and on Fig. 15-3 U13, and on Fig. 15-4 U28. Other chips connected to the bus are enabled by other logic signals, for example, U14 and U17 by signal LPS~.
A high IBEL signal disables the chips, and IBEL goes high when signal LPSL goes "high'l upon transition of the 18 volt source to le~ than 12.5 volt-~. It is necessary to disable th~ chips connected to the bu~ during the time period that microprocessor U24 is energized from the trickle po~er supply provided by capacitors C24, C46, in order to prevent a large current flow fro~ capacitors C22, C46 into the bus and through one of the chips to ground.
Also a bus enable signal connects to the ~icroprocessor U24 at por~ PC3, pin 25.

Unit Cur~e~-signals Referring to ~ig. 15-1, signals to the microprocessor giving measures o~ current ~low are ~aken fxom points A, A', 2~ )at9~
and B, B', and C, C' for measures o~ current flow in individual phasesO An output for the maximum phase c~rrent is taken between points MOBR and BRC. "BRC" stand~ for breaker co~mon. A ground ~ault signal is taken between points GFBR and BRC.
op-amp Ul-A has inputs connected to points MBR and B~C, and produces an output voltage proportional to maximum phase current. op-amp Ul-B, diode CR8 ~nd resistor R14 and capacitor C5 form a peak detector for the maximum phase current. Transistor Q2 provides a charge dump for capacitor C5. Transistor Q2 is controlled through lts ~ate electrode pin 2 by signals which will be described hereinbelow.
Op-amp U3-C has inputs connected between points GFBR and BRC" at its output provides a voltage proportional to ground fault current. Because the SUM transformer i5 1 to 5 rather than 1 to 10, the ground fault signal is proportionally largèr than the phase fault signal produced by op-amp U1-A.
:
A peak detector is formed by op-amp Ul-D, diode CR10, resistors R18,Rl9 and capacitor C7. Transistor Q3 provides a - 20 dump for discharging capacitor C7. Transistor Q3 is controlled by it~ gate electrode at pin 2, as will be described hereinbelow.
Op-amp U2-A has inputs connected to A, A' and generates at its output a voltage proportional to current ~low in phase A. A peak detector i~ ~ormed by op-amp U2-B, diode CRll, resistor ~20, an~ capacitor C8~ A dump circuit for discharging capacitor C8 i~ fo~med by op-amp U4-B. Dump op-amp U4-B i~ controlled by signals a~ its pin 6, as will be described hereinbelow.

-~3 op amp U2-C ha~ inputs connected to point~ B, B', and provides a voltage at its output proportional to current flow in phase B. A peak detector is for~ed by op-amp U3-A, diode CR20, resistor R27, and capacitor C12. Op-amp U4-C provides S a dump circuit for discharge of capacito~ C12.
Op-amp U2-D has inputs connected to point C,C' and an output providing a voltage proportional to current flow in phase C. A peak detector is ~or~ed by op-amp U3-B, diod~
CR21, resistor R29, and capacitor 13. Op-a~p U4-D is a dump circuit for discharge o~ capacitor C13. Transistor Q6 provides control of the dumping elements, transistor Q2, transistor Q3, op-amp U4-B, op-amp U4-C, and op-amp U4-D.
Op-amp U4-A, working in conjunc~ion with op-amp U6-C, whicp is connected as an approximately 3 volt Zener diode, provide~ control of dumping transistors Q2 and Q3. Also, op-amp U6 C provides control of dumpinq op-a~ps U4-B, U4-C, and U4-D. Also, control of the dumping units is provided by lin ~OD ~rom sheet 3 latch U14 at pin 15, as will be descrihed more fully hereinbelow.
A3 shown in Fig. 15-3, input to the microprocessor from an~log ~ignals is provided by analog to digital converter U13. Varlou~ analog units ar~ switched, under control rrOm the microprocessor, to an input o~ the analog to digital converter 13 by multiplexer U9. Input from maximum phase peak detec~or at the positive sid2 o~ capacitor CS is provided to multiplexer U9 at pin 17, input Y0. ~nput fro~
the ground ~ault peak detector from the positive terminal capacitor C7 i~ provid~d the multiplexer U9 at its pin 18 at input Yl. Input from th~ A phas~ peak detector ~rom the positive texminal o~ capacitor C8 i~ provid~d to m~?ltiplexer -44~

- U9 at its pin 16 input Y3. Input ~rom the B phase peaX
detector fr~m the positiYe terminal of capacitor C12 is provided to multiplexer U9 at its pin 1, input Y4. Input is provided ~rom the C phase peak detector at the positive terminal capacitor C13 to ~ultiplexer U9 at its pin 6, input Y5. ~ test signal input to multiplexer U9 is provided at te~minal 19 input Y2, as will be described herein below in the section describing the Test Set.
Two further inputs to multiplexer U9 are provided at its pins 2 and 5, inputs Y6 and Y7 to provide a power down history. Long term power-down history is provided by capacitor c36 and resistor R97. Capacitor C36 may be 47 microfarad and resistor R97 may ba 10 megohms, giving a time constant of approximately 470 seconds, or approximately 8 minutes. Capacitor C42 and resistor R108 provide a short time power-down history. Capacitor C42 may be 47 microfarad and resistor R108 may be 1 megohm, giving a time constant of approximately 47 seconds. During po~er-up operation of the electronics, capacitor C36 is charged, and also capacitor C42 2 0 i5 charged. In the event that the circui~ breaker trips "of~" the load charging current to both C36 and C42 ceases.
Capacitor C36 then commance~ discharg~ through resistor Rg7, and capacitor C42 commences discharge through resis~or R108. When th~ circuit breaker is again powered up, the microprocessor measure~ ~he voltag~ at points Y6 and Y7 of multiplexer U9, and digitizes these voltages by analog to digital conv~rter U13. By measuring the voltage across c2pacitor C36, and the ~oltage across capacitor C42, the microprocessor i~ capabl~ of determining t~ length of time that the circuit breakar ha~ been powered -O~fl'. The -~5 z~
microprocessor may then compare the measured time with a predetermined time and other information which was read into non-volatile memory, and trip "off" the circuit breaker i~ it has not been '-offl1 ~or a sufficiently long time, or initiate other appropriate action.
Multiplexer U9 s~rves as a number of electrically controlled switches. Each of its inputs may be connected to the output, mar~ed COM at its pin 4. Which input is connected to the output COM is determined by voltages applied to lines A, ~, and C. Lines A, B and C connect to a microprocessor data bus. Lina A connects to data bus D0, line B connects to data bus lins Dl and line C connects to data bus line D2. Line LE, pin 11 o~ multiplexer U9, connects to microprocessor U24 at its pin 14, port P B2.
Analog to digital converter (ADC) U13 is an 8 bit analog to digital converter. ADC U13 has an input at its pin 6, VIN, from ths COM output of multiplexer U9. op-amp Ul-C
provides amplification of the signal. Integrated circuit U11 provides switching und~r the control of the microprocassor U24 which control~ the yain o~ op-amp U1 C.
A~C U13 pxovides digital output on the data bus, at lines D0, Dl, D~, D3, D4, D5, D~, and D7~ Control of ADC U13 is provided by tha signal ADRDL provided by ~icroprocessor U24 at its port PB~, at pin 16.
Op-amp Ul-C, Fig. 15-3, provide~ our l~el~ of adjustable gain ~or tha analog ~ignal appearing at multiplexer Ug output CO~. ~hereby, an auto-ranging algorithm ad~ust~ the si2~ of tha signal applied to ADC U13 input VIN at it~ pin ~. Switch Ull actually controls the gai~ o~ amp U1-C. Latch Ul~ controls switch U11 through ~04~3~
input from data bus D0...D7 and the DL ChR signal, and through outputs Q6,Q7 at pin~ 16,19 of Latch U14.
Output from microprocessor U24 is provided by latch U14.
L~tch U14 takes output from data bus line D0, Dl, D2, D3, D4, D5, D6, and D7. Control o~ latch Ul~ is arcomplished by signal DLCLR provided by microprocessor U24 from its port P
B3 at its pin 15. Signal DLCLK commands Latch U14 to accept input from the data bus and to direct that output to an appropriate output port of latch U14.

TriP Unit Serial Communication~
Output serial communications are provided at microprocessor output port PD1 at pin 30. The LED at pins 1.2 of optoisolator U26 i~ driven by the P5.8 volt source and port PDl. Port PDl acts as a switch to ground and i5 either "open" or "closed" under control of microprocessor U24. The photodiode at pins 4,5,6 of optoisolator U26 provides switch op~rations between "closedl' and "open". Data bi~s are sent one 8 bit BYTE at a time durin~ each 12 millisecond loop - through the main software loop. The bits are sent at a 9600 baud rate.

T~i~ Uni~ Mic~Qprocessor Peri~erals Circuit U2S is a non-volatile memory. Clrc~ait U25 is accessed by microprocessor U24 through ports PD4, PD3, and PD2, at microprocessor pins 31, 32, 33. Non-volatile memory U25 also has an input from signal PB7 from microprocessor U24 at lts pin 13.

z~
Th ~icroprocessor clock is made up of the crystal controlled oscillator comprising crystal Yl, and integrated circuits U15-A and U15-B, The clock generate3 a 3.6864 megahertz pulse sequence. The clock signal is then input to microprocessor U24 at its input OS~l at pin 39O
Divider U16 also accepts an input ~rom the cloc~ at 3.6864 megahertz. Divider U16 divides the input clock signal by ~ factor of 8, and produces an output signal of 460.8 kilohertz. The output pulse stream of divider UlS is connected to the clock input of analog to digital converter ADC U13 at pin 4 of U13. The input CLK at pin 4 of U13 provides clock pulses for ADC U13's digitization.
The switch array shown in Fig. 15-4 is mada up of switch S1, S2, S3, S4, SS, S6, S7, S8, and rPsistors RP6. Switches Sl... S8 appear on the Trip Unit circuit board as shown in Fig. 2. Seven of the switches are controlled by ~nobs on the Trip Unit control panel, as sho~n in Fig. 3.
Switch S1 controls the time delay for the long time delay, LTD.
Switch S2 controls the current for the lang time pickup, LTPU.
Switch S3 controls tha time delay ~or the short time delay, STD.
Switch S4 controls current ~or short time pickup, STPU.
Switch S5 co~trols time delay ~or the ground fault pickup, GF~.
Switch S~ controls current for the ground fault pickup, GFPU.
Switch S7 controls current ~or the instantaneous pickup, IPU.

2~

Swltoh S8 ~ontrols a predetermined.
A switch that is not connected to a front panel knob, is set at the factory.
Resistors RP6 define the potentials o~ bus lines S~O.. ..sC7.
The switches raad out to a data bus having lines marXed SC0.. ..SC7. These lines are switched to data bus DO, D1, D2, D3, D4, D5, D6, and D7 by latch U28. Latch U28 is controlled by signal PCO derived from microprocessor U24 at lts port PCO, pin 28, and also the IBEL signal.
Multiplexer U29 controls which switeh transfers its information to microprocessor U24 through latch 28.
Multiplexer U29 is controlled by the microprocessor through data bus lines DO, Dl, and D2. Operation of multiplexer U29 is further controlled by signals PCO and PCl from microprocessor U24 from ports PCO and PC1. Multiplexer U29 is controlled at its pin 8 by signal PCO, and at its pin 11 by signal PCl~ Power-up control signal LPSL controls mul.~iplexer U29 at its pin 7.

A~ shown in Fig. 15-2, input com~unications o microproceqsor U24 are pr~vided through latch U21 from either a Display Unit or a Local Management Unit through ~a~k J5, or a universal test set through jack J4. Latch U21 is controlled by microprocessor U24 at its por~ PC4, pin 24 by connection to latch U21 at its pin 1. Latch U21 permits transfer o~ da~a from da~a bu~ D0, Dl, D~, D3, D4, D5, D6, and D7 to output ~ack J4 or J5. Also, resistor network RP4 provid~ a potential source ~or the output line Al, ~2, A3, A4, A5, A6, A7, and A8. Latch U21 permits tests to be run on the Trip Unit ~rom a variety of external equipment, including an LMU, a DU, or a universal test set.
Microprocessor U24 reads the rating plug through jac~
J6. ~atch U22 permits connection of data bu~ D0~..D7 to jack J6 to read the rating plug and the jack J4 plugs at pins 9, 1~, 11.
As shown in Fig. 15-2, the presence of Jumber JMP-l in~icates that the hardware i~ a circuit breaker trip unit, and the absence of JMP-1 indicates that the hardware is a motor protector.
The presence o~ Jumper JMP2 inhibit~ the internal self test program and the absence of ~MP2 enables the internal self test program.
Resistors RP4-A are pull up resistors to define the potentials on the input lines to switch U21. Resistors RP4-B
are pull up resi~tors to define the potentials on the input line~ to switch U22. As shown in Fig. 15-4, resistors RP6 are pull up resistors to define the potentials on the switch line~ which ser~a as inputs to switch U28.
- 20 Switch S9 has three single pole switches which can be used to ground lines connected to pin~ 3, 4, 5 of latch U22.
The single pole switche3 are used to indicate the calibration o~ thQ sensor used with the hardware as i set out in the table of Note 2 in Fig. 15-1.

-5~-TRIP UNIT SOFT~IARE
Power Up Code Fig. 17 shows a block diagram of the overall computer program ~low. Microprocessor operation begins with the receip~ of a hardware power-up signal. k~ hardware power-up signal is generated by the "power up sequence control". The power up sequence control provides a reset pulse to microprocessor U24, and also provides reset pulses, such as signal LPSH, to other elements of the circuit, as is discussed in greater detail hereinabove.
Upon receipt of the power-up signal, tho "power-up code"
program block is executed. Figs. 22B, 22C are a flow chart for the "power up code" block. The power-up code sequence block first determines the type of start: the t~p~ may be:
lS ;1. Cold Start A cold start is a start in which no power has been àpplied to the apparatus for a time greater than five minutes.
2. Warm Start A war~ ~tart i5 a start in which power has been applied within the last five minutes to the apparatus.
The "power-up code'~ selects a cold start or a "hot start"
by perfor~ing the following functions:
Initialiæe the microproces or by setting input and output ports to appropriate states; define a clock rate for the communication ports; initializ~ external hardware which needs to ba initialized; resets variou~ latch controls; reset front~nd an~log multiplexer Ug: set buf~e~ amplifier Ul-C
gain control by s~ing the switche~ of controllable swi~ch U11, checks three power loss hlstory indicators~ (13 capacitor C3~, a "5 minute 105s timer", ~2) capacitor 42, 2 "30 second'~ power loss timer; (3) capa~ltor C22 and C46, which are power hold capacitors.
Functionally, capacitor C42, C46 provide a power sourca for microprocessor U24 in the event of a power failure.
Microprocessor U24 power is supplied through pin 40 at port V~D. Port PD5 is tied to port VDD, by pin 34 being tied to pin 40, in order to hold pin PD5 high for signalling purposes to the microprocessor U24. Power is supplied to pin 40 of microprocessor U24 from voltage source L5.8 volts thxough op-amp U12-A. Capacitor~ C22, C46 are charg~d by the output of op-amp U12-A. Current flow through diode CR29 supplie~
ordinary power to microprocessor U24 while the unit is in a powered-up stage. In the event o~ th~ loss of voltage on the L5.8 volt line, capacitors C22, C4~ discharg~ through diode CR29 to supply power to microprocPssor U24 at pin 40. When capacitor C22 and C46 are fully charged, they are capable of operating ~icroprocessor U24 for a tim~ period of approximately 30 seconds, if microprocessor U24 is in a "low power" operating stateO Microprocessor U24 i~ driven into a "low" power operating state through signal LPS~ going low at pin 22 port PC6 of microprocessor U24, and LPSH goes "low"
when ~ha 18 volt source goes below 12.5 volt5.
In executing "power-up", the microprocessor first m~asures the vo}tage by looking at the output of comparator U27-A, sho~n in Fig. 15-2. The voltage at the positive terminal of capacitors ~22, C46 is compared with the 2.5 volt supply by op-amp be read by microprocessor U24, and therefore a measurement made by U24 to deter~ine i~ capacitor C22,C46 aro charged to a voltag~ in exces~ o~ 2.5 volt~. In th~
event that capacitor~ C22, C46 ar~ not charq~d to excess of -5~

2.5 volts, "Save" registers of microprocessor U24 are erased. In the event that capacitor C22, C46 are charged to excess of 2.5 volts, a~ determined by "power-up code", the microprocessor register values are retained.
"Power-up code" then proceeds to m2as~re the voltage on 30 second timer capacitor C42 by commanding multiplexer U9 to connect its input Y7 to its output COM, and co~manding ADC
U13 to digitize the capacitor C42 voltage and read the output to data bus DO...D7. Upon completion of digitization of the capacitor C42 voltage, ADC U13 interrupt output at pin 5 provides a signal to microprocessor U24 pin 36 at port PD7, thereby signalling microprocassor U24 that the digitization by ADC U13 is complete.
Certain accumulators of microprocessor U24 must be retained for power losses of 30 seconds or less, and the accumulator value i~ discarded in the event o~ power losses in excess o~ 30 secondsO Therefore, the accumulators are cleared in the event that capacitor C42 voltage has decayed to less than 2.5 volt~. If the measured value of capacitor C42 voltage excaeds 2.S volt~, then the appropriate accumulator values are retained.
Th~ microprocessor next r~ads the voltage of 5 minute timer capacitor C36 by directing multiplexer U9 to connect its input terminal Y6 to it~ output te~minal COM, and ?5 commanding ADC U13 to digitize the voltage of capacitor C36.
Upon comple~ion of the digitization, ~DC U13 provide~ the digiti~ed information on the data bu~ and s~ts ~n intexrupt flag on its intsrrupt INT output line at pin 5. C~rtain cumulators must be reset in accordance with the measurement o~ the voltage o~ 5 mirlute timer C36. For examplP, if an ( ~--.-. acc~mulator has accumulated a value greater than one-hal~ the : total trip accumulation Yalue, and the power was lost for less than five minutes, the accumulator ~ay be set to substantially 0.5 of the programmed accumulator trip value.
In the event that power wa~ lost for moro than five minutes, accumulatoxs may be set to zero.
Capacitor C30 and op-amp U27-B provide a 35 millisecond timer to input pin 6, input A5 o~ latch U21. "Power-up code"
reads output pin Y5 of switch U21 in order to read 35 millisecond timer capacitor C30. Comparator U27-B gives a logical high signal on input pin AS of switch U21 in the event that 35 millisecond timer capacitor C30 retains a potential in excess of 2.5 volts. In the event that power-of~ has been for 35 milliseconds or less, the microprocessor i5 instructed to retain all registers, if RSC
is good, that is, power hold capacitor C22, C46 are charged.
~he RSC test indicates that the apparatus has been up and running before the 35 millisecond power loss. Since capacitor C2~, C46 are capable of operating microprocessor U24 ~or up to 300 milliseconds, all registers retain valid data in the event that the power outage was for less than 35 milliseconds.
In tha event that ~SC tests bad for a power loss of 35 milliseconds or less, ths indication is that the apparatus wa~ no~ "up and running" before the 35 millisecond power los , and so the contents of all registers of microprocassor 24 are discarded.
Next, "power up code" read~ switche~ Sl, S2, S3, S4, S5, S6, S7, and S8, a~ shown in Fig. 15-4.

-~4-2~0~

Switch Sl gives the long time delay LTD. Switch S2 gives the long tim~ pick-up LTPU. Switch S3 gives tha short time delay STD. Switch S4 gives the short time pick-up STPU. Switch S5 gives the ground fault delay GFD. Switch S6 gives the ground fault pick-up GFPU. Switch S7 giYes th8'` instantaneous pickup IDU. Switch S8 gives PUPU. Switch S7 is read to give the instantaneous pick-up value. ~he instantaneous pick-up delay time is ~ixed at a particular ti~e, for example, it may be lO
milliseconds.

The switche~ Sl... S8 are read by microprocessor U24 commanding analog multiplexer U29 through data bus lines DO,Dl,D2 and through signals PCO from port PC0, signal LPSL, and signal PCl ~rom microprocessor port PC1. Switch U28 is turned on by si~nal PC0 ~rom microprocessor port PC0. The switch settings axe then read on data bus line DO... D7~
Microprocessor U24 next clears and resets particular - bytes depending upon the results of the tests of the various "power down" history timers.
The cod~ then distinguishes between the breaker closing into a fault 3ituation, and secondly, a fault developing after the brea~er closed.
. Following the "power-up code", th~ program starts a 1 milIisecond timer. A d~vic~ driver routine recognizes the timar inputs generated by the 1 microsecond timer. The device driver initiates operation o~ tho front end multiplexer U9 Fig. 15-3, by commanding it, on signal AML~
fro~ microprocessor U24 port PB2, pin 14, and commanding it to read da~a bus lin~s DO, D1, D2. Upon ~ompletion of an analog to di~ital conv~rsion by ADC U-13, ADC U13 generates an interrupt ~ignal in its INT output at its pin 5. The -5~-2~
interrupt signal interrupts microprocessor U24 at its input port PD7 a~ pin 36. Transistor Qll controls interrupt port IRQ of microprocessor U24 at its pin ~ in order to prevent an erroneous interrupt on power-up. The 1 millisecond timer causes current measurements of the max phase current and the ground fault current to b~ made eY~ry 1. 0 millisecond.
Next, the program starts the 12 millisecond timer. The 12 millisecond timer is an overflow timer and runs for 142 milliseconds, that i5, until the byt2 fills up with FFF. The timer generates variouq interrupt signals such as a 10 second signal and a 10 minute signal. The 12 millisecond timer control~ the main code timing.
After initialization of the 12 miilis2cond timer, the "power up code" waits Z milliseconds. At the expiration of 2 milliseconds, the "po~r up code" enters the main code as shown in -Fig. 17. Upon completion o~ the main code, the program waits for the expiration of 12 milliseconds from the !
time of entering th~ main code. At the expiration of 12 milliseconds, the program again executes the main code. This 12 millisecond loop is repeated forever, or until power is lost by the electronic3.

Main Code The internal`steps of the "main code" are shown in Fig.
19. Operations of the "main code'l are broken up into ~
tasks. Task #1 through task ~8. Also, th~ 12 ~illisecond ~imes ar~ shown.

TasX, 1 Task 1 sends a BYTE to tha serial communications interfac~ ~or transfer ~o a Local Manag~ment Unit or other -5~

- Z~4~3~
device. The serial communications interface is driven by port PDl at pin 30 of microprocessor U24, as shown in Fig.
15-2. When pin 30, port PDl, goes low, current flow occurs through the light emitting diode o~ optocoupler U26. When current ~lows through optocoupler U26, from pin 30 of microprocessor U24, an output signal is generated at pins 4, 5, and 6 of the optocoupler, U26. Signals RNVCC, TD0 and TDR
are directed to output jacks J5, J4, and TB4 from pins 4, 5, and 6 of optocoupler U26. These output signals provide communication from the Trip Unit to other equipment. The other equipment may consist of, for example, a Display Unit DU, or a Local Management Unit, LMU, or a remote indicator unit, RIU.
Each time ~he program passes through the "main code", task ~l transmits a byte out through the serial communications port. The proper byte to be transmitted is - asse~bled from the last pass of ~he program by task #7, to be discussed ~urther hereinbelow~

Task Ths progra~ entars task #2 upon the completion of task #1. In tas~ #2 the square o~ the current is cal~ulated from the peak phasa measurement, as obtained from diode bridge CR1 and the peak detector capacitor C5.
The program reads a jumper JMP out in ord*r to determine if it should act as a circuit breakar or act as a motor protector.

-5~-Task 3 The program enters task #3 upon the completion of task #2. Task ~3 accumulates the square of the current for the long time function, in the event that the measured peak current exceeds a ~raction of ~, for which accumulation for the long time function begins. The fraction of P is input ~rom switch S2, LTPU when the program reads the switches through multiplexer U29. The accumulator accumulates the values of peak phase current on each pass _hrough the main program. Switch LTD, the long time delay, selects a value from a table stored in software. The accumulated value i~
compared against the table value selected by switch LTD. In the event that the accumulated value exceeds the table value, task #3 activates the "long tima trip routine". The "long time t~ip routinei' ultimately activates trip coil drive transistor Q12. Trip drive transistor Q12 is driven into conduction by an output signal from microprocessor U24, through switch U17, at port Q0 at pin 2 of U17.

Task 4 The program enters task ~4 upon completion of task #3.
At task #4 the program executes the short time trip. The short time trip may be either with:
I2T=Constant or may be for a fixed time delay. Th position of switch STD, S3 read by ~ul~iplexer U29 determines t~e short time delay characteristic. I thQ maximu~ phase measurement exceeds a threshold detenmined by LTPU switch S2, controlled by multiplexer U2~, value~ o~ ~quared current are accumulated in the short tima accumulator. Position~ o~ switch STD S3 determine whether I2T equal~ a constant or a ~ixed time delay i5 employed. The position of ~witch STD S3 directs ~he program to look up table values for comparison against ~he accumulated value. In the event that the accumulated value exceeds thQ table value, then task #4 actiYates the short time trip routine. The short time trip routine results in the trip coil being activated by initiation o~ conduction of trip driver tran~istor Q12.

Task 5 The program goes to tas~ #5 upon completion of task #4.
In task #5 ground faul~ pickup and ground fault delay are executed. The square of the ground fault current i5 acc~mulated in a ground fault accumulator. The ground ~ault current is compared with a fixed delay or an (I2T =
const~nt) type delay, much like the short time delay in task #4. In the event that the accumulated value exceeds a threshold value pointed to by settings of switch GFD,S5, in a table, then task # 5 initiate~ t~e ground fault trip routine. ~he ground fault trip routines results in snergization of the trip solenoid and tripping of the circuit break~r into the "Off" position.

Task 6 The program enters task #6 upon completion of task #5.
Task #6 1~ a self-te~t function. Ths self-test function has two ~ode~ o~ operation:
Moda 1 i~ an internal self-test;, Mode ~ is an external sel~-test.

~0 f z~
The program normally exe~utes Mode 1, the internal self-test function unless an external test set is plugged into the Trip Unit, in which case the external test overrides the internal self-test. An external test unlt may be the Display Unit or a ~ocal Management Unit, DU or LMU.
In the internal self test under normal operation of the program, Task #6 checks a nu~ber of functio~ls including:
The analog to digital conver~er U13 shown in Fig. 15-3, is tested. The analog to digital converter is tested; first, by applying a ground voltage to the analog to digital converter, ADC U13. The ground voltage is applied by opening switch ENB o~ multiplexer U9 under control from microprocessor U24 through switch U14. The switch U}4, controlled by signal ENBl at pin 7 of multiplexer U9, opens lS the circuit to output COM under control of signal of EN81 at pin 7 of multiplexer U9. When switch ENB is open, r~sistor R88 gives a ground input to ADC U13 at its pin 6. The sel~-test prosram of task #6 checks the reading from the ADC
against it~ i~tended value of zero. In the event that the value di~agree~ by more ~han the allowable amount from zero, the progr~m display~ an error message and may trip the - breaker.
The ssl~ t2st function then applies 5 volts to th~ ~DC
input by measuring th~ voltag~ acros~ 30 second timer capacitor C42. Tha voltage across capacitor C42 is available to multiplexer U9 at it~ input Y7, at pin 5, and this input is connected to COM in order to apply a 5 volt output signal to output COM of multipl~xer U9. The output o~ ADC U13 is compared with it~ expected valuQ by ~icroprocessor U24. In 30 ~ the event that the measured v~lue disagree~ with the expected o60--by more than an allowable amount, the microprocessor U24 displays an error message and may trip the breaker.
The test function, task #6 sets a good or bad flag. If the zero volt test is bad, task #6 sets a "bad" zero volt flag. If the 5 volt test i~ bad, task #6~sets a "badl' 5 volt flag.
Task ~6 performs additional tests. Next, 'cask #6 compute~ 80% of the latPst peak phase current measurement.
The 80~ value of the latest peak phase current measurement is compared with the latest current measurements ~or phase A, phase B, and phase C. One phase must be greater than the 80%
of peaX phase current, or there i9 something wrong with the analog front end of the Trip Unit. Task #6 signals the 80%
test by the use of an 80% flag. The 80% ~lag is s~t to "good" if the test is good, and the flag is set to "bad" if no phase is greater than the 80% of peaX phase current measurement.
~Next, the self-test function section computes 120% of the latest maximum phas~ current measurement, and compares this 120% value with the latest value3 measured ~or phase A, phase B, and phasa C. All phas~ values must be less than the 120%
~ax phase current measurement, or there i5 a problem with the analog ~ront end. Task #~ uses a 120% flag to signal the results o~ this test. In ~he event that all phases are good, the 120$ flag i~ set to l'goodn, and if a phase i~ had, the 120% flag i5 set to "bad!'.
Next, task ~6 compare~ the 120~ of max phase curr~nt measurement with th~ latest grol~nd fault current measurement. The ground fault current mea~urement must be les~ than 120~ of peak phasa curr~nt, or t~ere is a problem L~

with the analog front end of the apparatu The ground fault test signal~ with a yround fault flag. Th~ ground fault flag is set to "good" if the test is passed~ and is set to "bad"
if the the tes~ is not passed. The above ~eries of tests are repeated every 12 milliseconds.
An external test may be performed on the apparatus ~y an operator utilizing a Display Unit, DU, or a Local Management Unit, LMV. The DU or LMU supplies test voltages to test the unit. A request ~or external self-test comes in on control line~ S W, SD1, SD2 in plug J4 or J5 to switch U21, as shown in Fig. 15-2. A test voltage is applied through jack J5 and is la~eled VTST and i~ applied to terminal Y2 of front end multiplexer shown in Fig. 15-3. When the control lines request a self-test, then the devic driver routine commands U9 to transmit the signal VTST at its connection Y2, pin 19, to its C0~ output.
-The test voltage VTST may be interpreted by the :
microproces~or to be an input voltage on any o the current mea~urement input~. ThU3, the external test May test all functionq in the circuit breaker. In interpreting the measured valus of YTST, microprocessor U24 uses measured valu~ o~ the vol~age appearing at pin Y2, interpre~s thsm as current measurement~, on any one o~ the chann~ls, but uses a different register for accumulation. Thu~, a test and an accumula~ion may occur simultaneously, without loss of pro~ection to th0 Local Trip Unit.
Tha internal self-test is done continuously avery 12 millisecond~, that i~, each time the program goes through task #~. The external sel~-test is done only when the - apparatu~ is commanded ta do ~o by an operator~

-6~-Task 7 The program enters Task #7 after completion of Tas~ ~6. Task #7 prepares information for transmission on the serial communications interfacQ, port PDl of microcomput2r U24. For example, if in task #1, byte 11 was transmi~ted, then at task #7, byte 12 will be prepared. The output data stream thro~lgh the serial communications interface is specified hereinbelow in the section entitled "Serial Communications Interface Datastream".
Task #7 also performs calculations in the event that the apparatus is installed as a "motor protection unit". The Trip Unit, TU functions as a motor protector unit by the installation of ~ jumper. To func~ion as a motor protector unit;, the apparatus must compute phase unbalance. The unit uses t~he measured current flows in phase A, phase B, and phase C to comput~ phase unbalance. Op~ration o~ the apparatus as a motor protector is determined by ~he prasence or absence o~ jumper JMPl. If the jumper i5 in, the apparatus is a Trip Unit. I~ jumper J~P1 is out, the apparatus functions as a motor protector unit. Jumper JMPl is connected to input pin A2 of switch U21.

Task ~
The program enters task $8 upon completion of task #7.
Task #8 performs both validation and softdog routine for internal checks. The program ~irst checks the flags set by the internal self-test routinaJ task #6. If internal self-~est fails too many times, then the task #~ tak~s action. The action i9 deter~ined by the pre~ence or absence o~ ju~per JMP5 and jumper 6, J~P5 and JMP6, a~ appears at the 2~49~
bottom of Fig. 15-3. I~ JMP S is in, the program trips the brsaker. If JMP6 i~ in, the program sounds an alarm horn.
Both JMP5 and JMP6 may be in simultaneously. The use of jumper~ ~MP5, JMP6 to determine the action of the apparatus in the event of the ~ailure of an internal te~t provides flexibility for a system designer to make a ~isfunctioning breaker perform as he desires.
A second function performed by tas~ #8 is the softdog routine. The softdog routine monitors the voltage on a capacitor which must ba periodically discharged by microprocessor U24 in order to determine if micro~rocessor U24 is functioning. Comparator U27-C appearing at the lower left corner of Fig. 15-4 compares the voltage developed across capacitor C10 with 2.5 volts. Capacitor ClO is on Fig.; lS-l, and it~ voltage is signal WDE14. In the event that the voltage across capacitor rlo exceed~ 2.5 volts, output pin 14 of op-amp U27-~ goes high, thereby driving coil drivsr transistor Q12 into conduction and tripping the breaker, in the event that JMP5 is in place. Capacitor C10, shown in Tig. 15-1, i3 p~riodically discharged by transistor Q4 being driven into conduction along with the dump cycle for th~ peak detectors. If the dump cycle fails and transistor Q4 ~ails to discharge capacitor C10, then comparator U27-C
will yo high at it~ output terminal 14, thereby in the presence of jumper JMP5, tripping the breaker by driving transistor Q12 into conductance.

Hardwa~s ThQ ~o~twar~ passe~ through the main cod~ once each 12 milliseconds. An AC line cycle period is 1000/60 or 16 2~3 ~64-milliseconds. The program loop timing i5 completely independent of the AC line cycle. Thus, the peak detector dump switches ar~ closed more than onc~ each AC cycle, on the average.

s Peak_Detector Dump Control The peak detector dump switches are controlled by line MGD
shown in Fig. 15-1 connecting to switch U14 at its pin 12, and by line DOD, connecting to switch U14 at its pin lS.
Switch U14 is on Fig. 15-3. Switch U14 is, in turn, controlled by signal DLCLK connected to microprocessor U24 at its port PB3 at pin 15. Dump o~ the peak detector capacitors is controlled by the software so that it occurs once each pass through the main code.
. .
Restraint In and Restraint Out Circuit.~
Overioad "restrain in" signal OLRI drives buffer P~0 at pin 12 of microprocessor U24. Ground fault ~restraint in"
signal, GFRI drives microprocessor U24 at input port P~l at its pin 13. The voltage at OLRI drive~ input pin 8 of op-amp - 20 U7-C. Microprocessor U24 opQrates normally when a restrain in lin~, OLRI or GFR~, is logically t'low". A logical "low"
signal i~ a ground connection for OLRI and GF~I.
In the event that overload "restrain in" signal in OLRI
go~s positive sufficiently to caus~ a transition at output pin lS of comparator U7-C, then microprocessor port PBO will go lsgically t'highn. Microprocessor U24 detects the logical hiyh as a so~tware interrupt upon the occurrence of a high transition at port PBO, and branches to a restrain in look-up 21~ 9~
table for the overload pickup and delay values. The result is tha~ microprocessor U24 keeps the breaker a~tive for a longer tim~ period upon the receipt of a transition of line OLRI to logical high, that is, upon the receipt of a "restrain in" signal, in order to permit ~ downstream breaker to trip first into an "Off" state.
A ground ~ault "restraint in" signal, GFRI, is connected to pin 10 of comparator U7-D. Normal operation of the circuit breaker occurs when signal GFRI is logically low, that is, at ground potential. In the event that signal GFRI
makes a transition sufficiently high to cause comparator U7-D
to turn off, microcomputer U24 at port PB1 makes a transition to logical low, and the transition to logical low at port PBl signals microprocessor U24 that a ground fault "restraint in"
signal has been received. Microprocessor U24 interprets the rec~ipt o~ a ground fault restrain in signal by going to a i'ground fault restrain in look up table" for n~w trip values for ground ~ault pick-up and ground ~ault delay. The result is that ~icroprocessor U2~ ke~ps the circuit breaker from tripping to an "Off" situation for a longer time upon the rec~ipt of a ground fault "restrain in'l signal, in order to permit a downstream breaker to trip ~irst.
As circuit breaker U24 enters a trip routine such as tasX
#3, task #4, task #5, a~ shown in Fig. 1~, microprocessor U24 generate~ a "restraint out'l signal a~ an input signal to upstream break~rs, wh~ra that input signal is a "restrain in"
signal ~or thQ upstream breakers. The "restraint out" ~ignal iY developed by a combina~ion o~ controls on databus DO.~.D7 and control by signals output by microprocessor U24 at its - 30 port PCS at its pin 23, and these control signals control switch U17, shown in Fig. 15-2. Switch U17, at its output ports Q6 and Q7, gene~a~e the "restrain outl' signals. Output port Q6 o~ switch U17 produce~ the overload "restrain out"
signal OLR0. Output port Q7 o~ switch U17 generates the groun~ fault "restrain out" signal GFR0. Normal operation of the upstream breaker occurs wh~n the overload restrain out signal OLR0 is at ground potential, and restrained operation of the upstream breaker occurs whan signal OLR0 goes logically "high". Normal operation of the upstream breaker occurs when the ground fault restrain out signal, GFR0, is logically "low", and restrained action o~ the upstream breaker occurs when signal GFR0 goes logically "high".
Contro} of the circuit breaker from a Display Unit DU, or a 10cal ~anagement Unit "LMU" occurs,. Fig. 15-3, through jack J5,-at its pin 12, using signal TREXT. Current ~low in TREXT
causes the light-emitting diod~, LED, in optocoupler U23 to illuminate, and drive its associated phototransistor into conduction. Conduction of the p~ototransistor and optocoupler U23 drives tran~istor Q1~ into conduction, thereby tripping the circuit breaker.

~i~ Unit ~ackg~ound Code The Trip Unit background code controls reading of data from ~ront end multiplexex U9. The background program is driven by interrupts~ A timing interrupt initiates operation of data r~ading. A "convarsion complete" interrupt signal generated by ADC U13 signals the end of data reading and conversion. Da~a i~ read every 1 millisecond.

2~
Front end multiplexer U9 permits measurement of each of its inputs in sequence, and this measurement runs continuously in backyround under control of the 1 millisecond clock pulse and the interrupt output on line INT pin 5 of ADC
U13, as will ~e described in greater detail hereinbelow in the section entitled ~ACKGROUND.
A device handler routine controls initiation of data reading. The device handler initiates data reading upon expiration of 1 millisecond, as signaled by the 1 millisecond timer set~ing a "time-out" flag. The device handler provides signals to switch U14 to set the proper gain using switches Ull. The device handler also commands front end multiplexer U9 to connect the proper input channel to analoy to digital converter ADC U13. The device handler initiates analog to lS digital conversion, and then waits. Analog to digital converter ADC U13, upon completion of analog to digital conver~ion, generates an interrupt signal INT at its pin 5, and this signal is input to the microprocessor at its port PD7 at i~s pin 36. The devic~ handler, whil~ waiting, continuously tests for a transition in the INT signal at microprocesaor 24 input port PD7, and when it detects the converslon, initiates furthsr action by ~he background progra~. The background program store~ the measured value, and updates the appropriata accumulators for either current accumulation or current square accumula~Lsn.
The ~ain program is executed once each 12 milliseconds.
During Qach 1 millisecond wi~hin ~his 12 millisecond period, the 1 millisecond timer initiate~ data reading by the device driver. During time period~ 1, 2, 3, 4, 5, and 6, the device driver com~and~ ~he front end multiplexer U9 and ~DC U13 to 2~

measure peak phase current and ground fault current. During 1 millisecond time period~ 7, 8, 9, }O, 11, and 12, the devic~ driver commands front ~nd multiplexer U9 and A~C U13 to measure, as before, peak phase current and ground ~ault cuxre~t, plus one other input parameter. ~he "one other input parameter" is one chosen from the following list: A phase, B
phasQ, ~ phase, Test Voltage VTST, Y7 voltage for self-test (S volts), and Ground potential ~or self test by opening switch EN~ in serie~ with output COM by activating ignal ENB1 at pin 7 of multiplexer U9. Each of these six measurements is taken in seriatim, with one item beinq measured during each 1 millisccond time interval, from interval 7 through interval 12.
The potential applied to input channel Y6 at pin 2 of multiplexer g is mea ured by the device driver only during a power up s~quence in order to measure the power down history by sa~pling the potential on capacitor C36.
Transistor Qll i~ controlled by the 'ipower up sequence controllarl' in order to permit the microprocessor to operate ~or 2 milliseconds before beginning initiation of current mPa~urements. Thi~ 2 millisecond waiting time permits the microprocessor to develop stable operation before measurements ara initiatedO
The microprocessor retains histor~cal informa~ion in non-volatile memory U25. Th2 background program updates storagQ of in~orma~ion in non-volatil~ memory U25.
In~ormation retained in non volatile memory U25 includes: the nu~ber o~ long time trip~, th~ number of short circuit trips inclu~ing shor~ tima trip~ and short circuit ~rips, th~
number of ground fault trips, and the causa and level o~ last --6go trip. The level o~ the trip is the ~easured amount of current c~using it to trip. When the system is powered up, the program first reads a location in non-volatile memory.
This "Pirst read location~ in non-volatile memory tells the progràm either: no trip occurred at last power down, or there was a trip at last power down. In the event that the location states there was no trip a~ last power down, then the program doe~ not update trip.history in the non-volatile memory.
In the event that there was a trip at last power down, the non-volatile memory says to the microprocessor, "Take information that I am giving you from my "non volatile"
memory and update the trip histories in my non-volatile mem~ry. The action with the non-v~latile memory may occur during~ the 2 millisecond waiting time on power up.
Non-volatile memory U25 may be a Xicor, part, Product X2444. The Xicor X2444 has a RAM and an E2 PROM, an electrically erasable programmable read only memory. The microprocessor reads and writes into the internal RAM of the - 20 X2444. The microprocessor then initiate~ a store cycle into th~ E2 PRO~ when it is required to update storage in the non-volat~le memory.
Th~ follQwing component parts have b~en found useful in the practice o~ the present invention:
U9 and U29 ar~ generic 8 to 1 analog multiplexers of type ?4HC4351. U13 may be an ADC0804 typ~ Na~i~nal Semiconductor analog to digita~ converter.
U14 may be a latch of typ~ 74HC273. Upon the rising edge of receipt o~ a CLK signal, th¢ inpu~s then present at input pins 3, 4, 7, 8, 13, 14, 17, 18 are latch~d and h~se values 2~ 9~
:~ appear at the output terminals Q0, Ql, Q2, Q3, Q4, Q~, Q6, Q7.
U21, U22J may be type 74HC541 octal buffers of g~neric manufacture. When control terminal OEl goes logically "low", the input is coupled to the output. Subs~equent chang~s in input cause corresponding changes in input voltages.
U16 may be a type HC4024 shift register or divider, of the type manufactured by National Semiconductor.

~0~
- TRIP UNIT SERIAL COMMUNICATIONS
Overview This section details the serial communications protocol from tha Trip Unit to external devices such as an LMU, a DU, or a Remote Indicator Unit (RIU). The Trip Unit continually transmits a serial data stream when fault power is sufficient. The first byte ~Byte O) of the data always contains a 1 in the lowest bit position ~bit 0) to identify itself. The receiving unit then recognizes this as byte 0.
Subsequent bytes have a O in the lowest bit position and are counted by the receiving unit to keep track of the byte number.
The byte transmission restart~ at byte 0 whenever any of the following occur: .
A. Power-on restart has occurred B. A trip is about to take place C. The sequence of 31 BYTES transmission has been completed.
The receiving unit checks every 8YTE for a 1 in the lowest bit po~ition to see~if byte number O is being transmitted~

Requirements 1. Output: Opti~-ally Isolated Serial Data Stream ~. Frame ~ormat: 1 Start Bit, 8 Data Bits, } Odd Parity 3i~, 1 Stop Bit 3. Transmission Rata: 9600 Baud 4. Byte Transmission Sequence:
4O1 Number of Bytes: 31 (Byte O through Byte 30) 3~
~72-2~
4.2 Byte Zero Identification: Byte Zero contains a 1 in its bit 0 position. All other bytes contain a 0 in this positionO
4.3 Byte zero transmissiono Byte zero is transmitted, upon receipt of a T~B~ ~Transmit Buffer Empty) interrupt and the comple~ion of a 250 microsecond (minimum) delay, when any of the following conditions is true:
4.3.1 Upon power-up of the microprocessor. This synchronizes external devices to the byte stream.
4.3.2 Just before the microprocessor commands a trip. This alerts external devices that a trip is taking place~
4.3.3 Every 31st 12 millisecond period. This will be the start o~ the next cycle of byte transmission.
-4.4 Bytes l, 2 and 3 Transmission: Bytes 1 and 2 -always follow 8yte 0. Byt~ 3 will follow Byta 2, unless a trip i5 occurring. The minimum delay between thece ~ytes will depend on whether or not a trip is occurring.
- 20 These Bytec ar2 transmitted ~s ~ollows:
4.4.1 If no trip is occurring, ~yte l/ the Self Test Status Byte, will ba transmitted ~t the start of the next 12 millisecond period following Byte 0. Bytes 2 and 3 will then follow ln the next ~wo 12 millisecond period~ ~ollowing byte 1. They contain the value o~ Phase A current.
4.4.~ When a ~rip is taking place, By~e 0 will ~e transmitted not sooner than 250 microseconds after th~ end o~ th~ Stop Bit of the Byta currently being 3~

( ~?104~3~

transmitted, but as soon as possible thereafter.
Bytes l and 2 contain the magnitude of the highest phase current and Byte 3 is not transmitted. Byte 1 will be transmitted not sooner than 250 microseconds a~ter the end of Byte O's Stop B~t, but as soon as possibla thereafter. Byte 2 will be transmi~ted not sooner than 250 microseconds after the end of Byte l's Stop Bit, but as soon as possible thereafter.
Transmission ceases after Byte 2 and does not resume until the breaker opens and re-closes.
4.5 BytQ 4 through Byte 9 Transmission: Bytes through 9 will be transmitted in order in the 12 millisecond periods following byte 3. Bytes 4 through 9 will not be transmitted during a trip.
` 4.6 Byte 10 through Byte 30 Transmission: Byte 10 through byte 30 will be transmitted in order in the 12 ~illisecond periods following every fifth transmission of byte 9.
Twelve millisecond periods lO through 30 will contain no transmissions during the other 4 tran~mission cycle~. This will allow the r~ceiYing unit extra time to process data received in previous periods. Bytes 10 through 30 will not be tran~mitted during a trip.
4.7 Byte Data: The following summarizes the data conten~ of each byte Qf ~h~ Trip Unit Serial Communications S~ream:
4.7.1 The following su~mari~ss data transmitted during normal operation of the breaXer, i.e., while no trip is occurring:

-?4-;~0~ 9~L
A BYTE contains 8 bits, bo--~b7.
Schematically, the bit~ are laid out as follows in a BYTE;

s ~7 b6 b5 b4 b3 b2 bl bo .. . .
x : x : x _ . x_: x _._ x_ ._ x : 1 :

Bit 0 is transmitted first and bit 7 is transmitted last.

BYTE Zero: Pickup/trip indicating BYTE
b7: 1 for Phase Unbalance pickup or trip O otherwise b6: 1 for ground fault pickup or trip o otherwise b5: 1 ~or short time pic~up or trip o otherwise b4: 1 for long time pickup or trip O otherwise b3: i for 90 percent of long time pickup - O otherwise b2: 1 ~or instantaneous pickup or trip O otherwise b~ trip i~ occurrin~ (indicates other bits are for trip) - 0 i~ no trip is occurring (indicates other bi~s are for pickup) b~ Always 1 ~o indicate byte 0 BYTE O~e. S~l~ Test Status Word b7: 1 indicates aborting sel~ t2st 0 otherwise b6: 1 indicate~ a ground fault pickup condition O otherwise b5: 1 indicate~ a short ti~s pic~up condition O otherwi~;P
b4: 1 indicate~ a long ti~ pickup condition O oth~rwis~

2~0a~
b3: TBD
b2: 1 lndicates an instantanQous pickup condition O otherwise bl: 1 indi~ates the occurrence of a Self Test trip condition O otherwise bo: Always O
BYTES Two and Three: Phase A current - Amps R~S

b7: Always O
b6-b~: Two bit BCD exponent. Indicates tha power of 10 applied ~o the ~ollowing digits.
b4-b : Mo~t Significant Digit of Phase A Current Leve~ (BCD encoded~
bo: Always O

~7~bs: Always O
b4-b : Least Signi~icant Digit of Phase A Current - -~eve~ (BCD encoded) bo: Always O
BYTES Four and Fiv~: Pha~e B current - Amps RMS

b7: Alway-q O
b -b~: Two bit BCD exponent. Indicates the power of 1~ applied to the following diqits.
b4-b : Most Significant Digit of Phase B Current Leve~ (~CD encoded) bo: Always O
~5 ~YTE 5 ~7~bs: Always O
b4-b : Least Signific~nt Digit of Phase B Current Leve~ (~CD encoded~
bo: Always O

~76-~ - ~o~
BYTE~_Six and Seven: Phase C current - Amps RMS

b7: Always O

b -b5: Two ~it BCD expon~nt~ Indicates tha power of 18 applied to the following digits.
b4-b : Most Significant Digit of Phase C Current Leve~ (BCD encoded) bo: Always O

b7-b5: Always O
b4-b : Least Significant Digit of Phase C Current Leve~ (BCD encoded) bo: Always 0 BYTES Ei~ht and Nine: Ground Fault Current - ~mps RMS
BYTE B

b7: Always O
b ~b5: Two bit BCD exponent. Indicates the power of lg applied to the following digits ~ 4-b : ~ost Significant Digit o~ Ground Fault Current - Leve~ (BCD encoded) bo- Always O

b7 ob5 Always 0 b4-bl: Least Siqnificant Digit of Ground Fault Curren~ Level (BCD encoded~
bo: Alway O
BYTE Ten: Option ~yte b7: Always 0 2~

b6: indicates Trip Unit configuration; 1 indicates Motor Protection Unit configuration b5-bo: Always 0 BYTE E.leven: Sensor Plug Identification Indicator b7: Sensor Identifier Bit S3 b6: Sensor Identifier Bit S2 b5: Sensor Identifier Bit Sl b4: Sensor Identifier Bit S0 b3: Plug Identifier Bit P2 b2: Plug Identifier Blt P
bl: Plug Identifier Bit P0 bo: Always 0 BYTE Twelve: Long Time Switch Positions b7-b5: Long Time Delay Switch Position (0-7).
;b4-b2: Long ~ime Pick Up Switch Position (0-7) bl: 1 indicates Instantaneous Function is in the "OFF"
position . O otherwise -- bo: Always 0 BYTE Thirteen: Short Time Switch Positions b7-b5: Short Time Delay Switch Position (0-7).
b4-b2: Short Time Pick Up Switch Position (0-7) bl: 1 indicates Short Time Function is not installed O otherwise bo Always 0 BYTE Fourteen: Ground Fault Switch Positions b7-b5: Ground Fault Delay Switch Position (0-7) b~-b2: Ground Fault Pick Up Switch Position (0-7) bl: 1 indicates Ground Fault Function i~ not installed O otharwisa bo: Always 0 qLg~L
B~te Fifteen: Instantaneous/Phase Unbalance Switch Positions b7-b5: Instantaneous Pickup Switch Position (0-7).
b4-b2: Phase Unbalance Percent Switch Position (0-7) bl: 1 indicates Pha~e Unbalance Function is not installed a otherwise bo: Always O
By~tes SiXteen and Seventeen: Long Time Trip Memory b7-b2: Six Most Significant Bits of Num~er of Long Tlme Trips in binary (Bit 7 is ~S bit) bl-bo: Alwa~s O

bl: 1 indicates Short Time Function is not installed O othexwi~e bo: ~lway3 0 b?-b2: Six Least Signi~icant Bits of Number of Long Tl~e Trips (Bit 2 is LS Bit) - b1-bo: Always O
-b1: 1 indicates Short Time Function i~ not installed O otherwise bo: Always O

- 20 Byte~_Eiqhteen and Nineteen: Short/Instantansous Trip Memory b7-b2: Six Most Significant Bits o~ Num~er of Short Tlme or Instantaneous Trip~ in binary (Bit 7 is MS Bit) bl-bo~ ~lway~ O

b7-b2: Six Least Significant Bits o~ Num~er o~ Short Tlms or Instantaneou3 Trip3 (Bit 2 is LS ~it~
b}-bo~ Always O
Bytes ~wenty and Twenty-On~: Ground Fault Trip Me~ory b7 b : 5ix Mo~ Signi~icant 3its o~ Number of Ground Faul~ Trip~ in bina~y ~Bit 7 is MS Bit) 7g-34~

b1-bo: Always 0 b7-b : Six Least Signi~icant Bits o~ Number of Ground Faul~ Trips (Bit 2 i~ LS Bit) bl-bo: Always 0 Bytes Twenty-Two and Twenty-Three: Last Fault Level Memory -Amps RMS
BYTE 22: Amps most recent fault ~7 ~lways 0 b -b5: Two bit BCD exponent. Indicates the power of 1~ applied to the following digits.
b4-bl: Most Significant Digit of Current Level of most recent fault (BCD encoded) bo: Alway~ 0 BYTE 23: Cause of Last Trip b7~b5: Cause of Last Trip, encoded as follows:

b7 b6 b5 Cause of Trip 0 0 0 None . 0 0 1 Instantaneous '0 1 0 Short Time - O 1 1 Long Time 1 0 0 Ground Fault 1 0 1 Phase Unbalance 1 1 0 So~tdog/Self~test b4-bl: Least 5ignificant Digit of Current Level o~
most recent ~ault (BCD encoded) b~: Alway~ 0 Bytes Twenty-Four ~hrouqh Twenty-Seven: Not Used BXTES Twenty~ ht Throuqh_Thirty: Percent Unbalance by Phase b7-bl~ Percent unbalance, in binary, of phase bo: Always 0 2~

b7-b~: Percent unbalance, in binary, o~ phase B
bo~: Always O

b7-bl: Percent unbalance, in ~inary, of phase C
bo: Always 9 END OF NO~MAL DATA STREAM
TRIP EVENT DATA STRE~M
; The following summarizes data transmitted while a trip is occurring:
Byte O: Pickup/Trip indicating byte b7: 1 for Phase Unbalance pickup or trip O otherwise . b6: 1 ~or ground fault pickup or trip O otherwise .;b5: 1 for short time picXup or trip ~ O otherwise b4: 1 for long time pickup or trip .- O otherwise --b3: 1 for 9O percent of lon~ time pickup O otherwise b2, 1 ~or instantaneous pickup or trip O otherwise b~ trip is occurring (indic~tes other bits are ~or trip) O if no trip is occurring (indicates other bits or pic3cup) b~: Always 1 to indicate byte O
Byte~ One and Two: Highest Phase Current - Amps RMS

b7: Always O
b -b5: Two bit BCD exponent, Indicates the power of 1~ applied ~o the ~ollowing digit~
-bl: ~ost significant Digit o~ Highest Phase Curxent Level (BCD encoded) 3 0 bo: Alw~y~ o _~ lo - f - 2~0 BYTE. 2 ~7~bs: Always 0 b4-b ~,: Least Significant Digit of Highest Phase Current Lev~l ( BCD encoded) bQ: Always 0 END OF TRIP MESSAGE

.
:. !

~0 D}SPLAY UNIT
Fig. 20 is a schematic diagram of a Display Unit (DU).
Fig. 21 is a menu diagra~ of the Display Unit readout. Also, the Display Unit keyboard is shown in Fig 21.
The Display Unit has a self-contained power supply operated by a step down transfoxmer, and may be operated on 115 volts between transformer connections 12, 13.
Alternatively, the DU may be operated on 230 volts by connection between transformer pins 11, 13. A diode bridge : 10 CRl produces a +24 volt DC supply. Diode bridge CR2 produces a -30 volts DC source. A +5 volt precision source is provided by diode C~3, CR4.
Microprocessor Ul is powered from the +5 volt source and is connected b~tween pin 4 (VCC) and pin 1 (VSS). In addition, pin 7 (Vpp) is connected to pin 4 (vcr? to disa~le the programming function-of the chip. The time ba~e clock for.microprocessor Ul utilizes the internal clock generator and is derived using two external components Y2 and C15. It has been found satisfactory to use a 4 megahertz crystal for Y2. Microproc~ssor Ul may satisfactorily use a Motorola type 68705U3 microprocessor chip.
The Asynchronous Communicatlons Interface Adaptex (ACIA) U2 is powered from the ~5 volt source connected between pin 12 (VCC) and pin 1 (VXX). The ACIA connects to microprocessor Ul using an 8 bit parall~l data bus configuration. In addition, three control lines and an intarrupt request line are provided by Ul to operate and e~tra~t information from the ACIA. ACIA U2 receives input data from the trip unit at input pin 2 (RXD~. Pin 2 of the A IA i~ connactad to pin 8 o~ the Display Unit jack P5. The J Lf~
input data arrives at jack P5, pin 8. The input data line at - ACIA U2 pin 2 i~ cla~ped by d~ode CR17 so that its potential cannot exceed the level of the ~5 volt DC power supply.
Signal RMVCC is supplied through pin lB of jack P5 in order to supply a +5 volt op~rating voltage to'the serial data optoisolator U26 located in the trip unit, as shown in Fig. 15-2.
The 14-stage ripple carry ~inary counter U4 is configured as a crystal oscillator. A 2.4576 megahertz crystal (Y1) has been found satisfactory to produce the serial data receiver clock timebase required at the RXC input : pin 3 of ACIA U2.
Display Controller U5 controls the Display Unit's 16 character alphanumeric display (DSl). Control signals for the display controller are supplied by microprocessor Ul through its output line PBO, PB1, PB2 at its pins 25, 26, 27 respëctiv21y. A Futaba typa 16-SY-03Z display panel has been found useful, and a display controller U5 type 10937PE-50 has been ~ound to be satisfactory.
The DU has a set of four input switches connected at jack J9, pins 1, 2, 3, 6. The switche~ connect ~o microprocessor Ul at its port PD7, PD6, PD5, PD4 at it~ pin~ 17, 18, 19, 20 respectively. Pull up resis~ors RPl-C defin~ potentials on the switched line5 by connec~ion to the +5 volt source.
Tests of the Trip Unit may be initiated ~rom the DU.
Microprocessor Ul may initiate test procedure~ through i~s ports PC0, PCl, PC2, PC3 at its pins 9, 10, 11l 12. Self te3t commands to the TU are provided a~ siqnal~ ST0, STl, ST2, and also a~ shown in Fi~. 15-2. The signals can be applied by en2rgization of relay~ ~1, K2, K3, X4. The r~lays are energized by driving transistor Ql into conduction by a signal from output port PC3 of microprocessor U1.
A variable test voltage VTST may be applied to th2 TU by adjustment o~ variable resistor R2. Variable resistor R2 has an adj`ustment knob which is accessible by` an operator at the front panel of the Display Unit. A ~24 volt external power supply voltage is supplied by jack P5 at its pin 5 for operation of the trip unit for self test purposes. A +5 volt external test voltage i5 applied to the TU by pin ~ of jack P5.
operation of the Display Unit is discussed by reference to Fig. 21. Referring to Fig. 21, the Display Unit ~eyboard is shown to have four switches, identified as ~'Select Function", "Select Data", "Auxiliary Power", and "Test Mode:
Trip/N~o Trip". These four push button switches are shown in Fig. 20 as the switch strip connected at ~ack P9.
Adjustable resistor R5 has a knob ~isible on the front -panel o~ the DU, and is indicated as "Test Level", and goes from a counter clockwis~ "MIN~ position to a fully clockwise "MAX" positio~.
Pressing th~ "Auxiliary Power" push-button located on the front panel of the Disp}ay Unit activates the internal relays to apply auxiliary power of an unpowered Trip Unit. If a Trip Unit is connected and operational, the ~isplay Unit will then advance ~o the select function mode.
ThQ Select Function key select~ "group" data for viewing on th~ display pane}. Tha various "groups" includQ:
"Meters'~, "Breaker DataN, "System Testing", and "Event ~istory".

(- 2q~

The "Select Data" button permits viewing on the display panel of various quantities in each group. When viewing in the "Meters" group, the "Select Data" button permits viewing currents in Phase A, Phase B, Phase C, and ground fault. The "Select Function" button in the "Meters" group, has a "Current Unbalance" position. In the "Current Unbalance"
position the "Select Data" push button permits current unbalance to be read in "Phase A", "Phase B", or "Phase C".
When th~ "Select Function" push button is in the "Breaker Data" group, there are two positions, and they are "Breaker Ratings" and "Breaker Settings". The "Select Data" push button when the '1Select Function" push button is in the "Breaker Ratings'1 position permits reading on the display the "Sensor Amps" or the "Plug Ratio". .~he sensor amps and plug lS ratio are read by the trip unit from a switch array, and the results are transmitt~d in the s~rial data stream into the Display Unit.
Th~ "Select Data" push button, when the "Select Function"
button is in the "Breaker Settings" position permits reading either one or two groups, depending on whether the ~U is in a "Circuit Breaker" version or a "Motor Protect" version. In tho "Circult Break~r" version, the "Select Data" push button permits reading: long time pickup, long tima delay, short tim~ pickup, short time delay, instantaneous pickup~ ground fault delay, or ground fault pickup setting~ of the TU. In the "Motor Protect" version, the "S~lect Data" push button permits readinq the: ~ull load current, overload delayJ lock rotor current; saf~ stall time~ in~tantaneous pickup, ground fault picXup, ground fault delay, current ~nbalance -8~-2~
pickup~ settings of the TU. Alternatively, both motor protector data and circuit breaker data may be displayed on a single menu.
~hen the "Select Function" push button is in the "System Testing" group, there are two positions: "Test Phase Fault", and "Test Ground Fault". When the "Select Function"
push button is in the "Test Phase Fault" position, the "Select Data" push-button permits access to the test mode.
Next, the "Select Trip/No Trip" push-button allows the selection of either a breaker trip or no trip test mode.
Each press of the "Select Trip/No Trip" push-button will toggle the selection between these two modes. Once the type of trip mode has been determined, the "Select Data"
push-button is pressed to lock in the mode in addition to selécting the test current display mode. Using the "Test Level" adjustment pote~tio meter, the test current is adjusted as indicated on the alphanumeric display. Once the test current lev~l is adjusted, pressing the "Select Date"
push-button will initiata the breaker test. At the conclusion o~ the test, the test delay time will be indicated on the alphan~eric display. Pressing the "Select Data"
- push-button after the test delay ti~e display will return the Display Unit to tha selPct trip/no trip mode. I~ the "Selection Function" push-button i5 pressed instead of the "Sel~ct Data" pus~-button, the Display Unit returns to ~he select function mode. The implementation of the "Test Ground Fault" po~ition is exactly the same as that ~or the "Test Phase Fault~ position.

2~

When the 'ISelect Function" push button i3 in the "Event History" group, there are two position~, "Last Trip", and "Number o~ Trips". The "Select Data" push button, when the "Select Function" is in the "Last Trip" position, permits readiny the magnitude of the lask trip on the display panel.
The "Select Data" push but~on, when the "Select Function"
push button is in the "Number of Trips" position, permits reading the number of trips in: overload trips, short circuit trips, ground fault trips, current unbalance trips.

REMOTE I~DICATOR UNIT
Fig. 22, the RIU receives the serial data stream output by the Trip Unit. The RIU interprets byte zero o~ the serial data stream, and ignores the 31 other bytes in the serial data stream.

R mote Indicator Hardware Dat~ enters the remota indicator unit through pin 9 of terminal block TBl, as shown in Fig. 22. Input data is a negative going pulse. The pulse proceeds through resistor R19 to both AND gate U3C and input port PC0 of microprocessor Ul. The input pulse is shaped by U3C and gated with AND gate U3D, from which it is connected to interrupt INT port at pin 2 of microprocessor U1.

Upon the r~ceipt of a start bit at port INT, at pin 2 of microprocessor Ul, the microprocessor generates a disable sig~àl on port PC1 and applies it to pin 12 o~ AND gate U3D.
The di~le signal applied from port PCl has a duration that is not less than the time required for the TU to transmit a complete byte of in~ormation. In addition, the disable signal is removed from pin 12 o~ AND gate U3D to allow re~eption of a trip mes~age within 250 ms after the last byte transmitted.

After receipt of an interrupt signal, microprocessor U1 reads the 8 following bits. If bit zero (DO) iS set to a "0"

value, all remaining bits of the byte are ignored.
If the value of ~he first bit is set ~o "l", then microprocessor Ul read~ the remaining 7 bits. The values o the bits ar2 interpreted as follows:
Bit 1: z~ro if no trip i3 occurring.
1 i~ trip i~ occurring . -89-Bit 2, 1 for instantaneous trip O otherwise.
Bit 3: is ignored, but could be interpreted as a 90~ of long time pick-up situation.
O otherwise.
Bit 4: 1 for long time pick-up or trip O otherwise.
Bit 5: 1 for short time pick-up or trip.
0 otherwise.
Bit 6: 1 ~or ground ~ault pick-up or trip.
O otherwise.
Bit 7: 1 for phase unbalance pick-up or trip O otherwise.
AftPr interpreting the bits of byte 0, the microprQcessor Ul checks the parity bit which follows the 8 data bits tra~smitted by the Trip Unit. In the event that the parity bit is in agreement with the data bits, the microprocessor concludes that the data transfer wa~ a transfer o~ valid data. Receipt of the stop bit transmitted by the Trip Unit i~ int~rpreted by microprocessor Ul and p~rmits the micxoprocessor to drive the output port PC1 high in ord~r to enable port INT. Enabling input port INT permits the microprocessor Ul to b~ in a ready state for further receipt of data bytes.
Microprocessor U1 then generates output signals on lines PAO...P~7~ thereby providing input to latch U2. Latch U2 is latched "on" by a ~ignal ~ro~ port PB0 o~ microprocessor Ul.
The nutput o~ latch U2 is applied to FET transistors Ql... Q7. WAen an output tran~i~tor i9 driven into conduction, a relay, Kl..,K6 closes. Tr~nsistor Q5 energizes latching relay X6. Transistor Q6 resets latching relay K6.
Closure of contacts of relay~ Xl...K6 provide indications of the information carried in byte 0 from the Trip Unit data stream. Indications o~ the following are'presented by contacts of relays Kl...K6:
1. ~ong time trip is indicated by relay Kl.
2. Short time or instantaneous trip is indicated by relay X2.

3. Ground fault trip i3 indicated by relay K3.
4. Phase unbalance trip is indicated by relay K4.

5. Long time pick-up is indicated by relay K5.

6. The existence of a trip is indicated by a relay K5.
Relay K6 is a latching relay. Latching relay K6 may be reset by a pulss applied to transistor Q6.
In the ev~nt of an el2ctric power failure of the power supplied to the remote indicator unit, the microprocessor Ul will lose power. Ho~2ver, capacitor C4 will 510wly discharge and hold khe latch U2 ln an activa state. If the power is off for less than 5 seconds, infor~ation latched by the latch will be preserved. If the electric power returns within lass than 5 saconds, then the 5 volt power supply through diode CR2 will r~turn latch U2 to its active state.
Upon tha return of electric power to microprocessor U1~

microprocessor U1 read~ line~ connectad to port~ ~B5 and PB4 in ordar to determinQ the state of latch U2 before los~ o~
power. In th~ ev~nt that a trip has occurred, microprocessor U1 will obtain ~hi~ information fro~ port 7Q of latch U2. In the evant that a long-ti~e pick-up had occurred before the 2~
power failure, microprocessor Ul will obtain this information by reading port SQ of latch U2.
Upon restoration of power to microprocessor Ul, a hardware reset occurs through RESET pin 28 of microproc~ssor U1. Microprocessor Ul then gQeS to an initialization portion of its program. Part o~ the initialization is to read ports PB4 and PB5. If power has been off for longer than 5 seconds, both ports 5Q and 7Q of latch U2 will be "low". Note information content is present in two low values of ports 5Q and 7Q o~ latch U2, and so microprocessor Ul will start with a Presh st~rt.
In order that latch U2 draws sufficiently little current that capacitor C4 can keep it active for at l~ast 5 seconds, FET Q8 and FET Q9 are used as buffers between ports 5Q and 7Q
of latch U2 and ports PB4 and PB5 of microprocessor U1. By having the port of the latch connected to the gate of an FET, substantially no cu~rent is drawn from the latch by the FET
during a power loss si~uation. Thus, FET Q8 and FET Q9 act as bu~fer on the output of latch U2. Al~o, FET Ql...Q7 have thair gate~ connected to respectiYe output pins of latch U2, and therefore, draw sub~tantially zero current ~rom the latch. FET Ql.~.Q6 act as buffers on the output of latch U2 so that capacitor C4 can hold latch U2 in an active condition for th~ re~uired time period during a power outage.
In summary, thQ Remote Indicator Unit has a microprocessor driving a latch. The latch power supply has a capacitor to hold th~ latch activa during a po~er outage a~d thQ latch drîves relays through low current drain bu~ers~

Low current drain buf~er~ are connected to at least one ~92-f ~ 4~

output line of the latch, and the buffer output connected to input ports of the microprocessor. The microprocessor reads the input ports upon reset, and a reset occur~ on "power up", thus the microprocessor uses the latch as memory to preserve in~ormation during the power outage.
Jack TBl provides connection between the remote indicator unlt and the Trip Unit. The re~ote indicator unit power supply provides a 5 volt source to the top of resistor R1, and throu~h diode CR6 provides input power RMYcc to power the phototransistor of the optoisolator and the Trip Unit. The output signal from the Trip Unit is applied to pin 9 of jack TB1 and is connected from pin 9 to input pin 9 and pin 10 of AND gate U3-C. The return conductor ~Dr the signal line connects to pin 10 of ~ack TBl whi~h is referenced to circuit lS ground potential in the RIU.
A power supply voltage monitor comprises comparator U4B.
iena~ diode VRl sets a potential below which, should the potential on pin 7 of comparator U4~ go, causes comparator U4B to make an output transition which res2ts ~icroprocessor Ul at its reset port at pin 28.
A watchdog test of softwara functioning i5 provided at output port PB3 o~ microproces~or U1. As the so~tware in microprocessor U1 executes its normal sequence, it generates a low transition periodically at output por~ P83. The low pulse gen~rated a~ outpu~ port PB3 causes comparator U4D to go low at its output, ther~by discharging capacitor C5.
Capacitor C5 normally tend~ to ch2rge toward ~5 volts through resistor R8 and resi~tor R14. In the event that capacitor C5 is not discharged by a low going transition at ol~tput port -~3-z~
PB3 of microprocessor Ul, then the voltage at the positive terminal at capacitor CS will approach 5 volts. Comparator U4C has its input terminal 11 tied to a fixed fraction of 5 volts by voltage divider R16 and R17. If the voltage at the positive terminal of capacitor C5, which is connected to input pin 10 of comparakor U4-C goes above the potential at pin 11 of comparator U4-C, then the output terminal of pin 13 of compaxator U4-C goes low, thereby resetting microprocessor Ul at its reset input at its pin 28. In the event that the so~tware ceases functioning for an extended time period, then the negative input terminal at pin 8 of comparator U14 will be pulled toward 5 volts through resistor RP2 and resistor R15, thereby per~itting capacitor C5 to charge to 5 volts, and microprocessor Ul to be continuously reset by comparator lS U4C. This action prevents uncoordinated noise from being trans~itted through latch U2 to relays ~l...R6.
` .~icroprocessor Ul attempts to reset upon receipt of a reset pulse at reset pin 28~ As part o~ the initialization routine, microprocessor Ul generates lo~ going pulses at port PB3 at its pin 15. These low going pulses discharge capacitor C5. In the event tha~ thQ program ceases functioning again, then capacitor C5 ch~rges to the +5 volts through resistor R8 and resistor R14 thereby generatinq another reset pulse. The new reset puls~ generates further low pulses at port PB3 during the initialization routine of microprocessor Ul. Port PB3 is pulled up to +5 volts by resistor RP2.
In the event tha~ a trip occur~, even in the pres~nce of a powQr loss or microprocessor mis~unction, latchiny relay K6 _9~_ -z~o~
will stay latched and continue the output indication that a trlp has occurred.
The output indicators of the remote indicator unit must be manually reset by an operator by his depressing manual reset switch Sl. Microprocessor Ul reads input port PBl, and in the event the manual reset switch Sl is depressed, it clears all the output indicating relays.

, _9~
.

4~
LOCAL ~ AGEMENT UNIT HARDWA~E
Fig. 23 and Fig. 24 are a block diagram of the Local Management Unit, LMU, hardware. A three phase alternating current power line has Phase A, Phase B, Phase C, and a neutral line. Current transformer CTA is re~ponsive to current flow in th~ conductor on Phase A. Current transformer CTB is responsive to the current ~low in Phase B. Current transformer CTC i~ responsive to the current flow in Phase C. Potential transformer PTA develops an output voltage proportional to the potential in the conductor of Phase A. Potential transformer PTB develops an output voltage proportional to the potential of the conductor in Phase B. Potential transformer PTC develops an output voltage proportional to the potential in the conductor of Phase ~. The primaries of the potential transformers connect b~tween their respect~ve ~onductors and the neutral conductor.
The current tran3formers are connected into circuits carrying current fro~ 0-10 amperes, and each drives a re~pective input transformer. The current transformer~, CTA, CTB, CTC are chosen so that the maximum expected current 1GW
in their respectiv~ phase~ results in a 10 ampere flow in the current transformer ~econdary. Current trans~ormer CTA
drivQs input transformer CTl. Current transformer CTB drives input transformer CT2. Current tran~ormer CTC drives input transformer CT3.
The ~econdari~ of ~he cu~rent trans~ormer input transformers, CTl, CT~, CT3 conn~ct to signal conditioning ~ircuit~ S/C~ The ~utput o~ the respactive ~i~nal conditioning circuits provide~ a voltage proportional to 2~ 9~
- the~r input current~, and supply that ~oltage to the double pole analog multiplexer and the signal conditioning circuits limit the voltage~ appearing at their output in order to protect downstream equipment from over-voltage~.
Potential transformers PTA, PTB, PT~ each drive a respective input transformer. Potential transformer PTA
drives input transformer PTl. Potential transformer PTB
drives input transformsr PT2. Potential transformer PTC
drives input transformer PT3. ThQ secondaries of the potential input trans~ormers PT1, PT2, PT3 drive signal conditioning circuits S/C. The output of thQ signal conditioning circuits are connected to the double pole analog multiplexer. Signal conditioning circuits S/C limit th~ir output voltages in order to protect downstream electronics ~rom over-voltage~.
An additional output from the Phase A input transformer PT1 connects to the sampling interrupt (z~ro crossing/phase-lock loop~ block. The sampling interrupt block contains a zero cros~ing det~ctor and generat~s 32 interrupt ~ignals during each Phase A voltage cycle. The interrupts are egually spaced and are used to control the reading of data through the double pola analoq multiplexer.
The in~errupt directly controls the co-processor shown in ~5 Fig, 24~
Th~ double pol~ analog multiplexer has a first switch labeled Drain A which connects to the current signals, and to a ~ull ~cal~ lin~ and a grounded line. The double pol~
analog ~ultiplexer ha a ~econd ~witch labeled Drain B which connect~ to th~ output 3ignal proportional to phase ,. !
- 2~
potential, and also connects to a ~ull scale line and a grounded line.
Tha double pols analog multiplexer ls controlled by the co-processor. The co-processor controls the analog multiplexer by a signal on its databus to~the peripheral selection block, and by a signal on the channel select line to the channel select sampling control block. The channel select sampling control bloc~ has input from both the databus and the channel select line. The channel select sa~pling control block controls the double pole analog multiplexer.
The double pole analog multiplexer Drain A provides input to the "sample and hold" bloc~ U76. The Drain B output of the double pole analog multiplsxer provides input to "sample and hold" block U77. Analog switch U81 controls which "sample and hold" circuit, U76, U77r is digitized by the analog to digital converter U~0. The analog switch is controlled by the channel select sampling control block. A
-programmable gain tage, U82, follow~ analog switch U81 providing an increased dynamic rang~ o~ measurement.

Output o~ the analog t~ digital converter U80 provides input to the digital latch U62, U63. The digital latch U62, U63 provides output to the ~o-processor databu~.
A dual port random acces~ memory, dual port RAM, receives input from the data bus o~ the ro-proces~or.

The co-processor measure~ current in Phase A, Phase B, and Phase C. It also measures pokential in Phase A, Phase B, and Phase C. The measureMents o~ curr~nt and potent~al are made 32 timeq during each AC cycle of Phase A. The measurements are made in resp~nse to interrupts generated by th~ sa~pling interrupt blocX which i~ respon~ive to zero _9~ _ crossiny o~ the Phas~ A potential. 32 egually spaced interrupts are genexatad by ~he sampling interrupt block and delivered directly to the co-processor on the interrupt line.
During each Rhase A ~C cycle the co-processor measures 32 equally spaced values of the various curr~nt and voltage inputs. The co-processor then stores a running sum of, for example, the measured quantitie~, desired products of instantaneous current and voltage value~, and of the square of the measured quantities, in the dual port RAM. Also, a message cell in the dual port ram is updated to indlcate the end o~ a PhasQ A AC cycle.
The main processor, shown in Fig. 24, reads data from the dual port RA~I. A read cycle from the dual port RA~ is initiated by an update of the mess~g~ cell indicating the end of an AC cycle on PhasQ A. The main processor reads the accumulated running sum5 from the dual port RAM and reinitializes thQ appropriate registers to zero.
The main processor then compute~ several parameters ~or each phase, including, R~S voltage, RM5 curr~n~, av~rage power, and power factor. Al~o, the AC frequency ls cal~ulated on the ba3i3 of the Pha~ A zero crossing time interval3. Each o~ the R~S ~alues is computed by taking the square root o~ 1/32 o~ tha sum of the squared value~.
The average power for each phase i~ computed by taking 1j32 of the sum o~ the 32 samples o~ instantaneous voltag~
multiplied by inst~ntaneous current. The power factor for each phase is computed by dividing the average power by the product of th~ ~S current and the RMS voltag~. Th~ pha~e angl~ may th~n be ccmputed, and th~ pow~r ~actor i~ equal to the cosine o~ the pha3e angls~
_ - z~

Th~ co-processor periodically tests the ~ront end circuitry by connecting a precision 4.75 volt reference source through the dual port analog multiplexer, and also by connecting a ground through the dual port analog multiplexer.
Calibration measurements using the 4.75 volt reference and the ground connection are made at the end of th~ 32 time periods during each AC cycle. A full calibration is acco~plished each 8 AC cycle~. Two values of gain are available to the analog to digital converter. Two calibration voltage~, 4.75 volts and, ground, or 0 volts, are available for calibration. Calibration is per~ormed on either Drain A for current measurements or on Drain B for potential measurements. Thu~ there are 8 possible combinations o~ calibrated value~, and since one is done each AC cycle, a complete calibration sequence is done aach 8 AC
cycles.
Additionally, th~ co-processor does oth~r internal self checks on the RO~, RAM, and itsel~.
Th~ main processor controls a number of peripherals through it8 databus and address bu~. As shown in Fig. 4, the LMU contains a num~er of keypad switche~ and a display devic~. The keypad switche~ command th~ dlsplay device through a menu, ànd ths device~ are ~ontrolled by the main processor. Ths internal statu~ of many func~ions of the LMU
ara displayed in the display device.

L~U H~RDW~RE SCHEM~
The apparatu~ shown in block ~orm in Fig. 23 and Fig. 24 is shown in ~raater detail in ~h~ ~chematic~, Fig. 25-1 through Flg. 25-12. The individual schematlcs are tied to --10~ ;`

2~

ap~aratus shown in Figs. 23 and 24 by numbers placed in hexagons on Fig. 23, Fig. 24. The number within the hexagon re~ers to the designation 1...12 in Fig. 25-l...Fig. 25-13.
The numbering of the schematic diagrams Fig. 25-l...F`ig.
25-13 proceeds with Fiq. 25-1 containillg the main procl~ssor, as shown on Flg. 24, and proceeding to the left in tlle block diagram with Fig. 25-11 containing the input current transformers, potential transPormers, the analog multi~)lexer, and the sample and hold circuits. It is more convenient to discuss the schematic diagram in the order in which the si~Jnal is *etected by the apparatus and processed throughout the apparatus.

Co-Processor The schematic diagram Fig. 25-l ..Fig. 25-13 will be discussed by tracing the input signal through their processing by the electronics, inclu~ing the co-processor U56 Fig. 25 9. The main processor U1 Fig. 25-1 will be discussed hereinbelow.
The co-processor U59 provides rapid sampling of both voltage and current from each of the phases of a 3 pt)ase AC
line. Simultaneous values of voltage and current are sampled uslng an analog sample and hold chipo Also, the co~processor do~s multiplications and sums based on the measured values of current and voltage. A Texas Instruments type TMS 320L0 microprocessor has been found suitable as a co-processor~

~, ;~o~

Volta~e and Current In~ut Signals Fig. 25 11 show~ the input current transformers CTl, CT2, CT3, and also ~how~ the input potential transformers PTl, PT2, PT3. The input trans~or~ers are also shown in Fig. 23.
S The secondaries of the transformers are clamped so that their output voltage doe~ not ~xce~d approximately +lQ.7 volts and -10.7 volts. The source of the clamping voltage is shown in Fig. 25-11 at the upper right corner. A VLSI chip, U75, provides a precision 10 volt output voltage at its pin 6. The U75 VLSI chip i~ particularly insensitive to temperature changes, and so the +10 volt reference output voltage at pin 6 of U75 is substantially independent o~ the temperature of the apparatus. A Linear Technologies type LT1021CCN8-10 device has been found satisfactory as chip U75. `The +10 volt reference source is amplified by op-amp U78-D op-amp U78-C, and finally has current amplification by transistor Q6. The emitter of ransistor Q6 provides an approximately 10.7 volt signal SRCC. Signal SRCC connects to diode CR6, CR3, C~10, CR12, CR14, and CR16 in order to provida a clamping voltage for ~hs input transformers. Also, the +10 volt reference, lOVR, provides input to op-amp U78-A
and current a~plifying transistor Q7 ~o provid~ an approximately -10.7 volt reference identified as signal SNKC~ Si~nal SNKC provides clamping voltage to diode CX5, CR7, CR9, CRll, CR13, and CR15 on tho secondaries of th~
~nput tran~form~rs.
~ preci~ion 4.75 volt source is provid~d by ths ~10 volt reference, lOVR at t~ outpu~ of op-amp U73-3. The 4.75 vol~
sourcQ is .idanti~ed as FSC. Slgnal FSC i~ u~ed to calibrate - - 2~
the analog to digital converter, as will be described more fully herein~elow.
The secondarie~ of the txansformers connect to analog multiplexer U73. The output of the current transformers CTl, CT2, CT3 connect to input Al at pin 19, input A2 at pin ~0, and input A3 at pin 21, respectively. Inputs A4, A5, A6, and R8 connect to ground, and thereby provide a zero reference input to the multiplexer U73. Potential transformers PT1, PT2, and PT3 connect to input 31 at pin 11, B2 at pin 10, and B3 at pin 9, respectively. Input~ B4, B5, B6 and B8 connect to ground. Input A7 at pin 25 and input B7 at pin 5 connect to signal FSC, the 4.75 volt preclsion calibration voltage provided at the output o~ op-amp U78-B, as shown in the upper right side oP Fig. 26-11.
;Analog multiplexer U73 has an output at Drain A at pin 28 connecting to "sample and hold" circuit U76. Analog multipl~xer U73 has an output at Drain B pin 2 connec~ing to "sa~ple and hold" circuit U77.
The output o~ 'isample and hold" ~ircuits U76, U77 connect to ~eparate inputs, pin 2 and pin 10, respectively, of analog multiplexer U81. one input or the other may be directed through an output switch to op-a~p U82, at its input pin 3.
The output o~ op-amp U82 provide~ an input to analog to digital converter, ADC U80. The gain o~ op-~mp U~2 is controlled by switch B of multiplex~ U81. Thus, op-amp U82 provide~ an adjustable gain buffer on the input line to ADC
U80.
~ultlplQx~r U73 i~ controlled by signals on line ~NA0, ANAl, and ANA2 on pin~ 17, 1~ and 1~, r~spectively.
Mul~iplexe~ U81 ie controlled by signal~ ISEL, VSEL, and 2XH

2~
at its pins 1, 9, 16. These control signals all derive from various pins of output latch U64, where latch U64 is conneoted to the 16 bit data bus of the co-processor, as shown in Fig. 25-lO.
In operation, potentials proportional to current flow and voltage on th~ conductors controlled by the LMn appear at respective input pins of analog multiplexer U73. Beginning at a particular instan~ in time, sample and hold circuits U76,U77 sample a selected current signal and a selected voltage signal. The two signal~, one current and one voltage, are both sampled durinq the same time interval, beginning at the selected instant. The two respective signals are "held" for digitization by ADC U80. ADC U80 then digitizes the two signals in a prescribed ord~r, and transfers the results of each digitization to the 12 bit bus, ANDBO...ANDB11, at its output channel DBO...~Bll at pins i6..-.27 of ADC U80. The 12 bit bus ANDB0...ANDB11, connects to digital buffers U62, U63 a~ shown in Fig. ~5-lO. Digital buffers U62, US3 pas~ tha digitized values to the 16 bit data bus TDO...TD15, o~ the co-processor U56 under the conkrol of clocX strobe RS0 at their input pin l. Strobe R50 is generated by address de~oder U60 under ~he con~rol o~ address bus TAO...TAll of co-proce~sor U56. Digital buffers U62, U63 provide inpu~ of the digi~iz~d curren~ and voltage signals ~o thQ 16 bit data bus TDO... TDlS o~ the co-processor U56.
Also shown in Fi~. 25 11 i~ a precision quiet power supply for the ADC U80. Precision voltage re~erence chips U83,U84 provide power suppli~ for op-a~p u7s-a. The output of op-amp U79-B at its pin 7 provide~ a power supply to --10~ ~

transistor Qll. The output of transistor Qll at its pin 3 provides a precision quiet 5 volt 50 ~illiampere power supply for AD U80, and iR supplied to ADC U80 at its pin 1.

Zero Crossinq Detector As shown in Fig. 25-11, a zero crossing detector is for~ed from op-amp U79-A, which takes input at its pin 2 from the phase A potential signal by connection to the secondary of potential transformer PT1. Output pin 1 of op-amp U79-A
undergoes a transition at each zero crossing of the potential at pin 3 o~ the secondary o~ potential transformer PT1, and thereby causes the logical state of the output of transistor Q8 at pin 3 to undergo a transition. The logical transition of the output of transistor Q8 is coupled into a phase locked loop consisting of VLSI chips U71, U72, U74-A, and U57-C.
Output pin 6 of VLSI chip U74-A carries 32 pulses per phase A

AC~cycle. The sign~l at output pin 6 is designated ~MSINT
and connects to co-processor U56 at its input pin 5 to generate an interrupt to co-processor U56. The interrupt control~ sampling of voltag~ and curr~nt values at 32 equally spaced time intervals in the phase A AC cycle. Co-processor U56 is shown in Fig. 25-9.

Co-e~;Qcessor ClocX
Co-processor U56, shown in Fig. 25-9, ha~ an internal cloc~ controlled by cry~tal Y3. For example, crystal Y3 may operate the internal clock at a frequency of approximately 14.3 megahertz.
~s sho~n in Fig. 25-10, thr~e 4 bit counter~ U67, U68, U~ coun~ pulse3 on signal CLOCKOUT ~ro~ co-pracessor U56 at -105- ~

pin 6, and derived from the clocX controlled by crystal Y3, in order to generate "accurat~ clock time"O Counters U67, U68, U69 are controlled through digital latche~ U65, U66.
Latches U65, U66 latch accuratQ clock time onto the da~a bus TD0...TD15 of co-processor U56, as shown 'in Fig. 25-10.
Service o~ latches U~5, U66 is done each of the 3~ sample periods generated by the phase A zero crossing circuit, as initiated by the sig~al TMSINT input to co-processor U56 at its input pin 5.

Additional Co-Processor Peripherals As shown in ~ig. 25-9, input and output for co-processor U56 i5 provided by the 16 bit data bus TD0...TD15 at pins 18...26 of co-procsssor U56. Data bus pull up resistors RP13-A, RP14 pull up the data bus lines to +5 volts in order to defino data bus line potential.
A 12 bit address bus TA0...TAll for co-processor U56 connects ~o the co-processor at its port A0~..All. The address bu~ uses pull up resistors RP16-B, RP13-B in order to define potentials on the address bus line.
A3 chown in Flg. 25-~, elec~rically erasable programmable read only ~e~ory chips U53 and U54 each have 64X bits or 8K
BYTES of memory for holdin~ the co-proc~ssor U56 program.
As shown in Fig. 25-9, output strobes are generated from the address bu~ by address decoding logic circuits U57-B, U8-D, U57-A, U58-B, U59-A, U59-B, and U59-D, as s~own in ~ig~ 25-7. The output s~robe~ aro identified as signals TROMEN ~or th~ EPROH U54, and TWDP0RT and TDPORTCE, for the dual port RAM U51.

201~04~
Write strob~s ara generated from the address bus ~y d coder U61 shown in Fig. 25-9 for the devices shown in Fig.
25-10 an~ Fig. 25-11.
Read strobes are generated from the address bus by decoder U60 as shown in Fig. 25-9 to acti,vat~ bufferq to send data to co-processor U56 from devices shown on Fig. 25-10 and Fig. 25 11.

Dual Port RAM Co-Processor Side Fig. 25-8 shows the dual port memory. U51 and U52 each provide 1 K BYTES of 8 bit dual port RAM. The 16 bit data bus TDO...TD15 of co-processor U56 connects to RAM U51 at its input ports DOR...D7R at its pins 25...32, and connects to dual port RA~ U52 at its input ports DOR...D~R at its input pin~ 25...32. The co-processor U56 address bus TAO...TA12 connects to dual port RA~ U51 at its input ports AOR... A9R, and connects to dual port RAM U52 at its input ports AOR...A9R, that is at pins 33...42 o~ U51, U52 res~ectively.
Dual port RAM U51, U52 transfers information from co-processor U56 to main processor Ul, shown in Fig. 25-1.
Input to main processor Ul is provided once each AC cycle : on phase A ~rom th~ dual port RAM, s~own in Fig. 25-8. Also input to main proces~or U1 occurs from the k~ypad switches, the trip unit serial communications inpu~ port, and the optical ring serial communications port, the programmable read only ROM, U47, Fig. 25-7, associated with the ~ain ~roca~sor U1, and from the other peripherals.

2~

Main Processor The main proc~ssor's hardware will be described starting with thQ main proces~or Ul as shown on Fig. 25-1, and working through the peripheral devices.
Main processor Ul has a 23 pin address bus Al.. ...A23.
~ain processor Ul has a 16 bit data bus DO..... D15.
Resistors RP3, RP4 serve as data bus pull up resistors to define the potentials on the data bus DO...D15.
Resistors RP1-B, RP5, RP6, RP7-A, RP2, and RP10 serve as addres~ bu~ pull up resistor~ to define the potential on the address bus Al...A23.
It has been CQnVenient and satisfactory to use a Motorola type 68000 microprocessor for microprocessor Ul. Signals appear at the pin~ of microprocessor Ul as follows:

. PIN SIGNAL

` 14 A +5 volt operating voltag~ is applied to microprocessor Ul.
lS Ground conn2ction.

18 RESET, pull "low" and return "high" to start the microproces~or at a known addrPss. Hold "high" to keep the microprocessor running.

. ~ .
DTAC~ Input to the microprocessor as a peripheral handshake.

21 VPA ~n input signal to ~he microprocessor as a handshake signal from th~ M6800 family of chips.

19 VMA An output signal from the microprocessor as a handshake signal to th~ M6800 family o~ chips.

~ 20 ~ Clo~k Output siynal a~ an intarface to ~00 ~amily Or chips.
~108--17 HALT The halt and reset signa}s are pulled "low" and pulled 1'high"
simultaneously~
12 Not used.

l3 - 11 IPL0 Interrupt requ~st bus for interrupt coming from a peripheral.

24 IPLl Interrupt request bus for interrupt coming from a peripheral.

23 IPL2 Interrupt request bu~ for interrupt coming from a paripheral.

; 6 AS Address Strobe, output from microproce sor, verifies that a valid lS address has been outputted by the ~icroprocessor.
.

- 7 UDS Upp~r Data Strobe microproc2ssor output.

8 LDS Lower Data Strobe microprocessor output.

9 R/N Read/Write Strobe ~icroprocessor ou~pu~ .

C~ Microprocessor clock input pulss.

28 FC0 Function Code outputted by microprocessor which re~lects state of ~5 processor, includlng recognitiQn or acknowledgment of an interrupt signal from a periph~ral~

2? FCl Sa~e USQ a5 FCO.

26 FC2 Sam~ u~e a~ FCO.

~ n abbreviated diagram of the main processor Ul bus cycle i~ shown in Fig. 26. As shown in Fig. 26, the main microprocessor U1 sets addresses on the addrass bus. The microprocessor then generates a data strobe, such as AS, LDS, or UD5, as shown in Fiy. 26-~. An enable'si~nal is generated by the microprocessor to permit tha peripheral tc become active, as shown in Fig. 26-D. The enable signal is generated by circuitry external to the microprocessor Ul, but in response to data strobe signals and addresses generated by the microprocessor. The strobe signals are usually the LDS, UDS and AS signals. Also, an output enable signal as shown in Fig. 26-E is generated by circuitry external to the microprocessor to activate the output of a peripheral. llhe peripheral responds by providing a DTACK signal after receipt o~ the strobe, as shown in Fig. 26-C. The DTACK signal enables the microprocessox to proceed with the bus cycle.
The signal R/W, as shown in Fig. 26-F is generated by the ~icroprocQssor U1 at its pin 9 in order to activatQ a peripher 1 to either read or write. If the R/W signal is "high" then "read" is true and the peripheral is activated for microprocessor Ul to read from it. If the R/W signal is "low" then "write" i~ true and the peripheral is activated to be written to by microprocessor U1.
As shown in Fig. 26 G, a validated transfer occurs on the data bu~ so~e~ime after the approyriat~ strobe signal and the appropriate other con~rol signals reach their l't~ue"
value, and after the microprocessor receives a ~TACR signal.
The timing is arranged so that the data tran~fer occurs after suf~icient time has pa sed for tra~sient3 to di~ out~

Control lines provide signal~ to main proc~ssor U1, as shown by the arrowheads pointing ~oward main processor Ul in Fig. 25-1~ Control signals provided by main processor U1 are shown by lines having arrowheads pointing away from the main procPssor in Fig. 25-1.
Fig. 25-2 show addresq deco~er U3. Address decoder U3 derives signals from 2ddress bus lines A20...A23.
Output of address decodar U3 are OR gated with one of the following signals, UDS, LDS, or AS. The signals are "active low" signals. Circuits such as U6-D, U6-A, U5-D, U5-C, etc are OR gates. The OR gates provide Boolean ~ND logic function Eor active low signals. If both inputs are low, the output will be low. I~ one input is low and one input is high, the output will be high. If b4th inputs are high the output will b~ high. Thus, a generation of an output active low output signal only occurs wh~n both input signals ar2 low! and ther~fore ~he OR gate provides a Boolean AND
function for the "active low" signals~
As shown in Fig. 25-3, the signals ROMSEL, RAMSEL, and DPORTSEL are taken directly from outputs YO, Yl, Y2 o~
addre~s decoder U3. 5ignals produced by OR with th~ upper data strobe signal UDS and the output-~ o~ YO, Y1, Y2 includa ROMENH, RA~ENH. Signals produced by a logic OR of the lower data strobe signal LDS and the outputs o~ YO, Yl, Y2 include - . .
th~ signals RO~ENL, R~ME~, and D~ORTDS. O~her signals produced by a logical OR between the signal LDS and anoth~r output o~ handshake strobe gensrator U3 include tha signals EEPROMENL, DPORTW~. Signal DI5PENL i5 produced by a logical OR between ~ignal VMA ~rom microprocessor U1 pin 19 and output Y1~ o~ handshak~ generator U3. Signals produced by a logical OR between address strobe signal AS and output of and sha~e strobe generator U3 include the signals DPORTEN, TIMENL, DUARTlEN. Signals produced by a logical OR between R/W and previously generated signals include; RAMOEH, RAMOEL, _ .
and EEPROMEL, DPORTOE. All of the afore~entioned signals are "active low" signalsO
The signal~ ROMSEL, RAMSEL, and DPORTSEL connect to multiplexer U13 Fig. 25-3. Multiplexer U13 generates data transfer acknowledge signal~ for the main processor Ul for the electrically erasable programmable only memory, EEPROM, the RAM, and the dual port RAM. Multiplexer U13 includes a timer which allows time for the peripheral to settle before generation of the DTACK signal.

Functionally, signals ROMSE~, RAMSEL, DPORTSEL connect to data ~ransfer acknowledge generation chip U13. U13 generates the DTACX signal as the handshake acknowledge signal input to the microprocessor.~
Signal ROMENH strobes the high BYTE of EPROM chip U45 shown in Fig. 25-7.
Siynal RA~EN~ ~robes high BYTE of R~M chip U46 as shown in Fig. 25-7.
Signal ROMENL strobes lower RO~ BYTE chip U48, and EEPROM
chip shown in Flg. 25-7.

Signal RAMENL ~trobes lower BYTE RAM chip U49 as shown in Fig. 25-~.

Signal DPORTDES is a dual port ~AM data strobe, and connects ~o gate U~l-A at Fig. 25-3, and provides input ~o the data trans~er acknowledg~ g~neration chip Ul30 4~

Signal EEPROMENL strobes th~ EEPRO~ chip U47 shown in Fig. 25-7, and also enables generation of a DTACK signal at chip U20~A shown in Fig. 25-3.
Signal DPORTWE is the dual port read/~rite enable siynal S and strobes both dual port RA~ chip U51 and chip U52 at their pins 2 a~ shown in Fig. 25-8.
Signal ~ISPENL enables the display, and strobes the display control chip U30 at its pin 23 a~ shown in Fig. 25-4.
Signal DPORTEN i~ the dual port RAM anabl~ strobe and strobes both upper dual port RAM chip U51 and lower dual port RAM chip U52 at their pin 1 as shown in Fig. 25-8.
Signal TI~ENL strobes a timer reeident in the keypad control chip U34 as shown in Fig. 25-5.
:Signal DU~RTIEN is the enable signal ~or the dual universal asynchronous receiver transmitter chip U38 at its pin 35 as shown in Fig. 25 6.
.
Siynal RAMOEH enables RAM high BYTE chip U46 for the microproce~sor to read or write.
Signal RAMOEL enables th~ low BYTE RAM chip U49 for the - 20 microproce~sor to read or write to it as s~own in Fig. 25-7.
Signal EEPROMOEL enables EEPROM chip U47 at its pin 20 for the microproces~or tQ read or write to it as shown in Fig. 25-7.
Signal D~ORTOE enables dual port RAM chips U51, U52 for th micropro~essor to r~ad or write to the~ as shown in Fig.
25-8.
ClocX pul~e~ are devalop~d by chip U12-B and chip U12-A
from an input of si~nal SYSCLX. Signal SYSCLK is g~nerated by crystal Y~ and i~ provid~d to main proces~or U1 at its input terminal lS.

2~ ~4~3~
Signals produced by chips U12~, U12A include MFPCLX, a 4 megahertz signal connected to U34 at its pin 35 as shown in Fig. 25-5: and signal SIUCLK, a 500 kilohertz signal connected to circuit U38 2 as shown in Fig. 25-6; and signal MFPTIMER, a 11.25 kilohertz signal connected to chip U34-17 as shown in Fig. 25-5.
As shown in Fig. 25-3, chip U18 is connected to address bus line Al, A2, A3 and develops output signals INTACX5 and INTACK6 as interrupt acknowledge signals for smart peripheral U34, shown in Fig. 25-5. Also, signals FC0, FCl, FC2 from main processor Ul serve as input to gate U17-A, and the output of gate U17-A is ~ND gated with output of chip U18 to produce the signals INTACX5 and INTACK6.
Signal VPA is an acknowledge signal ~rom peripheral to the main processor Ul that a data transfer is ready for transfer into the main processor Ul from a 6800 type chip.
Signal VPA is an input signal to main processor Ul at it~ pin 21, and ~ignal VPA is developed by tristate buffers U15 A, U15-B, after logi~ proc~sing oP output from chip U18, 2 signal FC0, FCl, FC2, and signal AS, and signal DISPSEL
obtained ~rom chip U3 at pin 14 as shown in Fig. 25-2.
The HALT and RESET signals for ~ain processor Ul at its pins 18 and 17 ar~ generated by inverters U2?-A, U27-F. The HALT and RESET signals simul~aneously pull the HALT and RESET

inputs at pins 17, 18 of main processor Ul low. The signals ar2 generated by chip U2S in response to an output signal from chip U29-A at its pin 4. Chip U~9-A i9 controlled by a number oP signals including switch Sl, a SPDT momentary contact switch controlling tho inp~t to gate U7 B, and a - 2~4~.
watchdoy reset signal WATCHDo~ RST from chip U36 pin 3 as shown in Fig. 25-5 and a~ d~scribed hereinb~low in the watchdog section.

Out~ut Display Yig. 25-4 shows chip U30, a versatile interface adapter, which is a parallel to serial converter for oontrolling the output display. It i5 used also as a timer for software interrupt for timing service of the keypad switches. The keypad input is checked every 10 milliseconds under control o~ the timer. Chip U30 receives input fro~ main processor data bus DO...D7. Also, chip U30 receives input on main processor address lines Al...A4. A strobe to reset the display is generated through tran~istor Ql using output signals from port CA2 pin 39 o~ chip U33. Also control signals for the display arP derived fro~ pins 18, 19 of chip U30. The display controller is chip U31. The vacuum display is ~ 1~ alphanu~eric unit indicated as DSP1. A filament power supply ~or ~he display unit i3 provided on pins 1,33 of unit DSP1.
Also shown in Fig. 25 4 is comparator U41-A which serves as a power ~ailure detectorO Comparator U41-A ha~ an input of +5 volt3 and an input o~ -30 Yolt~. In the event of a pow~r failure, signal IPWRF~IL i~ produced a~ tha output of comparator U41-A, and prevents the main proces~or Ul ~rom tripping the circuit breakar if th~ LMU loses power.
Fig. 25-5 shows the s~art peripheral U34, which may be a Motorola t~p~ MC S8501 ~ultifunction I~0 port. A

demul~iplexsr U35, and k~ypa~ swi~che~ S3, S4 ar~ also shown ;~Q~
- in Fig. 25-5. Switch S3 is ~ine ~eypad switche3. Switch S4 is 12 keypad switches. The keypad switches operate through demultiplexer U35. Demultiplexer U35 is controlled by address select lines ~or reading Xey switch rows derived from s~art`peripheral U34 at its output pins 27, 28, 29. Reading columns of switches is controlled by smart peripheral U34 at its input lines I2, I3, I4 at pins 24, 2S, 26. The smart peripheral U34 i~ connected to main processor data bus DO...D7, and also is connected to main processor address bus line Al... A5. The Xey switch and the set up ~witch are serviced through output pins 22 and 23 of smaxt peripheral U34. The watchdog square wave signal WATCH~OG-RST is provided by an oscillator in smart peripheral U34 at its output port TAO pin 13.

Switch line potentials are defined ~y pull up resistors RP10 and RP7. Key switch and set up line potentials are defined by pull up resistors ~P12-B, RP12-C~

Manual Reset - Switch S1, Fig. 25-3, is a SPDT ~omentary contact switch that is no~mally open. Depression o~ switch Sl by an operator c~uses the main processor to reset. Switch Sl is us~ul in testing the LMU.
A resat pulse is generated by input of a pulse to chip U29-A at its pin 1 through AND gate U7-B. Chip U29-~
generates an ou~put pulse in response ~o its input pulse at pin 1, and the output pulse appears at pin 4~ The output puls~ ser~es as input to chip U2S. In response to its input pulse, chip U26 ~anerates a output pulsa at it~ pin 3. Th output pu1s2 a~ pin 3 o~ chip U26 is buf~er~.d by open -~16 collector inverter U27-A which provides a signal ~ALT to main processor Ul at its pin 17 Fig. 25-1. Also, the output of chip U26 at its pin 3 provide input to open collector inverter U27-F which provides a signal RESET which rese~s a variety of peripherals as shown in Fig. 25-3.
In operation, chip U26 reset~ the main processor by driving its output pin 3 low and holding it low for approximately 1/2 second. At the expiration o~ approximately 1/2 second, the output pin 3 of chip U26 is driven "high", thereby restarting the main processor Ul. The main processor does not requlre a full 1/2 second of a low halt signal, but by using a 1/2 second "low" signal the peripherals have ti-me to stabilize in preparation for a high transition on the RESET signal. Chip U29-A is a pulse shaping circuit providing an input trigger to chip U26. Chip U2~ generates the HALT and the ~ESET signals.
Upon the event o~ a halt signal going low for a sufficiently long time period, and then going high~ main processor U1 starts at a known addr2ss with a known supervisor set p~int.

Watchdoq On power up the main processor Ul instructs peripheral U34 to begin generating a square wave output at it~ port TA0 pin 13. This square wave provide~ input to inverter U33-B

2[3~4~
and tristate buffer U36-A. The output of tristate bu~fer U36~A provides the signal ~ATCHDOG RST, which is input to chip U9 pin 1 FigO 25-3. A square wave having a period of approximately 1/6 seconds is produced as signal WATCHDOG
RST. A~ter power up, a clock in peripheral U34 continually generates the signal WATCHDOG RST. Even if the main proc~ssor dies and ceases operation the square wave signal WATCHDOG RST continues being produced by peripheral U3 4 .
Signal WATCHDOG RST provides input to chip U9-A pin 1.
Chip U9-A is a 4 bit counter which counts the incoming pulses at its pin 1. In the event that 8 input pulses at its pin 1 are counted, output of chip U9-A at its pin 6 goes high, and cause~ a reset of main processor Ul.

~Signals AS, G are applied as input to OR circuits U5-A
and thè; output i~ applied to OR circuit U7-A along with signal RESET~ The output of OR circuit U7-A provides input to pin 2, RST, of c~ip U9-A. An input pulse at pin 2 causes U9 A to reset it3 internal counter. When the main processor is operating prop~rly, input pulses will occur at pin 2 of chip U9-A suf~iciently often to prevent a count of 8 pulses fro~ signal WATCHDOG RST coming into chip U9-A at its pin 1.
In ths event that main pros:essor Ul should cease operation, then no res~t pulse will be applied to chip U9-A at its pin 2, and a reset pulse will be appli~d to the main processor after chip U9-~ counts 8 W~TCHDOG RST pulses.
Th~ signal WATCHDOG RST provide-~ a mean~ ~or resetting the main processor in the ~vent that it should cease functloning. Thus, th~ signal W~TCHDOG RST provides a recovery means in th~ evant that the ~ain processor should hang up, for example, from a power glit~h, or other cause.
o:L18--2~
In an alternativ~ embodiment, the occurrence of output pulses ~rom chip U9 A pin 6 as a result of counting 8 or more WATCHDOG RST pulses may trigger the transmission of a waxning signal ~rom the LMU to the SIU, or in some other way alert an operator that the main processor ic misfunctioning.

InterruPt Request Generation As shown in Fig. 25-3, interrupt request generator U28 ~ccepts input signals from peripherals requesting an interrupt o~ the main processor U1. Interrupt generator U28 then generates an interrupt signal on the interrupt bus comprising main processor lines IPLO, IPLl, IPL2, at pins 25, 24, 23, xespectively o~ the main proressor~
A Motorola type 74HC147 chip has been found sati~factory as tha interrupt request generator U28.
The interrupt request bus is a 3 bit bus, ~nd the value of the binary signal on this bu d~t~rmines the priority of the int2rrupt r~-~uest. The priority of the interrupt request is determin~d by the location on the interrupt reguest generator input at which the interrupt request occurred. The interrupt request i~ "acti~e low", and a low signal on any of tha U28 chip input lines D2...D3, D5...D7 gen2rates a corresponding signal on the interrupt bus.

A power fail interrupt request has highest priority~ and is provided by chip U41 at it~ pin 2 in Fig. 25-4. Re~erring to Fig. 25-4, chip U41-A drive~ its outpuk "low" in th~ event that the power supply goe~ low. The signal IPWRFAIL goes --l~g--- low, or "true'7, and causes a highest priority interrupt on the interrupt bus. The power failure interrup~ prevents the main processor from tripping the circuit breaXer in the event that the LMU loose~ power.

Signal IDUAR~ provides input to the interrupt request generator at its pin 3, and signal IDUART comes ~rom DUART
U38 pin 21 Fig. 25-6. When signal IDUART goes low, or "true", an interrupt request is provided by interrupt request generator U28 on the interrupt bu~, causing the main processor to service the DUART U38. The DUART has a number of register~, and the main processor services the DUART by reading and writing these registers. The registers in~orm the:main processor what has happened, including: that an input signal has been received from the trip ~nit, that an inpu~ signal has been received ~rom th~ optical ring, or that a transmission into the optical ring has been completed.
Other functions signaled through the DUART include signals neces~ary for perfor~ing and controllin~ external tests o~
the trip unit. A ~e~ory map of the main processor and also the register~ in the peripherals is given in Fig. 27.

Signal IMFP provides input to interrupt request gsn2rator U2~ at its pin 2. Signal IMFP derives ~rom chip U34 a~ its pin 32 Fig. 25-5. Chip U34 is the keypad decoder, and the interrupt request signal IMFP indicates that a key ha~ b~en depressed, and request3 that th~ ~ain proc~ssor service ~ha keypad.
Signal IDPORT i5 input to the interxupt request gen~rator at its pin 13. When signal IDPORT goes "lown, it signals ~he 2~
interrupt request gen~rator to request the main processor to read the dual port RAM.
Signal IVIA i~ input to interrupt reques~ generator U2B
at its pin 12. Signal IVIA i~ produced by chip U30 at its pin 21 a~ shown in Fig. 25-4. Chip U30 rs the vacuum display versatile interface adaptor. Signal IVIA is necessary for operation of the vacu~m display by the main processor.

Handsha~e ~TACX Signal The DTACK signal is generated by a number of peripheral device~ to indicate that it is ready to either provide data on the data bus or receive data from th~ data bus. Also, the DTACK signal may be generated external to the peripheral when the generator delays generation of DTACK by using a timex long enough for the peripheral to respond. The DTACK signal connects to microprocessor Ul at its pin 10, Fig. 25-1.

Dual Po~t RAM IDPORT Signal The co-processor writes information into the dual port RAM once each AC cycle. A semaphore works by the co-processor setting a signal indicating that l'yes, the data is good and valid~. Th~ main processor then completes a rea~
of ~he in~ormation stored in the dual port RAM, and clears the semaphore. The next time that the co-procsssor ~egins to writs in the dual port RAM, the co-processor checks the semaphor2, and if it has not been cleared by the main processor, the co-processor signals an error to th~ main proces~or. The semaphore ~ignal~ operate a~ messages stored in Rk~ and a~ parame~ers ~n software.

!' zo~o~g~L

The IDPORT siqnal is genPrated by the co-processor simply writing to a specific addres~ in the dual port RAM. The int~rrupt is cleared by the main processor reading that cell in the dual port RAM. By reading that cell in the dual port RAM, the main processor clears the interrupt so that the dual port RAM is ready for the next Phas~ A AC cycle.

LMU Communications ~ ig. 25-6 shows the LMU serial communications circuits.

Chip U38 is a dual universal asynchronous receiver transmitter, DUART. DUART chip U38 connects to the main processor U1 data bus DO...D7, and connects to the main processor address bus lines Al...A4. A crystal clocX is controlled by crystal Y2, and may, ,for example, generate a signa~ of 3.S864 megahertz. Also, DUART chip U38 is controlled by a number of signals including R/W, IRQ, IACK, CS," RESET, and SIVC~K. Chip U38 generates a DTACK signal at its pin 9.
Co~munications on the fiber optic ring between the LMU
and an SIU i~ controlled through chip U38 output pin~ 29, 30, 31. Photo diode J901 receive~ the input optical signals from the optical fiber. The voltage generated across photo diode J16 is ampli~ied by op-amp U901-B. A second stage of amplification is provided by op-amp U901-A~ An adaptiYe threshold circuit is provided by op-a~p U901-C. Comparator U902-A and the adap~ive thr~shold circui~ provid~ a data detection function~

~ uffer amp U903-C operate~ as a data paS5 switch~ When input pin 10 i~ "low" th~n ~uff~r amp U903-C provid~s an output that reproduces its input. When pin 10 of buffer amp U903-C is ~'high", then bu~fer amp U903-C acts as a high impedance at its output pin ~, and prevent~ the input signal at input pin 9 from appearing at output pin 8.
A~ input signal is applied to inverter U904-A at its input pin 1 by either the output o~ buffer amp U903-C pin 8 when buf~er amp U903-C is enabled with a "low" at pin 10, or a~ternatively the input to inverter U904-A is provided by outp~t pin 30 of DUART chip U38. Pin 30 of DU~RT chip U38 connects to input pin 12 o~ ~uffer amp U903-D, and signals pass from output pin 11 o~ buffer amp U903-D to input pin 1 o~ inverter U904-A. The output of inverter U904-A drives the gate of transistor Q902. Transistor Q902 drives light emitting diode, LED, at ja k J902. LED at jac~ J902 is a light ~sourc~ providing optical signals in th~ output optical fiber cable. Transistor Q901 provides current limiting for output transistor Q902.
A "transmit'1 or "receive" control signal is provided on output pin 29 by DUART chip U38. Pin 29 then can go either "high" or "lown. Wh~n pin 29 is "high" it blocks an outgoing signal through bu~fer amp U9Q3 D. The "high" value also is input to inverting inverter U904-B, and provide~ a "low"
signal at pin 10 of buffer amp U903-C, khereby enabling buffer amp U903-C to pass an incoming ~ignal on it~ pin 9 through to LED driv~r transistor Q902. In the event that DUART chip U38 pin 29 go~ "low", the "low" signal enable~
buf~er amp U903-D and therefora p~rmit~ an output ~ignal on chip U38 pin 30 to pas~ through to LED driver tran~istor Q902, and simultaneously inverter U904-~ inverts the logic signal th~reby applying a ~highN to pin 10 o~ buffer amp U903-C and blocking any input signal at pin 9 of bu~fer amp U903-C from appearing at output pin 8 of buffer a~p U903-C.
Pin 31 of DU~RT chip U38 provides an input for the LMU
from th~ optical ring.
In operation, pin 29 of DUART chip U38 is normally "high"
so as to block an output pulse from the DUART, and enables an input signal coming from the optical ring to pass through buf~er amp U903-C. The input signal i~ provided to main processor Ul through input port pin 31 of DUART chip U38. In the event that mairl processor U38 decides to transmit a message into the optical ring for receipt by the SIU, then first the control line at pin 29 of DUART chip U38 is driven "low" to enable buffer amp U903-D, and to inhibit buffer amp U903-C. After the outgoing message is transmitted by the main processor Ul, then the control line at pin 29 of DUART
U38 returns to its normal "high~ level.
A test sequsnce for the circuit breaker Trip Unit TU can be initiated by DUART U38 at its output ports OPl, OP2, OP3, oP4, OP5, and OP6. Transistor Q4 may be driven into conduction by a ~ignal on output port OP6 at pin 26 of chip U38. Transistor Q4 drive~ relay Xl.
Outpu~ port 0~5 may drive transistnr Q5 into conduction.
Transistor Q5 con~rols relay K2. ~hen relay ~2 is energized, then a +24 volt supply is connected to variable resistor R70 which i~ a front panel knob on the LMU front panel. Variable resi~tor R70 may be adjusted to supply a variable test voltage VTST to the trip unit. A 24 volt supply or upplying electrical power to the ~rip Unit i~ provided on jack J5 at pin 5 a~ +24V EXTJ

-1~4-2~0~
Output ports OPl, OP2, OP3 provide a 3 bit control bus to control the Trip Unit in test mode. Optoisolatcrs U42, U~3, U44 provide electrical isolation between the L~U and the Trip Unit.
Output port OP4 provides an external trip for the Trip Unit. If OP4 goe~ "low" then th~ Trip Unit trips and opens the circuit breaker.
Input port RXDB at pin 10 of chip U38 provides input to main processor Ul for the serial daka stream transmitted by the Trip Unit. The serial data stream passes through an optoisolator in the Trip Unit. That optoisolator is powered by the LMU using transistor Ql~ and op-amp U85-A as a voltage regula~or. The power for the Trip Unit's optoisolator is pro~ided as ~ignal RMVCC and appears at pin 15 of jack J5.
The input signal TDO from the optoisolator in the Trip Unit enters the LMU at pin 8 of jac~ J5, and provides input to buf~èr op amp U40-B. The output of op amp U40-B is connected to pin 10 of DUART chip U33. DUART chip U3~ then provides input to main processor U1 of the serial data stream transmittsd by the Trip Unit.
RAML~d ~EPRO~
Fig. 25-7 shows EPROM U45, U~8. Each EPRO~ is a 256k bit device, and therefore holds 32X BY~ES. EPRO~ U48 connects to main proce~sor data bu~ line~ DO..... D7, and EPROM U45 connect~
to main processor data bus line~ D8.. ...Dl50 Both EPRO~ chip~

U45, U48 connèct to main processor address bus lines Al...A15. ~PROM chip U45 provid ~ a high BYTE and connects at pin 22 ~o ~ignal ROMENH ~rom c~ip US pin 11 Fig. 25-2.
EPROM chip U48 provid~ a low BYTE and connects at pin 22 t~
signal RO~ENL from chip U5~ ig. 25-2~ ~
-1~5-, f As shown in Fig. 25-7, chips U46, U49 are both scratch pad RAM for main processor Ul. RAM chip U49 connects to main processor data bus lines D0...D7. RAM chip U46 connects to main processor da~a ~us lines D8...D15. Both RAM chips U46, U49 connect to main processor address bus line~ Al.. All.

Both RAM chips U46, U49 receive read write signal R/W at each chip's pin 21. RAM chip U49 provides a low BYTE and is controlled by signals RAMENL derived ~rom ~hip U5 pin 8 Fig.

25-2, and signal RAMOEL derives fro~ chip U16 pin 3 Fig 25-2. R~M chip U46 provides a high BYTE and is controlled by -signal RAMENH derived from chip U6 pin 3 Fig. 25-2 and signal RAMENH derived from chip U8 pin 8 Fig. 25-2.
Chip U47 is an electrically erasable programmable read only~memory, EEPROM. EEPROM chip U47 connects to main processor data bus lines D0...D7, and connects to main procëssor address lines Al...A11. EEPROM chip U47 is - .
controlled by signals including read/write signal R/W, EEPROMOE~ signal derived from chip U16 pin 6 shown in Fiy.
25-2, and signal EEPROMENL derived from chip Ul6 pin 11 Fig.
25-2.
Chip U50 is a real time clock. The real time clock connects to main processor data bu~ lin~s D0...D7 and main processor address line Al...A13. Jumper 1 controls whether ~._ the real ti~e clock is reset by the signal RESET as shown in Tabla 1, also i~ Flg. 25~7O The clock enable signals WATCHCE

and ~ATCHOE deriva from chip Ul9 and chip U8 shown in Fig.
25-3, and serve as inputs to the real time clock U50. The clock enable signal WATCHWE derives fro~ chip U59 pin 8 shown -12~-in Fig. 25-3 is input to real time clock chip US0, under he co~trol o~ jumper ~MP2. Jumper connections are shown in table 2, also shown in Fi~. 25-7.

Dual Port RAM - Main Processor Side Fig. 25-8 show~ the dual port memory chip U51, U52. The left side o the dual port m mory connects to the main processor Ul.
Dual port RAM chip U51 connects to main processor data bus lines D0...D7, and connects to main processor address bus lines Al...A10. Dual port memory chip U52 connects to main processor data bus lines D8...D15, and connects to main processor address bus line Al...A10. The main processor data bus lines connect to their respective chips U51, U52 at ports DOL... D7L. Tha dual port memory chips U51, U52 connect to the main processor address bus line~ at their port AOL...A9L.
.The dual port read and write ~unctions are controlled by the signal DPORTEN derived from chip U4 pin 3 Fig. 25-2, a read/write signal DTQRTWE derived ~rom chip Ul~ pin 8 Fig. 25-2, BUSYL deriv~s from chip U13 pin 17 Fig. 25-3, and read ~ignal DPORTOE derives from chip U8 pin 3 Fig. 25-2.
Dual port memory chip U51 port INTL pin 4 provide~ the IDPORT signal. The corresponding port on dual port memory chip U52 is simply tied to +5 volts. Signal IDPORT provides an input to interrupt request chip U28 shown in Fig. 25-3.
Interrup~ raquest generation chip U28 provide~ output signals for input to the main processor Ul interrupt bus lines IPEL0, IPELl, IPEL2 on pins 25, 24, 23 of ~ain processor Ul.

U56 signal IDPORT signals the main processor Ul that the co-yrocessor ha~ loaded the dual port RAM chips U51, U52, which the co-processor U56 does at the conclusion of each Pha~e A AC cycle. In operation, the co-processor retrieves phase voltage and current information from the A to D
converter 32 times per Phase A AC cycle. The co-processor computes running sums of a square current for that cycle, and a sguare voltage for that cycle, and the voltage times the current for that cycle for each of the phases. At the end of an AC cycle the results o~ these calculations for the 32 samples are then loaded into the dual port memory. Also, when the co-processor loads results into the clual port memory, it sets a ready semaphore by writing into the dual port RAM by writing it into a cell in the dual port memory.
Also the co-processor writes that signal which generates an interrupt to the main processor. The interrupt signal is the IDPORT signal at pin 4 of U51. The IDPORT signal then goes as ~input to interrupt request generator U28 pin 13 Fig.
25-3. Interrupt request generator U28 then provides an interrupt re~uest to the main processor U1.
LMU ME~U CQ~E
Fig. 28 shows the LMU push button switches, and a 16 character alphanumeric readout. A ~irst panel has a 9 switch ~eypad for selecting functions, and al~o a continuously ~dju~tabla po~en~iometer for applying a te~t voltage to the Trip Unit associated with the L~Uq. A second k~ypad contains 1~ or alternatively 16 push button switches con~aining ~he numeral. O...9, a '~clear entryl' an~ "data" push buttons.
~ig. 29 through Fig. 32 giv~ the ~ta read out of the LMU
3~ 16 character display. The variou~ item~ available to the Ll~g~
display are selected by pressing a proper combination of the con~rol push buttons. The control push buttons step through a menu, and tha menu~ are shown in Fig. 29 through Fig. 32.
The "select group" provides large scale selection o~
functions. The "select group" button ha~, for example, the following functions a~ exhibited in the accompanying figures, "meters" shown in Fig. 29; "view (or set) relays" as shown in Fig. 30; "view circuit breaker data" as shown in Fig. 31:
"view system testing" a~ shown in Fig. 31; "view event history" as shown in Fig. 31; "change or view the setup" as shown in Fig. 32, and changing the set-up i~ accomplished in combination with turning "on" a rear "set up" switch.
An LMU display option tree is sho~n in Fig. 33. The LMU
display option tree summarizes the operation o~ the various control buttons. Xeferring to Fig. 33, pressing the "select group" button once takes it to the 'Imeters" option, pressing the select group button again taXes it to th~ "rQlays"
option, pressing th~ select group button again takes it to the "breaker data" option, pressing th~ select group button again taXes it to the "system tests" option, pressing the select group button again takes it to the "ev~nt history"
option~, and pressi~g the select group button again take~ it back to the "meters~ option. Re~erring to Fig. 28, the left arrow button permits tha group selected by the "select group"
button to go in reverse ord~r, as shown by the double ended arrows connQcting ~he variou~ options in Fig. 33.
`Setting the "select group'l button to the "meters" option, per~it~ the "select ~unct~ann button to select quantities to be r~ad in the display. At the amps option, th~ s~lect data button can be pressed to permit the operator to view current -1~9-flow in either Phase A, Phase B, Phase C, or ground fault, as shown in both Fig. 27 and Fig. 33. Pressing the select function button oncQ again permits volts to be displayed, and the "select data" button permits the voltage on Phase A, Phase B, or Phase C to be displayed. Pressing the select function button again to the power factor option permits the select data button to select display of either average powar factor, Phase A, Phase B, or Phase C power factor, as shown in both Fig. 29 and Fig. 33.
Selecting the "PWR" option using the "select function"
button permits the "select data" button to permit viewing average power, reactive power, or Volt Amperes, VA.
Setting the "select ~unction" button to "demand" permits display of the present kilowatt hours demand, a predicted value entered into memory and available for viewing, and the peak value that has been observed Using the "select function~ button to select the "KWH"
option per~its viewing total energy in kilowatt hours. Also, - the ~requency of the Phase A AC line cycle and the current unbalance in Phase A, Phase B, Phase C are viewable by selection using the "se}ect function" button and the "select - data" button.
Setting ~he select group but~on to "view (or set) relays"
permits viewing o~ various alar~ thres~olds by a proper combination of pressing the select function and select data buttons. A~ shown in Fig. 30 and Fig. 31, the over-current alarm threshold may be viewed, and an alarm threshold, a trip threshold, and a trip delay tim~ may be observed for s ttin~s for undercurrent, over-voltag~, under-voltage, current 2~4~
unbalance, over-frequencyl under-frequency, and demand alarms.
As shown in Fig. 31 and Fig. 33, the breaker data option on the '~select group" button permits vi~win~ circuit breaker data.` Ths circuit breaker data is transm.itted to the LMU
through the Trip Unit serial communications link one BYTE
each 12 milliseconds. The "select function" button permits selection for viewing circuit breaker ratings or br~aker settings, where the settings are for either a circuit breaker or motor protector option. The breaker ratinc3s option permit3 viewing o~ the sensor current ampere rating and the plug ratio P. The breaker settings option, sel~cted by the "select function" button, permits viewing of the following in the circuit breaXer option mode, long time picXup, long time delay~ short time picXup, short time delay, instantaneous pickup, ground fault delay, and ground fault pickup. In the mo~or pro~ection version the followinq may be viewed, full load current, overload dQlay, locked rotor current, safe stall time, instantaneous pickup, ground fault pickup~ ground fault delay, and current unbalance PiCkuP
A i~system test" option may be selected by the "select group" button as shown in Fig. 31 and Fig. 33. The system test option permits testing tha circuit break2r Trip Unit ~y entering commands from the LMU push button panel. The "select function" button permits s~lPc~ing one of the options "tPs~ phase faul~ est ground faul~", or "test LMU". The "select data'^ push button, ~or both the phase ~ault and ground fault options permit testing "trip~ or "no trip'l, applying a test current, and applying a delay time. The "test LMU" option p~rmits checking the processor, the memory, the co~munication link loop back, and the volt~ or amps inpu~
to the analog to digital converter check.
The l'event history" option selected by the "select group'l push b`utton, a~ shown in Fig. 30 and Fig: 33, permits r~adout of the event history data gathered by the circuit breaker Trip Unit. The level of the last trip may be viewed, or the number of trips since the last reset may be viewed for overload, shor~ circuit, ground fault, curren~ unbalance, or LMU trips.
A rear control switch on the LMU permits changing from a "view" mode to a "change set up" mode. Fig. 32 shows the selection tree for t~e "select group" push button in the event that the set up switch is in the "on" position. By use of the "select function" push button, it is possible to either set or view an access code, the LMU unit number, a system type indicator, an input current xating, a display mode parame~er, communications parameters, and error trap responses. The "select data" push button permits viewing or setting variou~ options as shown in Fig. 32.
The ~MU may serve as a circuit breaXer or motor protector by tripping its a~sociated circuit breaXer. Functions available to the LMU are shown in Fig. 31.
Softwara ~or contrQlling the LMU push buttons and the LMU
display unit run in tha main processor. Fig. 34 is a block diagram of the main processor software. ~n executiv~ routine monitors operation o~ ~he main processor. The executive routin~ responds to intexrupt~ from the co~proc2s~0r signaled by updating the co~munication~ cell in th~ dual port RAM.
The exQc~tive routin~ transfer3 data from the dual port RAM

-~32-Z~ 4~

into the main processor RAM -dynamic d~ta memory.
Calculation of RMS current, voltage, power, reactive power, and other quantities is perfQrmed by the main processor.
Also, the power factor and other scientific calculations are performed by the main processor.
The computation block calculates the information requested at tha keypad and Display Unit. The command interpreter interprets the keypad commands and requests data calculated by the computations bloc~, and then displayed.
The protective relaying block sets limit~ and compares the limits with computed value~ in order to provide an alarm signal. Any of the quant~ties measured by the LMU or transmitted by the Trip Unit (TU) to the L~U may be compared with limits by th~ "protective rel~y" block.
Th$ "communications" block interprets incoming data from the Trip Unit on the Trip Unit ~erial communications link.
Also, thP communications blocX interprets the inroming BYTES
from the Trip Unit, a~ th~ BYTXS are described hereinabove under the Trip Unit com~unications section. Also, the communications hlock handles communications with the System Interface Unit ~S}U). The SIU communications will be describ~d in greater detail her~inbelow. A tsst function for ~he communications block permits ~esting for the various communica~ions functions.
The u~ilitie~ block includes interrupt servica routines and hardware intarfaces. ~ardware interfaces are provided for the keypad, the display, and the watchdog.

-1~3-In an alternative embodiment, the LMU watchdog may be similar to the Trip Unit watchdog, as described hereinabove.
The LMU main processor then must discharge a capacitor at a regularly established cyclical time on the order of a few milliseconds in order to prevent the capàcitor from charging above a set point voltage. In the event that the capacitor charges above the set point voltage, the LMU does a complete hardware and software initialization. The capacitor charges as a result of the failure of the watchdog circuit to discharge it, and thus a high voltage on the capacitor is indicative of failure of the main processor.
The testing block permits testing of the Trip Unitr testing the L~U through the self test, production testing, and testing of test modules.
The scheduler block permits polling of devices such as the Xeypad and Display Unit, and also generates alarms and timing cycles.
The initialization bloc~ provides standard functions to the ~ain processorO
A Texas Instruments TMS32010 type processor has been found satisfactory for the co-processor. The device contains a hardware ~ultiplier that performs a 16 x 16 bit multiplication with a 32 bit result in a singl2 285 nanos~cond cycle. Thi~ speed is sufficient to permit sampling voltage and current waveshapes of each phase of the 60 cycla ~C line frequency 32 times per cycle.
It ha~ been satisfactory to use a Motorola type MC68000 processor for the main processor. A Motorola typa MC68901 multifunction peripheral ha~ be~n found usPful to use in ~0 -13~-~Q4~

conjunction with the main processor. The multifunction peripheral provides both veotored and polled interrupt schemes, including its 16 interrupt sources. Additionally, handshake lines facilitate interfacing.
The dual port memory satisfactorily utilizes an Integrated Devices Technologies unit Nos. 7130 and 7140.

L~U COMMUNICATIONS TO SIU
The opttcal ring loop i5 a data communications bus. The System Interfa~e Unit, SIU serves as a bus master. The LMU
units serve as bus slaves. The SIU transmits a message to a selected LMU on the optical ring. There may ba up to 64 different LMU units on the optical ring. The designated LMU
responds to the message. Upon receipt of the message, the SIU acknowledges receipt to the LMU.
Types of messages transmitted by the LMU include:
A polling message to determine which LMU units are on the optical ring bus.
A second type of message from the SIU to a selected LMU
is a reguest for information. The request contains the number of a register. The LMU centains 51 data re`gisters. Upon receipt of a request for information çontained in a particular register, the LMU transmits the -contents of that register to the ~IU. The SIU then acXnowledgPs xecsipt of the message.
A third type o~ message transmitted by the SIU to a selected L~U i~ a write message. The LMU transmits a regist~r number and the "new" contents af that regis~e~.
The L~U r~ceives the "new'9 register contents and writes them into the appropriate register.
Th~ register struc~ure is that each of the LMU units contains 51 data registers, registers 0-50. There are up to 64 independent LMU unit~ The SIU memory has a map o~ each of the registers of each of the LMU units. Thus the SIU has a map of 51 x 64 = 3,264 registers. There is a one-to-one correspondence between the register numbers and the contents of that register in an LMU and the mapping of that set of registers in the SIU. Thus, a register can be a~cessed either on the bus or in the SIU memory, and the addressing is by an LMU number and a ragister number.
A description of the registers, along with the re~ister numbers, and the contents of the registers, ~ollows:

SIU MEMORY LAYOUT
This section describes the actual memory layout of the System Interface Unit data.
A.} Programmable Controller Area Reqister Address Description 1 Progra~mable Controller Processor 2 Active LMU
3 Bit 4 ~ap Are~
6 Unused A.2 ~asic Data Arsa The ba-~ic data area i~ co~posed o~ ~our registers. These registers are located with t~o addresse~ - an LMU number and a register offsat. ~egister offsats are given below.

- Offset Reqister Descri~tion O Pick-up Trip 1 Alarm and Trip Contacts 2 LMU Status/LMU Outputs The complete LMU basic data area occupies registers 7 through 198. Layouts for the first two LMU da~a recor~s are shown below with a for~ula following to calculate addresses fox the remaining LMU data area.
Re~ister Description 7 LMU 1 Pick-up Trip 8 Alarm ~ Trip , 9 Status/Output ` 10 ~MU 2 Pick-up T~ip 11 Alarm & Trip 1~ Sta~us/Output Register Address = 3 * LMU ~ 4 + NOS
Where LMU = LMU num~er (1-64) NOS - register o~fset given above (0-2) - A.3 Full Data Area The full dat~ area is compo~ed of ~orty-nine register~
for each LMU, ~s with the basic data area, individual registers are located with ~wo number~ - an LMU number and a register of~set. The offset num~ers for the 4g registers are given below:

2~
Description O Over Freq~ Alarm/Trip 1 Over Freq. Delay 2 Under Freq. Alarm/Trip 5~ 3 Under Freq. Delay 4 Over Volt Alarm Over Voltage Trip 6 Over Voltage Delay 7 Under Voltage Alaxm 108 Under Voltaga Trip 9 Under Voltage Delay Under Current Alarm - Phase A
11 - Phase B
12 - Pha6e C
1513 Over Current Alarm - Phase A
14 Phase B
- Phas~ C
16 Present Demand Alarm 17 Instantaneous Demand Alarm 2018 Predicted D~mand Alarm 19 Demand Interval/Phase Unbalance Alarm 20 Current Level - Phase A
21 - Phase B
22 - Phase C

23 Ground Fault Current 24 Voltag2 Level A-B
B-C

-~39 2~

30 Power Level KW

`32 KVA
33 PF Phase A/PF Phase B
34 PF Phase C/Unbal Phase A
Unbal Phase B/Phase r 36 Present Demand KW

38 Instantaneous Demand KW
39 ~ ~VARS
Predicted Demand KW
, 41 " " " gVARS
42 Peak De~and X~
43 KVA~S
44 Accumulated KWH
45 KWH/Frequency 46 Sensor Rating Plug/Breaker option ~7 Long Time/Short Time Switch Settings 48 Ground Fault/Instantaneou~/Phase 49 Unbalanc~ Switch Settings ADDRESS ~ 49 * LMU ~ 152 ~ NOS

with LMU ~ LM~ number (1-64) NOS ~ register o~set (0-49) -l4a-2~
SYSTEM INTERFACE UNIT HARDWARE
Fig. 35 is a schematic diagram sho~ing both the receiver and transmitter for the system interface unit ~iber optic adaptPr. The electronics shown in Fig. 35 plug into a standard programmable controller registe~ transfer card. For example, the Square D SYMAX register transfer module type CRM211 ~or a SYMAX system may conveniently support the electronics shown in Fig. 35.
Photodetector PDl receives incoming light signals from the fiber optic ring. The signals are amplified by op-amp Ul, at its input pin 6 and output pin 7. Further amplification is provlded by op-amp Ul at lt~ input pins 3, 2 and output pin 1. Op-amp amp Ul at its input pins 10, 9 and output pin 8 provides an active zero referance to the foliowing stages. Op-amp amp U1 at is input pins 12, 13 and output pin 14 along with capacitor C4 provides an adaptive threshold for the signal discri~inator. Comparator U2 at its input pins 7~ 6 and output pin 1 functions as a signal discriminator, and provides a siqnal to buffer U3. Buffer U3 2 drives a standard serial communications port in the programmabl~ controller (not shown in Fig. 35)0 The ~ransmitter for the SIU fiber optic adapter is driven by signals provided by the host proqramma~le controller through jack Jl pin~ Jl-22 and J1-25. Up-amp U3 provides an interfaco to the standard serial communication port in the programmable controller (not shown in Fig. 35). Transistor Q2 provide~ a current limi~ing function. Transis~or Q1 is driv2n into conduction and out o~ conduction by the incoming signals~ Whcn conducting, tran-~istor Ql drives current through light emitting d~ode PEl, causing light to be thereby -141~

~01~
emitted~ When transistor Q1 is driven out o~ conduction by the incoming signals then no light is emitted by light emitting diode PEl. Optical ~ignals into the ~iber optic ring are couplad optically from light emitting diode PEl.
Thus, digital ~ignals arriving at jack Jl~pins 22, 25 drive transistor Ql into co~uction, thereby providing equivalent light signals into the fiber optic ring by emission from light emitting diode PEl.
Ul, U2 and U3 shown as rectangular blocks, give the power connections to the respective chip~. A filtered power supply V+l is filtered by capacitor C7, and a filtered power supply V+2 is filtered by capacitor C8.
Software in the programmable controller reads the incoming signals provided by th~ receiver at jack Jl pins 19, 16. Also, software within the programmable controller generate~ the outgoing signals applied to the transmitter at jack Jl pins 22, 25.
PDl is a MFOD71 Motorola pin diode.
PEl is a Motorola MFOE76 visible red LED.
In U3, output pins 3 and 4 ar~ a non-inverti~g output, and pin~ 1, 2 are an inverting output. The output to jack J1 pins 19, 16 is taken between the non-inverting and the inverting ou~puts. U3 may conveniently be a type SN75116N
chip made by Texas Instruments Corp.

~5 SIU-LMU_CO~MUNICATIONS PROTOCO~
GENE~A~
The System Interface Unit communicates with up to 64 Local ~anagem~nt Unit~ via a ring-connected ~iber-optic linX. ~ata transmissio~ i5 asynohronou~, bit~serial, Simplex at 31.25 kilo~ytes/second. ~yte forma~ i5 onQ start bit, eight da~a ~its, one odd parity bit, and one stop bit.
--1~ Z--1.C Communications Interface The System Interface Unit resides on the Programmable Controller bus and communicates with up to 64 Local ~anagement Units via a single loop optical co~unication channel. ~he SIU operates at 310 25 kilobytes per second. A simple pac~et structure i~ adopted for the SIU/L~n communications.
1.1 SIU/LMU Message Packet Format All communications ~etween the SIU and LMUs are controlled or initiated by the SIU. The messages take the ~orm of an interrogation message addressed to a particular LMU. The addre~sed ~MU, in turn, sends a response to this interrogation. To complete , thQ sequence, the SIU acknowledge~ receipt of the respons~. Additionally, each interrogation and response message is framed by "start of message" and "end of message" character sequences.
1.1.1.1 Polling Message A Polling Message sequence is used to identify those L~Us which are presen~ in th~ network. The format o~ a polling messag~ is:

DLE SOH ID DLE ETX C~K
The ~or~at o~ t~e respons~ to a polling me~sage is:
DL~ STX ID DLE ETX CHX
In the~ mess~ges, all characters are the standard ASCII
deflnitions, ~xcept ID and CHK, which ar~ de~ined below.
For convQnience, th~ pat~arn~ ~or tha standard ASCII
character~ used in ~hese message are:

~143 2~
-- 1~ lo 1~1 ASCII CHARACTER CODES
Hexadecimal codes for control characters are listed ~elow:
DLE lOH
` SOH OlH

1.1.1.2 ID Character In the polling message above, the ID byte is de~ined as~
, b7 b6 b5 . .. . bO

1 5 ~ #
The ~MU # is a number ranging ~rom O to 63 and is the address of the LMU being polled.
1.1.1.3 CH~ Character In the polling message above, the CHK byte is the ~o 2 ' 5 complement of the 8-bit sum of all characters ~rom the opening DLE through the closing ETX, inclusive. In other words, the su~ o~ all charac~ers in a packet, ignoring carries, will be zero after the check su~ is received.

1.1.2 READ LMU DATA
The Read LMU Data messaqe is used ~o accomp}is~ two function~: update LMU output~ and to reque~t data from -~44 f one of the L~U registers. The format o~ a Reaa LMU data message is:
DLE SOH ID POINTER OUTS DLE ETX CHK
The response to a Read LMU data message is:

DLE STX ID PU INS ALARM/TRIP STATU5 DATA DT~ ETX CHK

In both messages, the CHK byte is as defined in paragraph 1.1.1.3 above. Similarly, the definitions of DLE, SOH, STX, and ETX are simply the ASCII equivalents shown above. Additional bytes of this message and response are de~ined below.
1.1.2.1 ID
ln the read data message, the ID byte is defined as:
~ b7 b6 b5 . . ~ bO
O LMU #
The LMU # i~ a 6-bit binary number ranging in valu~ from O ~o 63 and i5 ~he address of ~he L~U from which ~ata is requested.
1.1.2.2 POINTER
Th~ pointer byte is an 8-bit binary number identifyin~
th~ r~gister in the addressed LMU ~or which data is requested. This number will range from 0 to 50.
1.1.2.3 OUTS
The output byte contains informa~ion which will appear at the addressed LMUI~ output port. This byte represents, on a one-for-one basis, ths information to be reflected in the L~U output~

1.1.2.4 PU
The PU byte contains information fro~ th~ addressed LMUs pick-up/trip byte. Thi~ byta i~ simply transferred from the addressed LMU to the SIU's register space.
~.1.2.5 INS
The INS byte contains information from the addressed LMUs input port. This byte is transferred and represents on a one-~or-one basis the information appearing at the LMUs input port.
1.1.2.6 ALARM/TRIP
Two bytes are transferred and represent the contents of the addressed LMUs Alarm-Trip register. This data is transferred low ord~r bytP first followed by the high .order byte.
1.~1.2.7 STATU~
one byte is transf~rred and represents the contents of the addressed LMUs ~tatus byte.
1.1.2.8 DATA
Two bytes are transferred and represent the contents of the r~gister pointad to by th~ POINTER byte in the interrogation message. As with the Alarm ~egister~ the information i3 transmitted low order byt~ first, followed by the hi~h order byte.
1.1.3 WRITE LMU DATA
The Write LMU Data ~essage ls used to update a specific .register in an LMU. The ~ormat of a Write LMU Data m~ssag~ i5:
DLE SOH ID POINTER OUT5 REGL REGH DhE ETX CHK

The response to a Writ~ LMU Data message is:
DLE STX ID PU INS ALARM/TRIP STATUS DLE ETX CHX
In both message~, the CHX byte is as defined in paragraph 1.1.1. above. Similarly, the de~initiona o~ DLE, SOH, STX, and ETX are simply the ASCII equ'ivalents as shown above. Additional bytes of thi~ message and response are dein2d below.
1.1.3.1 ID
In the Write LMU data message, the ID byte is defined as.
b7 b6 b5 . . . bO
O 1 ~MU #
The LMU # is a six-bit binary number ranging in value from O to 63 and is the address of the LMU to which data ~, s directed.
lS 1.1.3.2 POINTER
The Pointer byt~ is an eight-bit binary number identifying tho register in the addressad L~U to which the data is directed. This number will range from O to 50.
1.1.3.3 OUTS
The definition of the OUTS byte in a ~rit~ L~U data me~ag~ is identical to tAa definition o~ paragraph 1.1.2.3 regarding the OUTS byte in the R~ad LMU data message.
1.1.3.4 REGL & REGH
The REGL and REG~ byt~s contain th~ information to be written int~ ~h~ register addres~ed by the pointer byte.
~EGL rapresent~ the low srder byte of in~ormation and is tr~ns~itted first, followed by ~he high order information byts ~EG~.

1~70 1.1.3.5 PU
In the LMU's response, the PU byte represents the Pick-up Trip byte ~rom the addre~sed LMU~
1.1.3.6 INS
In th~ LMUs re ponse, th~ INS byte represents data present at the eight-bit input port.
1~1.4 AC~NOWLEDGMENT
The SIU acknowledges an LMU response. A complete message cycle proceeds as follows:
SIU > LMU Interrogation LMU > SIU Response SIU > LMU Acknowledgment The acknowledgment takes one of two forms based upon the result of the check sum calculation.
1~.1.4.1 VALID MESSAGE
In the case of the SIU receiving a good response from the LMU, a positive acknowledg~ent is sent to the LMU.
This acknowledgment has the form:
Dr~ ACK ID
ACK i~ an ASCII character definsd above, ID is an echo o~ thQ Interrogation message ID byta as previously defined.
1.1.4.2 INVALID MESSAGE
In the cas~ of the SIU receiving a ~ad response from the LM~, a nega ive acknowledgment is sent to the LMU. This ~essage takes the for~ of:
DLE NAX ID
NAK is an ~SCII character d~fined aboYe, ID i~ an echo o~ ths Interrogation ~essag~ ID byt~ as previously defined.

1.1.5 CHARACTER FORM~T
All characters are transmitted in an eleven bit asynchronous format. Each eight-bit data byte is precedëd by a start bit and followed by an odd parity bit and one stop bit. Data is trans~itted least significant bit`~irst.
Start d0 dl...d7 Par Stop 1.1.7 RESPONSE TIME
In any message sequence, the SIU waits approximately 25 milliseconds for a response fro~ an LMU to begin. Any delay in respons~ of great~r than approximately 25 milliseconds is interpreted as a nonexist~nt LMU.
1.1.8 UPDATE TIME
, Update time is defined as the maximum time required to ~ffect a change at an L~U from a SIU, or vice versa.
This time is dependent upon a number of factors, two of which are the n~ber of LMU's connected and number of messages in error. Typical values o~ update time using the following assumptions, - no errors in trans~ission occur and the network is fully populated, are;
(1) At 31.25 kilobytes/sec, the network is interrogated within 0.54 ~econds; (2) the full 50 registers at a node are updated a~ter 47 polling cycles or 2~.4 seconds.
1.1~9 RETRIES
In the case of the SIU sending a Nsgative Acknowledgment, the responding LMU re-transmits its last message. Only one retry i~ attempted.
1.2 FIBE~ OPTIC LIN~
The physical link between an SIU and a ne~wor~ o~ LMU's is a single ~iber optic cable. The modula~ion scheme is ~149-Zq~ 49~

on o~ keying. A space bit or data "zero" i5 defined as the drivPr LED "on:~ while a mark bit or data ~one" is defined a~ the driver LED "offn.
It i~ to be understood that the above described embodiments are simply illustrative of the principles of the invention. Variou~ other modifications and changes may be made by those skilled in the art which will embody the principles of the invention and ~all within the spirit and scope thereof.

~5

Claims (21)

1. A tripping system for interrupting electric current flowing through at least one conductor from a source of electrical energy to a load, comprising:
a tripping unit having a current sensor for measuring the current, and processing means, responsive to the current sensor, for disconnecting the load from the source in the event that the measured current exceeds a predetermined threshold and for transmitting data representing the status of the tripping unit;
a data path, coupled to the tripping unit, for carrying the transmitted data from the tripping unit; and a peripheral device, coupled to the data path, for receiving the data transmitted by the tripping unit;
wherein the peripheral device includes a processor for receiving the data from the tripping unit at a rate that is independent of the rate at which the data is transmitted from the tripping unit.

2. A tripping system, according to claim 1, further including a plurality of peripheral devices coupled to the data path for monitoring and displaying the status of the data transmitted on the data path.

3. A tripping system, according to claim 1, wherein the peripheral device includes a local monitoring unit for monitoring the data transmitted by the tripping unit and further includes means for independently tripping the tripping unit.

4. A tripping system for interrupting electric current flowing through at least one conductor from a source of electrical energy to a load, comprising:
a plurality of tripping units, each unit having a current sensor for measuring the current flowing through one or more associated conductors, processing means, responsive to the current sensor, for disconnecting the load from the source in the event that the measured current exceeds a predetermined threshold and for transmitting data representing the status of the tripping unit;
a plurality of data paths, each coupled to an associated one of the tripping units, for carrying the transmitted data from the associated tripping units; and a plurality of monitoring units, each monitoring unit being coupled to a respective one of the data paths, for analyzing the transmitted data from the tripping units.

5. A tripping system, according to claim 4, wherein each of the monitoring units receives the data from the associated tripping unit at a rate that is independent of the rate at which the data is transmitted from the tripping unit.

6. A tripping system, according to claim 4, wherein each of the monitoring units includes means, responsive to the transmitted data, for monitoring the measured current and for tripping the associated tripping unit.

7. A tripping system, according to claim 6, further including a central computer, coupled to each of the monitoring units, for monitoring the status of the plurality of tripping units and for setting trip parameters in the associated local monitoring unit.

8. A tripping system, according to claim 6, wherein each tripping unit further includes means for delaying the transmission of the data for a predetermined time period to allow the associated monitoring unit to receive the data at a slower rate than the rate at which the data is transmitted.

9. A tripping system for interrupting electric current flowing through at least one conductor from a source of electrical energy to a load, comprising:
a tripping unit having a current sensor for measuring the current, processing means, responsive to the current sensor, for disconnecting the load from the source in the event that the measured current exceeds a predetermined threshold and for transmitting data in prioritized sets wherein more critical data sets are transmitted more frequently than less critical data sets;
a data path, coupled to the tripping unit, for carrying the transmitted data from the tripping unit; and a peripheral device, coupled to the data path, for receiving the data transmitted by the tripping unit.

10. A tripping system for interrupting electric current flowing through at least one conductor from a source of electrical energy to a load, comprising:
a tripping unit having a current sensor for measuring the current, processing means, responsive to the current sensor, for transmitting data in prioritized sets wherein more critical data sets are transmitted more frequently than less critical data sets and for disconnecting the load from the source in response to a trip event in which the measured current exceeds a predetermined threshold;

a data path, coupled to the tripping unit, for carrying the transmitted data from the tripping unit; and a peripheral device, coupled to the data paths, including a processor for receiving the data transmitted by the tripping unit at a rate that is independent of the rate at which the data is transmitted from the tripping unit.

11. A tripping system, according to claim 10, wherein the processing means includes:
means for determining the cause of the trip event; and means for dividing the data into a first set and a second set, wherein the first set represents the cause of the trip event and is processed as the more critical data.

12. A tripping system, according to claim 9, wherein the data path carries the data in a serial stream.

13. A tripping system for interrupting electric current flowing through at least one conductor from a source of electrical energy to a load, comprising:
a tripping unit having a current sensor for measuring the current, processing means, responsive to the current sensor, for disconnecting the load from the source in the event that the measured current exceeds a predetermined threshold and for transmitting data representing the status of the tripping unit;
a data path, coupled to the tripping unit, for carrying the transmitted data from the tripping unit;
a monitoring unit, coupled to the data path, for receiving the data transmitted by the tripping unit and for tripping the tripping unit; and a central computer, capable of sending data to and receiving data from the monitoring unit, for monitoring the status of the tripping unit and for setting trip parameters in the monitoring unit.

14. A tripping system, according to claim 13, wherein the data is received by the monitoring unit at a rate that is independent of the rate at which the data is transmitted from the tripping unit.

15. A tripping system, according to claim 13, wherein the monitoring unit further includes nonvolatile memory.

16. A tripping system, according to claim 13, wherein the nonvolatile memory is in the form of electrically erasable programmable only memory (EEPROM).

17. A tripping system for interrupting electric current flowing through at least one conductor from a source of electrical energy to a load, comprising:
a tripping unit having a current sensor for measuring the current and for inducing current to power the tripping unit, processing means, responsive to the current sensor, for disconnecting the load from the source in the event that the measured current exceeds a predetermined threshold and for transmitting signals representing the status of the tripping unit;
a cabinet for mounting the tripping system therein;
a display circuit, powered using induced current from the electric current and located at a position remote from the cabinet, for displaying the signals from the tripping unit, wherein the display circuit includes an associated circuit for providing at least temporary secondary power to the display circuit and for retaining an indication of the status of the tripping system in the event that the load is disconnected from the source.

18. A tripping system, according to claim 17, wherein the display circuit includes a microcomputer for receiving the signals and controlling the display circuit.

19. A tripping system, according to claim 18, wherein the signals transmitted from the tripping unit comprise digital data in serial form that is received by the microcomputer at a rate that is independent of the rate at which the data is transmitted from the tripping unit.

20. A tripping system, according to claim 17, wherein the processing means includes means, responsive to the current reaching the predetermined threshold, for delaying the disconnection for a predetermined period of time to allow the processing means to store the cause of the trip.

21. A tripping system for interrupting electric current from a three-phase source of electrical energy to a three-phase motor, comprising:
a tripping unit having first, second and third current sensors for measuring the current in each corresponding phase of the current, processing means, responsive to the current sensors, for disconnecting the three-phase motor from the three-phase source in the event that the measured current exceeds a preprogrammed parameter and for transmitting data representing the status of the tripping unit;
a data path, coupled to the tripping unit, for carrying the transmitted data from the tripping unit; and a peripheral device, coupled to the data path, for receiving the data transmitted by the tripping unit;
wherein the peripheral device receives the data from the tripping unit at a rate that is independent of the rate at which the data is transmitted from the tripping unit.