CA2002729A1 - Distributed router of connectionless packets over connection oriented networks - Google Patents

Abstract

ABSTRACT

A network for routing datagrams which include at least one segment, the network comprising at least one segment switching means and a plurality of routers connected between the switching means and a plurality of terminals and adapted to process data in a datagram transferred from a first terminal so as to pass the datagram from a first router to a second router via the switching means and pass the datagram from the second router to a second terminal. A
method of routing datagrams is also provided with the datagrams being routed through a hierarchical arrangement of switching means on the basis of their final destination addresses. A router for connecting the switching means and processing the final destination address to enable transfer of datagrams across the network is also provided.

Description

2OVER CONNECTION ORIENTED NETWO~KS

FIELD OF THE INVENTION

7 This invention relates to the field of packet routers, 8 in particular, to routers of datagram packets over a 9 connection-oriented network, with plurality of hierarchical levels and plurality of routers at any hierarchical level 11 distributable over the network.

Computer communications over Local Area Networks (LANs) 16 are typically carried on by datagrams without prior set-up 17 of connection between the communicating equipments. This is 18 advantageous because of simplicity in protocol, requiring no 19 set-up procedure, and because of speed of communication, obviatiny the time delay that would be incurred by the 21 connection set-up. It is desirable to have the possibility 22 of such connectionless datagram communications also over 23 wide area, without limitations brought about by distance.

For economic reasons wide area communications are most 26 advantageously provided in a shared or common carrier 27 manner. Therefore the desire for wide area datagram 28 communication must realistically be linked with the 29 evolution of public networks and the means for bringing it about must be made part of such networks.

32 There are two developments already in the realm of 33 public networking that are centrally relevant to the quest 34 for wide area datagrams communication. They are the development of Metropolitan Area Networks (MANs) being 36 standardised by the Institution of Electrical and Electronic 37 Engineers Project 802.6 and the development of Broadband ~91110.9- -:e.002.~

" .

1 Integrated Services Digital Network (B_ISDN) being 2 standardised by the International Consultative Committee on 3 Telegraphy and Telephony (CCITT) Study Group XVIII. Among 4 recent published overview references to the two developments are respectively an article by R.M. Newman, Z.L. Budrikis 6 and J.L. Hullett entitled "The QPSX MAN", IEEE
7 Communications Magazine, Vol. 26, No. 4, pp 20-28, April 8 1988 and an article by T.M. Chen and D.G. Messerschmidt 9 entitled "Integrated Voice/Data Switching~, IEEE
Communications Magazine, Vol. 26, No. 6, pp 16-26, June ll 1988.

13 A MAN will provide integrated digital communications, 14 including datagram communication, typically over the area of a city. B_ISDN is intended to be universal and may 16 eventually subsume MANs, provided it will also offer 17 datagram communications. However the gamut of services by 18 the B_ISDN as presently conceived contains only connection-19 oriented communications, with data~ram communication only as a specialist limited service rendered by a centralized 21 server on a subscription basis.

The invention disclosed here is of a router for 26 datagrams that is applicable to MANs and ~ ISDN, though not 27 restricted in scope to t~ose particular network 28 developments. The present invention provides a network for 29 routing datagrams which include at least one segment, the network comprising at least one segment switching means, and 31 a plurality of routers connected between the switching means 32 and a plurality of terminals and adapted to process data in 33 a datagram transmitted from a first terminal so as to pass 34 said datagram from a first router to a second router via said switching means and pass said datagram from said second 36 router to a second terminal.

891110.gcp-pe.002,gp-~,2 1 The invention also provides a method of routing 2 datagrams in a network having at least one segment switchlng 3 means, and a plurality of routers connected between the 4 switching means and a plurality of terminals, said method comprising processing data in a datagram transmitted from a 6 first terminal so as to pass said datagram from a first 7 router to a second router via said switching means and pass 8 said datagram from said second router to a second terminal.

In known arrangements a central datagram server is 11 generally envisaged for the purpose but this cannot perform 12 satisfactorily and, in accordance with the invention a 13 distributed routing scheme is provided. In the system of 14 the invention the routing task of a datagram router can be reduced to directing the datagram to the appropriate other 16 router when there is no diversity (i.e. only one possible 17 path from source to destination), or to an appropriate other 18 router when there is diversity. It has also been recognised 19 that the datagram can be sent from the one router to the oth~r over the connection-oriented network without requiring 21 circuit set-up, provided a set-up circuit exlsts permanently 22 between the two routers. These principles apply equally 23 when the connection-oriented network has actual physical 24 circuits and when it has virtual circults.
26 It has been further recognized that routers can be 27 grouped into domains and that domains can be interconnected 28 hierarchically. It has been further recognized that 29 advanta~eously the routers should be logically at the edge of a domain and thus be edge devices having two distinct 31 directions. A router directed from domain j into domain 32 may be designated Rji. It is an edge device of both 33 domains, j and i. It has its input socket from domain j and 34 its output socket into domain i. Similar observations with reversed direction apply to router Ri~.

37 For universal connectionless datagram transfer, all ô91110,gcp~pe.002,qp~,3 1 routers entering a domain must be permanently connected to 2 routers that leave the domain. The exception is that the 3 output of R~i is not connected to the input of Ri~. A
4 further requirement for unlversal connectlvlty ls that ln all domains except the domain at the hlghest hlerarchical 6 level, there ls at least one router whose output goes 7 directly or indirectly to a domain at higher hierarchical 8 level. Yet further requirements are that there be only one 9 domain at the highest hierarchical level and that every domain be reachable from that highest level domaln.

12 A domain may comprise a fast packet switch or 13 Asynchronous Transfer Mode Switch (ATM switch) having a 14 plurality of input and output ports, all ports being interconnected. An example of a fast packet switch is 16 described in the article by "Starlite, A Wideband Digital 17 Switchn ~ A. Huang and S. Knauer, 1984 Proceedings of IEEE
18 Conference on Global Telecommunications pp 5.3.1-5.3.5.

It has been recognized, that given the above structure 21 and properties, routing can be done everywhere on the basis 22 of a global final destination address. Also, the process of 23 routing can be done expeditiously provided that the address 24 itself is subdivided into hierarchical subfields, as for instance, a fifteen digit number divided into three or four 26 subfields approximating the existing practice in telephones 27 numbering. It has been recognized that the task at any 28 router is that of translating the final destination address 29 to a route label that indicates the circuit on which the datagram has to be sent so as to reach the appropriate next 31 router.

33 It has been further recognized that the translation can 34 be done by look-up of cand~date labels and of values of particular logical variables, associated with the candidate labels, minimally one label candidate associated with each 37 subfield of the final destination address. The actually 891110, g~pl~pc . 002, qp~y, ~

l applicable label can be determined by simple deduction based 3 on the values of the logical variables. This procedure of 4 determining the applicable label amounts to a novel algorithm. The translation carried out in a~cordance wlth 6 this algorithm can be done at great speed so that the 7 routing can be implemented on the fly even when datagrams 8 are transmitted at 100 Mbit/s or even h$gher.
g The present invention is applicable both when the ll datagrams are transmitted as variable length packets where 12 all bits of the packet are transmitted contiguously and when 13 the datagrams are segmented into parts. The IEE~ 802.6 and 14 the B_ISDN schemes have segmentation into segments of fixed length and the detailed description of the invention which 16 follows is for that case.

18 The reassembly of datagrams from segments that are 19 transferred in an interleaved manner over a connection-oriented network poses a problem of sim~lar ma~nitude in 21 memory or speed requirement as does rout2 selectlon. In 22 accordance with the invention it has been recognized that it 23 is also a problem of label translation from a large to a ~4 smaller space. The invention also provides a router for a network for routing datagrams having at least one segment, 26 said router comprising:
27 first means for receiving said datagram and accessing 28 said destination address from said datagram;
29 second means responsive to said first means for determining output connection data (VCI_OUT) on the basis of 31 said destination address; and 32 third means for including said output connection data 33 (VCI_OUT) in said datagram;
34 said datagram being routed in said network on the basis of said output connection data (VCI_OUT) after being 36 outputted from said router.

as~llo. gcp~pe. 002. gp~. 5 :

BRIEF DESCRIPTION OF THE DRAWINGS

3 The invention together with the operation and practice 4 of it will be more fully described, by way of example only, with reference to the accompanylng drawings, in which:
6 FIGURE 1 iS a block diagram of a hierarchical network 7 em~odying the routing scheme of the invention~
8 FIGURE 2 shows the format of an IEEE 802.6 standard 9 segment;
FIGURE 3 shows the format of an IEEE 802. 6 MAC (Media 11 Access Control) level packet header;
12 FIGURE 4 shows the format of the CCITT E.164 service 13 number;
14 FIGURE 5A is an overview block diagram of a router circuit;
16 FIGURE 5B is a block diagram the address-to-VCI
17 translator embodying the principle of label translation of 18 the invention;
19 FIGU~E 6 shows a block diagram of a reassembly message identlfier determinlng clrcuit;
21 FIGURE 7 shows a block diagram of a tag serv~r which ls 22 part of the system of Figure 6;
23 FIGURE B shows a logic circuit that may be used for the 24 priority encoding called for in the scheme of Figure 5, FIGURE 9 shows a block schematic of the multiplexor of 26 the scheme of Fi~ure 5; and 27 FIGURE 10 is a flow diagram of the program Pxecuted by 28 the Controller of Figure 7.
2~
DETAILED DFSCRIPTION

32 In the prior art it seems to be taken ~or granted that 33 the r~uting of datagrams should be given to one or more 34 centralised servers. These would be computers to which subscribers would have prearranged circuits. A subscriber 36 would send a datagram to that computer including in the 37 datagram an indication of the intended destination(s) and, ~glllo~9cp~p~ o~2~qpfi~t~6 l in turn, the computer would send the datagram to that 2 destination or those destinations, agaln using prearranged 3 circuits. Since the circuits over which the datagrams are 4 sent are permanently set up, there is no delay due to circuit set-up and in that sense the scheme of the prior art 6 is high speed. But the fact that all datagrams have to be 7 channelled through the one processor robs the scheme of any 8 chance of having truly high speed or real time performance.
9 Moreover the scheme is llmited in interconnectivity to a finite number of subscribers.

12 This problem is avoided, ~n accordance with the 13 invention ~y distributing the service function and making it 14 such that the scheme can grow without limlt, even to covering a substantial portion of the communicating 16 equipment on earth, and achieve connectionless or datagram 17 connectivity for all. The system of the invention 18 superimposes on a connection-oriented switched network which 19 may be established especially for that purpose or whlch could exist to carry other communication traffic.

22 With reference to Figure 1, the overall connectionless 23 routing system is divided into domains. By way of 24 illustration doma1ns at Level zero are shown aæ circles and labelled 81 through to 85. A Level zero domain may comprise 26 a QPSX MAN referred to earlier. The domains at Level one, 27 two and three are shown as square boxes, Level one domains 28 being labelled as 101 and 102, a Level two domain as 103 and 29 a Level three domain as 104. The system includes three Type I routers 111, 113 and 129 which take input from a Level 31 zero domain and output into a Level one domain. Type II
32 routers, examples of which are 112, 114 and 130 take input 33 from a Level one domain and output into Level zero domain.
34 Type III routers, examples of which are 119, 120, 121, 122, 126 and 128, have inputs and outputs in Level one and higher 36 domains.

891110,gcpcpe.002,qpu~,7 1 Inherent in the system of Figure 1 is the assumption 2 that Level zero domains require no routing. Customers or 3 end equipments are attached exclusively to Level zero 4 domains. End equipments are illustrated by small circles, such as 91 and 92 a*tached to Level zero domain 81. There 6 is no need for routing over these domains either because 7 they have only one piece of end equipment or because it is a 8 connectionless subnetwork, like that standardized as the 9 IEEE 802.6 MAN, which supports connectionless datagram transfers. The latter alternative reduces the number of 11 routers required for the overall scheme and is the more 12 advantageous of the two.

14 The Level one domain, labelled 101 is illustrated with fixed circuits connecting the output socket of Router 113 to 16 the input sockets of all Type II and Type III routers on the 17 domain, except 114, namely 112, 116, 118, 119 and 121.
18 Similarly the input to Router 114 is shown connected to all 19 outputs of Type I and III. Routers 113 and 114 have been slngled out for brevlty; simllar llnes go from each router 21 to every other router in the domaln, and slmilarly for the 22 routers on domains 102, 103 and 104 but these are not shown 23 in Figure 1 for clarity of illu~tration.

Assuming that there are N incoming routers and N
26 outgoing routers around the edge of a domain and two domains 27 are connected by a sin~le oppositely directed pa~r of 28 routers, then the number of one-way, or simplex, circuits 29 emanating from each output soc~et is (N-l), and that is also the number of simplex circuits terminating on each input 31 socket. The total number of fixed simplex circuits in the 32 domain is 2N(N-l).

34 Still referring to Router 113 on domain 101 of Figure 1, consider the instance of a datagram that has originated 36 in domain 82, that is intended to go beyond domain 82. It 37 has to be routed by Router 113 to another router with input 891110. gcp-pe . 002, qp~c, B '.

l socket in domain 101. The routing ls made on basis of the 2 final destination address which is carried in the header of 3 the datagram.

This task and its implementation embodying the 6 principles of the invention will be described for the case 7 of the format of the datagram and its transmission being in 8 conformance with the IEEE 802.6 Draft Standard (Draft D9, 9 August lg89). The datagram is carried in a succession of fixed length segments. The format of a segment is shown in 11 Figure 2.

13 With reference to Figure 2 the rows represent groups of 14 eight binary digits, or octets, with the sequence of transmission left to ri~ht and top to bottom. The first 16 seven octets, labelled 01-07, are segment header and of the 17 remaining 46 octets, 44 are payloaded with data for 18 transmission and 2 are a segment trailer.

A datagram may have any lenyth up to 8000 oc~ets and by 21 the above is carried in segments 44 octet long. The IEEE
22 802.6 Standard provides for two other classes of service 23 besides connectionless datagram namely isochronous and 24 connection-oriented non-isochronous. The segments of all three classes share the segment header octets 01 through to 26 05. Whether a segment is part of a connectionless datagram 27 is indicated by a particular value of the final four bits of 28 the VCI (Virtual Circuit Identifier) field 71, i.e. the 29 first four bits of row 04. When these are all zeros, the segment is connectionless. In the description which follows 31 the expressions "VCI" and "Label" are used synonomously.

33 Given that the segment is connectionless, the 34 information of whether it is ~arrying the beginning of a message (~OM), continuation of a message (COM), end of a 36 message (EOM) or a single segment message (SSM) is disclosed 37 by the two-bit S_T~pe field, or subfield 75 in Figure 2.

B91110,gcp-pe 002,qp-~,9 2 All se~ments of a message must carry the same message 3 identifier, (M_ID) field 76.

A datagram beglns with octet 08 of an SSM or ~OM
6 segment and is started by an ISO (International Standards 7 Organisation) Level 2 header followed by an ISO Level 3 8 header. By a principle of the present invention routing is 9 on the basis of the final destination address. That address will in all cases be present in the Level 3 header. It is 11 possible by the IEEE 802.6 Standard that the CCITT E.164 12 final destination address is also present in the Level 2 13 header, and the routing can then be done on the basis of 14 that header. In the following description it is assumed that the latter applies. Should in a given circumstance the 16 Level 2` header not have a final destination address then 17 what is described here would be done with little change on 18 the basis of the destination given in the Level 3 header.

Figure 3 shows the Level 2 header format confo~ming to 21 the IEEE 802.6 Standard. There are seven fields alto~ether 22 w~th only the destination address (DA~ field 142 of 23 immediate interest. It consists of two subfields, the first 24 of four bits indicating the address type and the second a 60 bit subfield of address. When the address is according to 26 CCITT E.164 then all 60 bit positions are taken up by the 15 27 binary-coded dec~mal numbers of that address. Its format is 28 shown in Figure 4.

The connectionless routing task and the principles of 31 the invention for implementing it can be understood with 32 reference to Figure 5A which is a block diagram of a router.
33 The router takes in segments serially having the format of 34 Figure 2 on an uninterrupted time basis on input line 520, modifies them in the appropriate manner and puts them out 36 serially on output line 538. Input and output, in use, are 37 continuous and regular, at the rate of the network 891110, gcpspe . 002, qp~t ,10 1 transmission. For instance, if the rate is 44.210 Mbit/s, 2 one of the standard net rates in public network digital 3 transports and currently planned to be used in DQDB networks 4 in North America, then the rate of segment input and output is 104, 269 segments/second. A router with the architecture 6 of Figure 5A and with components of the invention is 7 feasible at that and higher rates, for instance 140 and 155 8 Mbit/s which are also currently contemplated in DQDB
9 networks. The input and output can be serial ln lndividual bits or in groups of bits, for instance 8 bit groups or 11 octets, and that will not alter the principles of the 12 invention.

14 The router is comprised of identifiable sta~dard components: latches 503 and 504, demultiplexors 506, 507 and 16 508, multiplexors 509, 510, 511, 512 and 513, and delays 17 541, 542, 543 and 544. It incorporates two systems of the 18 invention: the address-to-VCI translator 501 and the packet 19 re-assembler/label server S02. The timing of events in all components and the systems i~s under the control of Timing 21 Control 505, which itself is synchronized to the bits or 22 yroups of bits and segment starts in the input.
~3 24 Latch 503 captures S_Type, which is field 75 in the format of Fi~ure 2 and indicate~ the segment type. The 26 contents of latch 503 provides an indication to 27 DemultiplexOr 506 and also to the systems 501, 502 and 28 Multiplexor 513. If the segment is a single segment message 2g (SSM) or a beginning of message (BOM), the Demultiplexor 506 puts the segment on line 521. If it is a continuation of 31 message (COM) or end of message (EOM) then it is put on line 32 522. Delay 541 delays the segment sufficiently to allow a 33 decision to be made, having re~ard to the contents of latch 34 503 as to which output to switch to in time for the arrival of the first bit of the segment.

37 The segments leaving the router must have the same bit 891110, gcpsp~. 002, ~s~, 11 1 fields as they came in Witll, except for the VCI and M_ID
2 which are fields 71 and 76 in Figure 2. Further exceptions 3 are two cyclic redundancy fields that are recalculated and 4 changed. We assume that these are not done in the router but in a further unit that follows it. But of course that 6 function could also be incorporated in the router system 7 without altering the invention.

9 The segments leaving the router must have VCIs and M_ID's appropriate for their passage to their next immediate 11 destination. The VCIs are the labels by which the ATM
12 switch, for instance 101 or 103 of Figure 1, transfers the 13 segments from a given input port to intended output ports.
14 The M_ID's are the labels that logically link the separate segments of a message, and must be different for different 16 messages~ that are concurrent or interleaved in their 17 segments for a given source and destlnation.

19 The appropriate VCI is determined from the flnal destination address or subscriber number, such as that of 91 21 or 97 in Figure lr which is carried at the head end of the 22 message, i.e. at the start of field 77 of SSMs and BOMs.
23 The final destination is latched from the lncoming SSM and 24 BOM by Latch 504 and presented on line S27 to the Address-to-VCI Translator 501 whi~h determines the 26 appropriate VCI and puts it on line 528. The SSM or BOM is 27 demultiplexed in Demultiplexor 508 which places the VCI and 28 M_ID that it has on entry on line 525 and the remaining 29 fields on line 526.
31 In the case of a BOM the VCI_IN and M_ID_IN on line 325 32 and VCI_OUT on line S28 are read into the Message 33 Reassembler~Label Server 502, so that this unit is able to 34 recognize the subsequent COMs and EOM of that same message and give to these the same VCI_OUT and M_ID_OUT as are given 36 to the BOM~ The remaining fields on line 526 are applied 37 via Delay 543 to Multiplexor 512 which multiplexes them with 8glllO,gcp~pc.002.qp~.12 1 VCI_OUT and M ID_OUT to make up BOM OUT. The M_ID_OUT is 2 given out by the Message Reassembler/Label Server 502.

In the case of an SSM, the M_ID is in all cases a null 6 field and there is no linking of any subsequent segments 7 with the first. Therefore there is no need to place the 8 VCI_IN, M_ID_IN and VCI_OUT into store in the 9 Reassembler/Label Server 502, which supplies the appropriate (null) M_ID_OUT for the SSM. Therefore SSM_OUT is formed by 11 the same multiplexing as is BOM_OUT and appears on the same 12 line 536.

14 COM and EOM segments are similarly demultiplexed, by Demultiplexor 507, which places the incoming VCI and M_ID on 16 line 524,` and the remaining fields on line 523. The VCI_IN, 17 M_ID_IN are input to the Reassembler/Label Server 502 whlch 18 recalls the VCI OUT and M_ID_OUT that had been given to the 19 BOM segment o~ that message. The VCI_OUT and M ID OUT are multlplexed in Multiplexor 510 and the output of thi~
21 multiplexor is multiplexed with the remainlng fields of the 22 segment, COM R_IN or EOM R IN in Multiplexor 511 wh~ch 23 places the resulting segment, COM OUT or EOM_OUT on line 24 535. Finally, Multiplexor 513 selects for output as SEG OUT
on line 538 the input either on line 536 or 535, whichever 26 is appropriate by the S_Type indication on line 540.

28 Demultiplexing and multiplexing are shown in Figure 5A
29 as being performed in progressive stages. This is for the sake of description only. In actual implementation all of 31 the demultiplexing, shown in units 506, 507 and 508, would 32 be more effectively done in a single demultiplexor, and of 33 all the multlplexin~, shown in units 509-513, in a single 34 multiplexor. Also for the sake of description only, BOM_R_IN and SSM_R_IN are shown as distinct from COM_R_IN
36 and EOM_R IN. In implementation they would not be 37 distinguished and would be on common line. Hence the two 891 1 10 . gcp~p~ . 002, qp-~ . 13 , 1 delays 542 and 543 would also be a single delay.

3 The delays, shown in Delay unlts 542, 543 and 544 are 4 important for ensuring proper time alignment of the different components of the outputted segment. The delays 6 542 and 543, if not common, must be equal to each other, and 7 equal to the larger of the delays in unit 501 or 502 in 8 producing the VCI_OUT and M_ID_OUT~

If the larger delay is in Unit 502, Unit 544 is 11 inserted as a trimming delay in line 528 to make the delay 12 with which VCI_OUT from Unit 501 is available for 13 multiplexing equal to the delay from Unit-502. If 501 had 14 the lon~er delay, then the trimming delay would instead be applied to VCI_OUT and M ID_OUT from 502.

17 Since segments may come into the router one after the 18 other without any time gap between them, and succeedlng 19 segments may quite arbitrarily be any of the four types, ~OM, SSM, COM or EOM, the tasks performed w~th xespect to a 21 segment by the Unlts 501 and 502 with the architecturing of 22 Figure 5A should be completed ln a single segment period.
23 This incidentally means that the delay of Delay Units 542 24 and 543 i~ limited to a maximum of one segment period and more significantly that the systems 501 and 502 in fact 26 perform their tasks in the limited time.

28 The task of the Address to_VCI translator can be 29 accomplished in the short time that is available if the translation can be done by simple memory look-up. For each 31 possible destination address there would be in memory an 32 appropriate VCI. But at present that is not practical, 33 given the size of the address space. Since the destination 34 address has 60 bits, the number of possible different addresses is 260 or lol8 37 An approach has been developed that makes it practical 891110, gcp-pe . 002 . qpslt, 1~1 l to accomplish the address_to_VCI translation by memory 2 look up and has been termed simultaneous partitioned memory 3 look-up. The total address is divided into subfields, each 4 of which is small enough to access a corresponding memory that is of practicable size.

7 With reference to Figure 5B, which illustrates a bloc~
8 schematic of system 501 of Figure 5A, the destination 9 address D ADDR on line(s) 522 is demultlplexed into the (n+l) fields, Field_0, Field_l...Field_n on lines 11 211,214,...216. These fields are presented as addresses to 12 the random access memories 221,222,...225,226. From each 13 memory a read-out is madP of a candidate VCI, VCI_0 on line 14 244, VCI_l on line 234,...VCI-n on line 236. Also read out from each memory is a logical variable, Io on line 243, Il 16 on line 244,...,In on line 246. The candidate VCIs ar2 17 input to the multiplexor MUX 270 and the logical variables 18 to the logical unit 250. The logical unit produces control l9 signals on lines 260 which collectively select the appropriate VCI and this becomes VCI_OUT on the multiplexor 21 output llnes 528.

23 The VCI and logical variables stored and retrieved from 24 the memories are dependent on the particular partitioning of the address and the particular ~nterconnectlons of 26 hierarchical domains that are made. The task of wrlting to 27 the ~emories would be done by a network management system.
28 In the description which follows the selection of the VCI is 29 for the case where the partitioning of the address is strictly hierarchical and where furthermore this 31 partitioning corresponds exactly to the hierarchical 32 division into domains. The logical variable is then simply 33 a single binary bit indicating whether a routing to at least 34 that level is indicated and the selection is then effected by a priority encoding by the logical unit or priority 36 encoder 250.

aglllogcp~p~oo2~qp~s 1 The task of priority encoding is known and can be 2 understood from the following mathematical descriptlon of 3 the function of a priority encoder.

Let Ik, k = 0,1,..n be the binary valued inputs to the 6 priority encoder and let xJ~ ~ = 0,...m be the binary-valued 7 outputs from the encoder. Collectively the outputs can be 8 taken as a binary coded decimal positive integer y whose 9 value is ll m 12 y = ~ 2jXJ ~1) 13 j=0 16 The largest possible value of y must at least equal n.
17 This is assured if 19 m ~ log 2 (n+1) (2) . 21 The output of the encoder has the value y = z lf and 22 only if 24 Iz = 1 and I~ = 0 for ; = z~l,... ,n (3) : 25 26 The truth table of a priority encoder for the case of 27 n=7, and therefore m=3, is glven in Table I.

3~

891~10.gcp~p~.002,qp-~. 16 I TABLE I

_ _ _ __ _ ~ Io I1 I2 I3 I4 I5 I6 I7 x2 x1 xO y 17 A realization of th~ encoder is given in Fi~ure 8. The 18 loyical variables I1, to I7 are put on lines 285 through 19 291. These or their negations or inverseS, as for lnstance the negation of I2 by the negator or inverter 292, are put 21 in the different combinations shown to the OR gates 300 to 22 304. The outputs of the OR gates along with certain 23 combinations of Ij's or negation Ij's are input to the AND
24 gates 305, 306 and 307 that produce as their outputs and put on lines 308, 309 and 310 respectively xO, x1 and x2. Io is 26 not an input to the circuit because the output x~ = O, x1 =
27 O, x2 = O, that corresponds to Io ~ 1 is produced by the 28 encoder as a default when I1 through I7 are all zero.

The label selection is implemented by the multiplexor 31 270 of Figure 5B. A realization of a multiplexer for the 32 simplified case of selecting one from four sixteen bit 33 labels is illustrated in Figure 9. In this case there are 34 only two x components, xO and xl. These are presented to the decoder 410. Dep~nding on the values of xO, xl, one 36 particular output line 421, 422, 423 or 424 is asserted.
37 The truth table ior the decoder 410 is given in Table II.

891 1 10, 9cp-p~ . 002, qp-~, 17 '' ' ' ' : . ~ , ', ' ' '' ' 1 These lines are applled to the ENABLE inputs of trl-state 2 buffers 440, 441, 442 and 443. The input to the buffers are 3 respectively VCI_O, VCI_1, VCI_2 and VCI_3 and depending on 4 which buffer is asserted, that Label appears on the buffer output and is placed on the output bus 528.

7 TA~LE II

VALUE INPUT (bits) 12 y xl xO ~h bits) 14 1 0 1 LABELl 19 The tasks of the Message ReassemblerJLabel Server 502 of Figure 5A, should also be completed in less than a 21 segment period, and to accomplish this, memory look-up t S
22 again required~ The address space for this 18 the union of 23 VCI and M_ID which is 34 bits, and hence the number of 24 address locations required would be of the order of 2 x 101. Again this is far too large to be practical.

27 A two sep memory look-up to enable this has been 28 developed and an embodiment is described with reference to 29 Fi~ure 6. The VCI_IN and M_ID IN of the ir.coming segment on line 524 are presented to and are demultiplexed by 310 and 31 respectively passed to the VCI TAG server 317 and M_ID TAG
32 server 318 which produce a VCI TAG of k bits on bus 322 and 33 an M_ID TAG of 1 bits on bus 323. The two buses are 34 combined into the common bus 324 of (k+l) bits and presented to the M_ID_OUT Server 326 which in turn produces the 36 M_ID_OUT 328 and to the VCI_OUT Server 325 which produces 37 the VCI_OUT 327.
38 .
~91-10.9 r-~e~ 9r~

-.

1 The required memory sizes in the four servers are 2 related exponentially to the number of lnput bits and 3 linearly to the number of output bits. The total number of 4 bits stored over the four memorles ls :

6 Nl = k2m +12n + ~2(k+1) + m2(k+1) 8 If a single memory look-up was used then the number of 9 stored bits would be 11 N2 = (m+n) 2(m+n) (5) 13 When (k+l) is an appreciably smaller number than (m+n), 14 then Nl is very much smaller than N2. For instance, with m equal to 20 and n equal to lg and if k and 1 are both equal 16 to 8, Nl is approximately elevsn million, while N2 is in 17 excess of 5 x 1011 or five hundred thousand million.

19 The four servers 317, 318, 325 and 326 in the block schematio of Figure 6 are all simllar circuits di~fering 21 only in numerical sizes of memories and lines and can be 22 understood with the help of Fi~ure 7. The Key 350 in Figure 23 7 represents any one of the inputs VCI_IN 311 or M_ID_IN 312 24 or combined VCI TAG and M ID IN TAG 324 of Figure 6. The TAG 396 in Figure 7 represents respectively the VCI TAG 322 26 or M_ID IN TAG 323 or VCI_OUT 327 or M ID OUT 328 of Figure 27 6.
29 . With reference to Figure 7, the key 350 is applied on bus 356 as address selection to Count RAM 340 and on bus 355 31 as address selection to Label RAM 365. This enables the 32 read-out and write-in of data stored at the selected memory 33 locations. A count value 347 from the RAM 340 is read out 34 into a counter 346, and a label value 389 from the RAM 365 is read into Tag_latch 395. Writing into the RAMs and 36 operation of the counter 346, latch 395 and TAG_FIFO 380 are 37 under the control of a controller 385.
38 .
,-I!~91110,gcp-p-.002,qp~ 9 ' ' ~ ' ' .

2 The controller 385 receives segment type indication on 3 bus 397. It also receives on bus 390 the Tag value as read 4 out from the Label RAM 365, and on bus 348 the updated count value produced by the counter 346. It also has the 6 possibility of input of externally generated labels on bus 7 399.

9 When appropriate, the controller issues:
11 (i) to the Count RAM 340 a Write command on line 341;

13 (ii) to the counter 346 a Load command on line 342, an 14 Increment command on line 343, a Decrement command on line 344, and a Clear command on line 345;

17 (iii) to the TAG FIF0 380 a Read command on line 370, a 18 Write command on line 391, and Tag out on bus 37~;

20 (iv~ to the Label_RAM 365 a Wri~e command on line 360, 21 a data word of all-zeros on bus 366; and 23 (v) to the Tag_latch 395 a clear command on line 371 24 and Load command on line 394.
26 Also, when appropriate, the controller 385 outputs the 27 error code on bus 386 and the New_output indication on line 28 387.

The controller can be a micro-programed processor with 31 a wide choice of specific embodiments. The processor may 32 comprise an EPS 448 or a number of these cascaded in 33 parallel. Its functions can be achieved by executing a 34 program described by the following pseudo-code (which is somewhat similar to the languages Pascal and C):

~191110 . gcp-pe . 002 . qp~c . 20 1 repeat {CONTROL LOOP}
2 repeat {do nothing} until new_input; {SYNCHRONIZATION ON}
3 clear (new inp~t); {LINE 398}
4 load (counter);
case segment_type of 6 BOM: begin 7 if ( ( counter=0) and (tag=0)) 8 then begln g error_code:=0;
read(tag_fifo,data);
11 write(label_ram,data);
12 increment(counter);
13 write(counter_ram,counter);
14 load(tag latch) end 16 else if((counter<>0) and (tag<>0)) 17 then begin lY error_code: 30;
19 increment(counter), write(counter_ram,cQunter);
21 load(tag_latch);
22 end 23 else begin 24 error_code:=l;
clear(tay_latch);
26 end;
27 end;
~8 29 COM: begin if((counter<>O) and (tag<>O)) 31 then begin 32 error_code:=O;
33 load(tag_latch);
34 end B9'110.gcp~pe.002,qp~l.Zl l else begin 2 error_code:=2;
3 . clear(tag_latch);
4 end;
end;

7 EOM: begin 8 if((counter<>O) and (tag<>O)) 9 then begin load(tag_latch);
11 decrement(counter);
12 write(counter_ram,counter);
13 if(counter=O) 14 then begin write(tag_fifo,tag);
16 write(label_ram,O);
17 error code:=O;
18 end;
l9 end else begin . I
21 error_code:-3:
22 clear(tag_latch);
23 end;
24 end; {END OF CASE}
~5 pulse(new_output);
26 until forever;

28 A flow diagram of the program is illustrated in Figures 29 lOA to 10~. :
31 The operation of the tag server and actions of its 32 controller 385 may be explained more fully by reference to 33 Figure 7 for the case of a VCI TAG server i.e. the server 34 317 of Figure 6. In this case the Key 350 appearing on buses 355 and 356 is then the VCI as it has come in the 36 header of the current segment. If the segment ls a COM
37 (continuation of message), the Label read out from the Label 38 1.

r911~0 g~r~P-.002,~1,Z:~

:

l RAM 365 is non-zero, and previously stored for that VCI.
2 The Count read-out of the Count RAM 340 is also non-zero.
3 The controller checks if the read out Label and Count are 4 non-zero. If either or both were zero that would signify an error condition and the controller would signal it by 6 producing an error code on bus 386. If the VCI TAG is 7 valid, the controller lssues a Load command on the line 394 8 and the VCI TAG is latched into the Tag latch 395.

10 When the segment is a BOM (beginning of message) there ll may or may not be a VCI_TAG for it. If there i8, then the 12 Count and Label, as read out, are non-zero. In that case 13 the Controller will latch the VCI TAG into the Tag Latch 395 14 as before. It will also put an Increment command on the 15 line 343 which increase the Count of the counter 346 by one.
16 Following` this the controller will put a Write command on 17 the line 341 to write the updated Count into the Count RAM
18 340. If there is no VCI TAG for the given VCI, then the l9 Count and Label, as read out are zero, and a VCI_TAG has to 20 be assigned.

22 Assigning of the VCI TAG occurs from the ~AG FIFO 380 23 on command from the controller. Assumlng the TAG_FIFO 380 24 is not empty, the next in line unused VCI TAG is read out by 25 command on line 370 onto bus 366, and by command on line 26 360, it is written into the Label RAM 365 which also makes ?
27 the VCI_TAG appear on the bus 389. The valid VCI_TAG is now 28 latched in*o the Tag_Latch 395. Also the Count is 29 incremented making it one, and written into the Count RAM
30 340 as before. I

32 Should the TAG_FIFO 380 be empty when a BOM arrives and 33 assigning of a tag is necessary, then no assignment can be 34 made. It will be an error condition that will result in the 35 loss of that message. The numerical size of ~he TAG space 36 can be selected so as to ensure that the possiblity of 37 running into depletion is of negligible probability.

891~10.gcp~pe.002.qp-~,23 1 Finally, when the segment is an EOM (end of message), 2 the conditions and actions in reading the Label RAM 365 are 3 the same as for a COM. But there is the possibllity that 4 the tag becomes free and is returned to the pool. The 5 controller 385 puts a Decrement command on the line 344 to 6 the counter 346. This reduces the Count by one and the 7 updated Count is written into the Count RAM 340. If the 8 resulting Count equals zero then the Tag has become free.

9 The tag is latched into the Tag_Latoh 395 and also by Write 10 command on the line 391 written into the TAG_ FIFO 380.

11 Following this, an all-zeros tag is put by the controller on 12 the bus 366 and by Write command on line 360 written into 13 Label RAM 365.

15 The operation of the other two servers in Figure 6, the 16 M_ID_IN TAG server 318 and the M ID OUT server 326, are 17 similar and can be understood by analogy. The M ID_OVT

18 server 326 differs from the other two only in that M_ID OUT

19 labels are limited in their total number by the number 20 allocated to the server by an external ~anager (not shown) 21 and not the size of space. Labels can be brought in from an 22 outside source via label in bus 399 and into the TAG_FIFO

23 380 via bus 372. Also the ~ey, comprised of VCI_TAG and 24 M ID TAG, is unique for a particular datagram and the Count 25 will be one for a particular Key following BOM and go baok 26 to zero, following EOM. Thus the function of the Count RAM

27 340 is nil and may be dispensed with in this case.

29 The VCI_OUT server differs from the M_ID_OUT server 30 only that it does not have a pool of labels and therefore 31 does not require the service of a TAG_FIFO. Also, in common 32 with the M_ID_OUT server, it does not require a COUNT RAM. 7 33 A VCI_OUT is determined by the system of Figure 5 on entry 34 of BOM. It is passed to the Controller of the VCI_OUT

35 server via bus 399 as shown in Figure 7. The Controller 36 writes it via bus 366 into label RAM 365. On arrival of 37 EOM, that address location is zeroed, again via bus 366.

891110 . 9Cp~p~! . 002, qp-~, 2~ 1 2 Although three types of router, Types I, II and III
3 have been described, it will be appreciated that a generic 4 embodiment is possible. By appropriate change of executable programs in the controllers a generic router can be changed 6 from one type to another.

8 It will also be appreciated that the overall system of 9 Figure 1 can be altered materially and still achleve the same functions. It has already been noted that the 11 connectionless zero level domains can be dispensed with by 12 connecting the end equipment directly to the routers, one 13 pair of routers for each separate end equipment but this is 14 less favourable in that it requires a substantially larger number of routers. The zero level domains act as 16 concentrators, allowing one router to serve a large number 17 of equipments while at the same time providing a 18 connectionless switched service for intradomain 19 co~munication.
21 It will also be appreciated that the concentration 22 function can also be achieved by a connection-oriented 23 domain with a simplified routing function from the separate 24 end equipments, if all connectionless messages are sent to a single router. The router then approximates the central 26 connectionless server.

28 The connection-oriented concsntrator does not itself 29 provide any connectionless intradomain communication, and the router functionality has to be accordingly enlarged to 31 provide it.

33 Although a specific context of network standards and 34 specific embodiment of the invention within that context are shown and described herein, this is merely for the purpose 36 of illustration. Those skilled in the art wlll be able to 37 devise other arrangements which, although not specifically ~91110.9cp~pe.002.qp~l,25 1 shown or described hereln, embody those ~rinciples and which 2 do not depart from their spirit and scope. For example, the 3 system described above is in the context of segmented 4 transfer of datagrams, but it is applicable with some deletions to the less demanding context of unsegmented 6 transfer. Also, for example, particular types of hardware 7 such as random access memories, multiplexers, priority 8 encoders, FIF0 memories etc. are described but these could 9 be replaced by more elementary or specially constructed components to perform similar functions.

;

~91110,qcp~p-.002.qp~.26

Claims (32)

1. A network for routing datagrams which include at least one segment, the network comprising at least one segment switching means, and a plurality of routers connected between the switching means and a plurality of terminals and adapted to process data in a datagram transmitted from a first terminal so as to pass said datagram from a first router to a second router via said switching means and pass said datagram from said second router to a second terminal.

2. A network as claimed in claim 1, comprising a plurality of segment switching means connected by said routers so as to correspond to respective hierarchical segment transfer levels, switching means of a first level being coupled to said terminals and switching means of a second level, which is coupled to at least two switching means of said first level.

3. A network as claimed in claim 2, wherein one switching means of said first level is connected to another switching means of said first level.

4. A network as claimed in claim 3, wherein said switching means are all coupled to a switching means of a higher segment transfer level, except the switching means of the highest segment transfer level.

5. A network as claimed in any one of the preceding claims, wherein a datagram is transferred through said network on the basis of a final destination address of said datagram.

6. A network as claimed in any one of the preceding claims, wherein said terminals are connected in at least one group by at least one area network means connected to said switching means by said routers.

7. A network as claimed in claim 5, wherein said routers comprise:
first means for receiving said datagrams and accessing said destination address from said datagram;
second means responsive to said first means for determining output connection data on the basis of said destination address; and third means for including said output connection data in said datagram;
said datagram being routed in said network on the basis of said output connection data after being outputted from said router.

8. A network as claimed in claim 7, wherein said second means includes:
memory circuits having connection data and selection data stored therein;
fourth means for dividing said destination address into fields and applying said fields to respective ones of said memory circuits to access a plurality of corresponding connection data and selection data; and fifth means for selecting said output connection data from said plurality of connection data on the basis of said selection data.

9. A network as claimed in claim 8, wherein said selection data correspond to a priority code such that said connection data is selected on a priority basis corresponding to said hierarchical segment transfer levels.

10. A network as claimed in claim 7, 8 or 9, wherein said third means includes message means for determining output message data for said at least one segment of said datagram on the basis of input connection data and input message data accessed from said at least one segment by said first means;

said third means including said output message data in said at least one segment;
said output message data indicating said at least one segment belongs to said datagram on output from said router.

11. A network as claimed in claim 10, wherein said message means further determines said output connection data for subsequent segments of a datagram after a first segment thereof has been processed by said router, said output connection data being determined on the basis of said input connection data and said input message data;
said third means including said output connection data in said subsequent segments.

12. A network as claimed in claim 11, wherein said message means includes at least two tag serving means which are adapted for access by said input connection data and said input message data, respectively, to output a connection tag and a message tag, respectively, said output message data and said output connection data being determined on the basis of said tags.

13. A network as claimed in claim 12, including further tag serving means responsive to said tags for outputting said output connection data and said output message data, wherein said tag serving means comprise:
an available tag store for storing available tags, a memory for storing a current tag for a datagram, and means for determining when the current tag is no longer required and returning said current tag to said tag store.

14. A network as claimed in any one of the preceding claims, wherein said routers process said datagrams in real time.

15. A router for a network for routing datagrams having at least one segment, said router comprising:

first means for receiving said datagram and accessing said destination address from said datagram;
second means responsive to said first means for determining output connection data on the basis of said destination address; and third means for including said output connection data in said datagram;
said datagram being routed in said network on the basis of said output connection data after being outputted from said router.

16. A router as claimed in claim 15, wherein said second means includes:
memory circuits having connection data and selection data stored therein;
fourth means for dividing said destination address into fields and applying said fields to respective ones of said memory circuits to access a plurality of corresponding connection data and selection data; and fifth means for selecting said output connection data from said plurality of connection data on the basis of said selection data.

17. A router as claimed in d aim 16, wherein said selection data correspond to a priority code such that said connection data is selected on a priority basis corresponding to said hierarchical segment transfer levels.

18. A router as claimed in claim 15, 16 or 17, wherein said third means further includes message means for determining output message data for said at least one segment of said datagram on the basis of input connection data and input message data accessed from said at least one segment by said first means;
said third means including said output message data indicating said at least one segment belongs to said datagram on output from said router.

19. A router as claimed in claim 18, wherein said message means further determines said output connection data for subsequent segments of a datagram after a first segment thereof has been processed by said router, said output connection data being determined on the basis of said input connection data and said input message data;
said third means including said output connection data in said subsequent segments.

20. A router as claimed in claim 19, wherein said message means includes at least two tag serving means which are adapted for access by said input connection data and said input message data, respectively, to output a connection tag and a message tag, respectively, said output message data and said output connection data being determined on the basis of said tags.

21. A router as claimed in claim 20, including further tag serving means responsive to said tags for outputting said output connection data and said output message data, wherein said tag serving means comprise:
an available tag store for storing available tags, a memory for storing a current tag for a datagram, and means for determining when the current tag is no longer required and returning said current tag to said tag store.

22. A router as claimed in any one of claims 15 to 21, wherein said datagrams are processed in real time.

23. A method of routing datagrams in a network having at least one segment switching mean, and a plurality of routers connected between the switching means and a plurality of terminals, said method comprising processing data in a datagram transmitted from a first terminal so as to pass said datagram from a first router to a second router via said switching means and pass said datagram from said second router to a second terminal.

24. A method of routing datagrams as claimed in claim 23, comprising transferring a datagram through said network on the basis of a final destination address of said datagram.

25. A method of routing datagrams as claimed in claim 24, further comprising:
accessing said destination address from said datagram, determining output connection data on the basis of said destination address, including said output connection data in said datagram, and routing said datagram in said network on the basis of said output connection data after said datagram is outputted from said router.

26. A method of routing datagrams as claimed in claim 25, further comprising dividing said destination address into fields, applying said fields to respective memory circuits having connection data and selection data stored therein to access a plurality of corresponding connection data and selection data, and selecting output connection data from said plurality of connection data on the basis of said selection data.

27. A method of routing datagrams as claimed in claim 25 or 26, wherein said selection data correspond to a priority code such that said connection data is selected on a priority basis corresponding to hierarchical segement transfer levels, which comprise respective segment switching means connected by said routers.

28. A method of routing datagrams as claimed in claims 25, 26 or 27, further comprising accessing input connection data and input message data from said at least one segment, determining output message data on the basis of said input connection data and said input message data, and including said output message data in said at least one segment, said output message data indicating said at least one segment belongs to said datagram on output from said router.

29. A method of routing datagrams as claimed in claim 28, further including determining said output connection data for subsequent segments of a datagram, after processing of a first segment thereof, on the basis of said input connection data and said input message data, and including said output connection data in said subsequent segments.

30. A method of routing datagrams as claimed in claim 29, further including accessing a connection tag and a message tag from tag serving means on the basis of said input connection data and said input message data, respectively, and determining said output message data and said output connection data on the basis of said tags.

31. A method of routing datagrams as claimed in claim 30, further including obtaining said output message data and said output connection data from further tag serving means on the basis of said tags, wherein in said tag serving means available tags are stored in a tag store, a current tag for a datagram is stored in a memory and the current tag is returned to the tag store when said datagram has passed through said router.

32. A method of routing datagrams as claimed in any one of claims 23 to 32, wherein the steps of the method are performed in real time.