CA1285069C - Image storage and retrieval apparatus - Google Patents
Image storage and retrieval apparatusInfo
- Publication number
- CA1285069C CA1285069C CA000570751A CA570751A CA1285069C CA 1285069 C CA1285069 C CA 1285069C CA 000570751 A CA000570751 A CA 000570751A CA 570751 A CA570751 A CA 570751A CA 1285069 C CA1285069 C CA 1285069C
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Abstract
Abstract of the Disclosure There is disclosed a still image storage and retrieval apparatus that is capable of storing and retrieving a large number of images from a magnetic disk storage medium. The apparatus uses a color under recording format, and the disk speed is synchronized to the video sync signal. The recording and playback signals are time base compensated to offset the effects of jitter in the disk speed by using reference frequencies from the disk drive to down-convert and up-convert the color signal. In another embodiment a reference signal from the disk is used to modulate the color signals. In another embodiment a digital "walk along" memory stores time base error information during recording for time base error correction during playback. A one image memory is also provided to allow for transition between images during playback.
Description
s IMAGE ST(:I~AGE AND
~RETRIlEVAL APPAlE~ATUS
E~ackgr~und of the In~rent~o~
This invention r~lates gcnerally to all ~age storage and retrieval apparatus and more pa~icularly relates to a~
S apparatus ~or storing m~re than 2000 still color video images on a storage medium, such as a magnetic disk, a~d r~trieving ~e images for display and lpr~cessillg.
~rre~t digital record~ng with its atte~da~t cnst has prevented high density storage of ~till color video images ~d high speed random acce3s wil:h ~rasability. The problem VVAth stora~e of color images i~ digital form is the tremendous ~nou~t of storage ca~ity requi~ed, typically 500+ ~ilobyte~ of storage pet ~age. (~tical discs9 while pro~iding high deDsity storage, a~ ot erasable at r~ able cos~.
I~ video recordi~g, ~he lulminance and eolor component~, of a video signal a~ ei~er recorded toge~er on a si~gle magnetic tra~k or are recorded separa~ely on two or more tracks. Predictably, ther~ are adval~tages alld drawbacks to each app~oach. Sil~gle track recording requires less recording media spa~e and ~ereby illcreases the llumber of images ~a~ caII be placed on a giveII magnetic media. Recording the video sign~l components on two or more tracks usually improves ~e image quality, but severely ~;
complicates ~e appara~s and reduces ~e storage capa~ity of a given media by one half or more.
Early Yideo disk recorders for ~plays were pio~eered by ~mpex and othe~s in the 1960's and used bo~
S rigid and floppy disk mag~etic media for storage of images.
~ese systems typically used a narrow band FM recording of d~e modulated analog signal and s~ored a single video frame with eac~ rotation of ~e disk. AI~Lough p~oviding ~he user with some excellent advantages, such as a high image storage density and quick access times, these units we~e suff~cie~ltly expe~sive to limit their use to high priced systems iII
broadcasting and medical ima~g. Fur~er, ~ese early uI~its we~e limited by ~e irregularities in and o~ the surface o~ the recording media. This led researchers at that timc to discover t~t frequency modulation, Yersus amplitllde modulation, was a more ef~ective way to e~ode ~e video signal. These systems also required a high head-te)-media relative velocity of 1,00~ to 2,000 i~ches per second~ due to head gap lengths, short video wave lengths required, alld high signal-to-noise requirements. In ~e floppy disk ~ersions of ~ese systems where the heads were in co~sta~t con~t w;th ~e media, the u~eful li~ ~as limited, usually less ~ 0 hou~. Irl the rigid disk ~ersio~s~ useful li~e migh~ approa~h 2,500 hours prolonged by the air space between ~he heads and media, but limited due to ~ u~ach~ring impe~feotions, wear from occasional head-to-media contact, a~d o~er ~actors.
Image storage technology today is c~aractetized by ~e mo~rement from ~llm and slides to videotape a~d video disk to digitized images in digital mass storage. This recent tech~ology has taken two directions: ~e ~Irst is a irend toward digita~ ~tideo disk or CD-ROM (Compact Disk - Read Only Memory); the second, a trend toward WORM (Write Once, Read Ma~y) storage. Both of these tech~ologi~s have signifi1cant drawbacks in ~at ~ey are not erasable and suffer ~om high media ~torage capacity reqllirements. The market today has seen ~e i~troduction of lower cost, high quality digitizetl storage of ima~es. However, ~e problem as p~eviollsly l~oted wi~ storage ~ color ~mages in digital ~orm is ~at it takes a tremendous arnount of info~mation storage c~acity9 typically soo~ kilobytes of sto~age per Image.
The need for a compact, ine3cpe~ive, to~ly self-contained image recorder, ~torage unit, playback and moni~ori~g dev;ce ~or storLng large ~umbe rs ~f hi~ ~uality lo s~ill color images is apparent in ~everal fields: secunty ~d sur~eillance, entry access system~ computer penph~rals, training devices, and pictu~e archiving ~y~tems~ d as a replacement for color slide p~jecto~, to name oI~y a few.
lS Summary of the In~vention It is ~erefore an object o~ ~e preseslt inve~tion to provide an ~mage storage and re~ie~al apparatus capable of storing a large ~umber of high quality 5till color images a~d retrievi~g those image~ rapidly for di~play and fur~er processing.
It i~ fur~er asl obj~ct of ~e pre~ent invention eO
provide mean~ ~or corrgcting ~omalies ~ ~e time base of the video signal~ whiçh anomalies l~sult ~rom storage and/or ~triev~l of ~e sdll color images.
It is likewi~e an object of the prese~t inventioll to :- p~ovide an image storage and retlieval apparab~s having an au~iliary memory for storing corrc~ponding data such as . time of day, da~e, c~era lens i~ormatio~, time base er~or information, etc., correspo~ding to each of ~e stored still color images.
It is also a:~ object of ~he prese~t invention to provide mea~ for huldi~g a first image rebrieved ~rom the : ~ storage medium dunn~ ~e subseque~t retricval of a second image from the storage medium so ~at ~e two images may be ~issolved, blended, overlaid, or ompared in other fashions.
l[t is likewise a:ll object of ~e prese~lt inven~ion to provide an ~age storage and re~ieval appa~atus in which the s~orag~ medium is erasable so ~at image~ may be s~ored or ~placed by o~er i~nag¢s as desi re~.
III order to a~tain ~he foregoing objec~iv s, ~e ~age storage and retrieval apparatus stores aIld retrieves a ~umber of still images from a storage medium. The apparatus comprises a ~to~lge medium7 prefer~bly a high speed magnetic hard disk, a servo~coII~olled motor îor rotating ~e disk at a presekcted speed, read/~te !heads and circuitry ~or selectively positio~g ~e read/~te: he~d~ to select aIly olle of a nu~nber of circul~r tracks on ~e ~torage disk. A secord ci~cuit proceses a ~onventio~al composite video sig~al and produce~ an analog sig~al which ls connected directly to dle read/write hea~ recorded on one tracl~ of th~ ~torage dis~. A play~k c~rcuit re~ieves ~e analog signal ~om one of ~e selected tlacks of ~e video - 20 disk v;a ~e ~eadJwnte head and ~eco~stitut~s ~e composite ~: ~ video signal. Control means, a microprocessor, respvnds to ~: ext r~ structio~s, ~ucb as ~ keyboard, a computer port ir~put, or similar con~ol input, selects ~e particular ci~cular ~rack on the storage disk, and selects ~e storage tnode or re~rieval mode fo~ ~e ~pparat~
^ ~ The record circ~ of the pre$en~ inveIItion separates a co~ventional composite video ~ignal into i~s lumi~ance alld chroma compo~ent~, dowII-converts the chroma comporlent by a reference frequency, preferably about 4 MlHz, freque~cy modulates the luminance colmponent, ~ecombine~ ~e modulated lumina~ce and down-converted chroma compunents to produce aIl analog signai for storage on ~e disk via o~e of ~e readJwnte ~eads. The ;;: playback circuit upon receivi~g ~e analog sig~al from the read/write head separates the luminance and chroma '~
~ ~35~,9 compone~ts7 de3nodulates and delay~ the luminance componellt, up~o~verts ~e chroma component lback to its origi~al frequency in a conventional video sig~al and subsequelltly recom~ine3 ~e ~omponen~s to reco~er ~e S composite video signal ~or dislslay on a standard video monitor.
In order to assure cle~ re-record3ng of substitute images7 an e~9e circuit is proYided whi~h may be either a high i~reque~cy oscillator or a dccreasi~g reversing d.c.
current switch. The micr~processor for ~e app~ratus upon receivirlg a command to record an image9 filrst i~itiates an erase sequence which9 in one emotiment, co~ects thc high ~requency oscillator to ~e ~eadlwrite head to rec:ord the erase freque~cy for 2 predetermi~ed time. In another embodiment, tlhe microproce~sor connects a decreasing reverse d.c. GUrreD~ switclbi to ~e read/write head so t~t each pass of ~he read/wnte head over ~e circular track has a decreasing ~nt density. Co~equently9 ~e track is totally degaus~ed prior ~o reco~d~ the ~e~t ~till color image on the particularly selected ~ircula~ trac~.
The image sto~ge and retrieval apparatus of the prese~t in~entio~ assures high quality image storage and re~ieval by compensati~g for jitter ~at irlevitably occurs in ~h~ speed of ~e spinning ~torage disk~ I~ o~e a~pect of ~e 2S invention, an en~oder connected to ~e spin~le of ~e~ seorage di~ produces a rota~ion sig~al which, during dle storage mod~, is cons~tly compared in a pha~e lock loop to ~e videv sync signal from ~e incom~g eoDQpo~ite ~ideo signal ~n order to control ~e seno-motor which drives ~c storage disk. In a~o~er as~ect o~ ~e pre~ent in~re~tion, ~e ou,hput of ~e encoder produces ~e refer~nce frequency which is used to bo~ dvw~o~vert ~e c~oma signal in th~ ~cor~ circuit and up~onvert ~e chroma signal in ~e playback circuit. In a~o~er aspect of ~e p~sent inyention, the encoder produces a rcference signal which is ul~ed in a signal processor to 3~ )9 modwlate the primary red, green, and blue si~als prior to pr~ducin~ ~e conventional composite video signal wi~ the lum~aance znd ch~ma composent$.
~n another a~pect of the present inve~ion, an S a~iliary addressable digital naemory is prwided which h~ a number of data ba~k~ each correspo~d~ng to a single 3~cordl~g track o~ ~e ~torage disk and a ~umber of words wi~in each bank. The au~ili~y memory is addressed by ~e miGroproCeSSor SimUl~aneQUSly YVith addr~ssing the sto~$e lo disk, alld ~he e~coder produce~ a word count wi~n each memrry bank so ~at as the storage dlisk spi~s, the digital memory under cont~ol of ~e e~coder steps along ~ ~e storage disk. Therefore, correspondil~g data can be stored in the auxiliary memory, and upon ~etrieval of ~e Istill image fr~m ~e s~orage disk, ~e auxilia~y memory, steppiag ~long with ~e storage disk, can output ~e auxiliary i~olmation to a display or to be used for ~ur~er con~ol.
Also, in accordance with the same auxiliary memory, ~e ~fonn~tio~ stored can be in~ormation relating to the jitter experienced by the storage disk during the storage mode. Upo~ retrieva~ Ihat s~oled e~T~r in~ormati~n ca~ be re~rievedl a~d u~ed to compensate ~e rgcoYered analog signal and re~Ye the e~ects of ~e ~ime base errors ~at occllr du~ng storage and re~iev~.
In ano~her aspect of the pre~nt inventio~9 a digital frame memory is provided to hold a single f~e or image while the ne~tt image is retrieved from ~e storage disk so that the two images c~ be mi~ed widl eaGh o~e~ to p~duce special e~fects such as dissolving, overlayin~, ble~ding, or ~e iike.
Other o~ects and adva~atage~ of the present Lnvention will become apparent upon reading ~e following detailed descripdon ar~d upon re~er~a~e to ~e drawings.
6~3 Brief Descriptlosl o~ the Dra~ng~
lE~igure 1 is a bl~k diagr~ showing the ~mag storage and r~ieval apparatu~ ~ the present iIlventio~;
Fig. 2 i~ a bl~k diagr~ of ~he ~co~d ci~ of ~e present invention;
Fig. 3 is a block dia~dlm of ~e pla~ack circuit oî
~e p~ese~t i~ention;
Fig. 4 is a block diagram o~F ~e e~e ci~uit of ~e pre~en~ inveD~ion;
Fig. S is a blocl~ diagraln of ~e servo~on~ol Ci~llit of the present i2lve~ion;
lFig. 6 is a block diagram show~g one me~s of àme base compensation ~uring ~e s~rage mode;
Fig. 7 is a bl~ diagram ~howi~g o~e ~aeans of t~e ba~e compensa~on d~g the retrieval mode;
Flg. B is a block diagIam showing ano~her mea~s of ~ne base compensation during ~e storage mode;
Fig. 9 is a block diagr~ showing a modified record circuit;
Fig. 10 is a block diagram showing a modified pl~yback circuit;
Fig. 11 i~ a block diagram showing an addres~able digital au~tilia~y memory which "wallcs along" wi~ the ~age di~k;
Fig.12 i~ a block diag~ showing one mea~s of using ~e auxili~y memory to provide time base co~rection during dle retIieYal modey a~d Fig. 13 is a block diagram showi~g a digi~al single image di~ital memory for mixi~g two images during t~e re~ieval mode.
Detailed De~cription of ~he Ill~e~ion While ~e inventio~ wiil be described ~ connec~ion with preferred embodime~t, it will lbe under~tood that I do 3s not intend to limit ~e invention to ~at embodiment. On the ~ A 2 ~3 5 5 ~ 9 con~ry, I intend to eover all alternatives, modificatiorls, and equivalent~ as m~y b~ included within the spin~ and scope of the invention as de~ d by ~e ~ppended cl~s.
Turning to Pi~use 1, ~here is ~hown the image s storage and retrieval appa~tus 10 s3f t!he present invention.
~e apparatu~ include~ a rnain storage med;um or disk drive 11. The sto~age medi~ cludes a set of mag~etic dis~s 12 a~d 14 mounted Oll a spindle 16 w}lich spindle i~ rota~ed by a servo-controlled mo~or 18 at a preselected speed. ~n 0 e~od~r 20 is a~so attached to ~d rota~es with the spindle 16.
The storage medium ll al~o i~cludc~ a readlwri$e head a~semlbly 22 which includes a re~d/write heacl 24 ~at is mounted adjace~t to d~e top sur~ace 13 oî ~e disk 12, a readJ~te head 26 wlhich i~ mou;~ted adjacen~ to the boKom surPace 15 of the disk 12, a read write head 28 whieh is mou~ed adjacent ~o ~e top surface 17 of ~e disk 14, and a .~ read/write head 30 which i8 mouIlted adiacent to ~e b~ttom surface 19 of ~e disk 140 The rçad/wnte head assembly 22 simultaneously move~ ~e heads 24, 26, 28, and 30 radially ; ~ 20 across ~e disks 12 ~d 14 u~der co~trol of a head drive means 32.
he disk~ 12 ~d 14 are divided in~o a number of collce:utric tracks on e~ch of ~he four sur~es, such as tracks 34 and 36 on the top sur~ace 13 of di~k 12 and radially :: 25 aligned co~pondi~g tracks 35 a~d 37 on the top surface 17 of disk 14. ~e tracks 34 and 35 toge~her (along widl two similar radially aligned tIac~ o~ the bot~om sul~aces 15 ~nd - 19 of dislcs 12 and 14) define a~ imaginary cyli~der. In order to record (write~ i~formatio~ onto ~e traclcs 34 ~d 35 in the storage mode or to 3ense (read) information recorded on ~acks 34 and 35 in ~e retrieval mode, ~e head drive means 32 positio~ ~e head assembly 22 so ~a~ d~e heads 24 and 28 are located above tracks 34 and 35 respectively. By moving ~e read/write heads 24, 26, 28, and ~: 35 30 radially toge~her to a particular selected cylinder and by :
selecting one of the four heads as will be descnbed in greater detaal, a palticular t~c~c on any one of ~e four disk surfaces can be selected for recording or for playback.
The storage snedium 11 also has a disk drive S micropr~essor 38, wh~ch by means of output 40, contsols the he~d drive 32 a~d ~erefore selects the desi~ed tracks by positio~ing readlwrite heads 24, 26, '28, and 3(). The output sig~al on line 42 controls dle speed of the motor 18~ A
sensor 44 is mounted adj~cent the encoder disk 20 and sen~es dle rotativn of ~e spindle and pr~vides ~at in~ormation to dle microprocessor 38 by means of input line 46 so that the mic~oprocessor 38, via output 42~ can control ~e æpeed of ~e spindle as required.
The storage medium 11 including the disks 12 ~nd 14, motor lB, encode~ 20, head assembly Z2, head dAve 32, and ~e microprocess~, 38 ar~ pre~erably implemented by use of a La Pine Ti~ 20 Disk Drive available from La Pine Technology, ~ilpitas~ California Su~ a disk drive, is typically used ;n connection with providing additional storage for digital information Ior persoD~l computers.
1~ addition to ~e disk drive 11, the Pv~rieval and storage apparatus of the present invention comprises a record circuit 50, a playback circuit 52, and con~o~ means ~: 80. The ~eco~d cir~uit S0 receives a conYentional composite video sig~al at its i~put 54, processes ~at signalS and transmits ~e processed video signal to head multiplexing cir~uit 56 via record ou~put 58, isolatio~ switc:h 6n, a~d t~ansmission line 62. 'llh~ p~cessed video signal on line 58 is an a~alog s~g~al which is co~ected ~rough the head multiplex circui~ 56 to any one of the four output lines 64, 66, 68, and 70 which are connected respectively to read/wri~e heads 24, 26, 28, and 30 for storing the analog sign~l onto one of the four selected tracks on one of the two disks.
1~
Alterna~ively, in the retrieval mode, the information se~sed by o~e of ~e four readl~te heads 24, ~6, 28, a~d 30 is co~nected via ~e head multiplex circuit 56 to the t~nsmission line 62, through isolation switch 6n, and s to illput 72 of the playback cir~uit 52. The playback circuit 52 receives ~e analog signal on line 72 and reconstitutes the composite video sigllal on its output 7~ ~vhic~ is connected to - moni~or 76 and t:o awciliary output 7~. The record circuit 50 and playback cir~uit 52 will be Idescribed in greatcr detail below ~ connee~on with Figs. 2 and 3.
The image storage and reb~eval appa~tus lû is operated under ~e control of co~trol means 80 which is a microprocessor. The micropro~essor 8û ~eives c:ommands f~om any appropriat~ input means such as keyboard 92 or RS-232 computer port ~4. l'he RS-232 port 94 l~fers to a s~ndard port with de~ned pin connec~ions, signal levels, and the like promulgated by the Electronics Industries Association of Washingto~; D.C., denoted as RS-232-C
(August 1969~ a~d en~itled "Interf~ce Betwee~ Data Terminal Equipment a~d Data CommuDications Equipment Employing Serial Bi~ary Data Interc}lange". The microprocessor also provides an indication on line 96 of the particular image being stored or retrieved w~ich status is the~ displayed o~ display 98~ Ths microprocessor 80 is 2s pre~errably a Zilog Z8 manufactured by Zilog, Inc. of Cupertino, Califon~ia.
The microprocessor 80 by means of` output 84 instructs ~e disk driYe microprocessor 3B to move ~e head assembly 22 radially in or out, and ~e output on li~e 82 tells microprocessor 38 how far the head assembly 22 should be moved radially. Upo~ receipt of ~e direction and step instructions on lines 84 and 82, the micr~processor 38 instructs head drive 32 to move the head æsembly 22 so that the read/write heads 24, 26, 28, and 30 are adjacent a .~ ,... .
.3 p~cular seles:ted cylinder and the four circular traeks on the disks ~at define ~at oyl~nder.
C)nce the microprocessor 30 has caused the microprocessor 38 to select a particular cyli~der, the s microprocessor 80 selec~s one ~f the read/write heads 24, 26, 28, or 30 by mea~s oï a multiple~ ins~ctio~ OD. line 86 which controls multiple~ ei~suit 56 and sallses multiple~
circuit 56 to select o~e of i~ signal lines 64, 66, 68, and 70.
The microp~ocessor 8Q also ~e~ect3 the storage 0 mode or the retrieva3i mode ~r ~e apparatu~ 10. If ~e storage mode is selected~ the microp~essor 80 first selects the track and headl and the~ ccordance with ano~er aspect of the present inve~gio~, ~he microprocessor 80 via ou~:put line 102 activates e~e circuit 100. lhe erase circuit 100 co~ec~s an erase signal to transmis~io~ e 62 via erase output 10~ and ~e~ to ~e seiectgd head ~ ~e disk drive via ~e multiplexer 56. While ~e erase s~que~ce i~ enabled, ~e microproce~sor also is~es a command on OlltpUt 108 to open i~olatinn switch 60 which a~su~es ~hat ~e erase signal on li~e 104 is not connected back into ~e r¢co~d circuit 50 or the . playback circuit S2. The erase circuit is selected for predetermined amou~t of time to assure ~a~ ~he sel~c~ed ~rack has been appropriately erased and deg~us~ed. The erase cir~uit will be described in greater detail lbelow i~
co~ec~ion wi~ Pig. ~.
S:)nce ~e era~e s~uence has ended, isolatio~ swit~h 60 is closed9 and ~e microproce~sor 8~ by means of output li~e 106 ~elects record circuit 50 and disabtes playback circuit 52. With ~e reeord circ~it 50 enalbled, the standard ~: 30 composite video signal on line 54 is p~ocessed a~ connectedvia lines 58 and 62 and multiple~ circuit 56 to ~e elected read/write head.
-~ Qnce the storage seq~ence has e~ded, and an ~: . instructio~ for retrieval ha~ been received lby the 3s microprocessor 80, ~e microprocessor, after se~ec~ing the .
~.2~ 9 desired track andl head, issues a command on line 106 to disable the record circuit 50 and to enable the playback circuit 52. The piayb~ck ei~cuie 52 receives the recorded - analog signal and reproduees ~e original composlte video signal.
In opgration ~e apparatus 10 comes up in the re~rieval mode when ~rlled on. An ~utomatic initialization seque~ce in disk dAve microproce~sor 38 oscurs which places ~e head stack a~sembly at tracks 000, ~e outermost 0 ~ack and gives an indic~ion to mic~opr~cessor 80 of the 000 ps:~sition on line 88. The main con~ol microproces~or 80 ~en takes co~ol ~F all aspects of ~e operation of the ~t including updating ~e display 98 with the current image number a~d monltori~g the keyboard 92 for ~perator input.
1S If one desires to view or record a di~erent image other than ~e one curre~tly bei~g viewed, ~e glumber is e~ltered through keybQard, calculatioDs are made wi~in main control m;croprocessor 80, a~d the appropriate direction and step signals are sent to the pro~essor 38 via lines 82 and 84 ~o move ~e head assembly 22 to ~e appropriate cylinder and traeks. In addition the microprocessor 80 selec~ the appropria~ read/w~ite head by mean~ of cont~ol line 86 and :~ ~nultiple~er S6.
While o~er track and ~age notation schemes can 2s be u~ilized by ~he apparatlls depending on the particular - application, the notatio~ standard used for ~he presentinvention is one i~ whi~h ~e outermost cylinder contain ~e lowest numbered tracks. S~ing at ~e top surface 13 and ~e outside track, dle surfa~es are numbered #0~ t2, and #3 (top to bottom) on ~he first cylindler, cylinder #0. l[he rst image, ima~e #0, is therefore on the topmost sur~aces 13 ~- of disk 12. It is very simple to dete~ine cylinder and sur~ace number for any given video image. One simply divides ~e number of the desired image by 4 (~e number of 33 surfaces). The quotient is ~e number of d~e cylinder, and ~ . .
:, .
the rem~inder i~ ~e sur~ace number. For example, to determine the l~ation of ~age ~1733, dividing 1733 by 4 gi~e~ a result o~ 433 wi~ a remainder of 1. Therefore, image 1733 is l~ated on ~ d~r #433~ surfa~e #1.
Re~rrin~ to Fig. 2, ~h~re is shown a block dia~ram for ~e record ci~cuit 50O The r~olrd circuit S0 includes a lumiIIance/chroma separator circuit 120, a lu~:ninance ~M
- modlllator 1229 a mixer 124, an enable switch 126~ a ~terodyne ~requency conver~er 128, a refere~ce o~illator 0 130, and a low pass fflter 144.
A st~da~d composite video ~ignal is connected to input ~4 of ~e ~cor~ ci~t 50. ~e composite video signal on ~put 54 is fed to lum~ee/chroma sep~rator 120 where, using convention~l separation ~ech~iques, ~e lumin~ce - 15 signal is separated and m~de ~vaii~le on liLle 132, ~e chroma signal i~ ~eparat~d a~d made available on line 134, and ~e video ~ync ~ sepa~a~d a~d made ~vailable OQ
line 136~ The h~nallce signal on line 132 is fed to ~e luminallce FM modulator 122 where it iB modulated in conventional ~as~ion, a~d the FM modulated luminance signal appea~, o~ 138.
l~e ~oma ~ignal on li~e 134 is csnnected to heterodyne freque~cy conv~r~er 128 wher~ ~e chroma sigD~l is beat wi~ a first re~e~ence ~requency on input 140 2s ~rom the refere~ce oscillator 130. Particula~ly, the re~re~ce frequenc~ is 4.268 MHz which, w~n heterodyned wi~h ~e 3.58 MHz ch~ma sign31 o~ line 1 3D" p~oduces sum ;: and di~feren~e f~uencies o~ output litle 142. 1~ low pæs : filter 144 elLminate~ ~e hi~h freque~cy produced by ~e sumof ~e reference frequency and the chroma signal and passes ~e low frequency di~er0nce signal to its output 146. l[~e signal on output line 146 from ~e low pass filter has a ~ii frequency of approxim~tely 688 KHz. The down-converted chroma signal on line 146 is then mixed with the F~l 3S modulated luminance signal on line 138 by mixer 124 to produce a compositc processed analog video signal on line 148. If the apparatus 10 is in the storage mode, the microprocessor 80 p~oduces a~ en~ble signal on line 106 which closes enalble switch 126 to connect the proce~sed a~alog video sigaal oa line 148 to the outpu~ 58 of the record circui~ 50. T~ p~ocessed analog video 5i~ C~ le 58 iS
the~ co~ec~ed ~hrough i~lation ~witch 60 s to tr~smission line ~2, to multiplexer 56, and ~ d~e selected he2d.
Turning t~ Fig. 3, ~here ~s shown a bl~ di~8~
- 10 of ~e playback cir~uit S2 which compri~es a disable switch 150, a high pass îiltcr 152, an amplifier clipper 154, a lum~a~ce FM demodulator 156, a dela~ line 158, a mixer 160, a low pass ~llter 162, an automatic gain con~ol 164, a re~ence oscillator circuit 166, and a heterodyne fhquency conYe~er 186.
The playbaclc circuit 52 receives thg a~alog video si~al from ~e ~ead O11 ~nput IjQC 72. If ~e retrieval mode ~as been selected by ~he microp~ocessor 80, disa~le switch 1 Sû is closed by a sigIIal 031 line 106 from the micr~proce~sor~ and ~e analog video sig~al o~ line 72 is co~nccted to line 170. ~18 ~Og SigI~al 011 li~e 170 haS ~e ~e frequency compo~itio~ as ~e si~al produced by ~e ~ecord cirG~it on line 58. The ~a}og video sig~al o~ line 170 i~ connectet to ~e high pa~s ~ilter 152 which separate~
~e high frequenGy component, which i~ ~e lumi~ance comLponent, and connects ~e luminance cornponent to line 172. The luminallce compone~t on line 172 is amplifled, and ~e peaks are clipped L~ c~ve~tio~al fa~hion by ampli~ler clipper 154. The output o~ e 174 is conneclted to dle luminance FM demodulator 156, and the luminance component of the original video ~ig~al is re60vered on line 176. The lu~nmance component îs then delayed for a predetermined arnount o~ time by a delay line 158, and ~e delayed ~uminance componen~ appears at line 178 which is 3s ~e input to mixer 160.
,~f~5q3~3 A~ the same time, the low pass filter 162 extracts ~he ch~oma compo~e~t from the processed analog video sig~al on line 170 and feeds ~e chroma component to ~e automa~ic gain control circui~ 164 via line 1~0. The au~oma~ic gain control adju~ts the gain of the chroma compone~ The c~roma com~nent on 1~ 182 at dle output of ~e a~t~ma~ g~ cont~ol ha~ a ch~teristic frequency of 688 ~Hz wi~ di~k ~itter ~rrors superimposed ~ereon.
The chroma component o~ e 182 is cosnected to up-co~verter modulator lgO which sums the fr~que~ he shroma signal (688 k~Hz with ji~e~ erro~ wi~ a refere~ce ~r~uency of 3.58 MHz on line 1843 the output olF ogsi~lator 1~6~ Oscillator 186 also produces a 3.58 P~Iz sign~l on its o~er output 188. The up co~ertgs mo~ula~or 190 produces 1~ a~ its outpu~ 192 the sum o~ ~e ~reque~cy on li~e 184 (3.58 ~Hz) and the chroma sig~al on l?~e 182 (6B8 ~IZ`J. The sum ~ig~a~ on line 192 ha~ a ~re~ue~y of 4.268 MHz and is connected to p~e loek lcop 194 where it is compared t~ the output of up-~conv~rter :modul~or 196 on line 198. The outp~ o~ the pbase loc~c IQOP on l~ 20~ con~ols ~e voltage controlled oscillator 202 to a ~equenGy of 6B8 klEIz which ~ppear~ at it~ output on li~e 204. The 688 kH2 output o~ line 204 is up~onver~d by the 358 MHz ~efernce frequency on ~ e 18~ by mean~ of up-conYerter modulator 196. The rewlting output on line 2~6 ha~ a relatively stabilized ~uency of 4.268 MHz which i~ con~e~ted t~ ~e fre~uency conve~er 168. The fre~ue~cy converter 168 up-con~erts ~e ch~oma ~ignal (688 kHz) by means of ~le reference fre~uellcy o~ line 206 (fl.268 MHz) to a signal on li~e 208 having a frequerlcy of 3.58 M~Iz. The up~onYerted chroma compoIlent on l~e 20R i~ coDnected to ~ mixer 160 w}lere it is combined with delayed lumina~ce compo~e~t on line 178 to reproduce the staIIdard video signal on line 74.
Turning to Fig. 4, ~ere is ~own a block diagram of ~he era~e circuit 100. The erase eircuit 100 include~ a flip-~ q~ 9 1~
flop 212, counter 214, alld decreasin~ current switch 216.
When ~e microprocessor 80 initiates an era~e sequence, it enables ~ rase ci~ui~ 1~0 by rneans of a~ erase command on input 102 which sets flip-f~op 212 produsing a logic "1"
s on il:s Q output 218. The logic "1" on line 218 enables counter 214 which begi~s coumting with each ~ucccssive index pulse o~ line 210. The in~e~ pulses on line 210 are produ ed by the microprocessor 8û each time ~e microprocessor 38 far t~he di~k drive determi~s that a single revolution of ~e disk ha$ occlllTed. ~e index pulses are ~ed from microprocessor 3$ to microprocessor 8~ by means Qf li~e 90, and ~ ~de~ pulses on li~ 90 a~ the~
passed by microprocessor 80 to ~e e~e c~it o~ line 210.
The count 214 sequentially puts a lo~ic "1" v~ ea~h of it~
ou~puts 220, 222~ 224, 226, ~28, 230, and 232. Wi~ each logic "1" an outpu~ 220-232 ~e curre~t swith 216 p~oduces a reverse d.c. current on its output 104 which is connected ~rough tran~is~ion line 62 and ~ultiplexer ~6 to ~Le selected head. When ~e first lin~ 220 is a logic " 1", ~e reve~ing cllITe~t switch 216 prodllce~ a ~gh d.c. current on ~: its output 104. Wi~ each successive lo~i~ "1" on lines 224, ~269 22~, and 230, the reversc cur~nt 3witc~ produces ::~ lower a~d lower d.c. ~e~t le~el~ at its output 104. Oncethe count has reached N wi~ a logic " ln o~ line 230, ~e 2~ reYerse curre~t switch produces ~he lowest cwre~t, and wi~
- ~he ncxt cou~ counter 214 produce~ a logic, "1" at its ~utpu$ 232 which r~sets flip-flop 212 and d;sables coullter ;: 214. ~ce tlhe colmter 214 ha~ counted ~ugh its sequence ~om 1 to N and ha~ been disabled, ~he erase sequence e~ds.
Alternatively, ~e reverse current switch 216 may be replaeed by a high frequency osoillator which produces a 12 MHz to 16 MHz o~tp~t at li~e 104. The oscillator is enabled until the counter 214 has cou~ted to N + 1. lhe erase sequence assures that the trac~ is totally erased of a prior 3s image and appropxiate1y degaussed so ~at storage on tha~
.
track will not be af~ected lby re~idual e~ects o~ ~e previous ~g~-.
Another im po~tant aspect of the present invention i5 ~he ability to compe~sate for time base errors in ~e S sto~ge and retIiçval of images ~at re~ult from ~he inevitable jitter in the speed of the spi~ ing mag~etic disks.
Particularly, wi~ refere~ce to Fig. 5, ~ere i~ ~hown a serv~
control circuit 250 compri~ing a phase l~k loop 252 and a voltage controlled o~cillator 2540 In accordaaace with conven~ional practice, the mic~oprocessor 38 o~ ~e di~k dnve 11 a ha~ stable oscillator which providles a timing re~ere~ce for the microprocesso~ to use ~ co~l~o~ g the speed of t~e spi~lile 16. The mic~processor 38 se~ds a co~ol signal on Ii~e 42 to motor amplifier 258 which in turn controls ~e speed of the moe~r 18. The speed of the spindle 16 is seDsed by meaas of ~h¢ encoder 20 alld sensor 44, a:~d ~e encoder ~ al is connected bac~ via Iine 46 to t~e mieropr~cessor 38 to p~vide adjustment of ~e speed of ~e motor accordingly In a~cordaDce wi~ ~e pres~ inveIltio~, line 46 is connected to ~he phase lock loop 252 through microprocessor 38 and mic~op~essor 80. ~e phase lock loop ~Lso receive~ ~e Yideo sy~c si~nal on li~ 256 from ~e reco~ c~i~ 50. The phase lo~k loop c~mp~ ~e speed of 2s the ~otor represented by ~h~ enc~der si~ o~ line 46 to ~e - video sync ~igIIal on line 256 ~Dd prod~ce~ a dif~erence ~: signsl Oll tin~ ~60 ~he diff~r~e sig~al on line 260 ~hen` :~ serve~ t~ c~n~ol the voltage co~t~olted os~illator 254 which : ~ produces a timing refet~ce o~ i~s o~lqpu~ ~62. Th~ ~o~tage controlled oscillator 254 thereby replaces the stable oscillator previously described which p~ovided ~he timing to - ~ ~e microprocessor 38. Conseque~tly, the seno-control cireuit 250 co~trols the speed of the motor 18 in synehronization wi~ ~he video sy~c sign~l, While the servo-control circuit 250 cannot eliminate jitter from ~e speed of , ,,'''' ;
.~s~35g3 1~
dle disks, it does assure ~at, iZl a gros~ scDse at least~ ~e disks are r~tating once for ea~h complete video ~age.
Turning to Fi8. ~, and i~ co~ection wi~ another important aspect of ~e present inve~ion, there i~ shown a s reîerence frequency c;rcuit 270 which comprises the encoder 20, its sensor 44, a3~d a freque~cy co~verter 272.
Figure 6 also show~ ~e record cia~ 50 which receives ~e composite video si~nal at its iDpUt S4 a~d produces the processed analog video sig~lal at its outp~t 58 as previously o described. The processed analog ~ideo si~al at ou~ut S$ i$
connected ~rough isola~don ~tch 60 a~d multiple~cer S6 to one of ~e four ~eads 249 26, 28, a~d 30. The reference frequency circuit 270 sen~es ~e s~eed ~ ~e spiDdle 16 by means of encoder 20 and se~sor 44. ~he encoder signal on line 46, which is pr~portio~al in ~quell~y to ~e speed of ~e spindle7 is co~ne~ed to t3he f~equency comerter 27~ (as wel~ as to ~e micr~oc~s~or 38) where it i~ convertcd to a reference frequency of 4.26$ MHz o~ line 274 ~or the ~ominal rotational speed of ~e di~ks. The reference frequen~y on line 274 ~es in ~regue~cy in ~cordance wi~
~; ~e v~ations in ~e speed of t3he spindle lG. Therefore, whe~ ~he refePvnce freque~cy on line 274 i5 co~e ted to heterodylle frequency converter 128 of ~e lecor~ clrcuit S0, ~e rcslllti~g freque~cies ~rom ~e he~er~dy~e frcquency converter 128 asd ~re~ore from ~e mixer 1~4 Yary in ` ~ acco~dance wi~ ~he variation~ in ~e gpeed of ~he disk.
Co~equently, ~e frequen~ o~ ~e sign21 on lini: 58 at the output of ~e r~ord circllit .is ~lme ba~e compeDsatcd whe~ it as recorded onto dle dis~c. It should ~e appreciated ~at ~e reference sig~al could al50 be produced by providing a prerecorded re~rence sig~al on ~e magne~ic disk and that ~e term encoder as used herei~ refers ~ bo~ a separate encoder such as 20 and the disk itself wi~ a reference frequency recorded ~ereon.
~ ~35~39 In connection wi~h ~etrieval of t3he analog vid~o signal g~om ~e disk and wi~ reference to Fig 7, ~ere is provided a ~ference frequency circuit 2~ comprising ~e same elements as ~e reference ~reque~cy circuit 270.
s During retrieval7 ehe 4,268 ~Hz signal at ~e output 274 of ~e freQuency co~verte~ 272 i~ ~:onnec~ed t~ lhe ~re~,uency conve~ter 168 of ~e playb~k c~cui~ 52. Cons~uent~r, if jitter resul~s i~ ~e speed of ~e disks du~g re~rieval9 that ji~ter also appears is~ ~ ~equency OD~ e 274 so ~at when lo ~e chroma compone~t is being up-converted, the jitt~ at ~e input 72 to the playba~ ci~ui~ 52 is compe~s~ed by an offsetti~g jitter in t~e frequensy on li~e at 274.
Consequent1y, ~ ~ference frequency circuits 2'70 and 280 together provide c~mp~ete time base compel~sation ~or ~e - 15 video signa~s bo~ d~g storage and re~ieYal.
In ascordance wi~ another asp~ct of ~e prese~t e~ioll, it is pos~ible to provide time base compensa~ion : ~: both in connectio~ wi~ ~e frequency c~ver~ion~ of ~e ehroma ~ignal or at a~ earlier s~age in connt~ction widl gene~a~ng ~e 3.58 MlHz C~¢OMa SigDaL II1 ~a~ connection - and with refere~ce to Figure 8, there is shown a signal proce~sor 300 whic~ i~cludes a ma~rix c~rcuit 302, a red-` ~ minus-luminance modulator 304, a blue-minus-luminance modulator 306, a phase shif~ circui~ 308; and a combining - ~ 25 amplifier 310. 'rhe outputs 132 ~d 134 of the signal processor 300 are connected to the record circuit 50 at lines 132 and 134 as ~own in Fig. 2. Consgque:ntly, in ~he ~: modified versioIl of ~ record circ~ 50 includi~lg ~e signal processor 3ûO, ~e Y/C sepa~ator 120 may be elimina$ed.
C)~herwise, the lumi~ance sig~al OB ~ 132 and~ the ehroma signal on l~ne 134 ~re plocessed for recording ~ ~he same - fashion a~ previously de~cribed in coDnection wi~ record eireuit 50.
In connection with ~e signal processor 300, an 3s image 312 is recorded by a vide~ camera 314 in con~ention~l ~
~a~hion to produce a red ~;gnal on ~ine 3169 a ~re n signal on line 318, and blu~ signal on li~s 320~ Th¢ camer~ 3~4 also h~ an o~cillator whi~ producs~ a sync Sig~ on l;ne 136.
lhe red, green, and blue sig~als ~e connected to ma~rix cixcui~ 30~ whi~ produce~ a hlm~ce signal on lins 132, a red-millus-lusn~ e signal on line 322, ~d a blue-minus-l~in~e signal a~ e 324. ~ color compon~ s on ~ineS
322 ~d 324 a~ modulated wi~ a 3.58 ~Iz re~rence signal on li~e 326. Th~ 3.~8 ~A[Hz signal on li~e 326 is derived from ehe ~reque3lcy ~o~verter 272 shown in Fig. 6 and 7 aIId varies i:~ ~cco~ance with any v~iation i~ the spee~ of ~e disk drlve. The 3.58 MHz re~erence sig~al on li~e 32,6 i~
cosnected to ~d-mi~us~luminance modulator 304 alld to blue-millus-lumin~ce modu31ator 3~6 ~ough 90 phase lS ~hift ~i~uit 308. The output 328 and 330 of ~he red-minus-lumi~aace modutator 304 a~d ~e blue-minus-lumi~ance modulator 306 re~pecti~e~y are co~ected to combining amp~ifier 310 w~i~ comb~es ~e two color ~omponent~ int~
~e 3.58 MH2 chroma sig~l o~ e 134.
Because the r~ere~e signal on line 326 varies in accor~ce wi~ the jit~er of ~e dislc drive, ~e chroma ~ig~al ~: is compensated at ~he ~ne it is modul~ted to 3.58 ~z andagain when it is down~o~ve~ted to 688 ~ in the conYerter 128 (~ig. 2). It should also be a~preciated ~hat ~e 113minance 2s sign~ on lil~e 132 ~d ~he ch~oma ~ignal on l~e 134 could be recorded on ~o separa~e ~acks on ~he disks ~or later - ~pa~ate retrieval a~d p~ocessi~g.
In ac ord~e wi~ a~oth~r aspect of the prese~t ~ventio~, it m~y be d~sirable in co~ection wi~ p~o~iding very high quali~y color pictures to record ~e red sig~al, gr~e~ signal, and blue sig~al ea~h on a separate ~ack on the magne~ic disks. With refere~ce to Figo 9~ ~e record circllit 50 of ~ig. 2 is replaced by a modified record circuit 360 which includes FM modulasors 362, 364, and 366 wi~h 3s output~ 368, 370, and 372 respec~ively. The video camera -314 generates separate red sig~al 3169 gr~en signal~ 318, and blue ~ignal 320. Each ~ eparately FM modulated by modlllator3 362, 364, and 366 which are co~ve~tiolla~ i~
nature. The output~ of ~e FM rnodulators are co~nected di~ctly to recordia~lg head~ 24, 26, al~d 28, respectively, through appropriate i~olation switche~ ~uch as ~8.
Consequently, e~h of the recording heads 24, 26 and 28 separa~ely ~cord~ the red, green~ or blue ~ignal o~ ~ree sep2~ate ~k3 of ~e disks.
With ~e modi~1ed ~co~l cir~uit 360 sho~ in Pig.
9, it is ~ecessary upo~ retrieval to modify ~he playback circuit to receive ~d process the individual recorded ~hree color compone~ts. Tu~ng to Fig. 10, there is sho~ an al~e~native playback circuit 380 which can be used where ea~h co~or component, red, gre~, ~d blue, i5 recordPd on a~ individual t~ck. The pl~y~ack ci~ui~ 380 comp~ises F M
demodulator~ 382, 384, a~d 386, mat~ix circuit 388,red-minus-lumi~ance modulat0r 390, blue-lninus-lumi~ance modulator 392, phase shiR c~uit 394, combi~ng amplifier 396, and combini~g arnplifier 398.
lC)uring retrieval, dle analog sig~ r~m heads ~4, 2~ d 28 are receiYed on i~t line 400 for r~d, 4û2 for green, ~nd 404 for blue. The color compo~ent signals are demodulate~ by ~ demo~ulators 382, 3~4, and 386, and ~e 2s demodul~ed sig~als are connected to ~e ma~ Ci~Uit 388.
The matri~ circuit 399 arithmetically combine~ the ~' demodula~ed color components to produce a luminance si~al o~ line 406, a~d red~minus-lum~ce signal~ o~ line 408, a~d a blue-m~nus-luminance signal on line 410. The two color comp~nent ~ignal on line 408 and 410 are modula~d by mo~ulat~r~ 3~0 and 392 to ~e ~equency oi 3.58 MHz widl ea~h modulat~d color componeat bein8 90 out of pbase from the o~er. The resulti~g modu}ated color compon~nts are combined by combining amplifier 396 to - ~ 3s produce a single chroma 5i~1al OII line 412. 17he chroma " .:
,''' : .~
signal on line 412 a~d the lumi~ance sig~al on line 406 are the~ combined by combining amplifier 39g to produce a sta~da~ composite vid&o signal on line 74 which is ~en, wi~ reîerence ~o Fi~ure 1, coanected to monitor 76 and to s au~iliary ou~pu~ 78.
ln acco~an~e wi~ ano~her aspect Qf ~e present inve~tion, it may upon occasion be desi~able to record certain information digitally concerning ~e ~ature of ~he image such as t~me, dlate, lens se~ g, or other pertinerl~
i~ormation at the time thc image i~ ~ecor~ed on the disk. II1 ~at regard and with re~erence to Fig. 11, there is shown ar~
au~iliary digital memoly 420 having a memory a~ay 425, w~ich is divided into N n~mb0r of memory banks 426 with each banl~ h~ g M ~umber of w~rds 428. The 'ba~ are selected by a bi~ary cou~ter 430, a~d ~e wor~is an~ selected by a bin~ry counter 4320 The au~iliary memory 420 has a data inpu~ 4229 a ~ata o~tput 424, a sloc~c input 350, and address lines ~2, 84, a~d 86. The au~ciliary memory 420 is addressed by ~e microp~ocessor $0 so that each bank cor}espo~ds to a single circular trac~ on l~e disks. The Sigllal5 on line 82 and 84 by mea~s o~ a b~ cou~ter 430 select a group of four banks co~esponding to the radial position of ~e head assembly ~, and ~e sig~al on ~ine 86 abas~ wi~in ~e elected g~up which co~responds to 2~ o~e ~P the ~our heads which has been selected ~or storage ~r retri@val. - -A~ ~e disk~ rotate, ~e e~coder 20, ~e sensor 44, and ~he frequency converter 272 produce a synch~onized cl~k oll line 350. The cloc~ on line 3S0 con~ols ~e b~nary counter 432 which continuously colmts from 1 to M number of wor~ ea~h bank. Consequently, wi~ ~he ban~Ls seleeted by ~he address fr~m ~2 processor 80, the au~ilia~y memory 420 cycles ~om word 1 to word M and repeats in ~ synchro~i~atio~ with the disk making one full revollltion.
;.
There~ore, it c~ be said ~at ~e words L~ each memory bank "walls ~long" wi~ ~ i~orm~ti~ on ~e disk~.
C)ne pa~icularly advan~ageous purpose of the ~u~cilia~y memory 420 is to store ~i~ae base e~ror~ which s ~cur during storage of ~e images o~ the disks. T~g to Fig. 12, there is showII a ~eheme ~or using the au~iliary mPmory 420 ~or ~a~ purpose. A tim e ba~e c~ction circuit soo compnses a compa~LbDr 502~ a stablc ~me b2~e oscillat~r 504, a ~witch 506, ~ m~g cirwit 508, a~d t~e base '!' 10 co~rector 510. Particularly, d~e compara~ receive~ at its input 46 the sig~al from t:he erL~oder 20 ~d ~ensor 44 ~d receives the output ~ ~e s~ble oscillator 405 at i~put 512.
The eompara~or produçe~ a digital error signal on ~e S14 which is proportional to the variation ~tween ~he ~lpeed of S ~e ~pindle 16 (line 46~ and ~he fr~uency of the stabl~ time base oscillat~r 504 (line 51~).
During the storage mode) switch 506 is co~nected to input 422 of ~e auxiliary memory 420, and ~h~ di~tized errvr ~i~nal on line S14 rel~t~B to the jitte~ is stored i~ the memory 420 as the dis~ make~ on one revolution. Upon eompletion of ~e storage mod~, s~ch ~ is to~led to line 516~ a~d ~e all~iliary memory 420 begi~s reading out ~e digi~zed error i~ormatio~ onto its ~utput 424. Duri~g the retrieval mode, ~e comparator co~tinues to produee digital 2s ~me base error i~formatiQ~ on Imc 514 (~d ~herefo~ lin~
516~ w~ich i~ summed wi~h ~e time ba~e error is~omlation Pf~m ~e ~wciliary memory 42~ by ~umming c~ui~ 508. By cornp~nng the tlme ba~e erro~ in~ormation stored in auxiliary memory 420 dunng ~e storage mode to ehe time base error information produced during ~e retrieval mode, a time base correctio~ signal is produced by ~e summing ci~r~uit 508 o~ line 518. The tim~ base correctio~l signal o~
line 518 is connected to ~he time base corrector ci~cuit input S10 where it controls dle delay of ~e signal on output 74 of 35~ j9 ~e playback circuit 52 tQ produce a time base corrector video output si&nal on line 520.
Fu~er i~ ~ccordance with ~he present i~ve~ion and wi~h re~erence to lE;ig. 13, ~ere is provided a single S frame memo~y circuit 60~ whi~ cooperat~s wi~ the s~orage and retrieval apparatus of ~e present L~vention to allow for tra~sitioIl betwee~ images during playbaclc ~uch as dissolving, ov rlay, fade, and other ~pecial ef~ects.
P~icularly, ~e frame memo~ c~it compris$~ a digital 0 memory ~02, an~log-t~digital (A/D) co~verter 604, digital-to-analog converter (DlA) 606, a~d ~er 608. I~ o~der to provide the special ef~ec~s of the îrame memory ~Oû, the p~oces~or 80 f~rst instmct~ the fr~e memory 602 via li~e 614 to store the image that is lbeing ~trieved ~ri~g ~he ~etAeval mode. That is accomplished by fe~ding the video signal on line 74 f~om ~e playb~ck ci~uit S2 to the A/D
co~verter 604 via input 610. The ~ con-~erter 604 digitizes ~he video signal form ~he pl~ack cir~uit and feeds the digitized image to ~he frame memory 6û2 via line 612.
t)nce the digital image ha~ be~n stored in ~rame memory 602, the main procsssor 80 call~ for ~ llext image to be retrieved ~rom the storage medium 11 as has been previously desc~bed. At the s~e timel t~e microprocessor B0 : ~ commands ~e f~e memo~y 602 via line ~14 to OUtpllt the 2~ st~d image in digital ~rm ontQ its outp~l: 616. Ihe image ~epresen~ed by ~e signal on line 616 is convelted from digi~l to analog by D/A con~rter 6~6, a~d aII analog video signal result~ on li~e 618. ~e playback circuit ~2 produces a composite video s ~ OII it~ output 74. The sig~al on line 61B represents the fir~t image, and ~he sig~al on line 74 presellts ~e next image. The two image~ ~e~, in allccordance wi~ c~n rentional mixing ~echniques ca~ied out by a mL~er circuit 608, carl be dissolved9 overl~d, faded one to the :~ other, or merged to provide a composite output on line 62G.
.:
~ ~ .
5~9 l~e pre~ t i~ve~ltion may al~o i~hlde additional - ~eaturgs which eDha~ee it~ use~ gs~. ~or e~ample, the microproce~or ~0 may b~ cont~lled by a remote control 622 much in ~e ~as~ion of the remote cs~trol of a s co~ven~ional slide projector. The micl~rocessor may also select image~ er ~e Coll~ol o a audio t~pe device ~24 wbicla can provide a time sequencc o~ image retrieval all in rela~onsbip to ~e audio being prese~ted.
~RETRIlEVAL APPAlE~ATUS
E~ackgr~und of the In~rent~o~
This invention r~lates gcnerally to all ~age storage and retrieval apparatus and more pa~icularly relates to a~
S apparatus ~or storing m~re than 2000 still color video images on a storage medium, such as a magnetic disk, a~d r~trieving ~e images for display and lpr~cessillg.
~rre~t digital record~ng with its atte~da~t cnst has prevented high density storage of ~till color video images ~d high speed random acce3s wil:h ~rasability. The problem VVAth stora~e of color images i~ digital form is the tremendous ~nou~t of storage ca~ity requi~ed, typically 500+ ~ilobyte~ of storage pet ~age. (~tical discs9 while pro~iding high deDsity storage, a~ ot erasable at r~ able cos~.
I~ video recordi~g, ~he lulminance and eolor component~, of a video signal a~ ei~er recorded toge~er on a si~gle magnetic tra~k or are recorded separa~ely on two or more tracks. Predictably, ther~ are adval~tages alld drawbacks to each app~oach. Sil~gle track recording requires less recording media spa~e and ~ereby illcreases the llumber of images ~a~ caII be placed on a giveII magnetic media. Recording the video sign~l components on two or more tracks usually improves ~e image quality, but severely ~;
complicates ~e appara~s and reduces ~e storage capa~ity of a given media by one half or more.
Early Yideo disk recorders for ~plays were pio~eered by ~mpex and othe~s in the 1960's and used bo~
S rigid and floppy disk mag~etic media for storage of images.
~ese systems typically used a narrow band FM recording of d~e modulated analog signal and s~ored a single video frame with eac~ rotation of ~e disk. AI~Lough p~oviding ~he user with some excellent advantages, such as a high image storage density and quick access times, these units we~e suff~cie~ltly expe~sive to limit their use to high priced systems iII
broadcasting and medical ima~g. Fur~er, ~ese early uI~its we~e limited by ~e irregularities in and o~ the surface o~ the recording media. This led researchers at that timc to discover t~t frequency modulation, Yersus amplitllde modulation, was a more ef~ective way to e~ode ~e video signal. These systems also required a high head-te)-media relative velocity of 1,00~ to 2,000 i~ches per second~ due to head gap lengths, short video wave lengths required, alld high signal-to-noise requirements. In ~e floppy disk ~ersions of ~ese systems where the heads were in co~sta~t con~t w;th ~e media, the u~eful li~ ~as limited, usually less ~ 0 hou~. Irl the rigid disk ~ersio~s~ useful li~e migh~ approa~h 2,500 hours prolonged by the air space between ~he heads and media, but limited due to ~ u~ach~ring impe~feotions, wear from occasional head-to-media contact, a~d o~er ~actors.
Image storage technology today is c~aractetized by ~e mo~rement from ~llm and slides to videotape a~d video disk to digitized images in digital mass storage. This recent tech~ology has taken two directions: ~e ~Irst is a irend toward digita~ ~tideo disk or CD-ROM (Compact Disk - Read Only Memory); the second, a trend toward WORM (Write Once, Read Ma~y) storage. Both of these tech~ologi~s have signifi1cant drawbacks in ~at ~ey are not erasable and suffer ~om high media ~torage capacity reqllirements. The market today has seen ~e i~troduction of lower cost, high quality digitizetl storage of ima~es. However, ~e problem as p~eviollsly l~oted wi~ storage ~ color ~mages in digital ~orm is ~at it takes a tremendous arnount of info~mation storage c~acity9 typically soo~ kilobytes of sto~age per Image.
The need for a compact, ine3cpe~ive, to~ly self-contained image recorder, ~torage unit, playback and moni~ori~g dev;ce ~or storLng large ~umbe rs ~f hi~ ~uality lo s~ill color images is apparent in ~everal fields: secunty ~d sur~eillance, entry access system~ computer penph~rals, training devices, and pictu~e archiving ~y~tems~ d as a replacement for color slide p~jecto~, to name oI~y a few.
lS Summary of the In~vention It is ~erefore an object o~ ~e preseslt inve~tion to provide an ~mage storage and re~ie~al apparatus capable of storing a large ~umber of high quality 5till color images a~d retrievi~g those image~ rapidly for di~play and fur~er processing.
It i~ fur~er asl obj~ct of ~e pre~ent invention eO
provide mean~ ~or corrgcting ~omalies ~ ~e time base of the video signal~ whiçh anomalies l~sult ~rom storage and/or ~triev~l of ~e sdll color images.
It is likewi~e an object of the prese~t inventioll to :- p~ovide an image storage and retlieval apparab~s having an au~iliary memory for storing corrc~ponding data such as . time of day, da~e, c~era lens i~ormatio~, time base er~or information, etc., correspo~ding to each of ~e stored still color images.
It is also a:~ object of ~he prese~t invention to provide mea~ for huldi~g a first image rebrieved ~rom the : ~ storage medium dunn~ ~e subseque~t retricval of a second image from the storage medium so ~at ~e two images may be ~issolved, blended, overlaid, or ompared in other fashions.
l[t is likewise a:ll object of ~e prese~lt inven~ion to provide an ~age storage and re~ieval appa~atus in which the s~orag~ medium is erasable so ~at image~ may be s~ored or ~placed by o~er i~nag¢s as desi re~.
III order to a~tain ~he foregoing objec~iv s, ~e ~age storage and retrieval apparatus stores aIld retrieves a ~umber of still images from a storage medium. The apparatus comprises a ~to~lge medium7 prefer~bly a high speed magnetic hard disk, a servo~coII~olled motor îor rotating ~e disk at a presekcted speed, read/~te !heads and circuitry ~or selectively positio~g ~e read/~te: he~d~ to select aIly olle of a nu~nber of circul~r tracks on ~e ~torage disk. A secord ci~cuit proceses a ~onventio~al composite video sig~al and produce~ an analog sig~al which ls connected directly to dle read/write hea~ recorded on one tracl~ of th~ ~torage dis~. A play~k c~rcuit re~ieves ~e analog signal ~om one of ~e selected tlacks of ~e video - 20 disk v;a ~e ~eadJwnte head and ~eco~stitut~s ~e composite ~: ~ video signal. Control means, a microprocessor, respvnds to ~: ext r~ structio~s, ~ucb as ~ keyboard, a computer port ir~put, or similar con~ol input, selects ~e particular ci~cular ~rack on the storage disk, and selects ~e storage tnode or re~rieval mode fo~ ~e ~pparat~
^ ~ The record circ~ of the pre$en~ inveIItion separates a co~ventional composite video ~ignal into i~s lumi~ance alld chroma compo~ent~, dowII-converts the chroma comporlent by a reference frequency, preferably about 4 MlHz, freque~cy modulates the luminance colmponent, ~ecombine~ ~e modulated lumina~ce and down-converted chroma compunents to produce aIl analog signai for storage on ~e disk via o~e of ~e readJwnte ~eads. The ;;: playback circuit upon receivi~g ~e analog sig~al from the read/write head separates the luminance and chroma '~
~ ~35~,9 compone~ts7 de3nodulates and delay~ the luminance componellt, up~o~verts ~e chroma component lback to its origi~al frequency in a conventional video sig~al and subsequelltly recom~ine3 ~e ~omponen~s to reco~er ~e S composite video signal ~or dislslay on a standard video monitor.
In order to assure cle~ re-record3ng of substitute images7 an e~9e circuit is proYided whi~h may be either a high i~reque~cy oscillator or a dccreasi~g reversing d.c.
current switch. The micr~processor for ~e app~ratus upon receivirlg a command to record an image9 filrst i~itiates an erase sequence which9 in one emotiment, co~ects thc high ~requency oscillator to ~e ~eadlwrite head to rec:ord the erase freque~cy for 2 predetermi~ed time. In another embodiment, tlhe microproce~sor connects a decreasing reverse d.c. GUrreD~ switclbi to ~e read/write head so t~t each pass of ~he read/wnte head over ~e circular track has a decreasing ~nt density. Co~equently9 ~e track is totally degaus~ed prior ~o reco~d~ the ~e~t ~till color image on the particularly selected ~ircula~ trac~.
The image sto~ge and retrieval apparatus of the prese~t in~entio~ assures high quality image storage and re~ieval by compensati~g for jitter ~at irlevitably occurs in ~h~ speed of ~e spinning ~torage disk~ I~ o~e a~pect of ~e 2S invention, an en~oder connected to ~e spin~le of ~e~ seorage di~ produces a rota~ion sig~al which, during dle storage mod~, is cons~tly compared in a pha~e lock loop to ~e videv sync signal from ~e incom~g eoDQpo~ite ~ideo signal ~n order to control ~e seno-motor which drives ~c storage disk. In a~o~er as~ect o~ ~e pre~ent in~re~tion, ~e ou,hput of ~e encoder produces ~e refer~nce frequency which is used to bo~ dvw~o~vert ~e c~oma signal in th~ ~cor~ circuit and up~onvert ~e chroma signal in ~e playback circuit. In a~o~er aspect of ~e p~sent inyention, the encoder produces a rcference signal which is ul~ed in a signal processor to 3~ )9 modwlate the primary red, green, and blue si~als prior to pr~ducin~ ~e conventional composite video signal wi~ the lum~aance znd ch~ma composent$.
~n another a~pect of the present inve~ion, an S a~iliary addressable digital naemory is prwided which h~ a number of data ba~k~ each correspo~d~ng to a single 3~cordl~g track o~ ~e ~torage disk and a ~umber of words wi~in each bank. The au~ili~y memory is addressed by ~e miGroproCeSSor SimUl~aneQUSly YVith addr~ssing the sto~$e lo disk, alld ~he e~coder produce~ a word count wi~n each memrry bank so ~at as the storage dlisk spi~s, the digital memory under cont~ol of ~e e~coder steps along ~ ~e storage disk. Therefore, correspondil~g data can be stored in the auxiliary memory, and upon ~etrieval of ~e Istill image fr~m ~e s~orage disk, ~e auxilia~y memory, steppiag ~long with ~e storage disk, can output ~e auxiliary i~olmation to a display or to be used for ~ur~er con~ol.
Also, in accordance with the same auxiliary memory, ~e ~fonn~tio~ stored can be in~ormation relating to the jitter experienced by the storage disk during the storage mode. Upo~ retrieva~ Ihat s~oled e~T~r in~ormati~n ca~ be re~rievedl a~d u~ed to compensate ~e rgcoYered analog signal and re~Ye the e~ects of ~e ~ime base errors ~at occllr du~ng storage and re~iev~.
In ano~her aspect of the pre~nt inventio~9 a digital frame memory is provided to hold a single f~e or image while the ne~tt image is retrieved from ~e storage disk so that the two images c~ be mi~ed widl eaGh o~e~ to p~duce special e~fects such as dissolving, overlayin~, ble~ding, or ~e iike.
Other o~ects and adva~atage~ of the present Lnvention will become apparent upon reading ~e following detailed descripdon ar~d upon re~er~a~e to ~e drawings.
6~3 Brief Descriptlosl o~ the Dra~ng~
lE~igure 1 is a bl~k diagr~ showing the ~mag storage and r~ieval apparatu~ ~ the present iIlventio~;
Fig. 2 i~ a bl~k diagr~ of ~he ~co~d ci~ of ~e present invention;
Fig. 3 is a block dia~dlm of ~e pla~ack circuit oî
~e p~ese~t i~ention;
Fig. 4 is a block diagram o~F ~e e~e ci~uit of ~e pre~en~ inveD~ion;
Fig. S is a blocl~ diagraln of ~e servo~on~ol Ci~llit of the present i2lve~ion;
lFig. 6 is a block diagram show~g one me~s of àme base compensation ~uring ~e s~rage mode;
Fig. 7 is a bl~ diagram ~howi~g o~e ~aeans of t~e ba~e compensa~on d~g the retrieval mode;
Flg. B is a block diagIam showing ano~her mea~s of ~ne base compensation during ~e storage mode;
Fig. 9 is a block diagr~ showing a modified record circuit;
Fig. 10 is a block diagram showing a modified pl~yback circuit;
Fig. 11 i~ a block diagram showing an addres~able digital au~tilia~y memory which "wallcs along" wi~ the ~age di~k;
Fig.12 i~ a block diag~ showing one mea~s of using ~e auxili~y memory to provide time base co~rection during dle retIieYal modey a~d Fig. 13 is a block diagram showi~g a digi~al single image di~ital memory for mixi~g two images during t~e re~ieval mode.
Detailed De~cription of ~he Ill~e~ion While ~e inventio~ wiil be described ~ connec~ion with preferred embodime~t, it will lbe under~tood that I do 3s not intend to limit ~e invention to ~at embodiment. On the ~ A 2 ~3 5 5 ~ 9 con~ry, I intend to eover all alternatives, modificatiorls, and equivalent~ as m~y b~ included within the spin~ and scope of the invention as de~ d by ~e ~ppended cl~s.
Turning to Pi~use 1, ~here is ~hown the image s storage and retrieval appa~tus 10 s3f t!he present invention.
~e apparatu~ include~ a rnain storage med;um or disk drive 11. The sto~age medi~ cludes a set of mag~etic dis~s 12 a~d 14 mounted Oll a spindle 16 w}lich spindle i~ rota~ed by a servo-controlled mo~or 18 at a preselected speed. ~n 0 e~od~r 20 is a~so attached to ~d rota~es with the spindle 16.
The storage medium ll al~o i~cludc~ a readlwri$e head a~semlbly 22 which includes a re~d/write heacl 24 ~at is mounted adjace~t to d~e top sur~ace 13 oî ~e disk 12, a readJ~te head 26 wlhich i~ mou;~ted adjacen~ to the boKom surPace 15 of the disk 12, a read write head 28 whieh is mou~ed adjacent ~o ~e top surface 17 of ~e disk 14, and a .~ read/write head 30 which i8 mouIlted adiacent to ~e b~ttom surface 19 of ~e disk 140 The rçad/wnte head assembly 22 simultaneously move~ ~e heads 24, 26, 28, and 30 radially ; ~ 20 across ~e disks 12 ~d 14 u~der co~trol of a head drive means 32.
he disk~ 12 ~d 14 are divided in~o a number of collce:utric tracks on e~ch of ~he four sur~es, such as tracks 34 and 36 on the top sur~ace 13 of di~k 12 and radially :: 25 aligned co~pondi~g tracks 35 a~d 37 on the top surface 17 of disk 14. ~e tracks 34 and 35 toge~her (along widl two similar radially aligned tIac~ o~ the bot~om sul~aces 15 ~nd - 19 of dislcs 12 and 14) define a~ imaginary cyli~der. In order to record (write~ i~formatio~ onto ~e traclcs 34 ~d 35 in the storage mode or to 3ense (read) information recorded on ~acks 34 and 35 in ~e retrieval mode, ~e head drive means 32 positio~ ~e head assembly 22 so ~a~ d~e heads 24 and 28 are located above tracks 34 and 35 respectively. By moving ~e read/write heads 24, 26, 28, and ~: 35 30 radially toge~her to a particular selected cylinder and by :
selecting one of the four heads as will be descnbed in greater detaal, a palticular t~c~c on any one of ~e four disk surfaces can be selected for recording or for playback.
The storage snedium 11 also has a disk drive S micropr~essor 38, wh~ch by means of output 40, contsols the he~d drive 32 a~d ~erefore selects the desi~ed tracks by positio~ing readlwrite heads 24, 26, '28, and 3(). The output sig~al on line 42 controls dle speed of the motor 18~ A
sensor 44 is mounted adj~cent the encoder disk 20 and sen~es dle rotativn of ~e spindle and pr~vides ~at in~ormation to dle microprocessor 38 by means of input line 46 so that the mic~oprocessor 38, via output 42~ can control ~e æpeed of ~e spindle as required.
The storage medium 11 including the disks 12 ~nd 14, motor lB, encode~ 20, head assembly Z2, head dAve 32, and ~e microprocess~, 38 ar~ pre~erably implemented by use of a La Pine Ti~ 20 Disk Drive available from La Pine Technology, ~ilpitas~ California Su~ a disk drive, is typically used ;n connection with providing additional storage for digital information Ior persoD~l computers.
1~ addition to ~e disk drive 11, the Pv~rieval and storage apparatus of the present invention comprises a record circuit 50, a playback circuit 52, and con~o~ means ~: 80. The ~eco~d cir~uit S0 receives a conYentional composite video sig~al at its i~put 54, processes ~at signalS and transmits ~e processed video signal to head multiplexing cir~uit 56 via record ou~put 58, isolatio~ switc:h 6n, a~d t~ansmission line 62. 'llh~ p~cessed video signal on line 58 is an a~alog s~g~al which is co~ected ~rough the head multiplex circui~ 56 to any one of the four output lines 64, 66, 68, and 70 which are connected respectively to read/wri~e heads 24, 26, 28, and 30 for storing the analog sign~l onto one of the four selected tracks on one of the two disks.
1~
Alterna~ively, in the retrieval mode, the information se~sed by o~e of ~e four readl~te heads 24, ~6, 28, a~d 30 is co~nected via ~e head multiplex circuit 56 to the t~nsmission line 62, through isolation switch 6n, and s to illput 72 of the playback cir~uit 52. The playback circuit 52 receives ~e analog signal on line 72 and reconstitutes the composite video sigllal on its output 7~ ~vhic~ is connected to - moni~or 76 and t:o awciliary output 7~. The record circuit 50 and playback cir~uit 52 will be Idescribed in greatcr detail below ~ connee~on with Figs. 2 and 3.
The image storage and reb~eval appa~tus lû is operated under ~e control of co~trol means 80 which is a microprocessor. The micropro~essor 8û ~eives c:ommands f~om any appropriat~ input means such as keyboard 92 or RS-232 computer port ~4. l'he RS-232 port 94 l~fers to a s~ndard port with de~ned pin connec~ions, signal levels, and the like promulgated by the Electronics Industries Association of Washingto~; D.C., denoted as RS-232-C
(August 1969~ a~d en~itled "Interf~ce Betwee~ Data Terminal Equipment a~d Data CommuDications Equipment Employing Serial Bi~ary Data Interc}lange". The microprocessor also provides an indication on line 96 of the particular image being stored or retrieved w~ich status is the~ displayed o~ display 98~ Ths microprocessor 80 is 2s pre~errably a Zilog Z8 manufactured by Zilog, Inc. of Cupertino, Califon~ia.
The microprocessor 80 by means of` output 84 instructs ~e disk driYe microprocessor 3B to move ~e head assembly 22 radially in or out, and ~e output on li~e 82 tells microprocessor 38 how far the head assembly 22 should be moved radially. Upo~ receipt of ~e direction and step instructions on lines 84 and 82, the micr~processor 38 instructs head drive 32 to move the head æsembly 22 so that the read/write heads 24, 26, 28, and 30 are adjacent a .~ ,... .
.3 p~cular seles:ted cylinder and the four circular traeks on the disks ~at define ~at oyl~nder.
C)nce the microprocessor 30 has caused the microprocessor 38 to select a particular cyli~der, the s microprocessor 80 selec~s one ~f the read/write heads 24, 26, 28, or 30 by mea~s oï a multiple~ ins~ctio~ OD. line 86 which controls multiple~ ei~suit 56 and sallses multiple~
circuit 56 to select o~e of i~ signal lines 64, 66, 68, and 70.
The microp~ocessor 8Q also ~e~ect3 the storage 0 mode or the retrieva3i mode ~r ~e apparatu~ 10. If ~e storage mode is selected~ the microp~essor 80 first selects the track and headl and the~ ccordance with ano~er aspect of the present inve~gio~, ~he microprocessor 80 via ou~:put line 102 activates e~e circuit 100. lhe erase circuit 100 co~ec~s an erase signal to transmis~io~ e 62 via erase output 10~ and ~e~ to ~e seiectgd head ~ ~e disk drive via ~e multiplexer 56. While ~e erase s~que~ce i~ enabled, ~e microproce~sor also is~es a command on OlltpUt 108 to open i~olatinn switch 60 which a~su~es ~hat ~e erase signal on li~e 104 is not connected back into ~e r¢co~d circuit 50 or the . playback circuit S2. The erase circuit is selected for predetermined amou~t of time to assure ~a~ ~he sel~c~ed ~rack has been appropriately erased and deg~us~ed. The erase cir~uit will be described in greater detail lbelow i~
co~ec~ion wi~ Pig. ~.
S:)nce ~e era~e s~uence has ended, isolatio~ swit~h 60 is closed9 and ~e microproce~sor 8~ by means of output li~e 106 ~elects record circuit 50 and disabtes playback circuit 52. With ~e reeord circ~it 50 enalbled, the standard ~: 30 composite video signal on line 54 is p~ocessed a~ connectedvia lines 58 and 62 and multiple~ circuit 56 to ~e elected read/write head.
-~ Qnce the storage seq~ence has e~ded, and an ~: . instructio~ for retrieval ha~ been received lby the 3s microprocessor 80, ~e microprocessor, after se~ec~ing the .
~.2~ 9 desired track andl head, issues a command on line 106 to disable the record circuit 50 and to enable the playback circuit 52. The piayb~ck ei~cuie 52 receives the recorded - analog signal and reproduees ~e original composlte video signal.
In opgration ~e apparatus 10 comes up in the re~rieval mode when ~rlled on. An ~utomatic initialization seque~ce in disk dAve microproce~sor 38 oscurs which places ~e head stack a~sembly at tracks 000, ~e outermost 0 ~ack and gives an indic~ion to mic~opr~cessor 80 of the 000 ps:~sition on line 88. The main con~ol microproces~or 80 ~en takes co~ol ~F all aspects of ~e operation of the ~t including updating ~e display 98 with the current image number a~d monltori~g the keyboard 92 for ~perator input.
1S If one desires to view or record a di~erent image other than ~e one curre~tly bei~g viewed, ~e glumber is e~ltered through keybQard, calculatioDs are made wi~in main control m;croprocessor 80, a~d the appropriate direction and step signals are sent to the pro~essor 38 via lines 82 and 84 ~o move ~e head assembly 22 to ~e appropriate cylinder and traeks. In addition the microprocessor 80 selec~ the appropria~ read/w~ite head by mean~ of cont~ol line 86 and :~ ~nultiple~er S6.
While o~er track and ~age notation schemes can 2s be u~ilized by ~he apparatlls depending on the particular - application, the notatio~ standard used for ~he presentinvention is one i~ whi~h ~e outermost cylinder contain ~e lowest numbered tracks. S~ing at ~e top surface 13 and ~e outside track, dle surfa~es are numbered #0~ t2, and #3 (top to bottom) on ~he first cylindler, cylinder #0. l[he rst image, ima~e #0, is therefore on the topmost sur~aces 13 ~- of disk 12. It is very simple to dete~ine cylinder and sur~ace number for any given video image. One simply divides ~e number of the desired image by 4 (~e number of 33 surfaces). The quotient is ~e number of d~e cylinder, and ~ . .
:, .
the rem~inder i~ ~e sur~ace number. For example, to determine the l~ation of ~age ~1733, dividing 1733 by 4 gi~e~ a result o~ 433 wi~ a remainder of 1. Therefore, image 1733 is l~ated on ~ d~r #433~ surfa~e #1.
Re~rrin~ to Fig. 2, ~h~re is shown a block dia~ram for ~e record ci~cuit 50O The r~olrd circuit S0 includes a lumiIIance/chroma separator circuit 120, a lu~:ninance ~M
- modlllator 1229 a mixer 124, an enable switch 126~ a ~terodyne ~requency conver~er 128, a refere~ce o~illator 0 130, and a low pass fflter 144.
A st~da~d composite video ~ignal is connected to input ~4 of ~e ~cor~ ci~t 50. ~e composite video signal on ~put 54 is fed to lum~ee/chroma sep~rator 120 where, using convention~l separation ~ech~iques, ~e lumin~ce - 15 signal is separated and m~de ~vaii~le on liLle 132, ~e chroma signal i~ ~eparat~d a~d made available on line 134, and ~e video ~ync ~ sepa~a~d a~d made ~vailable OQ
line 136~ The h~nallce signal on line 132 is fed to ~e luminallce FM modulator 122 where it iB modulated in conventional ~as~ion, a~d the FM modulated luminance signal appea~, o~ 138.
l~e ~oma ~ignal on li~e 134 is csnnected to heterodyne freque~cy conv~r~er 128 wher~ ~e chroma sigD~l is beat wi~ a first re~e~ence ~requency on input 140 2s ~rom the refere~ce oscillator 130. Particula~ly, the re~re~ce frequenc~ is 4.268 MHz which, w~n heterodyned wi~h ~e 3.58 MHz ch~ma sign31 o~ line 1 3D" p~oduces sum ;: and di~feren~e f~uencies o~ output litle 142. 1~ low pæs : filter 144 elLminate~ ~e hi~h freque~cy produced by ~e sumof ~e reference frequency and the chroma signal and passes ~e low frequency di~er0nce signal to its output 146. l[~e signal on output line 146 from ~e low pass filter has a ~ii frequency of approxim~tely 688 KHz. The down-converted chroma signal on line 146 is then mixed with the F~l 3S modulated luminance signal on line 138 by mixer 124 to produce a compositc processed analog video signal on line 148. If the apparatus 10 is in the storage mode, the microprocessor 80 p~oduces a~ en~ble signal on line 106 which closes enalble switch 126 to connect the proce~sed a~alog video sigaal oa line 148 to the outpu~ 58 of the record circui~ 50. T~ p~ocessed analog video 5i~ C~ le 58 iS
the~ co~ec~ed ~hrough i~lation ~witch 60 s to tr~smission line ~2, to multiplexer 56, and ~ d~e selected he2d.
Turning t~ Fig. 3, ~here ~s shown a bl~ di~8~
- 10 of ~e playback cir~uit S2 which compri~es a disable switch 150, a high pass îiltcr 152, an amplifier clipper 154, a lum~a~ce FM demodulator 156, a dela~ line 158, a mixer 160, a low pass ~llter 162, an automatic gain con~ol 164, a re~ence oscillator circuit 166, and a heterodyne fhquency conYe~er 186.
The playbaclc circuit 52 receives thg a~alog video si~al from ~e ~ead O11 ~nput IjQC 72. If ~e retrieval mode ~as been selected by ~he microp~ocessor 80, disa~le switch 1 Sû is closed by a sigIIal 031 line 106 from the micr~proce~sor~ and ~e analog video sig~al o~ line 72 is co~nccted to line 170. ~18 ~Og SigI~al 011 li~e 170 haS ~e ~e frequency compo~itio~ as ~e si~al produced by ~e ~ecord cirG~it on line 58. The ~a}og video sig~al o~ line 170 i~ connectet to ~e high pa~s ~ilter 152 which separate~
~e high frequenGy component, which i~ ~e lumi~ance comLponent, and connects ~e luminance cornponent to line 172. The luminallce compone~t on line 172 is amplifled, and ~e peaks are clipped L~ c~ve~tio~al fa~hion by ampli~ler clipper 154. The output o~ e 174 is conneclted to dle luminance FM demodulator 156, and the luminance component of the original video ~ig~al is re60vered on line 176. The lu~nmance component îs then delayed for a predetermined arnount o~ time by a delay line 158, and ~e delayed ~uminance componen~ appears at line 178 which is 3s ~e input to mixer 160.
,~f~5q3~3 A~ the same time, the low pass filter 162 extracts ~he ch~oma compo~e~t from the processed analog video sig~al on line 170 and feeds ~e chroma component to ~e automa~ic gain control circui~ 164 via line 1~0. The au~oma~ic gain control adju~ts the gain of the chroma compone~ The c~roma com~nent on 1~ 182 at dle output of ~e a~t~ma~ g~ cont~ol ha~ a ch~teristic frequency of 688 ~Hz wi~ di~k ~itter ~rrors superimposed ~ereon.
The chroma component o~ e 182 is cosnected to up-co~verter modulator lgO which sums the fr~que~ he shroma signal (688 k~Hz with ji~e~ erro~ wi~ a refere~ce ~r~uency of 3.58 MHz on line 1843 the output olF ogsi~lator 1~6~ Oscillator 186 also produces a 3.58 P~Iz sign~l on its o~er output 188. The up co~ertgs mo~ula~or 190 produces 1~ a~ its outpu~ 192 the sum o~ ~e ~reque~cy on li~e 184 (3.58 ~Hz) and the chroma sig~al on l?~e 182 (6B8 ~IZ`J. The sum ~ig~a~ on line 192 ha~ a ~re~ue~y of 4.268 MHz and is connected to p~e loek lcop 194 where it is compared t~ the output of up-~conv~rter :modul~or 196 on line 198. The outp~ o~ the pbase loc~c IQOP on l~ 20~ con~ols ~e voltage controlled oscillator 202 to a ~equenGy of 6B8 klEIz which ~ppear~ at it~ output on li~e 204. The 688 kH2 output o~ line 204 is up~onver~d by the 358 MHz ~efernce frequency on ~ e 18~ by mean~ of up-conYerter modulator 196. The rewlting output on line 2~6 ha~ a relatively stabilized ~uency of 4.268 MHz which i~ con~e~ted t~ ~e fre~uency conve~er 168. The fre~ue~cy converter 168 up-con~erts ~e ch~oma ~ignal (688 kHz) by means of ~le reference fre~uellcy o~ line 206 (fl.268 MHz) to a signal on li~e 208 having a frequerlcy of 3.58 M~Iz. The up~onYerted chroma compoIlent on l~e 20R i~ coDnected to ~ mixer 160 w}lere it is combined with delayed lumina~ce compo~e~t on line 178 to reproduce the staIIdard video signal on line 74.
Turning to Fig. 4, ~ere is ~own a block diagram of ~he era~e circuit 100. The erase eircuit 100 include~ a flip-~ q~ 9 1~
flop 212, counter 214, alld decreasin~ current switch 216.
When ~e microprocessor 80 initiates an era~e sequence, it enables ~ rase ci~ui~ 1~0 by rneans of a~ erase command on input 102 which sets flip-f~op 212 produsing a logic "1"
s on il:s Q output 218. The logic "1" on line 218 enables counter 214 which begi~s coumting with each ~ucccssive index pulse o~ line 210. The in~e~ pulses on line 210 are produ ed by the microprocessor 8û each time ~e microprocessor 38 far t~he di~k drive determi~s that a single revolution of ~e disk ha$ occlllTed. ~e index pulses are ~ed from microprocessor 3$ to microprocessor 8~ by means Qf li~e 90, and ~ ~de~ pulses on li~ 90 a~ the~
passed by microprocessor 80 to ~e e~e c~it o~ line 210.
The count 214 sequentially puts a lo~ic "1" v~ ea~h of it~
ou~puts 220, 222~ 224, 226, ~28, 230, and 232. Wi~ each logic "1" an outpu~ 220-232 ~e curre~t swith 216 p~oduces a reverse d.c. current on its output 104 which is connected ~rough tran~is~ion line 62 and ~ultiplexer ~6 to ~Le selected head. When ~e first lin~ 220 is a logic " 1", ~e reve~ing cllITe~t switch 216 prodllce~ a ~gh d.c. current on ~: its output 104. Wi~ each successive lo~i~ "1" on lines 224, ~269 22~, and 230, the reversc cur~nt 3witc~ produces ::~ lower a~d lower d.c. ~e~t le~el~ at its output 104. Oncethe count has reached N wi~ a logic " ln o~ line 230, ~e 2~ reYerse curre~t switch produces ~he lowest cwre~t, and wi~
- ~he ncxt cou~ counter 214 produce~ a logic, "1" at its ~utpu$ 232 which r~sets flip-flop 212 and d;sables coullter ;: 214. ~ce tlhe colmter 214 ha~ counted ~ugh its sequence ~om 1 to N and ha~ been disabled, ~he erase sequence e~ds.
Alternatively, ~e reverse current switch 216 may be replaeed by a high frequency osoillator which produces a 12 MHz to 16 MHz o~tp~t at li~e 104. The oscillator is enabled until the counter 214 has cou~ted to N + 1. lhe erase sequence assures that the trac~ is totally erased of a prior 3s image and appropxiate1y degaussed so ~at storage on tha~
.
track will not be af~ected lby re~idual e~ects o~ ~e previous ~g~-.
Another im po~tant aspect of the present invention i5 ~he ability to compe~sate for time base errors in ~e S sto~ge and retIiçval of images ~at re~ult from ~he inevitable jitter in the speed of the spi~ ing mag~etic disks.
Particularly, wi~ refere~ce to Fig. 5, ~ere i~ ~hown a serv~
control circuit 250 compri~ing a phase l~k loop 252 and a voltage controlled o~cillator 2540 In accordaaace with conven~ional practice, the mic~oprocessor 38 o~ ~e di~k dnve 11 a ha~ stable oscillator which providles a timing re~ere~ce for the microprocesso~ to use ~ co~l~o~ g the speed of t~e spi~lile 16. The mic~processor 38 se~ds a co~ol signal on Ii~e 42 to motor amplifier 258 which in turn controls ~e speed of the moe~r 18. The speed of the spindle 16 is seDsed by meaas of ~h¢ encoder 20 alld sensor 44, a:~d ~e encoder ~ al is connected bac~ via Iine 46 to t~e mieropr~cessor 38 to p~vide adjustment of ~e speed of ~e motor accordingly In a~cordaDce wi~ ~e pres~ inveIltio~, line 46 is connected to ~he phase lock loop 252 through microprocessor 38 and mic~op~essor 80. ~e phase lock loop ~Lso receive~ ~e Yideo sy~c si~nal on li~ 256 from ~e reco~ c~i~ 50. The phase lo~k loop c~mp~ ~e speed of 2s the ~otor represented by ~h~ enc~der si~ o~ line 46 to ~e - video sync ~igIIal on line 256 ~Dd prod~ce~ a dif~erence ~: signsl Oll tin~ ~60 ~he diff~r~e sig~al on line 260 ~hen` :~ serve~ t~ c~n~ol the voltage co~t~olted os~illator 254 which : ~ produces a timing refet~ce o~ i~s o~lqpu~ ~62. Th~ ~o~tage controlled oscillator 254 thereby replaces the stable oscillator previously described which p~ovided ~he timing to - ~ ~e microprocessor 38. Conseque~tly, the seno-control cireuit 250 co~trols the speed of the motor 18 in synehronization wi~ ~he video sy~c sign~l, While the servo-control circuit 250 cannot eliminate jitter from ~e speed of , ,,'''' ;
.~s~35g3 1~
dle disks, it does assure ~at, iZl a gros~ scDse at least~ ~e disks are r~tating once for ea~h complete video ~age.
Turning to Fi8. ~, and i~ co~ection wi~ another important aspect of ~e present inve~ion, there i~ shown a s reîerence frequency c;rcuit 270 which comprises the encoder 20, its sensor 44, a3~d a freque~cy co~verter 272.
Figure 6 also show~ ~e record cia~ 50 which receives ~e composite video si~nal at its iDpUt S4 a~d produces the processed analog video sig~lal at its outp~t 58 as previously o described. The processed analog ~ideo si~al at ou~ut S$ i$
connected ~rough isola~don ~tch 60 a~d multiple~cer S6 to one of ~e four ~eads 249 26, 28, a~d 30. The reference frequency circuit 270 sen~es ~e s~eed ~ ~e spiDdle 16 by means of encoder 20 and se~sor 44. ~he encoder signal on line 46, which is pr~portio~al in ~quell~y to ~e speed of ~e spindle7 is co~ne~ed to t3he f~equency comerter 27~ (as wel~ as to ~e micr~oc~s~or 38) where it i~ convertcd to a reference frequency of 4.26$ MHz o~ line 274 ~or the ~ominal rotational speed of ~e di~ks. The reference frequen~y on line 274 ~es in ~regue~cy in ~cordance wi~
~; ~e v~ations in ~e speed of t3he spindle lG. Therefore, whe~ ~he refePvnce freque~cy on line 274 i5 co~e ted to heterodylle frequency converter 128 of ~e lecor~ clrcuit S0, ~e rcslllti~g freque~cies ~rom ~e he~er~dy~e frcquency converter 128 asd ~re~ore from ~e mixer 1~4 Yary in ` ~ acco~dance wi~ ~he variation~ in ~e gpeed of ~he disk.
Co~equently, ~e frequen~ o~ ~e sign21 on lini: 58 at the output of ~e r~ord circllit .is ~lme ba~e compeDsatcd whe~ it as recorded onto dle dis~c. It should ~e appreciated ~at ~e reference sig~al could al50 be produced by providing a prerecorded re~rence sig~al on ~e magne~ic disk and that ~e term encoder as used herei~ refers ~ bo~ a separate encoder such as 20 and the disk itself wi~ a reference frequency recorded ~ereon.
~ ~35~39 In connection wi~h ~etrieval of t3he analog vid~o signal g~om ~e disk and wi~ reference to Fig 7, ~ere is provided a ~ference frequency circuit 2~ comprising ~e same elements as ~e reference ~reque~cy circuit 270.
s During retrieval7 ehe 4,268 ~Hz signal at ~e output 274 of ~e freQuency co~verte~ 272 i~ ~:onnec~ed t~ lhe ~re~,uency conve~ter 168 of ~e playb~k c~cui~ 52. Cons~uent~r, if jitter resul~s i~ ~e speed of ~e disks du~g re~rieval9 that ji~ter also appears is~ ~ ~equency OD~ e 274 so ~at when lo ~e chroma compone~t is being up-converted, the jitt~ at ~e input 72 to the playba~ ci~ui~ 52 is compe~s~ed by an offsetti~g jitter in t~e frequensy on li~e at 274.
Consequent1y, ~ ~ference frequency circuits 2'70 and 280 together provide c~mp~ete time base compel~sation ~or ~e - 15 video signa~s bo~ d~g storage and re~ieYal.
In ascordance wi~ another asp~ct of ~e prese~t e~ioll, it is pos~ible to provide time base compensa~ion : ~: both in connectio~ wi~ ~e frequency c~ver~ion~ of ~e ehroma ~ignal or at a~ earlier s~age in connt~ction widl gene~a~ng ~e 3.58 MlHz C~¢OMa SigDaL II1 ~a~ connection - and with refere~ce to Figure 8, there is shown a signal proce~sor 300 whic~ i~cludes a ma~rix c~rcuit 302, a red-` ~ minus-luminance modulator 304, a blue-minus-luminance modulator 306, a phase shif~ circui~ 308; and a combining - ~ 25 amplifier 310. 'rhe outputs 132 ~d 134 of the signal processor 300 are connected to the record circuit 50 at lines 132 and 134 as ~own in Fig. 2. Consgque:ntly, in ~he ~: modified versioIl of ~ record circ~ 50 includi~lg ~e signal processor 3ûO, ~e Y/C sepa~ator 120 may be elimina$ed.
C)~herwise, the lumi~ance sig~al OB ~ 132 and~ the ehroma signal on l~ne 134 ~re plocessed for recording ~ ~he same - fashion a~ previously de~cribed in coDnection wi~ record eireuit 50.
In connection with ~e signal processor 300, an 3s image 312 is recorded by a vide~ camera 314 in con~ention~l ~
~a~hion to produce a red ~;gnal on ~ine 3169 a ~re n signal on line 318, and blu~ signal on li~s 320~ Th¢ camer~ 3~4 also h~ an o~cillator whi~ producs~ a sync Sig~ on l;ne 136.
lhe red, green, and blue sig~als ~e connected to ma~rix cixcui~ 30~ whi~ produce~ a hlm~ce signal on lins 132, a red-millus-lusn~ e signal on line 322, ~d a blue-minus-l~in~e signal a~ e 324. ~ color compon~ s on ~ineS
322 ~d 324 a~ modulated wi~ a 3.58 ~Iz re~rence signal on li~e 326. Th~ 3.~8 ~A[Hz signal on li~e 326 is derived from ehe ~reque3lcy ~o~verter 272 shown in Fig. 6 and 7 aIId varies i:~ ~cco~ance with any v~iation i~ the spee~ of ~e disk drlve. The 3.58 MHz re~erence sig~al on li~e 32,6 i~
cosnected to ~d-mi~us~luminance modulator 304 alld to blue-millus-lumin~ce modu31ator 3~6 ~ough 90 phase lS ~hift ~i~uit 308. The output 328 and 330 of ~he red-minus-lumi~aace modutator 304 a~d ~e blue-minus-lumi~ance modulator 306 re~pecti~e~y are co~ected to combining amp~ifier 310 w~i~ comb~es ~e two color ~omponent~ int~
~e 3.58 MH2 chroma sig~l o~ e 134.
Because the r~ere~e signal on line 326 varies in accor~ce wi~ the jit~er of ~e dislc drive, ~e chroma ~ig~al ~: is compensated at ~he ~ne it is modul~ted to 3.58 ~z andagain when it is down~o~ve~ted to 688 ~ in the conYerter 128 (~ig. 2). It should also be a~preciated ~hat ~e 113minance 2s sign~ on lil~e 132 ~d ~he ch~oma ~ignal on l~e 134 could be recorded on ~o separa~e ~acks on ~he disks ~or later - ~pa~ate retrieval a~d p~ocessi~g.
In ac ord~e wi~ a~oth~r aspect of the prese~t ~ventio~, it m~y be d~sirable in co~ection wi~ p~o~iding very high quali~y color pictures to record ~e red sig~al, gr~e~ signal, and blue sig~al ea~h on a separate ~ack on the magne~ic disks. With refere~ce to Figo 9~ ~e record circllit 50 of ~ig. 2 is replaced by a modified record circuit 360 which includes FM modulasors 362, 364, and 366 wi~h 3s output~ 368, 370, and 372 respec~ively. The video camera -314 generates separate red sig~al 3169 gr~en signal~ 318, and blue ~ignal 320. Each ~ eparately FM modulated by modlllator3 362, 364, and 366 which are co~ve~tiolla~ i~
nature. The output~ of ~e FM rnodulators are co~nected di~ctly to recordia~lg head~ 24, 26, al~d 28, respectively, through appropriate i~olation switche~ ~uch as ~8.
Consequently, e~h of the recording heads 24, 26 and 28 separa~ely ~cord~ the red, green~ or blue ~ignal o~ ~ree sep2~ate ~k3 of ~e disks.
With ~e modi~1ed ~co~l cir~uit 360 sho~ in Pig.
9, it is ~ecessary upo~ retrieval to modify ~he playback circuit to receive ~d process the individual recorded ~hree color compone~ts. Tu~ng to Fig. 10, there is sho~ an al~e~native playback circuit 380 which can be used where ea~h co~or component, red, gre~, ~d blue, i5 recordPd on a~ individual t~ck. The pl~y~ack ci~ui~ 380 comp~ises F M
demodulator~ 382, 384, a~d 386, mat~ix circuit 388,red-minus-lumi~ance modulat0r 390, blue-lninus-lumi~ance modulator 392, phase shiR c~uit 394, combi~ng amplifier 396, and combini~g arnplifier 398.
lC)uring retrieval, dle analog sig~ r~m heads ~4, 2~ d 28 are receiYed on i~t line 400 for r~d, 4û2 for green, ~nd 404 for blue. The color compo~ent signals are demodulate~ by ~ demo~ulators 382, 3~4, and 386, and ~e 2s demodul~ed sig~als are connected to ~e ma~ Ci~Uit 388.
The matri~ circuit 399 arithmetically combine~ the ~' demodula~ed color components to produce a luminance si~al o~ line 406, a~d red~minus-lum~ce signal~ o~ line 408, a~d a blue-m~nus-luminance signal on line 410. The two color comp~nent ~ignal on line 408 and 410 are modula~d by mo~ulat~r~ 3~0 and 392 to ~e ~equency oi 3.58 MHz widl ea~h modulat~d color componeat bein8 90 out of pbase from the o~er. The resulti~g modu}ated color compon~nts are combined by combining amplifier 396 to - ~ 3s produce a single chroma 5i~1al OII line 412. 17he chroma " .:
,''' : .~
signal on line 412 a~d the lumi~ance sig~al on line 406 are the~ combined by combining amplifier 39g to produce a sta~da~ composite vid&o signal on line 74 which is ~en, wi~ reîerence ~o Fi~ure 1, coanected to monitor 76 and to s au~iliary ou~pu~ 78.
ln acco~an~e wi~ ano~her aspect Qf ~e present inve~tion, it may upon occasion be desi~able to record certain information digitally concerning ~e ~ature of ~he image such as t~me, dlate, lens se~ g, or other pertinerl~
i~ormation at the time thc image i~ ~ecor~ed on the disk. II1 ~at regard and with re~erence to Fig. 11, there is shown ar~
au~iliary digital memoly 420 having a memory a~ay 425, w~ich is divided into N n~mb0r of memory banks 426 with each banl~ h~ g M ~umber of w~rds 428. The 'ba~ are selected by a bi~ary cou~ter 430, a~d ~e wor~is an~ selected by a bin~ry counter 4320 The au~iliary memory 420 has a data inpu~ 4229 a ~ata o~tput 424, a sloc~c input 350, and address lines ~2, 84, a~d 86. The au~ciliary memory 420 is addressed by ~e microp~ocessor $0 so that each bank cor}espo~ds to a single circular trac~ on l~e disks. The Sigllal5 on line 82 and 84 by mea~s o~ a b~ cou~ter 430 select a group of four banks co~esponding to the radial position of ~e head assembly ~, and ~e sig~al on ~ine 86 abas~ wi~in ~e elected g~up which co~responds to 2~ o~e ~P the ~our heads which has been selected ~or storage ~r retri@val. - -A~ ~e disk~ rotate, ~e e~coder 20, ~e sensor 44, and ~he frequency converter 272 produce a synch~onized cl~k oll line 350. The cloc~ on line 3S0 con~ols ~e b~nary counter 432 which continuously colmts from 1 to M number of wor~ ea~h bank. Consequently, wi~ ~he ban~Ls seleeted by ~he address fr~m ~2 processor 80, the au~ilia~y memory 420 cycles ~om word 1 to word M and repeats in ~ synchro~i~atio~ with the disk making one full revollltion.
;.
There~ore, it c~ be said ~at ~e words L~ each memory bank "walls ~long" wi~ ~ i~orm~ti~ on ~e disk~.
C)ne pa~icularly advan~ageous purpose of the ~u~cilia~y memory 420 is to store ~i~ae base e~ror~ which s ~cur during storage of ~e images o~ the disks. T~g to Fig. 12, there is showII a ~eheme ~or using the au~iliary mPmory 420 ~or ~a~ purpose. A tim e ba~e c~ction circuit soo compnses a compa~LbDr 502~ a stablc ~me b2~e oscillat~r 504, a ~witch 506, ~ m~g cirwit 508, a~d t~e base '!' 10 co~rector 510. Particularly, d~e compara~ receive~ at its input 46 the sig~al from t:he erL~oder 20 ~d ~ensor 44 ~d receives the output ~ ~e s~ble oscillator 405 at i~put 512.
The eompara~or produçe~ a digital error signal on ~e S14 which is proportional to the variation ~tween ~he ~lpeed of S ~e ~pindle 16 (line 46~ and ~he fr~uency of the stabl~ time base oscillat~r 504 (line 51~).
During the storage mode) switch 506 is co~nected to input 422 of ~e auxiliary memory 420, and ~h~ di~tized errvr ~i~nal on line S14 rel~t~B to the jitte~ is stored i~ the memory 420 as the dis~ make~ on one revolution. Upon eompletion of ~e storage mod~, s~ch ~ is to~led to line 516~ a~d ~e all~iliary memory 420 begi~s reading out ~e digi~zed error i~ormatio~ onto its ~utput 424. Duri~g the retrieval mode, ~e comparator co~tinues to produee digital 2s ~me base error i~formatiQ~ on Imc 514 (~d ~herefo~ lin~
516~ w~ich i~ summed wi~h ~e time ba~e error is~omlation Pf~m ~e ~wciliary memory 42~ by ~umming c~ui~ 508. By cornp~nng the tlme ba~e erro~ in~ormation stored in auxiliary memory 420 dunng ~e storage mode to ehe time base error information produced during ~e retrieval mode, a time base correctio~ signal is produced by ~e summing ci~r~uit 508 o~ line 518. The tim~ base correctio~l signal o~
line 518 is connected to ~he time base corrector ci~cuit input S10 where it controls dle delay of ~e signal on output 74 of 35~ j9 ~e playback circuit 52 tQ produce a time base corrector video output si&nal on line 520.
Fu~er i~ ~ccordance with ~he present i~ve~ion and wi~h re~erence to lE;ig. 13, ~ere is provided a single S frame memo~y circuit 60~ whi~ cooperat~s wi~ the s~orage and retrieval apparatus of ~e present L~vention to allow for tra~sitioIl betwee~ images during playbaclc ~uch as dissolving, ov rlay, fade, and other ~pecial ef~ects.
P~icularly, ~e frame memo~ c~it compris$~ a digital 0 memory ~02, an~log-t~digital (A/D) co~verter 604, digital-to-analog converter (DlA) 606, a~d ~er 608. I~ o~der to provide the special ef~ec~s of the îrame memory ~Oû, the p~oces~or 80 f~rst instmct~ the fr~e memory 602 via li~e 614 to store the image that is lbeing ~trieved ~ri~g ~he ~etAeval mode. That is accomplished by fe~ding the video signal on line 74 f~om ~e playb~ck ci~uit S2 to the A/D
co~verter 604 via input 610. The ~ con-~erter 604 digitizes ~he video signal form ~he pl~ack cir~uit and feeds the digitized image to ~he frame memory 6û2 via line 612.
t)nce the digital image ha~ be~n stored in ~rame memory 602, the main procsssor 80 call~ for ~ llext image to be retrieved ~rom the storage medium 11 as has been previously desc~bed. At the s~e timel t~e microprocessor B0 : ~ commands ~e f~e memo~y 602 via line ~14 to OUtpllt the 2~ st~d image in digital ~rm ontQ its outp~l: 616. Ihe image ~epresen~ed by ~e signal on line 616 is convelted from digi~l to analog by D/A con~rter 6~6, a~d aII analog video signal result~ on li~e 618. ~e playback circuit ~2 produces a composite video s ~ OII it~ output 74. The sig~al on line 61B represents the fir~t image, and ~he sig~al on line 74 presellts ~e next image. The two image~ ~e~, in allccordance wi~ c~n rentional mixing ~echniques ca~ied out by a mL~er circuit 608, carl be dissolved9 overl~d, faded one to the :~ other, or merged to provide a composite output on line 62G.
.:
~ ~ .
5~9 l~e pre~ t i~ve~ltion may al~o i~hlde additional - ~eaturgs which eDha~ee it~ use~ gs~. ~or e~ample, the microproce~or ~0 may b~ cont~lled by a remote control 622 much in ~e ~as~ion of the remote cs~trol of a s co~ven~ional slide projector. The micl~rocessor may also select image~ er ~e Coll~ol o a audio t~pe device ~24 wbicla can provide a time sequencc o~ image retrieval all in rela~onsbip to ~e audio being prese~ted.
Claims (17)
1. An image storage and retrieval apparatus having a storage mode and a retrieval mode and comprising:
a. a storage disk mounted for rotation on a spindle and having a number of addressable circular tracks.
b. a servo-controlled motor connected to the spindle for rotating the storage disk at a preselected speed;
c. a read/write head moveably mounted adjacent the disk for selectively receiving an analog signal and for recording the analog signal on the disk during the storage mode and for sensing the analog signal on the disk and for transmitting the analog signal during the retrieval mode;
d. head drive means for selectively positioning the read/write head adjacent each of the addressable circular tracks or recording and sensing the analog signal;
e. record circuit operable during the storage mode for receiving a video signal on a record input, which video signal includes a sync signal, a luminance component, and a chroma component, separating the components, frequency converting the chroma component by a first preselected reference frequency, frequency modulating the luminance component, subsequently recombining the components to produce the analog signal on a record output for transmission to the read/write head;
f. playback circuit operable during the retrieval mode for receiving the analog signal on a playback input from the read/write head, separating the luminance component from the chroma component, frequency demodulating and delaying the luminance component, frequency converting the chroma component by a second preselected reference frequency, and subsequently recombining the components to recover the video signal at a playback output; and g. control means responsive to external instructions for selecting a particular one of the circular tracks in response to receiving an address and for selecting between the storage and retrieval mode.
a. a storage disk mounted for rotation on a spindle and having a number of addressable circular tracks.
b. a servo-controlled motor connected to the spindle for rotating the storage disk at a preselected speed;
c. a read/write head moveably mounted adjacent the disk for selectively receiving an analog signal and for recording the analog signal on the disk during the storage mode and for sensing the analog signal on the disk and for transmitting the analog signal during the retrieval mode;
d. head drive means for selectively positioning the read/write head adjacent each of the addressable circular tracks or recording and sensing the analog signal;
e. record circuit operable during the storage mode for receiving a video signal on a record input, which video signal includes a sync signal, a luminance component, and a chroma component, separating the components, frequency converting the chroma component by a first preselected reference frequency, frequency modulating the luminance component, subsequently recombining the components to produce the analog signal on a record output for transmission to the read/write head;
f. playback circuit operable during the retrieval mode for receiving the analog signal on a playback input from the read/write head, separating the luminance component from the chroma component, frequency demodulating and delaying the luminance component, frequency converting the chroma component by a second preselected reference frequency, and subsequently recombining the components to recover the video signal at a playback output; and g. control means responsive to external instructions for selecting a particular one of the circular tracks in response to receiving an address and for selecting between the storage and retrieval mode.
2. The apparatus of claim 1, wherein the speed of the servo-controlled motor during the storage mode is controlled by a servo-control circuit comprising a phase lock loop, a voltage controlled oscillator, and an encoder, wherein the encoder is connected to be spindle and produces a rotation signal proportional to the speed of the disk, the rotation signal and video sync signal are connected to first and second phase lock loop inputs and are compared by the phase lock loop which in turn has its output connected to and controls the voltage controlled oscillator, which in turn is connected to the servo-controlled motor, so that the servo-control circuit synchronize the speed of the servo-controlled motor to the video sync signal.
3. The apparatus of claim 1, wherein the apparatus further includes an encoder connected to the spindle for producing a rotation frequency signal on an encoder output proportional to the disk's speed, wherein the encoder output is connected to the record circuit and the playback circuit for supplying the rotation frequency signal to serve as the first and second reference frequencies.
4. The apparatus of claim 1, wherein the apparatus further comprises a signal processor for receiving red, green, and blue components of an image and producing the video signal at a processor output which video signal is fed to the record input of this record circuit, wherein the signal processor comprises a matrix circuit with a red input, a green input, and a blue input and a luminance output and at least two color-minus-luminance outputs for combining the red, green, and blue component to produce a luminance signal and at least two color-minus-luminance signals, modulators connected to the color-minus-luminance outputs for out-of-phase modulating the color-minus-luminance signals by a third reference frequency to produce modulated color-minus-luminance signals, means for combining the modulated color-minus-luminance signals and the luminance signal to produce the composite its video signal at the processor output, and wherein the apparatus further includes an encoder connected to the spindle for producing the third reference frequency at an encoder output which third reference frequency is proportional to the disk's speed.
5. The apparatus of claim 1, wherein the apparatus further includes an auxiliary addressable memory for storing and retrieving data comprising a data input for receiving data during the storage mode, a data output for transmitting data during the retrieval mode, an address input, a number of addressable memory banks each corresponding to one of the circular tracks on the disk, and a number of addressable data words within each bank, wherein the control means is connected to the address input and means simultaneously selects the corresponding bank and circular track and wherein an encoder is fixed to the spindle and produces a sequential count at an encoder output which is connected to the address input for sequentially selecting each of the words within each bank.
6. The apparatus of claim 5, wherein the apparatus further comprises a frequency comparator having one input connected to a stable oscillator and another input connected to the encoder and producing a first rotation error signal during the storage mode on a comparator output and for producing a second rotation error signal on the comparator output during the retrieval mode, switch means for alternatively connecting the comparator output to the data input of the auxiliary memory for storing the first rotation error in the auxiliary memory during the storage mode and to one input of a frequency summing circuit for communication of the second rotation error signal to the frequency summing circuit during the storage mode, wherein the frequency summing circuit has another input connected to the data output of the auxiliary memory for receiving the stored first rotation error signal and summing the first and second rotation error signal received at its inputs to produce a third rotation error signal at a summing output which third rotation error signal is connected to an input of a variable delay circuit where it controls the time delay of the video signal from the playback circuit to produce a time base corrected video signal.
7. The apparatus of claim 1, wherein the apparatus further comprises a digital frame memory having a data input, a data output, an address input, and memory locations, an analog to digital converter with an A/D input connected to the playback output and an A/D output connected to the data input, a digital to analog converter with a D/A input connected to the data output and a D/A output, and a mixer switch having a first mixer input connected to the playback output, a second mixer input connected to the D/A output, a mixer output, and a control input for receiving commands from the control means for switching between the first and second mixer inputs to produce a switched video signal at the mixer outputs.
8. The apparatus of claim 1, wherein the apparatus has an erase mode occurring before the storage mode and the apparatus further includes an erase circuit comprising a decreasing reversing current switch whereby the control means upon receipt of an instruction to select the storage mode first activates the erase circuit which when activated connects a d.c. current to the read/write head, and the decreasing reversing current switch under timing control of the control means progressively conducts decreasing levels of d.c. current to the read/write head for a predetermined erase time.
9. The apparatus of claim 1, wherein the apparatus has an erase mode occurring before the storage mode and the apparatus further includes an erase circuit comprising a high frequency oscillator whereby the control means upon receipt of an instruction to select the storage mode first activates the erase circuit which when activated connects the high frequency oscillator to the read/write heads for a predetermined erase time.
10. An image storage and retrieval apparatus having a storage mode and a retrieval mode and comprising:
a. a storage disk mounted for rotation on a spindle and having a number of addressable circular tracks;
b. a servo-controlled motor connected to the spindle for rotating the storage disk at a preselected speed;
c. a read/write head moveable mounted adjacent the disk for selectively receiving an analog signal and for recording the analog signal on the disk during the storage mode and for sensing the analog signal on the disk and for transmitting the analog signal during the retrieval mode;
d. head drive means for selectively positioning the read/write head adjacent each of the addressable circular tracks for according and sensing the analog signal;
e. record circuit operable during the storage mode for receiving a video signal on a record input, which video signal includes a sync signal and primary color signals, frequency modulating the primary color signals to produce the analog signal on a record output for transmission to the read/write head;
f. playback circuit operable during the retrieval mode for receiving the analog signal on a playback input from the read/write head, frequency demodulating the primary color signals, arithmetically combining the primary color signals to produce a luminance component and chroma components, modulating the chroma component by a first preselected reference frequency, and subsequently recombining the components to recover the video signal at a playback output; and g. control means responsive to external instructions for selecting a particular one of the circular tracks in response to receiving an address and for selecting between the storage and retrieval mode.
a. a storage disk mounted for rotation on a spindle and having a number of addressable circular tracks;
b. a servo-controlled motor connected to the spindle for rotating the storage disk at a preselected speed;
c. a read/write head moveable mounted adjacent the disk for selectively receiving an analog signal and for recording the analog signal on the disk during the storage mode and for sensing the analog signal on the disk and for transmitting the analog signal during the retrieval mode;
d. head drive means for selectively positioning the read/write head adjacent each of the addressable circular tracks for according and sensing the analog signal;
e. record circuit operable during the storage mode for receiving a video signal on a record input, which video signal includes a sync signal and primary color signals, frequency modulating the primary color signals to produce the analog signal on a record output for transmission to the read/write head;
f. playback circuit operable during the retrieval mode for receiving the analog signal on a playback input from the read/write head, frequency demodulating the primary color signals, arithmetically combining the primary color signals to produce a luminance component and chroma components, modulating the chroma component by a first preselected reference frequency, and subsequently recombining the components to recover the video signal at a playback output; and g. control means responsive to external instructions for selecting a particular one of the circular tracks in response to receiving an address and for selecting between the storage and retrieval mode.
11. The apparatus of claim 10, wherein the speed of the servo-controlled motor during the storage mode is controlled by a servo-control circuit comprising a phase lock loop, a voltage controlled oscillator, and an encoder, wherein the encoder is connected to the spindle and produces a rotation signal proportional to the speed of the disk, the rotation signal and video sync signal are connected to first and second phase lock loop inputs and are compared by the phase lock loop which in turn has its output connected to and controls the voltage controlled oscillator, which in turn is connected to the servo-controlled motors, so that the servo-control circuit synchronize the speed of the servo-controlled motor to the video sync signal.
12. The apparatus of claim 10, wherein the apparatus further includes an encoder connected to the spindle for producing a rotation frequency signal on an encoder output proportional to the disk's speed, wherein the encoder output is connected to the record circuit and the playback circuit for supplying the rotation frequency signal to serve as the first reference frequency.
13. The apparatus of claim 10, wherein the apparatus further includes an auxiliary addressable memory for storing and retrieving data comprising a data input for receiving data during the storage mode, a data output for transmitting data during the retrieval mode, an address input, a number of addressable memory banks each corresponding to one of the circular tracks on the disk, and a number of addressable data words within each bank, wherein the control means is connected to the address input and simultaneously selects the corresponding bank and circular track and wherein an encoder is fixed to the spindle and produces a sequential count at an encoder output which is connected to the address input for sequentially selecting each of the words within each bank.
14. The apparatus of claim 13, wherein the apparatus further comprises a frequency comparator having one input connected to a stable oscillator and another input connected to the encoder and producing a first rotation error signal during the storage mode on a comparator output and for producing a second rotation error signal of the comparator output during the retrieval mode, switch means for alternatively connecting the comparator output to the data input of the auxiliary memory for storing the first rotation error in the auxiliary memory during the storage mode and to one input of a frequency summing circuit for communication of the second rotation error signal to the frequency summing circuit during the storage mode, wherein the frequency summing circuit has another input connected to the data output of the auxiliary memory for receiving the stored first and second rotation error signal and summing the first and second rotation error signal received at its input to produce a third rotation error at a summing output at a summing output which third rotation error signal is connected to an input of a variable delay circuit where it controls the time delay of the video signal from the playback circuit to produce a time base corrected video signal.
15. The apparatus of claim 10, wherein the apparatus further comprises a frame memory having a data input, a data output, an address input, and memory locations, an analog to digital converter with an A/D input connected to the playback output and an A/D output connected to the data input, a digital to analog converter with a D/A input connected to the a output and a D/A output, and a mixer switch having a first mixer input connected to the playback output, a second mixer input connected to the D/A output, a mixer output, and a control input for receiving commands from the control means for switching between the first and second mixer inputs to produce a switched video signal at the mixer output.
16. The apparatus of claim 10, wherein the apparatus has an erase mode occurring before the storage mode and the apparatus further includes an erase circuit comprising a decreasing reversing current switch whereby the control means upon receipt of an instruction to select the storage mode first activates the erase circuit which when activated connects a d.c. current to the read/write head, and the decreasing reversing current switch under timing control of the control means progressively conducts decreasing levels of d.c. current to the read/write head for a predetermined erase time.
17. The apparatus of claim 10, wherein the apparatus has an erase mode occurring before the storage mode and the apparatus further includes an erase circuit comprising a high frequency oscillator whereby the control means upon receipt of an instruction to select the storage mode first activates the erase circuit which when activated connects the high frequency oscillator to the read/write heads for a predetermined erase time.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US068,268 | 1987-06-30 | ||
| US07/068,268 US4823196A (en) | 1987-06-30 | 1987-06-30 | Image storage and retrieval apparatus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1285069C true CA1285069C (en) | 1991-06-18 |
Family
ID=22081489
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000570751A Expired - Lifetime CA1285069C (en) | 1987-06-30 | 1988-06-29 | Image storage and retrieval apparatus |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1285069C (en) |
-
1988
- 1988-06-29 CA CA000570751A patent/CA1285069C/en not_active Expired - Lifetime
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