CA1285053C - T1 line format for robbed signaling for use with ccitt 32k bit per second adpcm clear channel transmission - Google Patents
T1 line format for robbed signaling for use with ccitt 32k bit per second adpcm clear channel transmissionInfo
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- CA1285053C CA1285053C CA000545523A CA545523A CA1285053C CA 1285053 C CA1285053 C CA 1285053C CA 000545523 A CA000545523 A CA 000545523A CA 545523 A CA545523 A CA 545523A CA 1285053 C CA1285053 C CA 1285053C
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/12—Arrangements providing for calling or supervisory signals
- H04J3/125—One of the channel pulses or the synchronisation pulse is also used for transmitting monitoring or supervisory signals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/0016—Arrangements providing connection between exchanges
- H04Q3/0025—Provisions for signalling
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- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Communication Control (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
ABSTRACT OF THE INVENTION
This invention provides for uniformly distributing signaling data in a T1 line format for unrestricted 32 kb/s and 64 kb/s transmission channels. This scheme provides for placing a portion signaling information within each frame of a T1 transmission. Digital switching systems may process this signaling information more uniformly, instead of receiving 24 channels of signaling information during one T1 frame. The signaling information provides the digital switching system with indications of such supervisory functions as on-hook, off-hook and switching digits.
This invention provides for uniformly distributing signaling data in a T1 line format for unrestricted 32 kb/s and 64 kb/s transmission channels. This scheme provides for placing a portion signaling information within each frame of a T1 transmission. Digital switching systems may process this signaling information more uniformly, instead of receiving 24 channels of signaling information during one T1 frame. The signaling information provides the digital switching system with indications of such supervisory functions as on-hook, off-hook and switching digits.
Description
Tl LINE FDRMAT FOR R~REFn SIGN~LrNG FOR USE WITH CCI
32X BIT ~ SEoOND ADPCM CLE~R CH~NNEL TRPNSUI ION
CROSS REFERENCE T~ REI~ED AEPIICATIONS
The pre~ent application is rela~ed to co-pending applications Canadian Serial Nos. 545,522 and 545,521, having the same inventive entity and being assigned to the same assignee as the presQnt applica~ion.
8acx3~uND OF THE INVENTInN
me present invention ~ a ms to Tl ~ransmission S~stems and more particularly to unrestricted 32 kb/s (32,000 bits per second) and 64 kb/s (64,000 bits per second) transmission chan~els which perform the rcbbed signaling ~unction.
Tl transmission line facilities operate at 1.544M bits per second. me T1 line transmission facilities u~ilize an alternating mark inversion (AMI) signaling scheme~ mis AMI
signal contains no more than 15 consecutive æe~o bit positions in a particular T1 bit stream. This requirement of not more than 15 zero bits in a string derives from the operation of repeaters in Tl transmission line systems. Ccmmonly used repeaters may not operate within specification if more than 15 consecutive zeroes are tran~itted. Repeater synchronization cannot be guaranteed for bit streams with m~re than 15 consecutive zerDes.
One technique used for 11 line O bits suppression is bipolar wi~h 8 zeroes substitution (B8ZS3. me E8ZS technique utilizes two special coding patterns oontaLning bipolar violations which are substituted for strings of ~ zeroes in the in~ut si~nal stream. Upon detecting bipolar violations with either of the two special patterns, the receiver pla~es 8-bits of zeroes in the corresponding positions in the cutput bit stream.
One tech~ical disadvantage of the B8ZS techm que is that it violates the AMI signaling standard on Tl lines. Since bipolar violations normally indicate transmission errDrs, the deliberate intro*uction of these transmission errors by B8ZS signaling reduces the effectiveness of determining real errors ~hich are detected by the AMI signaling scheme. Another " .~
.. .. .
3, ?d ~ .3 disadvantage of the ~8ZS technlque is that it detects strings of 8 zeroes and substitutes the special violation patterns more frequently than the specified Tl line operation requires. In addition to these disadvantages, the B8ZS patterns will not - 5 propagate through standard multiplexer derived DS1 facilities or protected Tl facilities.
Severe economic disadvantages obtain for the introduction of the B8ZS technique into the North American transmission network. This introduction would require a global 10 replacement of existing multiplexers, automatic protection switches, electronic cross-connect devices (DACS), digital switch interface hardware and any other item in the network with violation monitor and removal (VMR). Such an introduction of the B8ZS ~echnique presents an unreasonably large capital investment 15 requirement to change network hardware.
Another more commonly used technique for meeting the T1 llne zero suppression requirement is to place restrictions on the sources of bit sequences allowed in payload channels. For example, this restriction is applied at CODECS to transform a O
20 bit to a 1 bit whenever an all zero 8-bit chamlel appears as a PCM
code word. This same technique of forcing 1 bits into all zero 8-bit channels is used to further assure that no all zero 8-bit channels and therefore not more than 15 consecutive zero bits are transmitted in the T1 line format. This is a sufficient, but not 25 a necessary condition for achieving the requirement.
The disadvantage of the technique of Tl line æero suppression by restricting sources of bit sequences is tha~ all zero 8-bit strings are not permitted to be transmitted on any channel. This prevents the use of Tl lines for transmission of 30 clear channel data (which require sending all possible 8-bit strings including an all zero 8-bit string) and standard CCITT 32K
bit per second ADPCM. This technique also requires special treatment of all payload 8-bit strings by hardware such as CODECS
and digital trunk units to force 1 bits into all zero 8-bit 35 octets.
.3 Robbed signaling typically occurs by using the least significant bit of each channel during every sixth frame to provide signaling functions such as 9 on-hook, off-hook, etc.
Thus, the processing at a digital switching system for any channel may not begin until six frames of data have been received by the receiving digital switching office.
It is an object of the present invention to provide slgnaling data during each frame in order to facilitate uniform processing of the signaling data by the digital switching system.
SUMMARY OF THE INVENTION
This inventiorl is a Tl line format for transmitting robbed signaling data from one digital switching system to another digital switching system via Tl line facilities in a uniform manner. This Tl line format includes a Tl data frame. The Tl data frame has a predetermined number of data channels for transmitting data between the digital switching systems.
Each Tl data frame includes a predetermined number of clear channel data channels and at least one dedicated channel for transmltting signaling data and other non clear channel data between the digital switching systems. Clear channel data may be any combination of binary information within the 8-bit wide channel. The dedicated channel of each Tl data frame transmits the signaling data for a number of the clear channel data channels.
This Tl line format provides for transmitting a number of Tl data frames from the transmitting digital switching system to the receiving digital switching system. Each of the plurality of Tl data frames includes a portion of the signaling data. As a result, after receiving a predetermined number of the Tl data frames, the receiving digital switching system will have obtained all the signaling data in a uniform and distributed manner.
A BRIEF DESCRIPTION OP TEE DRAWINGS
Figure 1 is a layout diagram of typical Tl frPme data format.
Figure 2 is a layout diagram of channel 23 of each frame.
Figure 3 is a layout diagram of ~he bundling arrangement of the preæent invention.
Figure 4 is a flowchart of the ~undle encode logic of the present invention.
Figure 5 is a flowchart of the btmdle encode logic~
Figure 6 is a flowchart of the bundle decode logic of the present invention.
Figure 7 is a Elowchart of the bundle decode logic.
DESCRIPTION OF THE PREFERRED EMBODIMENT
The structure of the T1 line format is based on the standard 1.544~ bits per second DSl digital signal format. This structure is shown in Figure 1. The DS1 frame contains 193 bits of informationO This information is organized into a slngle bit of synchronization or framing data plus 192 bits of payload data.
The 192 bits of payload data are organized into 24 channels, each channel containing 8 bits and can be referred to as an octet.
In the DS1 signaling, the least significant bit, PCM 7, of each octet in every sixth frame is commonly used as a robbed or sto:Len signaling bit to indicate the signaling states of the active channels. These signaling bits are transmi~ted at a rate of 24 bits per 6 frames or 4 bits per frame.
A new T1 line fo~mat may be constructed to replace the robbed signaling scheme. Four bits of signaling information, bits ~, B, C and D shown in Figure 2 are transmitted with each frame.
The receiving end of the transmission system receives four signaling bits with each frame. Therefore, processing of the functions associated with these bits may proceed more uniformly.
Furthermore, by moving signaling bits to channel 23, true clear channel transmission capabillty is provided. These four bits reside in the firRt 4 bits of channel 23. The last four bits are zero octet indica~or bits. Over the span of six frames, the new format does obtain all 24 signaling bi~s (one bit per channel).
This arrangement provides for 46 unrestricted 32 kb/s channels or 5~3 23 unreætricted 64 kb/s (clear) channels. These bits are assigned a sequence which is indexed by reference to the signaling frame.
For example, bit A is channel O signaling informaeion in frame 1;
channel 4 signaling informa~ion in frame 5; channel 8 signaling information in frame 9, etc.
The DSl signal contains 23 full channels of 8-bits in length (PCM0 - PCM7) as shown in Figure 1. As shown in Figure 2, the new format of the 24th channel (channel 23) may contain a 1/2 payload channel (4-bits) of ~mrestricted information or 4 bits of signaling information (A, B, C and D) in the first four bits of channel 23. The remaining 4-bits of channel 23 are the zero octet indica~or bits. For CCITT 32 kb/s ADPCM there are either 46 or 47 unrestricted channels of 4 bits in length. In order to meet the Tl line zero suppression requirements, the unrestricted payload signal is transformed to a non-zero octet wherever an all zero octet (channel) is detected within the frame.
Referring to Pigure 3, a typical 24 channel frame of DS1 signallng is shown. The channels of the frame are shown grouped into 4 bundles, 1 through 4. Each bundle contains 6 channels of unrestricted data, except for channel 23 which has only a 4-bit payload. Bundle 1 contains channels 0 through 5;
bundle 2 contains channels 6 through 11; bundle 3 contains channels 12 through 17; and bundle 4 contains channels 18 through 23. Channel 23 is only a one-half payload channel. The other 4-bits of channel 23 contain the zero octet indicator bits as shown in Figure 2.
~ ach of the 4 zero octet indicator bits corresponds to an associated bundle as shown in Figure 3. If any of the channels of a particular bundle contains an all zero octet~ then the indicator bit, shown in Figure 2, corresponding to that bundle is set to a logic 1. Otherwise, the indicator bit is always set to logic ~.
The zero octet indicator bit for bundle 4 is always set last. The bundle 4 zero octet indicator bit is handled in a special manner. First, the bundle 4 bit is set to a binary logic .. . ..
0. Next~ each channel in bundle 4 is examined to determine whether any octet is all zero. If any octet in bundle 4 is all zero, then the bundle 4 bit is set to logic 1.
The scheme disclosed herein may be implemented via the firmware of a digital signal procefisor. One such dig~tal signal processor that may be employed is a Fujitsu digital signal processor part number MB-8764-DSP. The transmitting station will contain a digital signal processor and the necessary encode logic.
The receiving station contains the digital signal processor with the decode logic.
Referring to Figures 4 and 5, the encode logic for the T1 line format for CCITT 32 kb/s ADPCM and 64 kb/s clear channel transmission is shown. This logic begins at block 10 and first initializes the 4 indicator bits contained in the last half of channel 23 each to 0, block 20. Next, a 4-bit indicator register is initialized to 0, block 30. This register corresponds to the 4 indicator bits in channel 23 and at the end of the process, the register will be written into the 23rd channel.
An internal counter k is set equal to 1, block 40.
This is the bundle counter. Next, a mapping register is inltialized to the binary value 00000011, block 50. This register will locate the zero octets. Another internal counter i is said equal to 1, block 60. This is the octet counter.
Next, block 70 asks whether the i-th octet is equal to 0. If the particular octet or channel contains 8-bits of 0, the bit corresponding to that octet within the mapping register is set equal to 1, block 72. Next, the bundle indicator bit of the indicator register is set equal to 1 corresponding to the value of the internal octet counter k, block 74. The bundle indicator bits (zero octet indicator bits~ are shown in Figure 2.
Block 80 determines whether the internal octet counter i is equal to 6. If i is equal to 6, then control is passed to block 90 of Figure 5. This indicates that all 6 octets of a particular bundle have been examined for a contents of zero. If the internal indicator i is not equal to 6, then all of the octets or channels of that particular bundle have not been examined. As a result, the internal octet counter i is incremented by 1, block 82. Then, processing control is transferred to block 70. This processing continues until all octets or channels of the S particular bundle have been examined.
Block 90 detarmines whether the indicator register correspondlng to the bundle of octets which were just examined is equal to 0. If the indicator register for this particular bundle is not equal to 0, this indicates that at least one all zero octet exists within the bundle and the first octet or channel of that bundle is temporarily saved in a displacement register, block 92.
Next, the contents of the displacement register are transferred to the first zero octet, block 94. It is important to note that the first zero octet may not necessarily be octet number 1. Each additional zero octet within the particular bundle is set to ' binary 11111111, block 96. Since all zero octets will be recreated at the receiving end of the transmission system, the bits are altered to logic ones in order to provide additional synchronization for the repeaters and transmission equipment. As previously mentioned, the repeaters and transmission equipment require a minimum density of logic ones in order to maintain synchronization.
Ne~t, the contents of the mapping register are copied into octet number 1, block 98. The mapping register contains a 1 in each bit position corresponding to the location of a zero octet in the bundle of 6 octets. Since only the first 6 blts of the mapping register are required for the information about the 6 octets, the other 2 bits of the mapping register may be arbitrarily set. Again, to aid the transmission equipment and repeaters, these bits are arbitrarily set to logic 1.
After the above processing has been complete for the detection of a zero octet within the bundle or if the indicator register showed that no all zero octet was found, block 90, then the bundle counter k is examined to determine whether it is equal to 4, block 100. if the bundle counter k is less then 4, it is 5~3 incremented by 1 block 102, and processing is transferred to block 50 for the processing of the next bundle of octets. if the bundle counter k is equal to 4, all 4 bundles have been processed and processing control is transferred to block 110.
Block 110 tests the 4 bit indicator register to determine whether it is equal to the binary value 0001. This indicates that there is at least one all zero octet conta~ned in the 4th bundle, if the result of the test is positive. Block 120 interrogates the mapping register to determine whether it is equal to the binary pattern 00000111. If the result of this test is also positive, this indicates that the all zero octet is the 6th octet of the bundle. Special processing must occur for this situation.
Since it is known that only the 6th octet of this bundle is all zero~ the contents of the displacement register is copied back into the first octet of bundle 4, block 122. This is necessary since block 92 copied the contents of octet number 1 to the displacement register. The contents of octet 1 must be mo~ed back to avoid losing these contents since it is known that these contents are non-zero.
Next, the binary value 00000000 is moved to the 6th octet of bundle 4, block 124. Again, it is known that this octet was zero because the mapping register had a 1 set in the bit position corresponding to this octet. The last 4-bits of this octet are a don't care function and were set to 0 arbitrarily, since the indicator register will be written into these bits in order to form the zero octet indicator bits as shown in Figure 2.
The value of the zero octet indicator bits is guaranteed to be non-zero at this time.
At the completion of the processing of block 124 or if either of the tests of blocks 110 or 120 were answered in the negative, block 130 copies the indicator register to the last 4 bits of octet number 6 of bundle number 4. If octet number 6 was zeroed by block 124, it was known that the indicator register contained a 1 in the bundle 4 position. Therefore, this indicator register is wrltten over thP last 4 bits of octet number 6 of bundle 4. As a result, this octet will be guaranteed to have at least one logic 1.
The zero octet processing for this frame has been complete. The frame is then transmitted to the conversion logic which places the frame in the AMI format, block 140. The processing for this ~rame is then ended, block 150.
Referring to Figures 6 and 7, the frame/bundle decode logic is shown. The decode logic process i9 initiated at block 200. Block 210 moves the indicator bits from blts 5 through 8 of channel 6 of bundle 4 to an indicator register. Next, the indicator register is examined to detYrmine whether all 4 of the zero octet indicator bits are equal to zero. If all four ~ero octet indicator bits are zero, no channel within the particular frame contains an all zero octet. As a result, the frame is transferred for further processing exactly as it was received. ~o bit modification is required. Therefore, processing control is transferred to block 290, which ends the frame/bundle decode logic for this particular frame.
If the zero octet indicator bits contained ln the indicator register are not all zeroJ processing control is passed to block 240. Block 240 interrogates the 23rd channel or octet 6 of bundle 4 to determine whether the value of this channel is e~ual to the binary value 00000001. For a positive resu~t of the test of block 240, it is known that only channel 6 of bundle 4 was a zero octet in the particular frame. The bundle 4 zero octet indicator bit had previously been set to logic 1. Since this particular logic 1 in the bundle 4 zero octet indicator bit position is not a payload signalJ no modification of the frame need occur. As a result9 control is transferred to block 230 which transmits the fram~ exactly as received for further processing. This processing handles the special case of channel 23 being the only octet with an all zero value. Then, the decode logic processing is ended, block 290.
IE the test of block 240 was answered in the negative, block 250 sets an internal bundle counter k equal to 1. Next, the indicator register is examined to determine whethe- the k-th zero octet indicator bit is equal to 1. It should be remembered that if a particular zero octet indicator bit is equal to 1 there ls at least 1 all zero channel or octet in that particular bundle. If this particular zero octet indicator bit is equal to 1, then block 262 copies the first octet of that bundle to the mspping register.
For bundles in which there is at least one zero octet the first channel or octet contains the mapping for the locations of these octets. Next, the first octet whose mapping register bit is equal to 1 is copied to the displacement register, block 264. Then each octet of the bundle whose mapping register bit is equal to a 1 will have the binary value 00000000 written into that octet, block 280. Next, block 282 determines whether the mapping register bit for the first octet is equal to zero. If the mapping register bit for the ~irst octet is zero, then the displacement regist~r is copied back into the first octet, block 284. This indicates that the first octet of the bundle was non-zero and must be replaced with its original value which was displaced to another location so that the mapping bits could be placed in the first octet of each bundle.
~fter the displacement register has been copied by block 284 or if the question of block 282 is answered in a negative or if the question of block 260 i8 answered in the negative, then processing control is given to block 270. Block 270 determines whether the value of the internal bundle counter k is equal to 4. If ~his test is answered in the negative, the bundle counter k is incremented by 1, block 272. Then, processing control is begun again at block 260. If k i8 less then 4, processing for all 4 bundles comprising the particular frame is not yet complete. If the bundle counter k is equal to 4, then all octets which were originally zero before the transmission have been reconstructed to be zero. Lastly, block 274 transfers the decoded frame for further processing and the decoding process is ended, block 290.
5~3 Although the preferred embodi~ent of the invention has been illustrated, and that f orm described in detail, it will be readily apparent to those skilled in the art that various modifications may be made therein without departing from the spirit of the invention or from the scope of the appended claims.
32X BIT ~ SEoOND ADPCM CLE~R CH~NNEL TRPNSUI ION
CROSS REFERENCE T~ REI~ED AEPIICATIONS
The pre~ent application is rela~ed to co-pending applications Canadian Serial Nos. 545,522 and 545,521, having the same inventive entity and being assigned to the same assignee as the presQnt applica~ion.
8acx3~uND OF THE INVENTInN
me present invention ~ a ms to Tl ~ransmission S~stems and more particularly to unrestricted 32 kb/s (32,000 bits per second) and 64 kb/s (64,000 bits per second) transmission chan~els which perform the rcbbed signaling ~unction.
Tl transmission line facilities operate at 1.544M bits per second. me T1 line transmission facilities u~ilize an alternating mark inversion (AMI) signaling scheme~ mis AMI
signal contains no more than 15 consecutive æe~o bit positions in a particular T1 bit stream. This requirement of not more than 15 zero bits in a string derives from the operation of repeaters in Tl transmission line systems. Ccmmonly used repeaters may not operate within specification if more than 15 consecutive zeroes are tran~itted. Repeater synchronization cannot be guaranteed for bit streams with m~re than 15 consecutive zerDes.
One technique used for 11 line O bits suppression is bipolar wi~h 8 zeroes substitution (B8ZS3. me E8ZS technique utilizes two special coding patterns oontaLning bipolar violations which are substituted for strings of ~ zeroes in the in~ut si~nal stream. Upon detecting bipolar violations with either of the two special patterns, the receiver pla~es 8-bits of zeroes in the corresponding positions in the cutput bit stream.
One tech~ical disadvantage of the B8ZS techm que is that it violates the AMI signaling standard on Tl lines. Since bipolar violations normally indicate transmission errDrs, the deliberate intro*uction of these transmission errors by B8ZS signaling reduces the effectiveness of determining real errors ~hich are detected by the AMI signaling scheme. Another " .~
.. .. .
3, ?d ~ .3 disadvantage of the ~8ZS technlque is that it detects strings of 8 zeroes and substitutes the special violation patterns more frequently than the specified Tl line operation requires. In addition to these disadvantages, the B8ZS patterns will not - 5 propagate through standard multiplexer derived DS1 facilities or protected Tl facilities.
Severe economic disadvantages obtain for the introduction of the B8ZS technique into the North American transmission network. This introduction would require a global 10 replacement of existing multiplexers, automatic protection switches, electronic cross-connect devices (DACS), digital switch interface hardware and any other item in the network with violation monitor and removal (VMR). Such an introduction of the B8ZS ~echnique presents an unreasonably large capital investment 15 requirement to change network hardware.
Another more commonly used technique for meeting the T1 llne zero suppression requirement is to place restrictions on the sources of bit sequences allowed in payload channels. For example, this restriction is applied at CODECS to transform a O
20 bit to a 1 bit whenever an all zero 8-bit chamlel appears as a PCM
code word. This same technique of forcing 1 bits into all zero 8-bit channels is used to further assure that no all zero 8-bit channels and therefore not more than 15 consecutive zero bits are transmitted in the T1 line format. This is a sufficient, but not 25 a necessary condition for achieving the requirement.
The disadvantage of the technique of Tl line æero suppression by restricting sources of bit sequences is tha~ all zero 8-bit strings are not permitted to be transmitted on any channel. This prevents the use of Tl lines for transmission of 30 clear channel data (which require sending all possible 8-bit strings including an all zero 8-bit string) and standard CCITT 32K
bit per second ADPCM. This technique also requires special treatment of all payload 8-bit strings by hardware such as CODECS
and digital trunk units to force 1 bits into all zero 8-bit 35 octets.
.3 Robbed signaling typically occurs by using the least significant bit of each channel during every sixth frame to provide signaling functions such as 9 on-hook, off-hook, etc.
Thus, the processing at a digital switching system for any channel may not begin until six frames of data have been received by the receiving digital switching office.
It is an object of the present invention to provide slgnaling data during each frame in order to facilitate uniform processing of the signaling data by the digital switching system.
SUMMARY OF THE INVENTION
This inventiorl is a Tl line format for transmitting robbed signaling data from one digital switching system to another digital switching system via Tl line facilities in a uniform manner. This Tl line format includes a Tl data frame. The Tl data frame has a predetermined number of data channels for transmitting data between the digital switching systems.
Each Tl data frame includes a predetermined number of clear channel data channels and at least one dedicated channel for transmltting signaling data and other non clear channel data between the digital switching systems. Clear channel data may be any combination of binary information within the 8-bit wide channel. The dedicated channel of each Tl data frame transmits the signaling data for a number of the clear channel data channels.
This Tl line format provides for transmitting a number of Tl data frames from the transmitting digital switching system to the receiving digital switching system. Each of the plurality of Tl data frames includes a portion of the signaling data. As a result, after receiving a predetermined number of the Tl data frames, the receiving digital switching system will have obtained all the signaling data in a uniform and distributed manner.
A BRIEF DESCRIPTION OP TEE DRAWINGS
Figure 1 is a layout diagram of typical Tl frPme data format.
Figure 2 is a layout diagram of channel 23 of each frame.
Figure 3 is a layout diagram of ~he bundling arrangement of the preæent invention.
Figure 4 is a flowchart of the ~undle encode logic of the present invention.
Figure 5 is a flowchart of the btmdle encode logic~
Figure 6 is a flowchart of the bundle decode logic of the present invention.
Figure 7 is a Elowchart of the bundle decode logic.
DESCRIPTION OF THE PREFERRED EMBODIMENT
The structure of the T1 line format is based on the standard 1.544~ bits per second DSl digital signal format. This structure is shown in Figure 1. The DS1 frame contains 193 bits of informationO This information is organized into a slngle bit of synchronization or framing data plus 192 bits of payload data.
The 192 bits of payload data are organized into 24 channels, each channel containing 8 bits and can be referred to as an octet.
In the DS1 signaling, the least significant bit, PCM 7, of each octet in every sixth frame is commonly used as a robbed or sto:Len signaling bit to indicate the signaling states of the active channels. These signaling bits are transmi~ted at a rate of 24 bits per 6 frames or 4 bits per frame.
A new T1 line fo~mat may be constructed to replace the robbed signaling scheme. Four bits of signaling information, bits ~, B, C and D shown in Figure 2 are transmitted with each frame.
The receiving end of the transmission system receives four signaling bits with each frame. Therefore, processing of the functions associated with these bits may proceed more uniformly.
Furthermore, by moving signaling bits to channel 23, true clear channel transmission capabillty is provided. These four bits reside in the firRt 4 bits of channel 23. The last four bits are zero octet indica~or bits. Over the span of six frames, the new format does obtain all 24 signaling bi~s (one bit per channel).
This arrangement provides for 46 unrestricted 32 kb/s channels or 5~3 23 unreætricted 64 kb/s (clear) channels. These bits are assigned a sequence which is indexed by reference to the signaling frame.
For example, bit A is channel O signaling informaeion in frame 1;
channel 4 signaling informa~ion in frame 5; channel 8 signaling information in frame 9, etc.
The DSl signal contains 23 full channels of 8-bits in length (PCM0 - PCM7) as shown in Figure 1. As shown in Figure 2, the new format of the 24th channel (channel 23) may contain a 1/2 payload channel (4-bits) of ~mrestricted information or 4 bits of signaling information (A, B, C and D) in the first four bits of channel 23. The remaining 4-bits of channel 23 are the zero octet indica~or bits. For CCITT 32 kb/s ADPCM there are either 46 or 47 unrestricted channels of 4 bits in length. In order to meet the Tl line zero suppression requirements, the unrestricted payload signal is transformed to a non-zero octet wherever an all zero octet (channel) is detected within the frame.
Referring to Pigure 3, a typical 24 channel frame of DS1 signallng is shown. The channels of the frame are shown grouped into 4 bundles, 1 through 4. Each bundle contains 6 channels of unrestricted data, except for channel 23 which has only a 4-bit payload. Bundle 1 contains channels 0 through 5;
bundle 2 contains channels 6 through 11; bundle 3 contains channels 12 through 17; and bundle 4 contains channels 18 through 23. Channel 23 is only a one-half payload channel. The other 4-bits of channel 23 contain the zero octet indicator bits as shown in Figure 2.
~ ach of the 4 zero octet indicator bits corresponds to an associated bundle as shown in Figure 3. If any of the channels of a particular bundle contains an all zero octet~ then the indicator bit, shown in Figure 2, corresponding to that bundle is set to a logic 1. Otherwise, the indicator bit is always set to logic ~.
The zero octet indicator bit for bundle 4 is always set last. The bundle 4 zero octet indicator bit is handled in a special manner. First, the bundle 4 bit is set to a binary logic .. . ..
0. Next~ each channel in bundle 4 is examined to determine whether any octet is all zero. If any octet in bundle 4 is all zero, then the bundle 4 bit is set to logic 1.
The scheme disclosed herein may be implemented via the firmware of a digital signal procefisor. One such dig~tal signal processor that may be employed is a Fujitsu digital signal processor part number MB-8764-DSP. The transmitting station will contain a digital signal processor and the necessary encode logic.
The receiving station contains the digital signal processor with the decode logic.
Referring to Figures 4 and 5, the encode logic for the T1 line format for CCITT 32 kb/s ADPCM and 64 kb/s clear channel transmission is shown. This logic begins at block 10 and first initializes the 4 indicator bits contained in the last half of channel 23 each to 0, block 20. Next, a 4-bit indicator register is initialized to 0, block 30. This register corresponds to the 4 indicator bits in channel 23 and at the end of the process, the register will be written into the 23rd channel.
An internal counter k is set equal to 1, block 40.
This is the bundle counter. Next, a mapping register is inltialized to the binary value 00000011, block 50. This register will locate the zero octets. Another internal counter i is said equal to 1, block 60. This is the octet counter.
Next, block 70 asks whether the i-th octet is equal to 0. If the particular octet or channel contains 8-bits of 0, the bit corresponding to that octet within the mapping register is set equal to 1, block 72. Next, the bundle indicator bit of the indicator register is set equal to 1 corresponding to the value of the internal octet counter k, block 74. The bundle indicator bits (zero octet indicator bits~ are shown in Figure 2.
Block 80 determines whether the internal octet counter i is equal to 6. If i is equal to 6, then control is passed to block 90 of Figure 5. This indicates that all 6 octets of a particular bundle have been examined for a contents of zero. If the internal indicator i is not equal to 6, then all of the octets or channels of that particular bundle have not been examined. As a result, the internal octet counter i is incremented by 1, block 82. Then, processing control is transferred to block 70. This processing continues until all octets or channels of the S particular bundle have been examined.
Block 90 detarmines whether the indicator register correspondlng to the bundle of octets which were just examined is equal to 0. If the indicator register for this particular bundle is not equal to 0, this indicates that at least one all zero octet exists within the bundle and the first octet or channel of that bundle is temporarily saved in a displacement register, block 92.
Next, the contents of the displacement register are transferred to the first zero octet, block 94. It is important to note that the first zero octet may not necessarily be octet number 1. Each additional zero octet within the particular bundle is set to ' binary 11111111, block 96. Since all zero octets will be recreated at the receiving end of the transmission system, the bits are altered to logic ones in order to provide additional synchronization for the repeaters and transmission equipment. As previously mentioned, the repeaters and transmission equipment require a minimum density of logic ones in order to maintain synchronization.
Ne~t, the contents of the mapping register are copied into octet number 1, block 98. The mapping register contains a 1 in each bit position corresponding to the location of a zero octet in the bundle of 6 octets. Since only the first 6 blts of the mapping register are required for the information about the 6 octets, the other 2 bits of the mapping register may be arbitrarily set. Again, to aid the transmission equipment and repeaters, these bits are arbitrarily set to logic 1.
After the above processing has been complete for the detection of a zero octet within the bundle or if the indicator register showed that no all zero octet was found, block 90, then the bundle counter k is examined to determine whether it is equal to 4, block 100. if the bundle counter k is less then 4, it is 5~3 incremented by 1 block 102, and processing is transferred to block 50 for the processing of the next bundle of octets. if the bundle counter k is equal to 4, all 4 bundles have been processed and processing control is transferred to block 110.
Block 110 tests the 4 bit indicator register to determine whether it is equal to the binary value 0001. This indicates that there is at least one all zero octet conta~ned in the 4th bundle, if the result of the test is positive. Block 120 interrogates the mapping register to determine whether it is equal to the binary pattern 00000111. If the result of this test is also positive, this indicates that the all zero octet is the 6th octet of the bundle. Special processing must occur for this situation.
Since it is known that only the 6th octet of this bundle is all zero~ the contents of the displacement register is copied back into the first octet of bundle 4, block 122. This is necessary since block 92 copied the contents of octet number 1 to the displacement register. The contents of octet 1 must be mo~ed back to avoid losing these contents since it is known that these contents are non-zero.
Next, the binary value 00000000 is moved to the 6th octet of bundle 4, block 124. Again, it is known that this octet was zero because the mapping register had a 1 set in the bit position corresponding to this octet. The last 4-bits of this octet are a don't care function and were set to 0 arbitrarily, since the indicator register will be written into these bits in order to form the zero octet indicator bits as shown in Figure 2.
The value of the zero octet indicator bits is guaranteed to be non-zero at this time.
At the completion of the processing of block 124 or if either of the tests of blocks 110 or 120 were answered in the negative, block 130 copies the indicator register to the last 4 bits of octet number 6 of bundle number 4. If octet number 6 was zeroed by block 124, it was known that the indicator register contained a 1 in the bundle 4 position. Therefore, this indicator register is wrltten over thP last 4 bits of octet number 6 of bundle 4. As a result, this octet will be guaranteed to have at least one logic 1.
The zero octet processing for this frame has been complete. The frame is then transmitted to the conversion logic which places the frame in the AMI format, block 140. The processing for this ~rame is then ended, block 150.
Referring to Figures 6 and 7, the frame/bundle decode logic is shown. The decode logic process i9 initiated at block 200. Block 210 moves the indicator bits from blts 5 through 8 of channel 6 of bundle 4 to an indicator register. Next, the indicator register is examined to detYrmine whether all 4 of the zero octet indicator bits are equal to zero. If all four ~ero octet indicator bits are zero, no channel within the particular frame contains an all zero octet. As a result, the frame is transferred for further processing exactly as it was received. ~o bit modification is required. Therefore, processing control is transferred to block 290, which ends the frame/bundle decode logic for this particular frame.
If the zero octet indicator bits contained ln the indicator register are not all zeroJ processing control is passed to block 240. Block 240 interrogates the 23rd channel or octet 6 of bundle 4 to determine whether the value of this channel is e~ual to the binary value 00000001. For a positive resu~t of the test of block 240, it is known that only channel 6 of bundle 4 was a zero octet in the particular frame. The bundle 4 zero octet indicator bit had previously been set to logic 1. Since this particular logic 1 in the bundle 4 zero octet indicator bit position is not a payload signalJ no modification of the frame need occur. As a result9 control is transferred to block 230 which transmits the fram~ exactly as received for further processing. This processing handles the special case of channel 23 being the only octet with an all zero value. Then, the decode logic processing is ended, block 290.
IE the test of block 240 was answered in the negative, block 250 sets an internal bundle counter k equal to 1. Next, the indicator register is examined to determine whethe- the k-th zero octet indicator bit is equal to 1. It should be remembered that if a particular zero octet indicator bit is equal to 1 there ls at least 1 all zero channel or octet in that particular bundle. If this particular zero octet indicator bit is equal to 1, then block 262 copies the first octet of that bundle to the mspping register.
For bundles in which there is at least one zero octet the first channel or octet contains the mapping for the locations of these octets. Next, the first octet whose mapping register bit is equal to 1 is copied to the displacement register, block 264. Then each octet of the bundle whose mapping register bit is equal to a 1 will have the binary value 00000000 written into that octet, block 280. Next, block 282 determines whether the mapping register bit for the first octet is equal to zero. If the mapping register bit for the ~irst octet is zero, then the displacement regist~r is copied back into the first octet, block 284. This indicates that the first octet of the bundle was non-zero and must be replaced with its original value which was displaced to another location so that the mapping bits could be placed in the first octet of each bundle.
~fter the displacement register has been copied by block 284 or if the question of block 282 is answered in a negative or if the question of block 260 i8 answered in the negative, then processing control is given to block 270. Block 270 determines whether the value of the internal bundle counter k is equal to 4. If ~his test is answered in the negative, the bundle counter k is incremented by 1, block 272. Then, processing control is begun again at block 260. If k i8 less then 4, processing for all 4 bundles comprising the particular frame is not yet complete. If the bundle counter k is equal to 4, then all octets which were originally zero before the transmission have been reconstructed to be zero. Lastly, block 274 transfers the decoded frame for further processing and the decoding process is ended, block 290.
5~3 Although the preferred embodi~ent of the invention has been illustrated, and that f orm described in detail, it will be readily apparent to those skilled in the art that various modifications may be made therein without departing from the spirit of the invention or from the scope of the appended claims.
Claims (12)
1. A T1 line format for transmitting robbed signaling data from one digital switching system to a second digital switching system via T1 line facilities, said T1 line format comprising:
T1 data frame means, said T1 data frame means including a predetermined number of data channel means for transmitting data between said digital switching systems;
each T1 data frame means further including:
a predetermined number of clear channel data channels means;
at least one dedicated channel means for transmitting signaling data and non-clear channel data between said digital switching systems;
said dedicated channel means being operated to transmit said signaling data for a plurality of said clear channel data channels means;
said T1 line format further comprising:
a plurality of said T1 data frame means, each including said plurality of signaling data, said plurality of said T1 data frame means being operated to provide said all signaling data to said second digital switching system by providing a uniform portion of said signaling data during each said T1 data frame means.
T1 data frame means, said T1 data frame means including a predetermined number of data channel means for transmitting data between said digital switching systems;
each T1 data frame means further including:
a predetermined number of clear channel data channels means;
at least one dedicated channel means for transmitting signaling data and non-clear channel data between said digital switching systems;
said dedicated channel means being operated to transmit said signaling data for a plurality of said clear channel data channels means;
said T1 line format further comprising:
a plurality of said T1 data frame means, each including said plurality of signaling data, said plurality of said T1 data frame means being operated to provide said all signaling data to said second digital switching system by providing a uniform portion of said signaling data during each said T1 data frame means.
2. A T1 line format as claimed in claim 1, said predetermined number of data channels means of data channels means of said T1 data frame means is equal to twenty-four (24).
3. A T1 line format as claimed in claim 2, said predetermined number of clear channel data channels means of said T1 data frame means is equal to twenty-three (23).
4. A T1 line format as claimed in claim 3, wherein each said data channel means is eight (8) bits in width.
5. A T1 line format as claimed in claim 4, wherein said dedicated channel means of each T1 data frame means includes at least one signaling data bit.
6. A T1 line format as claimed in claim 4, wherein said dedicated channel means of each T1 data frame means includes a plurality of signaling data bits.
7. A T1 line format as claimed in claim 6, wherein said plurality of signaling data bits of each said portion includes four (4) signaling data bits.
8. A T1 line format as claimed in claim 1, wherein six (6) of said T1 data frame means are operated to provide said signaling data for up to twenty-four (24) of said data channel means.
9. A T1 line format as claimed in claim 7, said signaling data of each said T1 data frame means located in the four (4) most significant bits of the twenty-fourth (24th) data channel means.
10. A T1 line format as claimed in claim 9, said non-clear channel data of each said T1 data means located in the four (4) least significant bits of the twenty-fourth (24th) data channel means.
11. A T1 line format as claimed in claim 10, said signaling data of a first T1 data frame means including one signaling data bit for each of a first four (4) of said data channel means.
12. A T1 line format as claimed in claim 11, said signaling data of each succeeding T1 data frame means of said plurality of T1 data frame means including one signaling bit corresponding to each of a next four (4) of said data channels.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US902,823 | 1978-05-04 | ||
| US90282386A | 1986-09-02 | 1986-09-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1285053C true CA1285053C (en) | 1991-06-18 |
Family
ID=25416453
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000545523A Expired - Fee Related CA1285053C (en) | 1986-09-02 | 1987-08-27 | T1 line format for robbed signaling for use with ccitt 32k bit per second adpcm clear channel transmission |
Country Status (3)
| Country | Link |
|---|---|
| BE (1) | BE1000143A6 (en) |
| CA (1) | CA1285053C (en) |
| IT (2) | IT8721715A0 (en) |
-
1987
- 1987-08-26 IT IT8721715A patent/IT8721715A0/en unknown
- 1987-08-26 IT IT8721713A patent/IT8721713A0/en unknown
- 1987-08-27 CA CA000545523A patent/CA1285053C/en not_active Expired - Fee Related
- 1987-09-02 BE BE8700985A patent/BE1000143A6/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| IT8721713A0 (en) | 1987-08-26 |
| IT8721715A0 (en) | 1987-08-26 |
| BE1000143A6 (en) | 1988-05-10 |
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