CA1270572A - Microprogram control device - Google Patents
Microprogram control deviceInfo
- Publication number
- CA1270572A CA1270572A CA000522823A CA522823A CA1270572A CA 1270572 A CA1270572 A CA 1270572A CA 000522823 A CA000522823 A CA 000522823A CA 522823 A CA522823 A CA 522823A CA 1270572 A CA1270572 A CA 1270572A
- Authority
- CA
- Canada
- Prior art keywords
- instruction
- microprogram
- address
- memory means
- microprogram memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
- G06F9/262—Arrangements for next microinstruction selection
- G06F9/264—Microinstruction selection based on results of processing
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
A microprogram control device controls a data path section provided in a CPU, which operates according to a microcode stored in a microprogram memory, by using a microprogramming method. The control device includes an instruction register for storing an instruction code which is received from a data bus and an address generator for generating an address signal from the output of the instruction register to access the microprogram memory.
The address generator uses a first address decoder for decoding from a particular bit in the instruction code the type of instruction and a second address decoder for decoding from another particular bit of the instruction code the addressing mode of the instruction. A third address decoder is included for designating the timing for accessing the microprogram memory during each instruction cycle.
A microprogram control device controls a data path section provided in a CPU, which operates according to a microcode stored in a microprogram memory, by using a microprogramming method. The control device includes an instruction register for storing an instruction code which is received from a data bus and an address generator for generating an address signal from the output of the instruction register to access the microprogram memory.
The address generator uses a first address decoder for decoding from a particular bit in the instruction code the type of instruction and a second address decoder for decoding from another particular bit of the instruction code the addressing mode of the instruction. A third address decoder is included for designating the timing for accessing the microprogram memory during each instruction cycle.
Description
2~71)57~
The presen-t invention relates to a microprogram control device, and more particularly to that in which the address designation of a microprogram ROM by a successive address designating method is simpliEied by converting only the instruction cycle value oE the successive address from the microprogram ROM.
In the accompanying drawings:-Figure 1 is a block diagram showing a microprogram control device utili~ing a successive addressing method as an embodimen-t of -the present inven-tion;
Figure 2 is a timing chart for exemplifying the operation thereof;
Figure 3 is a block diagram showing the prior art successive addressing system microprogram control device; and Figure 4 is a timing chart for exemplifying the operation thereof.
Figure 3 is a block diagram showing microprogram control by a computer using the conventional successive address designating method described in Electronics, January 27, 1981, pp 107 to pp 111. ~his microprocessor is an 8 bit microcomputer. In Figure 3, reference numeral 1 designates an 8 bit data bus, reEerence numeral 2 designates an instruction register, reference numeral 3 designates an address signal line Eor sending -the content of the instruction register 2 to the multiplexer and address decoder 5. Reference numeral 8 designates an 8 bit signal line to the microprogram ROM 12. Reference numeral 11 designates a successive address 8 bit signal of the microprogram ROM 12 of the next cycle which is output from the microprogram ROM 12. Reference numeral 13 designates a 43 bit control line be-tween the data path section 25 and the microprogram ROM 12. Reference numeral 26 designates a selector signal line for controlling the multiplexer 5.
Figure 4 shows a timing chart of the operation of -the microprogram control device of Figure 3. In Figure ~L~70S~2 4, reference character ~ designates a system clock and reEerence character IF designates an instruction Eetch signal for -taking in the :instruction code to the instruction register ~ from the data bus 1. Reference character IR designates the content of the instruction register 2 such as an operation code taken in from the data bus 1 by the signal IF. Reference character A~l designates an address of the microprogram ROM, and -this address has an 8 bit width. Reference characters Sl to S3 designate -the output of the microprogram ROM 12 for controlling the control line 13 of -the data path section 25.
The operation of the microprogram control will be described with reference to Figures 3 and 4. The timing chart oE Figure 4 is -that in a case where an instruction tfour cycle instruc-tion) is executed by -the microprogram control of Figure 3. Suppose that the' instruction code is a provisional instruction such as AAh (hereinafter the h designates the hexadecimal representation).
In Figure 4, when the IF signal is l'H", an 8 bit instruction code is taken in by the instruction register 2 from the data bus 1. At the next first cycle the output from the successive address designating signal line 11, which is a portion of the microcode from -the microprogram ROM 12, is halted so as to be taken in by the multiplexer and address decoder 5 by the signal oE the selector signal line 26, which signal is a portion of the same microcode.
In this case, the content of the instruction register 2, that is, the 8 bit instruction code, becomes -the address of the microprogram ROM 12 through the multiplexer 5 (AAh in Figure 4), and it outputs a control signal to the data path section 25 in accordance with the microcode.
At the second cycle, as the address to be input to the microprogram ROM 12 the previous cycle 8 bit successive address from the microprogram ROM 12 is obtained because the input of the multiplexer 5 is switched in accordance with the selector signal 26. By .`7f ~
~;~7~)57~
this method it is possible to obtain a random value as the successive address.
In the cycles subsequent thereto, the address output at the previous cycle is input to the microprogram ROM 12 to conduct a control successively until this instruction is concluded. In Figure 4, as the Adl AAh A3h B4h C5h can be output in turn from the first cycle.
In such a prior art successive address designating system, in a case where the bit width of the instruction code is in the 8 bit class, the con-trol cannot be conducted when the number of combinations of the control pattern (control lines of 43 bits) for controlling the CPU becomes larger than 256.
Accordingly, in a case where a bit width of the instruc-tion code of a microcontroller or microprocessor is larger than 8 bits, for example, 16 bits, it is quite ineffective to utilize the access method against the microprogram ROM 12 in which the successive address has a 16 bit width similarly as the prior art method of Figure
The presen-t invention relates to a microprogram control device, and more particularly to that in which the address designation of a microprogram ROM by a successive address designating method is simpliEied by converting only the instruction cycle value oE the successive address from the microprogram ROM.
In the accompanying drawings:-Figure 1 is a block diagram showing a microprogram control device utili~ing a successive addressing method as an embodimen-t of -the present inven-tion;
Figure 2 is a timing chart for exemplifying the operation thereof;
Figure 3 is a block diagram showing the prior art successive addressing system microprogram control device; and Figure 4 is a timing chart for exemplifying the operation thereof.
Figure 3 is a block diagram showing microprogram control by a computer using the conventional successive address designating method described in Electronics, January 27, 1981, pp 107 to pp 111. ~his microprocessor is an 8 bit microcomputer. In Figure 3, reference numeral 1 designates an 8 bit data bus, reEerence numeral 2 designates an instruction register, reference numeral 3 designates an address signal line Eor sending -the content of the instruction register 2 to the multiplexer and address decoder 5. Reference numeral 8 designates an 8 bit signal line to the microprogram ROM 12. Reference numeral 11 designates a successive address 8 bit signal of the microprogram ROM 12 of the next cycle which is output from the microprogram ROM 12. Reference numeral 13 designates a 43 bit control line be-tween the data path section 25 and the microprogram ROM 12. Reference numeral 26 designates a selector signal line for controlling the multiplexer 5.
Figure 4 shows a timing chart of the operation of -the microprogram control device of Figure 3. In Figure ~L~70S~2 4, reference character ~ designates a system clock and reEerence character IF designates an instruction Eetch signal for -taking in the :instruction code to the instruction register ~ from the data bus 1. Reference character IR designates the content of the instruction register 2 such as an operation code taken in from the data bus 1 by the signal IF. Reference character A~l designates an address of the microprogram ROM, and -this address has an 8 bit width. Reference characters Sl to S3 designate -the output of the microprogram ROM 12 for controlling the control line 13 of -the data path section 25.
The operation of the microprogram control will be described with reference to Figures 3 and 4. The timing chart oE Figure 4 is -that in a case where an instruction tfour cycle instruc-tion) is executed by -the microprogram control of Figure 3. Suppose that the' instruction code is a provisional instruction such as AAh (hereinafter the h designates the hexadecimal representation).
In Figure 4, when the IF signal is l'H", an 8 bit instruction code is taken in by the instruction register 2 from the data bus 1. At the next first cycle the output from the successive address designating signal line 11, which is a portion of the microcode from -the microprogram ROM 12, is halted so as to be taken in by the multiplexer and address decoder 5 by the signal oE the selector signal line 26, which signal is a portion of the same microcode.
In this case, the content of the instruction register 2, that is, the 8 bit instruction code, becomes -the address of the microprogram ROM 12 through the multiplexer 5 (AAh in Figure 4), and it outputs a control signal to the data path section 25 in accordance with the microcode.
At the second cycle, as the address to be input to the microprogram ROM 12 the previous cycle 8 bit successive address from the microprogram ROM 12 is obtained because the input of the multiplexer 5 is switched in accordance with the selector signal 26. By .`7f ~
~;~7~)57~
this method it is possible to obtain a random value as the successive address.
In the cycles subsequent thereto, the address output at the previous cycle is input to the microprogram ROM 12 to conduct a control successively until this instruction is concluded. In Figure 4, as the Adl AAh A3h B4h C5h can be output in turn from the first cycle.
In such a prior art successive address designating system, in a case where the bit width of the instruction code is in the 8 bit class, the con-trol cannot be conducted when the number of combinations of the control pattern (control lines of 43 bits) for controlling the CPU becomes larger than 256.
Accordingly, in a case where a bit width of the instruc-tion code of a microcontroller or microprocessor is larger than 8 bits, for example, 16 bits, it is quite ineffective to utilize the access method against the microprogram ROM 12 in which the successive address has a 16 bit width similarly as the prior art method of Figure
3. Furthermore, in this case as the control pattern for controlling the data path section 25, 216 kinds of successive addresses can be output, but such a system is not practical. Furthermore, the instruction code in the microcontroller or the microprocessor are often constituted by such an instruction type designating bit as an operation instruction, a transfer instruction, or a jump instruction, or an addressing mode designa-ting bit.
Especially when the instruction code width is in the 16 bit class, the instruction type and the addressing mode are used qui-te often, and a sufficient performance cannot be accomplished by the prior art successive address designating method.
An object of the present invention is to provide an improved microprogram control device wherein a successive address designating method of the microprogram ROM is simply realized in an integrated circuit even if the bit number of the instruc-tion code and the number of the data bus control (the number of the control pattern) ~7~35~
are increased.
Other objects and advantages o.E the present invention will become apparent from -the detailed description given hereina:Eter; it should be understood, however, that the detailed description and specific embodiment are given by way of illustration only, since various changes and modifications within the spirit and scope oE the invention will become apparent to those skilled in the art from this detailed description.
According to the present invention, there is provided a microprogram control device for controlling a data path section provided in a CPU, comprising:
microp:rogram memory means for storing microcode, said microcode corresponding to operations of -the CPU;
instruction regis-ter means for storing an instruction reduction code which is received from a data bus, said instruction code representing an instruction;
address generating means, operatively connected to said instruction register means and said microprogram memory means, for generating an address, to access said microprogram memory means, from an output o-f said instruction register means;
said address generating rneans including, first address decorder means for decoding a particular bit in said instruction code to determine an instruction type, and second address decoder means for decoding another particular bit in said instruction code, to determine an addressing mode; and third address decoder means, opera-tively connected to said microprogram memory means, for designating timing for accessing said microprogram memory means during each instruction cycle;
said microprogram memory means having outputs for outputting said microcode, said microcode not being directly fedback into inputs of said microprogram memory means.
In Figure 1, which as indicated above ~.~7~S~
r illustrates an embodiment o.E the present invention, reference numeral 1 designates a data bus, numeral 2 designates an instructlon register, nume:ral 12 designates a microprogram ROM, and numerals 5 and 6 designate a :Eirst and a second address decoder which receives the instruction code in the inskruction register 2 and generates addresses for the microprogram ROM 12.
Reference numerals 17 to 20 designate circuits for decoding the output mic:rocode of the microprogram ROM 12 against each control bit on the da-ta path section 25 (hereinafter re:Eerred to as nano-program memory; nROM).
Reference numerals 21 to 24 designa-te output signal lines from the ROM to the data path section 25. Reference numerals 13 to 16 designate output signal lines from the microprogram ROM 12 to the nROMs 17 to 20. Reference numeral 7 designa-tes a decoder for receiving the output of the microprogram ROM 12 and designa-ting the successive address for designating -the cycle value of -the instruction.
Furthermore, Reference numeral 11 designates a successive address signal line from the microprogram ROM
12, and reference numerals 8 to 10 designate address output lines (AD10, AD20, AD30) from the address decoders 5 to 7 to the microprogram ROM 12. In this embodiment the successive address designation is conducted by the address decoder 7. Reference numeral 4 designates a signal line for sending the instruction code from the instruction register 2 to the ROMs 17 to 20.
Nex-t, -the operation o.E this microprogram control device will be described. Figure 2 shows a timing chart in executing an instruction (4 cycle inst:ruction) as the microprogram control of Figure 1. Suppose that the instruction code is a provisional instruction of A~h.
In Figure 2, when the IF signal is "H", a 16 bit instruction code from the data bus 1 is taken in into -the instruction register 2. A-t the next cycle components relating to the instruction type and the addressing mode are extracted from the ins-truction code which is taken in 57~
into the instruction register 2, and it is ~made an addres.s of the microprogram ROM 12. In Figure 2, the first cycle outputs are made, Eor example, ~Oh and BOho This value is held until the instruction is concluded. The Eirst cycle address decoder 7 takes out a microcode from the microprogram ROM 12 so as to enable oE setting the address at a cycle value (lh in Figure 2) at which the instruction is started.
In the cycles subsequent -thereto, that is, in the second, the -third, and the fourth cycles, the successive addresses are output from a portion of the microprogram ROM 12 successively. For example, the successive addresses are 3h 5h 6h as shown in Figure 2.
At each cycle the output from the microprogram ROM 12 is sent to the nROMs 17 to 20, and these are combined with a portion of the instruction code of the instruction register 2 to genera-te a control signal to be sent -to the data path section 25.
In this embodimen-t, the address input oE the microprogram ROM comprises three components of an instruction type, an addressing mode both separated from the instruction code, and an instruction cycle value output from the microprogram ROM, and the successive address designation Erom the microprogram ROM is conducted by only the instruction cycle value. Accordingly, it is possible to prevent the increase in the bit number of the microcodes for designating the successive addresses of the microprogram ROM even if the bit number oE instruction codes oE a microcomputer or microcontroller is increased in a case where the successive address designating method is used. This results in that a microcomputer or microcontroller which utilizes the successive address designating method with an increased bit number of instruction codes is easily realized on integrated circuits. Fur-thermore, it results in a tremendously efficient development of a microcomputer~
Especially when the instruction code width is in the 16 bit class, the instruction type and the addressing mode are used qui-te often, and a sufficient performance cannot be accomplished by the prior art successive address designating method.
An object of the present invention is to provide an improved microprogram control device wherein a successive address designating method of the microprogram ROM is simply realized in an integrated circuit even if the bit number of the instruc-tion code and the number of the data bus control (the number of the control pattern) ~7~35~
are increased.
Other objects and advantages o.E the present invention will become apparent from -the detailed description given hereina:Eter; it should be understood, however, that the detailed description and specific embodiment are given by way of illustration only, since various changes and modifications within the spirit and scope oE the invention will become apparent to those skilled in the art from this detailed description.
According to the present invention, there is provided a microprogram control device for controlling a data path section provided in a CPU, comprising:
microp:rogram memory means for storing microcode, said microcode corresponding to operations of -the CPU;
instruction regis-ter means for storing an instruction reduction code which is received from a data bus, said instruction code representing an instruction;
address generating means, operatively connected to said instruction register means and said microprogram memory means, for generating an address, to access said microprogram memory means, from an output o-f said instruction register means;
said address generating rneans including, first address decorder means for decoding a particular bit in said instruction code to determine an instruction type, and second address decoder means for decoding another particular bit in said instruction code, to determine an addressing mode; and third address decoder means, opera-tively connected to said microprogram memory means, for designating timing for accessing said microprogram memory means during each instruction cycle;
said microprogram memory means having outputs for outputting said microcode, said microcode not being directly fedback into inputs of said microprogram memory means.
In Figure 1, which as indicated above ~.~7~S~
r illustrates an embodiment o.E the present invention, reference numeral 1 designates a data bus, numeral 2 designates an instructlon register, nume:ral 12 designates a microprogram ROM, and numerals 5 and 6 designate a :Eirst and a second address decoder which receives the instruction code in the inskruction register 2 and generates addresses for the microprogram ROM 12.
Reference numerals 17 to 20 designate circuits for decoding the output mic:rocode of the microprogram ROM 12 against each control bit on the da-ta path section 25 (hereinafter re:Eerred to as nano-program memory; nROM).
Reference numerals 21 to 24 designa-te output signal lines from the ROM to the data path section 25. Reference numerals 13 to 16 designate output signal lines from the microprogram ROM 12 to the nROMs 17 to 20. Reference numeral 7 designa-tes a decoder for receiving the output of the microprogram ROM 12 and designa-ting the successive address for designating -the cycle value of -the instruction.
Furthermore, Reference numeral 11 designates a successive address signal line from the microprogram ROM
12, and reference numerals 8 to 10 designate address output lines (AD10, AD20, AD30) from the address decoders 5 to 7 to the microprogram ROM 12. In this embodiment the successive address designation is conducted by the address decoder 7. Reference numeral 4 designates a signal line for sending the instruction code from the instruction register 2 to the ROMs 17 to 20.
Nex-t, -the operation o.E this microprogram control device will be described. Figure 2 shows a timing chart in executing an instruction (4 cycle inst:ruction) as the microprogram control of Figure 1. Suppose that the instruction code is a provisional instruction of A~h.
In Figure 2, when the IF signal is "H", a 16 bit instruction code from the data bus 1 is taken in into -the instruction register 2. A-t the next cycle components relating to the instruction type and the addressing mode are extracted from the ins-truction code which is taken in 57~
into the instruction register 2, and it is ~made an addres.s of the microprogram ROM 12. In Figure 2, the first cycle outputs are made, Eor example, ~Oh and BOho This value is held until the instruction is concluded. The Eirst cycle address decoder 7 takes out a microcode from the microprogram ROM 12 so as to enable oE setting the address at a cycle value (lh in Figure 2) at which the instruction is started.
In the cycles subsequent -thereto, that is, in the second, the -third, and the fourth cycles, the successive addresses are output from a portion of the microprogram ROM 12 successively. For example, the successive addresses are 3h 5h 6h as shown in Figure 2.
At each cycle the output from the microprogram ROM 12 is sent to the nROMs 17 to 20, and these are combined with a portion of the instruction code of the instruction register 2 to genera-te a control signal to be sent -to the data path section 25.
In this embodimen-t, the address input oE the microprogram ROM comprises three components of an instruction type, an addressing mode both separated from the instruction code, and an instruction cycle value output from the microprogram ROM, and the successive address designation Erom the microprogram ROM is conducted by only the instruction cycle value. Accordingly, it is possible to prevent the increase in the bit number of the microcodes for designating the successive addresses of the microprogram ROM even if the bit number oE instruction codes oE a microcomputer or microcontroller is increased in a case where the successive address designating method is used. This results in that a microcomputer or microcontroller which utilizes the successive address designating method with an increased bit number of instruction codes is easily realized on integrated circuits. Fur-thermore, it results in a tremendously efficient development of a microcomputer~
Claims (4)
EXCLUSIVE PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS
FOLLOWS:
1. A microprogram control device for controlling a data path section provided in a CPU
comprising:
microprogram memory means for storing microcode, said microcode corresponding to operations of the CPU;
instruction register means for storing an instruction reduction code which is received from a data bus, said instruction code representing an instruction;
address generating means, operatively connected to said instruction register means and said microprogram memory means, for generating an address, to access said microprogram memory means, from an output of said instruction register means;
said address generating means including, first address decoder means for decoding a particular bit in said instruction code, to determine an instruction type, and second address decoder means for decoding another particular bit in said instruction code, to determine an addressing mode; and third address decoder means, operataively connected to said microprogram memory means, for designating timing for accessing said microprogram memory means during each instruction cycle;
said microprogram memory means having outputs for outputting said microcode, said microcode not being directly fedback into inputs of said microprogram memory means.
comprising:
microprogram memory means for storing microcode, said microcode corresponding to operations of the CPU;
instruction register means for storing an instruction reduction code which is received from a data bus, said instruction code representing an instruction;
address generating means, operatively connected to said instruction register means and said microprogram memory means, for generating an address, to access said microprogram memory means, from an output of said instruction register means;
said address generating means including, first address decoder means for decoding a particular bit in said instruction code, to determine an instruction type, and second address decoder means for decoding another particular bit in said instruction code, to determine an addressing mode; and third address decoder means, operataively connected to said microprogram memory means, for designating timing for accessing said microprogram memory means during each instruction cycle;
said microprogram memory means having outputs for outputting said microcode, said microcode not being directly fedback into inputs of said microprogram memory means.
2. The microprogram control device as claimed in Claim 1, further comprising code decoding means for operatively connected to said microprogram memory means, for decoding said microcode, said microcode including a combination of microcode read from said microprogram memory means according to an address designation generated by said first, second and third address decoder means and a bit in said instruction code, to control each block of the data path section.
3. The microprogram control device as claimed in Claim 1, wherein said microprogram memory means is accessed for each cycle of said instruction by a successive address designating method wherein a decoder portion of the previous cycle's output of said microprogram memory means constitute a portion of the address component of the next cycle.
4. A microprogram control device as claimed in Claim 1, wherein the control device is provided on a semiconductor integrated circuit.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25727985A JPS62117038A (en) | 1985-11-15 | 1985-11-15 | Microprogram controller |
| JP60-257279 | 1985-11-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1270572A true CA1270572A (en) | 1990-06-19 |
Family
ID=17304166
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000522823A Expired - Lifetime CA1270572A (en) | 1985-11-15 | 1986-11-13 | Microprogram control device |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPS62117038A (en) |
| CA (1) | CA1270572A (en) |
| GB (1) | GB2184578B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3788877T2 (en) * | 1987-03-24 | 1994-06-23 | Insignia Solutions Ltd | DEVICE FOR SOFTWARE EMULATION. |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS531432A (en) * | 1976-06-28 | 1978-01-09 | Nec Corp | Information processing unit |
| JPS57168345A (en) * | 1981-04-09 | 1982-10-16 | Hitachi Ltd | Data processing device |
| GB2099618B (en) * | 1981-06-02 | 1985-07-03 | Tektronix Inc | Algorithmic word generator |
| IT1153668B (en) * | 1982-11-24 | 1987-01-14 | Honeywell Inf Systems | CONTROL MEMORY ORGANIZATION |
| NL8205076A (en) * | 1982-12-31 | 1984-07-16 | Philips Nv | DATA PROCESSOR UNIT EQUIPPED WITH A CONTROL PART INCLUDING AN ADDRESS GENERATOR FOR GENERATING ADDRESSES COMPOSED OF CHARACTERISTIC ADDRESS PARTS. |
| JPS59220842A (en) * | 1983-05-27 | 1984-12-12 | Nec Corp | Data processor |
| JPS61170828A (en) * | 1985-01-24 | 1986-08-01 | Hitachi Ltd | Microprogram control device |
-
1985
- 1985-11-15 JP JP25727985A patent/JPS62117038A/en active Pending
-
1986
- 1986-11-13 CA CA000522823A patent/CA1270572A/en not_active Expired - Lifetime
- 1986-11-14 GB GB8627257A patent/GB2184578B/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| GB2184578B (en) | 1989-10-04 |
| JPS62117038A (en) | 1987-05-28 |
| GB8627257D0 (en) | 1986-12-17 |
| GB2184578A (en) | 1987-06-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4954943A (en) | Data processing system | |
| CA2313013C (en) | An instruction decoder | |
| US5046040A (en) | Microprogram control apparatus using don't care bits as part of address bits for common instructions and generating variable control bits | |
| KR920007253B1 (en) | Controlling apparatus for micro-program | |
| US4674063A (en) | Information processing apparatus having a sequence control function | |
| US5390306A (en) | Pipeline processing system and microprocessor using the system | |
| US5301338A (en) | System including central processing unit | |
| CA1270572A (en) | Microprogram control device | |
| US4831572A (en) | Polynomial vector arithmetic operation control system | |
| US5142630A (en) | System for calculating branch destination address based upon address mode bit in operand before executing an instruction which changes the address mode and branching | |
| US5345570A (en) | Microprogram control circuit | |
| EP0156162B1 (en) | Programmable controller | |
| US5454088A (en) | Microprogram control device for controlling data path section including designation of instruction cycle values | |
| US4959780A (en) | Microprogram processor with logic circuitry for combining signals from a microcode decoder and an instruction code decoder to produce a memory access signal | |
| JPH1091430A (en) | Instruction decoding device | |
| US5463747A (en) | Microprogram data processor processing operand address calculation and instruction execution with common hardware | |
| JP2826309B2 (en) | Information processing device | |
| JPS6226486B2 (en) | ||
| JP2637070B2 (en) | Micro instruction start address generation method | |
| JP3190945B2 (en) | Micro program control circuit | |
| US5109516A (en) | Sequence controller for controlling next operating state with a short sequence | |
| KR940000221B1 (en) | Ladder command processor apparatus | |
| JP3023959B2 (en) | Undefined instruction detection method | |
| JP3024410B2 (en) | Programmable controller | |
| JPH0128965B2 (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |