CA1268539A - Digital television receiver with digital video processing circuit - Google Patents

Abstract

Abstract of the Disclosure A digital TV receiver includes an A/D converter circuit for converting an analog video signal to a digital video signal, a signal separator circuit for separating a digital chroma signal and a digital Y signal from the digital video signal, a colour killer circuit for gating the digital chroma signal to generate a gated C signal when burst components are containing in the digital chroma signal, and a processor circuit for digitally composing RGB signals from the digital Y signal and the gated C signal. The RGB signals are used as tricolour signals for a colour CRT. The digital Y signal is composed from a delayed digital video signal and a digital Y signal obtained by removing the digital chroma signal from the delayed digital video signal.

Description

The present invention relates to a digital television receiver for performing digital processing of a base~band video signal and, more particularly, to a diyital television receiver for improving video resolution when the receiver is operating in a colour killer mode.

In a conventional television receiver, all signals are analog processed. Analog signal processing, however, has problems at the video stage and thereafter. These problems stem from the general drawbacks of analog signal processing with regard to time-base operation, speciEically, incomplete Y/C separation (which causes cross colour and dot interference), various problems resulting in degraded picture quality, and low precision of synchronization. Furthermore, from the viewpoints of cost and ease of manufacture of the analoy circuit, a hybrid configuration must be employed even if the circuit is primarily comprised by an IC. In addition to these disadvantages, many adjustments must be performed to set up the circuit.

In order to address the above problems, it is proposed to process all signals in a digital form from the video stage to the chrominance signal demodulation stage. In such a digital television receiver, improvements in picture quality should result due to the advantages of digital signal processing.

It is accordingly an object of the present invention to provide a digital television receiver having an improved colour killer rneans, and with the capability of improving picture quality, especially resolution, of a picture when the receiver is operating in a colour killer mode.

According to the invention there is provided a digital television receiver comprising :

3~
~ 2 digital converter means for converting an analog video signal to a digital video signal;
signal separator means coupled to said digital converter means, for separatinq a digltal chrominance signal and a digital luminance signal from said digital vldeo signal wherein said signal separator means includes:
(a) de~ay means for delaying said digital video signal by a given amount ko provide a delayed video signal;
(b) Y/C separator means coupled to said delay means for separating said digital chrominance signal and an unprocessed luminance signal from said delayed video signal;
and (c) Y processor means coupled to said delay means and said Y/C separator means, for composing said digital luminance signal from said delayed video signal and said unprocessed luminance signal;
colour killer means coupled to said signal separator means and being responsive to burst components of said digital chrominance signal, for gating said digital chrominance signal to generate a gated colour signal when said burst components are contained in said digital chrominance signal; and processor means coupled to said signal separator means and to said colour killer means, for dlgitally composing RGB signals ~rom said digital luminance signal and said ga~ed colour s.ignal, said RGB signals beiny used as tricolour signals for a co].our picture tube.

~ y composing the digital luminance signal in this manner, the characteristics of the signal may be varied according to whether a chrominance signal is present (allowing a broader bandwidth to be obtained when no chrominance signal is present), and various corrections can be applied to the lumi.nance signal.

353~3 ~ he drawings show the preferred embodiment o:E -the present invention, in which :

Fig. 1 shows the overall confi.guration of the video signal processing circuit;

Fig. 2 shows the configuration of the PLL circuit 53~3 of Fig. l;
Fig. 3 is a waveform showing sampled points of the color burs-t;
Fig. 4 is a block diagram showing the configuration S of the Y/C separator of Fig. l;
Fig, 5 shows waveforms for explaining charac--teristics of the comb filter;
Fig. 6 shows the detailed configuration of the NTSC/PAL switching circuit of E'lg. 4;
Fiy. 7 shows the detailed configuration of the Y signal processing circui-t of Fig. l;
Fig. 3 shows the detailed configuration of the vertical contour circuit of Fig. 7;
Fig. 9 shows the detailed conflguration of -the horizontal contour circuit of Fig. 7;
Fig. 10 shows diagrams for explaining the relation-ship among the pic-ture, the horizon-tal frequency and the ver-tical frequency;
Fig. 11 is a diagram Eor explaining the two-dimensional frequency;
Fig. 12 i.s a diagram showing the -television signal in the two-climensional frequency form;
Fig. 13 shows the de-tailed configuration of the contrast circuit of Fig. 7;
Fig. 13A shows -the circui-t configuration of LPF1336 shown in Fig. 13;
Fig. 14 shows -the overall configuration of the 353~

color control/color killer circuit oE Fig. l;
Fig. 15 shows the detailed configuration of the circuit shown in Fig. 14;
Fig, 16 shows the detailed configuration of the chrominance signal demodulator of Fig. l;
Fig. 17 shows a block configuration of an RGB matrix of ~'ig. ~;
Fig. 18 shows an example of a burst extraction circuit of Fig. 2;
Fig. 19 shows an example of a LPF of Fig. 2;
Fig. 20 shows an example of a pedestal clamp circult of Fig. 7;
Fig. 21 shows an example of a burst extraction circuit of Fig. 15;
Fig. 22 shows an example of an absolute value circuit of Fig. 15; and Fig. 23 shows an example of an underflow prevention circuit of Fig. 15.
Fig. 1 is a block diagram showing -the overall configura-tion of a video signal processing circui-t 100 for demodulating a base--band analog video signal by digital signal processing, thereby ob-taining an analog RGB signal. Throughout in the drawings, a thin line indicates an analog signal line or a one-bit digital signal line, and a thick line indicates a line of a quantized digital signal having a plurali-ty of bits. The digi-tal television receiver of the embodiment according -to the presen-t invention can demodulate both NTSC and PAL video signals. Either the NTSC or the PAL signal mode may be manually selected. A general description of video signal processing circuit 100 will be made with reference to Fig. 1, and the detailed configuration will then be described.
(1) A/D Conversion and Clamp Circuit System, PLL
Clrcuit System, Sync and Timing Circuit System An analog video signal 101 inputted to video signal processing circuit 100 is supplied to a low-pass filter (to be referred to as LPF hereinafter) 103 through a buffer 102. LPF 103 serves to eliminate high-fre~uency noise which results in a foldover distortion when an A/D converter (to be referred to as A/D hereinafter) 109 performs prescribed signal sampling. An output from LPF 103 is supplied to an adder 105 through a buffer 10~ and is added to an analog clamp signal 106 therein. A composite signal 107 obtained from adder 105 is supplied to A/D 109 through an amplifier 108. A/D 109 samples an inputted composi-te signal E108 and converts it into a digital video signal 110. Amplifier ]08 serves to amplify the amplitude of signal 107 in order to fully use a dynamic range of A/D 109.
A feedback control loop is constituted by, in order, A/D 109, a clamp circuit 112, a D/A converter 3~3 (to be referred to as D/A hereinafter) 114, adder 105, amplifier 108, and A/D 109. This control loop serves to set the pedestal level of digital vldeo signal 110 outputted from A/D 109 to a prede-termined target value.
In the control loop, clamp circuit 112 receives digital video signal 110 from A/D 109 and a burst extraction pulse 111 from a sync separator/timing generator 122 to be described later. In clamp circuit 112, an average value (pedestal level) of the burst component of digital video signal 110 is detected, a difference between the obtained pedestal level and the target value is detected, and the detected differ-ence is produced as an error signal 113. Error signal 113 is converted by D/A 114 into analog clamp signal 106. Signal 106 is added by adder 105 (described above) to the output signal from buffer 104. As a result, a DC component of composite video signal 107 from adder 105 changes such that the pedestal level of signal 107 comes close to the target value. Signal 107 is then converted into digital video signal 110 through amplitude control amplifier 108 and sampling A/D 109.
Digital video signal 110 is again supplied to clamp circuit 112, so that error signal 113 is detected again. Thus, pedestal clamping is performed.
On the other hand, A/D 109 samples the inputted signal in response to a sampling pulse (~Ps) 116 from a voltage-controlled quartz oscillator (to be referred s~ ~

to as VCXO hereinafter) 115. In this embodlmen-t, the frequency fS f sampling pulse (~S) 116 is preset -to 4fSC (where fSC is the frequency of the chrominance subcarrier: fSC = 3.58 MHz in NTSC and fSC = ~ 43 MHz in PAL). The hue components of the NTSC and PAL
chrominance signals are respectively phase-modulated in response to the corresponding chrominance subcarriers.
Therefore, the phase relationship between the sampling pulse (~S) 116 and the color burst determines an axis for demodulating the chrominance signal. This relation-ship thus determines the hue of the picture. For these reasons, the phase of sampling pulse (~S) 116 must be locked with that of the color burst. This control is performed by a phase-locked loop (PLL) constituted by, in order, A/D 109, a phase detector 118, a D/A 120, VCXO 115, and A/D 109. The control steps of this PLL
loop are as follows.
Digital video signal 110 and burst extraction pulse 111 are supplled to phase detector 118. Phase detector 118 extracts the color burst component of video signal 110 in response to burst extraction pulse 111.
A difference (~ - ~0) between an actual sampling phase (~) of the color burst component and the phase target value 117 (90) is detected. The difference (3 - ~o) is produced as a phase error signal 119. In practice, phase error signal 119 has a magnitude corre-sponding to sin(~ - ~0) to be described later. Phase 353~3 g error slgnal 119 is converted by D/A 120 to an analog error signal which is applied as a VC~O control voltage 121 to VC~O 115. Therefore, the phase of sampling pulse (~S) 116 is controlled to come close to that 5 of phase target value (~0) 117. When phase target value (~0) 117 changes, hue control is performed (the detailed configuration of the PLL circuit will be described later). Sampling pulse (~S) 116 is used as a re~erence signal in the video signal processing circuit 100.
Sync separator/-timing generator 122 receives digital video signal 110 and generates a horizontal/ver-tical sync signal 123 as well as burst extraction pulse 111 in accordance with a prescribed operation. Burst extraction pulse 111 is supplied to clamp circuit 112 and phase detector 118, and horizontal/vertical sync signal 123 is supplied to a count-down circuit 124.
Count-down circuit 124 counts down sampling pulse (~Ps) 116 and produces a horizontal/vertical sync pulse 125.
Horizontal/vertical sync pulse 125 ls used to drive a CRT through a sync driver (not shown).
The sampling phase, pedestal level and amplitude of diyital video signal 110 are controlled as mentioned above. Controlled digital video signal 110 is then supplied to an RGB demodulation/picture quality control system to be described below.

~L~6~5~5~

(2) RGB Demodulation/Picture Quality Control System A 2TH delay circuit 126 receives digital video signal 110 and delays it by OTH, lTH and 2TH (TH: one hori~ontal period), respectively, to generate delayed signals 127.
Delayed signa.ls 127 are used for various operations which employ line correlation to be performed later.
It should be noted that the sampling frequency fS = 4fSC
is given so that NTSC fS = 910 fH and PAL fS = 1135 fH, and that the NTSC signal requires a delay time corre--sponding to 910 bits and the PAL signal requires a delay time corresponding to 1135 bits (where fH: horizontal fre~uency = l/TH). Delayed signals 127 are supplied to a lurninance signal/chrominance signal separator (to be referred to as a Y/C separator) 128 and a Y signal processing circuit 129.
Y/C separator 128 has a comb filter for performing a line correlation operation using the OTH-, lTH- and 2T~I-delayed slgnals 127, and a band-pass fi.lter (to be referred to as BPF hereinafter) having a gain of "1"
for f = f~c~ The comb filter and the band-pass filter separate a chrominance signal (-to be referred -to as C signal hereinafter) 130 from delayed signals 127.
C signal 130 is then subtrac-ted from the lTH-delayed signal among delayed signals 127, thereby obtaining a luminance signal (to be referred to as Ysignal herein-after) 131 (to be described in detail later).

~ ~.2~35~3 Y signal processing circuit 129 receives delayed signals 127, Ysignal 131 and an externally supplied picture quality control signal 132. ~ siynal processing circuit 129 processes Ysignal 131 such that -the horizontal and vertical contours, contrast, and bright-ness of Ysignal 131 are corrected. Y signal processing circuit 129 then produces an updated Y signal 133. It should be noted that a flyback pulse 134 is used for contrast correction (to be described in detail later).
C signal 130 is supplied to a color control/color killer 135. Color con-trol/color killer 135 detects the burst amplitude of C signal 130 and performs color control/killer operation in accordance with this burst amplitude. A color killer signal 137 obtained by the operation of color control/color killer 135 is supplied to Y/C separator 128. In the color killer mode, the video signal per se is produced as Ysignal 131 so as to widen the bandwidth of Ysignal 131. :[n color control/color killer 135, the amplitude (color saturation) of C signal 130 is also controlled in accordance with an externally supplied color control signal 136 (to be described in detail later).
A C signal 138 from color control/color killer 135 is supplied -to a chrominance signal clemodula-tor 139.
Chrominance signal demodulator 139 demodulates C signal 138 in synchronism with a chrominance signal demodulation control pulse 140 outputted from phase detector 118.

:~2~ 3~

In general, the sampling phase oE A/D 109 is se-t along the I~ and Q-axes in the MTSC system and along -the U- and V-axes in the PAL system. Demodulated C signals 141 produced by chrominance signal demodulato~ 139 are I and Q signals in the NTSC mode or U and V signal in the PAL mode (to be described in detail later).
Y signal 133 and demodulated C signals 141 are supplied to an ~GB matrix circuit 142 in which signals 133 and 141 are multiplied with a predetermined demo~ula-tion coefficient and are then added to each other, thereby obtaining an RGB signal 1~3. RGB signal 143 is converted by a D/A 144 to an analog RGB signal 145. Signal 145 is supplied to the CRT through an RGB
output circuit (not shown).
It should be noted that the PAL and NTSC siynals are switched when an NTSC/PAL switching signal 146 is supplied to a given circuit.
The main circuits in video signal processing circuit 100 in Fig. 1 will now be described in detail.
(PLL Circuit) Fig. 2 shows a detailed configuration of a PLL cir-cuit 200 including phase detector 118. PLL circuit 200 serves to lock the phase of sampling pulse (~Ps) 116 with the burst phase of signal E108, and to control the hue of the picture by using phase target value 117 being variable. Referring to Fig. 2, digital video signal 110 is supplied to a burst extractor 201 of phase ~6~ 9 detector 118 and is gated by extractor 201 in accordance with burst extraction pulse 111, so that a color burst 202 is extracted. Color burst 202 is supplied to a phase error operation circuit 203. A typical example of the phase error operation is described in detail in, for example, U.S.P. No. 4,291,332. Fig. 3 is a waveform for explaining this phase error operation. Sampled points Pl, P2,..., and P4k of the color burst component are illustrated. Color burst 202 in Fig. 2 is regarded as a data array of sampled points Pl to P4k. Sampled points Pl to P4k are obtained by sampling a point being phase-shifted by 0 from the burst phase for every 90.
Therefore, the sampled points can be given as follows:

4n-3 = a + b~sin~
4n-2 = a + b-sin(~ + gOO

4n-1 = a + b-sin(~ -~ 180) P4n = a + b-sin(~ + 270), for n = 1 to k When the target sampling phase is given as ~0, the following equation holds:
n-l( 4n-3 P4n_l) n~l(P4n_2 P4n)tan~0 = 2kbsin(~ - 00)/cosaO --(1) The righ-t-hand side of equation (1) is a function of (~ - ~0) and can be considered to be a phase error signal 204. The left-hand side of equat:ion (1) indicates the operation for obtaining phase error signal 204. When the operation indicated by the left-hand side of equation (1) is performed, phase error signal 204 of equation (1) is obtained. In the left-hand side o:E equati.on (1), da-ta of the sampli.ng phase ~0 is in the form of tan~0, so that the value tan~0 is used as phase target value 117 instead of the targe-t sampling phase ~0. When -the reference sampling phase of the NTSC signal is taken along the I-axis, the target sampling phase ~0 is -57.
Phase target value 117 is thus tan30 = -1.54. On the other hand, when the reference sampling phase of the PAL signal is taken along the - U-axis (lS0), since the burst phase is shifted by 1~0 _45for every line, the target sampling phase ~0 is +45. Therefore, phase target value 117 must be switched by tan00 = +1 for every line. This switching is detected by determining the sampling phase of the color burst to be +45 or -45.
l'he switching signal is produced as a PAL ident signal 205. PAL ident signal 205 indicates that the V signal is modulated at a phase of +90 or -90. PAL ident signal 205 is used to demodulate the chrominance signal.
For this reason, PAL ident signal 205 is supplied as the chrominance signal demodulation control pulse 140 together with a reference phase pulse 206 indicating the reference phase of sampling to chrominance signal demodulator 139 (in this embodiment, the reference phase of sampling matches -the I-axis in the NTSC system and the U-axis in -the PAL system).
Phase error signal 204 obtained by the operation 685~3 indicated by the left-hand side of equation (1) is supplied to an LPF 207. LPF 207 serves -to determine a time constant of PLL operation. In this case, the time constant is preset to be equal to several tens of TH. An output 119 from LPF 207 is supplied to VCXO 115 through D/A 120 and serves to control the phase of sampling pulse (~S) 116. VCXO 115 has one of oscillation frequencies of 14.3 MHz (NTSC) and 17.7 MHz (PAL) which are switched in accordance with NTSC/PAL switching signal 146.
The hue control in accordance with phase target value 117 will be described hereinafter. When the target sampling phase being determined from -the burst phase is ~0, phase target value 117 is given by tan~0, as previously described in this embodiment. Therefore, when tan(00 ~ ~1) is used instead of tan~0, the demodu-lation axis is shifted by l' and the hues of all colors are changed by the same phase in the same direction.
The operation for hue control is indicated by the second term of the left-hand side of equation (1). Specifi-cally, the value ~l(P4n_2 ~ P4n) obtained from color burst 202 and phase target value (tan~0) 117 are multiplied together. Therefore, a circuit additionally used for hue control may cornprise a single multiplier.
The method for changing the hue in accordance with a change in the demodulation axis is the same as that in a conventional analog color television.

~ - 16 ~

There are two other methods for controlling the hue: one is a method in which the gains of demodulated C signals 141 (I and Q or U and V) change; and the other is a method in which a demodulation coefficient changes in RGB matrix circuit 142. In the former method, gain ad~ustment is performed for two signals, so that the size of hardware (-the number of multipliers) is increased. In addition to this disadvantage, since the differen-t hues change differently (an amount and a direction), complex control is required. In the latter method, six demodulation coefficients are used in the matrix circuit for each of the NTSC and PAL signals, so that the size of the hardware is Eurther increased and further complex control is required, as compared with the former method. Therefore, even in the hue control of the digital television receiver, the method of changing the demodulation axis is more suitable in consideration of the size of hardware and the degree of complexity of the control operation.
(Y/C Separator) Referring to Fig. 1, 2TH delay circuit 126 and Y/C separator 128 serve to separate C and Ysignals 130 and 131 of digital video signal 110. 2TH delay circuit 126 and Y/C separator 128 constitute a Y/C separation filter.
Fig. 4 shows a detailed configuration of 2TH delay circuit 126 and Y/C separator 128. Referring to Fig. 4, the opera-tion for separating digital video signal lJ0 into C signal 130 and Ysignal 13] will now be described.
A comb filter 401 is connected in series with a C signal band-pass filter 412. Comb filter 401 has a periodicity f fH and has zero transfer function or zero gain for f = nfH (n, ... 1, 2, ...). BPF 412 has a gain of 1 for f = fsc~ Comb filter 401 and 3PF 412 serve to extract a C signal 419 included in a lTH~delayed signal 405.
C signal 419 is produced as C signal 130 through an NTSC/PAL switching circuit 420. C signal 130 ls supplied to a subtractor 425 through a C signal gate 421. On the other hand, lTH-delayed signal 405 having a phase corre-sponding to the phase center of comb filter 401 is supplied to subtractor 425 through a phase delay circuit 423. Circuit 423 delays the phase (corresponding to the delay time) of lTH-delayed signal 405 so as to be aligned the phase of signal 405 with that of C signal 130. Subtractor 425 subtracts a C signal 422 gated through gate 421 from a video signal 424 obtained from delay circuit 423, thereby obtaining Ysignal 131.
The operation of the circuit shown in Fig. 4 will be described in detail. 2TH delay circuit 126 has a series circuit of lTM delay circuits 402 and 403. The delay time of each of the lTH delay circuits is switched between 910 TS (NTSC) and 1135 TS (PAL), where TS is the sample period such that TS = l/fS = 1/4 fSC
signals from 2TH delay circuit 126 comprise a 0TH-delayed ~6~353~

signal (no delay) 404, lTH-delayed signal 405 and a 2TH-delayed signal 406, and are supplied as delayecl si~nals 127 to Y/C separator 128.
Delayed signals 127 are fil-tered through comb filter 401 in Y/C separator 128. More particularly, OTH-, lTH- and 2T~I-delayed signals 404, 40S and 406 are multiplied by multipliers 407, 408 and 409 with given coefficients -1/4, 1/2 and -1/4, respectively. These multiplied signals are added to each other by an adder 410. Adder 410 then provides an added signal 411. The coefficients -1/4 and 1/2 are numbers of power of 2, so that coeffcient multipliers 407, 408 and 409 need not comprise special multipliers~ but can be obtained by wiring operations, and the negative coefficients can be obtained by adapting respective inverters. The frequency characterisitic HcOmb(f) of comb fil-ter 401 is given as follows:
H (f) ( 1/4)z-TH/TS + 1/2 + ( l/a)z+TH/TS
= (1/2){1 - cos(2lrf/f~l)} ...(2) Eor z = e~-J 2~rfTs C signal 411 can be separated in accordance with characteristics Hcomb(nfH) = and Hcomb{( H
BPF 412 for C signal 130 comprises ll's-delayed circuits 413 and 414, coefficient multipliers 415, 416 and 417, and an adder 418. Coefficient mul-tipliers 415, 416 and 417 can be obtained in accordance with proper wiring and the addition of inverters. ~he frequency ~L268~3~

characteristic HBpF(f) of BPF 412 ls given as follows:
H (f) = (-1/2)Z-1 + 1 + (-1/2)Z
= 1 - cos(~f/2fsc) ...(3) BPF 412 can be obtained by using simple hardware, so that its frequency characteristic can be given by simple equation (3). Furthermore, since BPF 412 is used together with comb filter 401, Y/C separation can be properly performed even though only simple hardware is used. An output from BPF 412 is supplied to NTSC/PAL
switching circuit 420.
NTSC/PAL switching circuit 420 passes C slgnal 419 per se when NTSC/PAL switching signal 146 indicates the NTSC mode. However, when NTSC/PAL switching signal 146 indicates the PAL mode, NTSC/PAL switching circuit 420 doubles the amplitude of C signal 419 and generates this doubly amplified signal as C signal 130. The switching operation of NTSC/PAL switching circuit 420 is based on the following. The frequency charac-teris-tic HComb(f) of comb Eilter 410 is given by equation (2) irrespective of the NTSC and PAL modes: HcOmb(nfH) = 0, HcOmb{(n + 1/4)fH} = 0.5, and HcOmb{(n -~ 1/2)fH} = 1.
Since the C signal has a frequency near f = (n + 1/2)fH, the C signal can be separated using the frequency characteristic indicated by equation (2) without modification.
Fig. 5(a) shows the relationships among the Y signal spectrum (dotted arrows), the C signal spectrum (solid ~L2~ 3~

arrows), and the characteristic HComb(f) in the NTSC
mode. On the other hand, in the PAL mode, the ~ si~nal has a frequency corresponding to f = nfH, -the U signal in the C signal has a frequency corresponding to s f = (n - l/4)fH, and the V signal has a frequency corresponding to f = (n + l/4)fH. When the frequency characteristic indicated by equation (2) is used without modification, the gain of the C signal for f = (n + 1/4)fH
becomes halved. Therefore, when the gain of -the HComb(f) is doubledl a proper C signal can be separated.
Fig. 5(b) shows the relationships among the Y signal spectrum (dotted arrows), the U signal spectrum (solid arrows), the V signal spectrum (alternate long and short dashed line) and the characteristic 2~Hcomb(f).
Referring to Fig. 5(b), the gain at f = (n + 1/2)fH is doubled. However, this gain corresponds to the vertical high-frequency component of the C signal and thus can be neglected. On the other hand, HBpF(f) has a gain of 1 at f = fSC for both the NTSC and PAL signals in accord-ance with equation (3). Therefore, the characteristic HBpF(f) can be commonly used in the NTSC and PAL modes.
When a combination of comb filter 401 and BPF 412 is considered, the characteristic HComb(f)~E~BpF(f) is used for the NTSC signal, whereas the characteristic 2HComb(f)~HBpF(f) is used for the PAL signal.
NTSC/PAL switching circuit 420 comprises a gain switching circuit 601 and an overflow/underflow prevention circuit 602, as shown in Fig. 6. NrrSC/PAL
switching signal 146 is se-t a-t loglc level "1" in the PAL mode and at logic level "0" in the NTSC mode. Gain switching circuit 601 passes C signal 419 therethrough in the NTSC mode in accordance with a predetermined gate arrangement. However, in the PAL mode, C signal 419 is shifted by one bit toward the MSB side and is thus doubled. Overflow/underflow prevention circuit 602 receives output signals from gain switching circuit 601. r~hen the signals have a binary weighting of 2 (= 1) or more, overflow/underflow prevention circuit 602 clamps the signals to a binary weighting which falls within a range of 2 to 2 7. However, when the signals having a binary weighting of -2 or less are supplied to overflow/underflow prevention circuit 602, these signals are clamped to ~2.
Overflow/underflow prevention circuit 602 is arranged for the following reason. The characteristic HComb(f)-HBpF(f) may exceed a gain of 1 within a video signal frequency range. In particular, the C signal is doubled in the PAL mode, so that the output signals from gain switching circuit 601 in accordance with a given picture pattern may fall outside the posible maximum range of -2 to (2 - 2-7). In other words, if over-flow/underflow prevention circuit 602 is not used,signals having a binary weighting of 2 or more are regarded as negative signals. Similarly, signals havi.ng

3~

a binary weighting of -2 or less are regard~d as positive signals. Using a predetermined ga-te arrange-ment, overflow/underflow prevention circuit 602 detects a 21 bit 603 and a 2 bit 604 of the input signals.
When bits 603 and 604 are set at logic levels "0" and "1", resoectively, overflow/underflow prevention circuit 602 determines that an overflow occurs, and generates signals having a weighting which falls within the range of 2 to 2 . However, when bits 603 and 604 are set at logic levels "1" and 1l0'l, overflow/underflow preven-tion circuit 602 determines that an underflow occurs, and generates signals having a weighting corresponding -to -2.
The NTSC/PAL switching syste~ has an advantage in that NTSC/PAL switching circuit 420 may be made only by 40 to 50 gates.
Referring to Fig. 4, C siynal 130 from NTSC/PAL
switching circuit 420 is supplied to color control/color killer circuit 135 and to C signal gate 421. Gate 421 also receives color killer signal 137 from color control/color killer circuit 135. Ga-te 421 is closed in the color killer mode so as to prevent the supply of C signal 422 to subtractor 425. Therefore, in the color killer mode, video signal 424 per se is used as Ysignal 131. In the conventional color killer operation, C signal 130 is set at logic level "0".
However, as previously described, -the color killer 3~
. - 23 -operation is also applied to Y/C separator 128 in this embodiment. For this reason, a bandwidth limi-t imposed upon Ysignal 131 is elimina-ted in the color killer mode, thereby widening the bandwidth.
The above description may be summarized concerning Y signal separation as follows. A Y signal separation characteristic Hy(f) used for separating Ysignal 131 from video signal 424 is given as follows:
J 1 - HcO~lb(f) HBPF for ~JTSC mode H (f) = ~ 1 - 2 HcOmb(f) BPF for PAL mode 1 (full-band through for color killer ~ filter) operation Ysignal 131 is supplied to Y signal processing circuit 129.
(Y Signal Processing Circuit) The Y signal processing circuit 129 corrects the horizontal and vertical profiles, contrast, and bright-ness of the Y signal 131, and supplies the updated or corrected Y signal to the matrix circuit 142.
Fig. 7 shows a detailed configuration of Y signal processing circuit 129. Y signal processing circui-t 129 comprises a vertlcal contour circuit 701, a horizontal contour circuit 702, a contrast circuit 703, an adder 711 and a pedestal clamp circuit 713. Picture quality control signal 132 includes a vertical contour control signal 704, a horizontal contour control signal 705, a contrast control signal 706, and a brigh-tness control 3~
_ 24 -signal 707. Delayed signals 127 from 2TH delay circuit 126 are supplied to vertical and horizontal con-tour eir euits 701 and 702 and to contrast cireuit 703. Vertical and horizontal contour circuits 701 and 702 and contrast eireuit 703 generate signals 708, 709 and 710, respee-tively. The gains of circuits 701 to 703 are controlled by the signals 704, 705 and 706, respeetively. Vertical and horizontal contour signals 708 and 709 and contrast signal 710 are added by adder 711 to the externally supplied Ysignal 131. Adder 711 then supplies an added result as a Y signal 712 to pedestal elamp eireuit 713.
Adder 711 and pedestal elamp eireuit 713 together perform brightness control wherein a DC eomponent of Ysignal 131 is eontrolled in aceordanee with brightness lS eontrol signal 707. The vertieal and horizontal eontours, eontrast and brightness of Ysignal 131 are eorreeted, and updated Y signal 133 is produeed. Y sig-nal 133 is supplied to matrix eireuit 142 (Fig. 1).
The eomponents of Y signal proeessing eireuit 129 will be deseribed in detail hereinafter.
(1) Vertieal Contour Cireuit Fig. 8 shows a detailed eonfiguration of vertieal eontour eireuit 701. Vertieal contour signal 708 is prepared by 2TH delay eireuit 126 and vertieal eontour eireuit 701. Vertieal eontour eireuit 701 eomprises a series eireuit of a ver-tieal HPF 801 of a eomb filter arrangement and an LPF 807. Vertieal HPF 801 serves 353~3 - ~5 -to filter a component having a large vertical variation on the TV screen. An output signal 806 from vertical HPF 801 includes the vertical contour component.
Vertical HPF 801 and the vertical frequency will be briefly described hereinafter. Vertical HPF 801 has the same arrangement as comb filter 401 (Fig. 4) for separating C signal 411 from video signal. In practice, comb filter 401 (Fig. 4) is also used as vertical HPF
801, but they are separately described for descriptive convenience. Coefficient multipliers 802 to 804 and an adder 805 (Fig. 8) correspond to coefficient multipliers 407 to 409 and the adder 410 (Fig. 4), respectively.
Vertical HPF 801 is the same as comb filter 401 since the C signal has a vertical high-frequency component.
The vertical frequency indicates the vertical repetition on the screen in units of cycle/picture hight (to be referred to as cy./p.h. hereinafter).
Fig. 10 shows a representation for e~plaining the relationship among -the vertical frequency F (cy./p.h.), the normally used frequency f (Hz) (to be referred to as a horizontal frequency in order to distinguish between the vertical frequency F and the normally used frequency f), and a picture pattern. The vertical Erequency corresponds to a vertical change in picture pattern, whereas the horizontal frequency corresponds to a horizontal change in picture pattern. The horizon-tal frequency f and the vertical frequency F are plotted on a two-dimensional coordinate system and are often called a two-dimensional frequency.
Fig. 11 shows a two-dimensional frequency being formed of frequency components respectively corresponding to picture patterns in Figs. lO(a), lO(b) and lO(c).
Fig. 12 is a graph showing the television signal in a two-dimensional frequency form. The normalized fre-quency scale is commonly used for the NTSC and PAL
systems. The horizontal frequency is normalized by the sampling frequency fS (= 4fSC) The vertical frequency is normalized by the scanning lines fH/fV (where fV is the field frequency) for one field. In general, the vertical frequency F (cy./p.h.) of a signal whose frequency is given by f (Hz) = (n + a)fH becomes F = (fH/fv)a where n = a natural number, 1 > a > 0, and fV is the field frequency. The vertical frequency of the NTSC chrominance subcarrier is 525/4 = 131.25 (cy./p.h.), the vertical frequency of the U signal in the PAL mode is 625/8 = 78.125 (cy./p.h), and the vertical frequency of -the V signal is 625 x 3/8 =
234.375 (cy./p.h.). The horizontal frequency of the chrominance subcarrier differs in the NTSC and PAL modes.
However, the horizon-ta:L frequencies of the NTSC and PAL
chrominance subcarriers can be expressed by a normalized frequency as fs/4~ Black dots in Fig. 12 indicate NTSC
and PAL subcarriers. An area Al in Fig. 12 shows an approximate frequency range of the C signal.

1~6~;3~

The characteristic of vertical ~IPF 801 will be described. The frequency characteristic of vertical HPF
801 is the same as that (Hcomb{f(Hz)}) indicated by equation (2) and is expressed using the vertical frequency F as follows:
comb(F) ll - cos(2~fv F/fH)}/2 (4) The characteristic given by equation (4) is constant along the axis of horizontal frequency and changes only along the axis o~ vertical frequency. The gain in this change is zero at F = 0 and is sinusoidally increased to reach "1" at F = 0.5 x fH/fV~ The bandwidth of vertical HPF
801 corresponds to an area surrounded by a dotted line Ql and a dotted line Q2 in Fig. 12 (the dotted line Ql indicates F = 0.75-fH/fV, and the dotted line Q2 indi-cates F = 0.25-fH/fV), I-t should be noted that the vertical frequency E' = 0.5(fH/fV) corresponds to a zigzag picture pattern repeated for every line and has a mirror symmetry about F = 0.5~fH/EV (a dotted line Q0).
Referring again to Fig. 8, output signal 806 from vertical HPF 801 is supplied to LPF 807 to eliminate the C signal component (the area Al in Fig. 12) included in output signal 806. LPF 807 comprises 2TS delay circuits 808 to 811, coefficient multipliers 812 to 816, and an adder 817, and has a low-pass filtration characteristic (bandwidth of about 1 ~Hz), By this characteristic, the C signal included in signal 806 is substantially eliminated together with the high-frequency 3~

component of the C signal. The bandwidth of the fil-ter constituted by a series circui-t of vertical HPF 801 and LPF 807 is indicated by an area A2 in Fiy. 12. This bandwidth corresponds to the bandwidth of a vertical contour signal 818. When the C signal is not completely eliminated, vertical contour correction results in dot interference in a portion subjected to a ~reat change in color, thus degrading image quality.
Another method for obtaining the vertical contour signal is proposed wherein the Y signal is filtered through a vertical HPF. However, in general, the Y signal has a wide bandwidth. When the Y signal is supplied to the vertical HPF, the C signal leaks con~
siderably, resulting in dot interference. According to the present embodiment, LPF 807 having a narrow bandwidth is combined with vertical HPF 801 so as to prepare the vertical contour signal 818 independently of Ysignal 131. Vertical contour signal 818 and vertical contour control signal 70~ are multiplied by a multiplier 819 so as to control the gain of the vertical contour signal 818. Thereafker, a corrected signal is ~roduced as -the vertlcal contour signal 708.
(2) ~lorizontal contour Circuit Fig. 9 shows the configuration of horizontal contour circuit 702. Horizontal contour signal 709 is prepared by 2TH delay circuit 126 and horizontal contour circuit 702. Horizontal contour circuit 702 comprises a series circuit of a vertical LPF 901 oE a comb filter arrangement and a BPF 907. Vertical LPF 901 comprises 2TH delay circuit 126, coefficient multipliers 902 to 904, and an adder 905, and has a characteristic opposite to that of vertical HPF 801 (Fig. 8). A vertical frequency characteristic HVLpF(F) of vertical LPF 901 is given as follows:
HVLpF(F) = {1 - cos(2~fv~F/fH)}/2 This bandwidth corresponds to an area below the dotted line Q2 in Fig. 12 (and actually, also to an area above the dotted line Ql)' An output signal 906 from vertical LPF 901 is supplied to BPF 907. BPF 907 comprises 4TS
delay circuits 908 and 909, coefficient multipliers 910 to 912, and an adder 913, and has a center frequency fs/8 (1.8 MHz in the NTSC mode, and 2.2 MHz in the PAL
mode) and a filtration bandwidth ~fS/16 (0.9 MHz in the NTSC mode, and 1.1 MHz in the PAL mode). BPF 907 serves to extract the horizontal contour signal of the picture pa-ttern in the vicinity of 2 MHz. The filtration bandwidth of the fil-ter constituted by a series circuit of vertical LPF 901 and BPF 907 corresponds to an area A3 in Fig. 12.
In general, in order to prepare -the horiæontal contour signal, the Y signal is filtered through a 2-MHz BPF. However, the vertical frequency of the Y signal has a wide bandwidth, so that the C signal (area Al in Fig. 12) may substantially leak into the 3~

horizontal contour siynal. When horizontal contour correction is performed, do-t interference oecurs in a portion which i5 subject to a great change in color.
However, according to this embodiment, a combination of BPF 907 for extracting the horizontal contour component and vertical LPF 901 for preventing leakage of the C signal is used to separate a horizontal contour signal 914. Horizontal contour signal 914 and horizon-tal contour control signal 705 are multiplied by a multiplier 915. The ampli-tude of horizontal contour signal 914 is thus controlled, and the corrected signal is produced as vertical contour signal 709.
(3) Contrast Circuit Fig. 13 shows a detailed configuration of contrast eircuit 703. Contrast circuit 703 comprises an integrator (or aceumulator) 1301, an average value eircuit 1303, a subtractor 1305, LPFs 1307 and 1336, and a multiplier 1309. Contrast circuit 703 prevents leakage of the DC component (brightness signal) of the video signal -to a contrast signal 1308, using integrator 1301 and average value circuit 1303. For this reason, the brightness will not change even if contrast of pictures is adjusted.
The overall operation of contras-t circuit 703 will now be described. A OTH-delayed si.gnal 404 from 2TH
delay circuit 126 is supplied to integrator 1301, so that data of a picture portion for one horizontal period is integrated or accumulated. An lntegra-ted result 1302 is supplied to average value circuit 1303 during the next horizontal period. Average value circuit 1303 divides integrated result 1302 by a predetermined value to obtain an average value 1304 of the picture portion.
Average value 1304 is supplied via LPF 1336 to sub-tractor 1305. LPF 1336 has a time constant correspondiny to several vertical periods, thereby averaging the value 1304 to provide an averaged output 1337. Averaged output 1337 corresponds to the average illuminance during one line period (lH). Subtractor 1305 also receives a lTH-delayed siynal 405 obtained from 2TH
delay circuit 126. Subtractor 1305 subtracts LPF
output 1337 from lTH-delayed signal 405, thereby obtaining an ~C component 1306 of the picture portion.
AC component 1306 has the horizontal DC component. For thi.s reason, -the transfer function from the lTH-delayed signal 405 to the DC component 1306 provides "0" at f = 0 (along the axis of vertical frequency) and "1" at any frequency other -than f = 0. O~ltput 1337 corresponding to OTH-delayed signal 404 is delayed by lT~. Therefore, -the lTH-delayed output 1337 is subtracted by subtractor 1305 from lTH-delayed signal 405 so as to match -the phases of output 1337 and lTH-delayed signal 405.
Contrast corresponds to a low-frequency component of the video signal since it is a change in brightness over a considerably large area on the screen. The 35~3 low-fre~uency component is extracted by LPF 1307, so that con-trast signal 1308 is obtained. This contrast signal 1.308 and constrast control signal 706 are multi-plied by mul~lplier 1309 so that the amplitude of contrast signal 1308 is corrected. A corrected signal is then produced as contrast signal 710.
Fig. 13A shows details of LPF 1336 shown in Fig. 13.
Average value 1304 is supplied to a subtractor 1338.
Subtractor 1338 subtracts said averaged ou-tput 1337 from average value 1304, and provides a subtracted result E1338. subtracted result E1338 is multiplied by 2 10 by a coefficient multiplier 1339. An output E1339 from coefficient multiplier 1339 is added to averaged output 1337 by an adder 1340. Adder 1340 supplies an added result E1340 to a latch 1341. Result E1340 is loaded to latch 1341 when latch 1341 is clocked by flyback pulse 134.
In LPF 1336, data corresponding to the difference between the present input (average value 1304) and the present output (averaged output 1337) is added to the present output 1337, thereby renewing the averaged output 1337. This operation corresponds to the operation of an RC integration circuit. The data of latch 1341 is renewed by every lTH period. When the gain A of coefficient multiplier 1339 is 2 , the time constant of LPF 1336 is A ~TH = 2 TH (~ 4TV
TV denotes a vertical period). By the time constant 3~

of LPF 1336, rapid change in average value 1304 is suppressed and thus, s-tripe-llke luminance noises on a displayed picture can be avoided.
The components of the contrast circuit shown in Fig. 13 will be described in detail hereinafter. Inte~
grator 1301 comprises an adder 1311, and latches 1312 and 1313, Latch 1312 performs latching at a timing of sampling pulse (~S) 116 and is cleared to zero during the flyback period in response to flyback pulse 134.
Therefore, when an output from adder 1311 is supplied to latch 1312 and an output from latch 1312 is fed back to adder 1311, picture period integration (accumulation operation) with respect to 0TH-delayed signal 404 is performed. Since latch 1312 is operated in response to sampling pulse (~S) 116, adder 1311 adds the signals for every sampling period Ts, and the number NA f additions for the entire integration period is given as follows:
NA = (TH ~ TFg)/TS
where TFB is the flyback period.
On the other hand, latch 1313 latches the output signal (integration result) from latch 1312 which is cleared in response to flyback pulse 134. The integra-tion result latched in la-tch 1313 in response to flyback pulse 134 is supplied as integration result 1302 to average value circuit 1303. Average value circuit 1303 divides integration result 1302 by NA (i.e., it is multiplied by l/NA) and generates a divided signal.

3~
. 34 -If TFB = 0.2-TH, and TH = 910~Ts (NTSC), or TH = 1135 TS
(PAL), NA is calculated as follows:
728 ( NTSC) lgo8 (PAL) In practice, in order to decrease the number of circuit elements, the value l/NA is appro~imated by one of the following equations in accordance with the operating mode:
NTSC: 1/728 ~~ 1/21 + 1/212 + 1/213 1/745 PAL 1/908 ~ 1/21 ~ 1/213 1/910 ................. (6) As described above, when only numbers comprising powers of 2 are added, coefficient multipliers 1331 1333 and 1332 for 2 10 2-12 and 2-13 a di obtained in accordance with proper wiring. In practice, only an adder 1.334 and a gate 1335 are required as hardware. Gate 1335 is controlled in accordance with NTSC/PAL switching signal 146. In the NTSC mode, an output from the 2 12 coefficient multiplier 1333 is supplied to adder 1334 through gate 1335 in order to perform operation in accordance with equation (5). In the PAL mode, gate 1335 serves to provide a null input -to adder 1334 in order to perform operation in accordance with equation ( 6). It should be noted that approximation errors in -the NTSC and PAL modes are 2.2o and 0.2 respectively, when NTSC and PAL numbers l/NA are approximated in accordance with equations ( 5) and (~).
These errors can be neglected in practice. LPF 1307 is the same as the LPF 807 (bandwidth of 1 MHz) shown in Fig. 8.
As described above, integrator 1301, average value circuit 1303 and LPF 1336 can be constructed using very simple hardware, thereby preventing leakage of the DC component into the contrast signal 1308.

(4) Brightness Control Referring to Fig. 7, brightness control is performed by adder 711 and pedestal clamp circuit 713. Unlike the horizontal and vertical contour controls and contrast control, brightness control is performed by controlling a DC component having the pedestal level of the picture as a reference. Therefore, brightness control signal 707 is directly supplied to adder 711 and is added together with other signals 704-706 and 708-710 to Ysignal 131 from Y/C separator 128. Y signal 712 is produced by adder 711. However, in this condition, the pedestal level of Y signal 712 from adder 711 changes, and the DC componen-t of the picture portion with respect to the pe~estal level is the same as Ysignal 131.
Therefore, in pedestal clamp circuit 713, Y signal 712 ls clamped to have a predetermined pedestal level in accordance with flyback pulse 134. Pedestal clamp circuit 713 then generates Y signal 133. The average luminance of Y signal 133 changes by an amount corre-sponding to the level of brightness control signal 707, as compared with the average luminance of Ysignal 131.

S3~

Thus, brightness contro]. is performed.
(Color Control/Color Killer Circuit) Fig. 14 shows a detailed configuratlon of color control/color killer circui-t 135. Color control/color killer circuit 135 serves to perform an automatic color control (ACC) for C signal 130, manual color control, and color killer operation, and to supply color killer signal 137 to Y/C separator 128 in order to produce video signal 422 (Fig. 4) as Y signal 131 in the color killer mode, as previously described.
Color control/color killer circuit 135 comprises a multiplier 1401, a color killer 1409, a burst ampli-tude detector 1404, a loop filter 1408, and a subtractor 1406. The overall configuration and operation of circuit 135 and then the components of circuit 135 will be described hereinafter.
C signal 130 is supplied to multiplier 1401 and is multiplied with an ACC signal 1402, so that the amplitude of C signal 130 is controlled. A C signal 1403 from multiplier 1401 is supplied to burst amplitude detector 1404 which then detects the arnplitude of the color burst. Burs-t amplitude detector 140~ detects a value proportional to the amplitude of the color burst.
A color burst amplitude signal 1405 is -then supplied to subtractor 1406. Subtrac-tor 1406 detects an error such that burst amplitude signal 1405 is subtracted from the ACC target value (i.e., the externally supplied manual control signal 136 for controlling -the color sa-turation). Subtractor 1406 generates an ACC error signal 1407. ACC error signal 1407 is supplied to loop fil-ter 1408 constituted by an LPF. Loop fil-ter 1408 serves to determine an ACC time constant. The time constant is set to be several tens of TH. An output signal from loop filter 1408 is supplied as ACC signal 1402 to multiplier 1401 and is multiplied with C signal 130 as described above. Ir. this manner, the ACC loop is constituted by, in order, multiplier 1401, burst amplitude detector 1404, subtractor 1406, loop filter 1408 and multiplier 1401. The ACC loop controls the amplitude of C signal 130 to match the ACC target value in accordance with manual color control signal 136, and generates the updated C signal 138.
The color control. circuit has the following two features. First, the ACC targe-t value (signal 136) is externally supplied, and color control is performed in accordance with the ACC target value. Second, the amplitude of the NTSC color burst is detected in accordance with ¦C+I I -~ ¦ C~Q ¦, and the amplitude of _ the PAL color burst is detected in accordance with ¦C~ul -~ ¦C~vl (where C[, CQ, Cu and Cv indicate the levels of the burst signals sampled along the I-, Q--, U- and V-axes, respectively).
~ egarding the first feature, it is advantageous that color control be perfor~ed by the variable ACC

~85;3 ~

target value since a special multiplier need not be prepared for color control. Regarding the second feature, it is advantageous that the absolute values of the respec-tive sampled points along the two axes shifted by 90 be added so as to readily perform hue control.
More particularly, hue control is performed by changing the sampling phase in A/D 109 by chanaing phase target value 117 in PLL circuit 200 (Fig. 2).
However, a problem arises here. When the sampling phase changes, the sampled value oE the burst component also changes. As a result, an erroneous burst amplitude value 119 may be produced. The value of ACC signal 1402 changes, and hence the value of C signal 1403 changes.
In short, when the hue changes, the color saturation changes. In order to prevent this, the value of burst amplitude signal 1405 must be corrected in accordance with phase target value 117 (Fig. 1). However, large-scale hardware is required for this purpose. Therefore, according to -the present embodiment, as a simple method to reduce the change in color saturation to a negligible degree while hue control is performed, the amplitudes of the NTSC and P~L color burst signals are detected in accordance wi-th ¦C~ C~Q¦ and ¦C~ul + ¦C~vl, _ respectively. Under these conditions, even if the sampling phase is shifted by +10 (hue variable range) from the I- and Q-axes (NTSC) or the U- and V-axes (PAL), the burst amplitude changes by only 5.2% (NTSC) or 35;~3 1.5% (PAL). These errors can be neylected ln practice.
The color killer operation will be described hereinafter. In aeneral, the color killer mode is set only when the burst amplitude of C signal 130 is less than a predetermined value. According to this embodi-ment, u-tilizing the fact that the value of ACC signal 1402 is inversely proportional to that of C signal 130, when ACC signal 1402 has a value exceeding a ~redeter-mined value K, the color killer mode is set. However, the value of ACC signal 1402 changes in proportion to -the amplitude of manual color control signal 136 even when C signal 130 keeps the same level. In order to stabl~ set the color killer mode, the predetermined value K must be proportional to the amplitude of manual color control signal 136. For this reason, color killer 1409 receives ACC signal 1402 and manual color control signal 136. Manual color control signal 136 is a multiplied by a given constant, and a multiplied signal value is preset to be the prede-termined value K. This predetermined value K is compared with ACC si.~nal 1402.
When the value of ACC signal 1402 is greater than -the predetermlned value K, the color killer mode is set.
When -the color killer mode is set, C signal 138 is set at zero, and the video signal 424 (Fig. 4) is produced as Ysignal 131 from Y/C separator 128. As a result, the bandwidth of Ysignal 131 is widened. The operation mode of the color killer as described above has an ~o -advantage in that a simple circuit may be used, as compared with the conventional system wherein the amplitude of the color burst of C signal 130 is detected, the color burst amplitude signal is supplied to LPF to determine the time constant, and the color killer mode is set when the value of the output signal from LPF is smaller than a predetermined value.
The components of color control/color killer circuit 135 shown in Fig. 14 will be described in detail with reference to Fig. 15. Referring to Fig. 15, burst amplitude detector 1404 comprises a burst extraction circuit 1501, an absolute value circuit 1502, an adder 1504, and latches 1505 and 1506.
Burst amplitude detector 1404 serves to integra-te or accumulate the absolute values of the color burst pulses (for six periods) while burst extraction pulse 111 is set at high level, and to supply an integrated or accumulated result 1405 to subtractor 1406 during one horizontal period (TH). C signal 1403 from multi-plier 1401 is gated in burst extraction circuit 1501 in response to burst extraction pulse 111. Signals (24 samples) for the six periods of the color burst are extracted hy extraction circuit 1501 and are supplied as signals E1501 to absolute value circuit 1502.
Absolute value circuit 1502 detects the sign bit of the color burst signal. When the sign bit is set at logic level "1", data is inverted. However, when the sign bit is set at logic level "0", the da-ta passes through absolute value circuit 1502. Absolute value circuit 1502 thus detects the absolute values of the color burst signal. Absolute value signals 1503 are accumu-lated by adder 1504 and stored in latch 1505 during the burst extraction pulse (111) period. Latch 1505 latches data in accordance with sampling pulse (~S) 116 and is cleared during a tlme interval excluding the period of burst extraction pulse 111. The latched value imme-diately before latch 1505 is cleared is then loaded into latch 1506 by pulse 111. The latched signal outputted from latch 1506 is produced as burst amplitude signal 1405.
Loop filter 1408 serves to determine an ACC time constant. Loop filter 1408 comprises a 2 n coefficient multiplier 1507, an adder 1508, a latch 1509 and an underflow prevention circuit 1510. Underflow prevention circuit 1510 prevents ACC signal 1402 from -taking a negative value. The 2 n coefficient multiplier 1507 has an arrangement for shifting the data by n bits toward the LSB side in accordance with proper wiring, special hardware can thus be eliminated. Latch 1509 performs latchiny in accordance with burst extraction pulse 111. Multiplier 1507 multiplies an inputted error signal 1407 by 2 n. A multiplied signal from multiplier 1507 is accumulated (integrated) at each TH by adder 1508 and latch 1509. An abrupt change (high-frequency 853~

componen-t) in error signal 1407 can be absorbed by the above accumulation. In this circuit arrangement, the ACC time constant is proportional to 2n~TH. Therefore, when n is properly determined, the ACC time constant can be determined to have a proper value. An output signal from loop filter 1408 is supplied as ACC signal 1402 to multiplier 1401.
In color killer circuit 1409, the value of ACC
signal 1402 is compared by a comparator 1513 with a value 1512 (color killer threshold K) obtained by multiplying the value of manual color control signal 136 by a constant (2m). When the value of ACC signal 1402 is greater than the multiplied value 1512, color killer signal 137 is set at logic level "0". This signal 137 is supplied 2S a gate control signal to a gate 1514 to which C signal 1403 is inputted.
Therefore, C signal 138 from gate 1514 is set at logic level "0", and C signal 422 from C signal gate 421 (Fig. 4) also becornes logic level "0". As a result, video signal 424 is produced as Ysignal 131 ~rom subtractor 425.
(Chrominance Si.gnal Demodulator) Fig. 16 shows a detailed configuration of chrominance signal demodula-tor 139. Chrominance signal demodulator 139 comprises latches 1601, 1602, 1605 to 1607, and a gate circuit 1613 including gates 1608 to 1611 and an inverter 1612. In the NTSC mode, chrominance signal 853~
_ a3 _ demodulator 139 serves to selectively latch the I-phase data in latch 1601 for demodulating an I signal 1603.
The O-phase data is selectively latched by latch 1602 to demodulate a O signal 1604. In the PAL mode, in chrominance signal demodulator 139, U-phase data in C signal 138 is latched by latch 1601 to demodulate U signal 1603. On the other hand, the V signal is inverted for every horizontal line. Therefore, the latch phase of latch 1602 must be switched between +V and -V for every horizontal line. This switching operation is performed in accordance with PAL ident signal 205. The operation of demodulator 139 will be described hereinafter.
C signal 138 is supplied to latches 1601 and 1602.
On the other hand, the reference phase pulse 206 from phase detector 118 (Fig. 1) is also supplied to chrominance signal demodulator 139. Reference phase pulse 206 has a phase along the I-axis in the NTSC mode and along the U-aY.is in the PAL mode. Reference phase pulse 206 is supplied as a load pulse -to latch 1601, so that the I- or U-phase data of C signal 138 is latched and I or U signal 1603 is demodula-ted.
Reference phase pulse 206 is sequentially shifted by a one-sampling phase (90) by latches 1605 -to 1607.
As a result, latch 1605 genera-tes the -Q- or V-phase pulse, latch 1606 generates the -I or -U-phase pulse, and latch 1607 genera.es the o or -V-phase pulse.

s~ l Gate circuit 1613 receives NTSC/PAL switching signal 146, PAL ldent si.gnal 205 and the output signals from latches 1605 and 1607, and produces a Q or V demodulation pulse 1614. This demodulation pulse 1614 is supplied as a load pulse to latch 1602. ~ or V demodulation pulse 1614 is used as the Q-phase pulse in the NTSC mode, and is used as the +V- or -V-phase pulse which corresponds to the content of PAL ident signal 205. Latch 1602 generates Q signal or V signal 1604. It should be noted that gate circuit 1613 is based on the assumption that NTSC/PAL switching signal 146 is set at logic level "0"
(NTSC) and at logic level "1" (PAL), and PAL ident signal 205 is set at logic level "1" along the +V-axis and logic level "0" along the -V axis.
Demodulated C signal 141 from chrominance signal demodulator 139 is supplied together with Y signal 133 to matrix circuit 142. Matrix circuit 142 performs a predetermined matrix operation, thereby obtaining RGB
signal 143. The contents of operation of matrix circuit 142 is switched in accordance with the NTSC/PAL switching signal 140.
Fig. 17 shows a block configuration of RGB matrix 142 in Fig. 1. Digi-tal demodulated I signal (NTSC) or U signal (PAL) 141 from chrorna demodulator 139 is supplied to multipliers 1700, 1702 and 1704. Digital demodulated ~ signal (NTSC) or V signal (PAL) 141 from chroma demodulator 139 is supplied to multipliers 1706, `~ 353~

1708 and 1710. NTSC/PAL switching signal 146 is supplied as a selection instruction -to da-ta sel.ectors 1730, 1740, 1750, 1760, 1770 and 1780. Selector 1730 selects one of a multiplicand RI (NTSC) from a matrix coefficient generator 1732 and a multiplicand RU (PAL) from a matrix coefficient generator 1734 according to NTSC/PAL switching signal 146. Similarly, selector 1740 selects one of multiplicands GI (NTSC) and GU (PAL) from generators 1742 and 1744. Selector 1750 selects one of multiplicands BI (NTSC) and BU (PAL) from generators 1752 and 1754.
Selector 1760 selects one of multiplicands RQ (NTSC) and RV (PAL) from generators 1762 and 1764. Selector 1770 selects one of multiplicands GQ (NTSC) and GV (PAL) from generators 1772 and 1774. Selector 1780 selects one of multiplicands BQ (NTSC) and BV (PAL) from generators 1782 and 1784.
Selector 1730 supplies the selected multiplicands (RI or RU) to multiplier 1700 in accordance with the NTSC/PAL switching signal 146. Then, multiplier 1700 outputs a signal E1700 corresponding to RI x I signal or RU x U signal. Similarly, multiplier 1702 outputs a signal E1702 corresponding to GI x I signal or GU x U signal. Multiplier 1704 outputs a signal E1704 corresponding to BI x I signal or BU x U signal.
Multiplier 1706 outputs a signal E1706 corresponding to RQ x Q signal or RV x V signal. Multiplier 1708 outputs a signal E1708 corresponding to G~ x Q signal or 3535~

- ~6 -GV x V signal. Multiplier 1710 outputs a signal E1710 corresponding to BQ x Q signal or BV x V signal. Signal E1700 is added to signal E1706 by an adder 1712. Adder 1712 supplies a sum E1712 to an adder 1718. Adder 1718 adds Y signal 133 from Y process circuit 129 (Fig. 1) to sum E1712, and provides an R signal. Similarly, signal E1702 is added to signal E1708 by an adder 1714 which supplies a sum E1714 to an addex 1720. Adder 1720 adds Y
signal 133 to sum E1714 and provides a G signal. Signal E1704 is added to signal E1710 by an adder 1716 which supplies a sum E1716 to an adder 1722. Adder 1722 adds Y
signal 133 to sum E1716 and provides a B signal. The out-put signals from adders 1718, 1720 and 1722 are supplied as the RGB signal 143 to D/A converter 144 (Fig. 1).
Digital clamp circuit 112 in Fig. 1 may be as dis-closed in Canadian Patent Application No. 433,627. The correspondence between Fig. 1 of the present invention and Fig. 1 of the above Application No. 433,627 is as follows:

20Fig. 1 Fig. 1 of Application ~433,627 111 32' Digital sync separator/timing generator 122 in Fig.
1 may be as disclosed in said application. The correspon-dence between Fig. 1 of the present invention and Fig. 1 of the above application is as follows:
Fig. 1 ¦ Fig. 1 of Application ~493,627 111 31, 2 123 29, 30 122 1 27 l Count-down circuit 124 may be as disclosed in Fig. 1 of the said application. The correspondence between Fig.
1 of the present invention and Fig. 1 of the above appli-cation is as follows:

Fig. 1 Fig. 1 of Application #433,627 123 29, 30 125 34, 37 124 32, 36 l Fig. 18 shows an example of a burst extraction cir-cuit 201 in Fig. 2. Thus r circuit 201 is an AND gate whose one input receives burst extraction pulse 111, while other inputs receive digital video signals 110.
Fig. 19 shows an example of a digital LPF 207 in Fig. 2. Thus, phase error signal 204 is supplied to an adder 207A. Adder 207A adds phase error signal 204 to a latched signal E207B, and provides a sum E207A to a latch 207B. Sum E207A is loaded into ...

- 48 ~

latch 207B when burst extraction pulse 111 is generated.
The latched result E207A becomes new latched signal E207B. La~ched signal E207B and phase error siynal 204 are inputted to coefficient multipliers 207C and 207D, respectively. Multiplier 207C multiplies inputted signal E207B by a given coefficient Cl, and supplies a multiplied output E207C to an adder 207E. Multiplier 207D multiplies inputted signal 204 by a given coefficient C2, and supplies a multiplied output E207D
to adder 207E. Adder 207E then adds the output E207D
to the output E207C, and provides said phase error signal 119.
Fig. 20 shows an example of a pedestal champ circuit 713 in Fig. 7. Y signal 712 from adder 711 is supplied to a data selector 713A. Supplied also to data selector 713A is a pedestal level signal E713B obtained from a pedestal level generator 713B. Data selector 713A
selects either one of signals 712 and E713B in accordance with flyback pulse 134, and provides the selected one as said updated Y signal 133.
Fig. 21 shows an example of a burst extraction circuit 1501 in Fig. 15. The configuration of Fig. 21 is the same as that of Fig. 18 and hence, the explanation will be omitted.
Fig. 22 shows an example of an absolute value circuit 1502 in Fig. 15. Digital signals E1501 from burst extraction circuit 1501 are formed of numeral bits ~ ~i8~3~
_ ~9 .

and a sign bit. These numeral and sign bi-ts are input-ted to an EXOR ga-te 1502A. The EXORed output rom gate 1502A
is used as said absolute value signals 1503.
Fig. 23 shows an example of an underflow prevention circuit 1510 in Fig. 15. Digital signals E1509 are formed of numeral bits and a sign bit. The numeral bits are inputted to an AND gate 1510A. The sign bit is inputted via an inverter 1510B to AND gate 151OA.
The ANDed output from gate 1510A is used as said ACC
signal 1402.
The present invention is exemplified by the particular embodiment. However, the basic circuit configuration and its system is not limited to the particular embodiment. Various changes and modifications may be made within the scope of the present invention.
Further, the present invention may be effectively applied to a monitor reciever which does not receive a broadcast signal.

Claims (7)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS :

1. A digital television receiver comprising :
digital converter means for converting an analog video signal to a digital video signal;
signal separator means coupled to said digital converter means, for separating a digital chrominance signal and a digital luminance signal from said digital video signal wherein said signal separator means includes:
(a) delay means for delaying said digital video signal by a given amount to provide a delayed video signal;
(b) Y/C separator means coupled to said delay means for separating said digital chrominance signal and an unprocessed luminance signal from said delayed video signal;
and (c) Y processor means coupled to said delay means and said Y/C separator means, for composing said digital luminance signal from said delayed video signal and said unprocessed luminance signal;
colour killer means coupled to said signal separator means and being responsive to burst components of said digital chrominance signal, for gating said digital chrominance signal to generate a gated colour signal when said burst components are contained in said digital chrominance signal; and processor means coupled to said signal separator means and to said colour killer means, for digitally composing RGB signals from said digital luminance signal and said gated colour signal, said RGB signals being used as tricolour signals for a colour picture tube.

2. A receiver according to claim 1, wherein said Y
processor means includes:
contrast means coupled to said delay means, for varying the contrast component of said delayed video signal and generating a varied signal corresponding to said contrast components; and combining means coupled to said contrast means and to said Y/C separator means, for combining said varied signal and said unprocessed luminance signal and generating as the result of combining said digital luminance signal.

3. A receiver according to claim 2, wherein said contrast means includes:
contrast accumulator means for accumulating said delayed video signal to generate an accumulates signal;
average means coupled to said contrast accumulator means, for averaging said accumulated signal for a given period of time to generate an averaged signal; and contrast filter means coupled to said average means, for smoothing the potential change of said averaged signal to generate a filtered signal;
means coupled to said delay means and to said contrast filter means and being responsive to a coefficient signal, for generating said varied signal from said delayed video signal and said filtered signal so that the difference between said delayed video signal and said filtered signal corresponds to said varied signal, the magnitude of said varied signal depending on said coefficient signal.

4. A receiver according to claim 2, wherein said Y
processor means further includes:
V contour means coupled to said delay means, for generating a vertical contour signal from said delayed video signal and supplying said vertical contour signal to said combine means so that said digital luminance signal contains a signal component of said vertical contour signal which modified the vertical contour of pictures displayed at a CRT.

5. A receiver according to claim 4, wherein said V
contour means includes:

V differential means for differentiating signal components of said delayed video signal for a prescribed period of time to generate a V differentiated signal;
V filter means coupled to said V differential means, for digitally low-pass filtering said V differentiated signal to generate a V filtered signal; and V coefficient means coupled to said V filter means and being responsive to a V coefficient signal, for multiplying said V filtered signal by said V coefficient signal to generate a vertical contour signal.

6. A receiver according to claim 2, wherein said Y
processor means further includes:
H contour means coupled to said delay means, for generating a horizontal contour signal from said delayed video signal and supplying said horizontal contour signal to said combining means so that said digital luminance signal contains a signal component of said horizontal contour signal which modifies the horizontal contour of pictures displayed at a CRT.

7. A receiver according to claim 6, wherein said H
contour means includes:
V average means for averaging signal components of said delayed video signal for a prescribed period of time to generate an averaged signal;
H filter means coupled to said V average means, for digitally low pass filtering said averaged signal to generate an H filtered signal; and H coefficient means coupled to said H filter means and being responsive to an H coefficient signal, for multiplying said H filtered signal by said H coefficient signal to generate said horizontal contour signal.