CA1250035A - Split-memory echo canceller - Google Patents

Abstract

SPLIT-MEMORY ECHO CANCELLER

Abstact of the Disclosure An echo canceller, for use in a digital transmission system, has two or more memory sections instead of one large memory. Each memory section is addressed by a part only of the outgoing signal word or history. Also, each memory section stores a partial echo estimate which comprises a part of the total echo estimate, which is obtained by summing the partial echo estimates. Such a "split" memory significantly reduces memory requirements.

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Description

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SPLIT-MEMORY ECHO CANCELLER

This application relates to Canadian patent application serial number 508,317 and Canadian patent application serial number 508,318, both filed May 2, 1986 in the name of M. Koohgoli.
Background of the Invention ._ .
The invention relates to echo cancellers and is especially, but not exclusively, related to echo cancellers for digital transmission systems, such as the telephone network.
To satisfy the demand for new services in the telephone network digital data must be transmitted over the usual two wire subscriber loops. Indeed, the specifications for the Integrated Services Digital Network (ISDN) require a minimum digital transmission rate of 144 kB/second on the subscriber loop. This rate is increased to about 160 kB/second by signalling, framing and other such overhead requirements. Of the various transmission techniques available, for example frequency division multiplexing (FDM), time compression multiplexing (TCM or "ping pong") and hybrid-plus-echo canceller (ECH), the hybrid-plus-echo canceller technique is preferred because it offers the greatest range.
In the hybrid-plus-echo canceller system signals are sent in opposite directions simultaneously and occupy the same frequency band.
The echo canceller is required because the incoming FAR END signal would be corrupted by echoes of the outgoing data signal (NEAR END).
Such echoes are due to leakage across the hybrid itself and reflections at discontinuities in the loop, for example gauge changes and bridged taps. The echo canceller reduces echoes by deriving, from ~P

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~2S0~35 the outgoing signal, an estimate of the echo signal and subtracting it from the incoming FAR END signal. If the estimate is accurate, the echo signal is subtracted out and only the actual FAR END signal remains. Such adaptive echo cancellers exploit the fact that the echo is a function of the signal sent out i.e. there is correlation betweén them.
In practice, there is a finite number (N) of preceding bits which contribute to the echo at any instant. The effect of earlier bits is negligible. Thus, the length of the echo is said to be N
bits. As an example, the echo length for a 160 kB/second TsDN signal is deemed, for practical purposes, to be from 8 to 16 bits.
In order to produce the echo estimate, the echo canceller must be supplied with information about the o~utgoing signal waveform for the preceding N bit period. One known kind of echo canceller, the ~ 15 transversai filter kihd, does this by feeding~ the slgnal through a `~ delay line and multiplying the delayed elements by adaptive :, coefficients. The multiples so produced~are summated to give the~
estimated echo signal for subtraction~from the~FAR~END slgnal. The~
coefflcients are adapted;progres~siv~ely until the~e~cho~ls eiiminated.
Unfortunately this kind of echo canceller is~not entirely satisfactory~
for cancell~ing "long" echoes,;especlally of~s1gnal~s~coded under, for~
example,~the AMI (~Automatlc Mark-~inversion~ format. ~Becau;se lt~has~t~o~
compute a~n~echo estlmate ln;each and e~very~sample~lnstant,~the conventl~onal transversal~;fi;~lt~er;~echo canceller~wo~ul~d gen~erally~be~
complex and require high speed components, and hence~not be sati~sfactory~for practlcal~appl1cat~ion~to such~sl~gnals. In: additlDn,~
it is limited to use with linear echo paths.

3~i A recent kind oF echo canceller, -the "memory" kind, is often preferred because it requires low speed hardware - since only one memory READ/WRITE and one addition are performed in sample time - and it can perform non-linear echo cancellation. Such a memory type of echo canceller is disclosed by ~essrs. Holte and S-tu-Fflotten in an article enti-tled "A New Digital Echo Canceller for Two-Wire Subscriber Lines", IEEE Trans. on Comm. Vol. 29, No. 11, Nov. 1981. They disclose a large digital memory used to hold echo estimates for all possible combinations of the N bits of the outgoing binary signal waveform~ The memory is addressed by the N bit word derived from the immediately preceding period of the outgoing waveform, the outgoing signal "history". The echo estimate corresponding to this word is read out of the memory, converted to an analogue signal by a D-to-A
converter and subtracted from the incoming (RECEIVED) signal. Each echo estimate in the memory is updated by incrementing/decrementing the estimate in a direction opposite to the sign of the estimation error i.e. such that the error is reduced.
A disadvantage of classical memory-type echo cancellers is that they require large memor1es. For an A~l signal, each outgoing data bit can take values of ~1, 0 or -I and thereFore requires 2 bits for identifying its value. For a 12 bit period echo canceller, sampled twice per bit, twenty-four outgoing samples, or forty-eight bits, are required to represent the history and therefore address the memory. The corresponding si~e of memory required, therefore, is

2**48 words, which is impractical. Accordingly such classical memory echo cancellers have limited use, restricted, say, to two-level transmission and to echo length less than eight bits.

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~ZS0~5 Another disadvantage oF the classical memory echo canceller is its long convergence time - typically measured in seconds. This is because each location o-F the memory must be accessed many times (depending on the initial value of each echo es-timate) for convergence to the true estimate.
Summary of the Invention The present invention seeks to eliminate, or at least mitigate, these disadvantages and, to this end, proposes to use two or more smaller memory sections instead of -the single large memory. Each memory section is addressed by a part only of the N bit outgoing signa7 word or history. Also, each memory section stores a partial echo estimate comprising only a part of the echo estimate corresponding to its own part of the outgoing signal "history" word.
The partial echo estimates from both or all memory sections are summed to give the total echo estimate for the N bit outgoing signal "history" word.
An advantage of such a split-memory echo canceller is that the total memory requirement is significantly reduced. For example, for a two-section split-memory echo canceller, the total memory requirement is reduced from 2**N to 2x2**(N/2). Since there is less memory to address, the convergence time is reduced proportionately.
Where a need arises to integrate the transmission/reception circuitry on one integrated circuit, it is desirable to reduce memory requirements even more, especially when AMI coded signals are used.
Since AMI signals have three levels, two bits of inFormation are required for each outgoing signal word. Therefore, for M transmitted data patterns, 2**M bits are needed to represent the outgolng data ~S~ [:)3~i history and address the memory. In order to reduce this requirement, embodiments of the present invention comprise an echo canceller For a digital transmission sys-tem including an encoder for converting a binary input signal to an alternate mark inversion (AMI) signal. The echo canceller may comprise:
a memory device having two or more sections for storing a plurality of digital words~ each comprising an estimate of the echo corresponding to a unique address word;
address means for addressing each said memory section with a plurality of unique addresses each comprising a sequence of said binary input signal and at least one state bit, the state of which represents the coding of the encoded signal corresponding to said sequence, summing means for summing the outputs of said memory sections;
a digital-to-analogue converter for converting said outputs to provide an echo signal estimate, subtractor means for subtracting said echo signal estimate from said binary input signalj and updating means responsive to the output of said subtractor means for increasing or decreasing the value of the corresponding digital word in the memory section.
With such an arrangement the length of the "history" word, i.e. the sequence of the binary input signal used to address the memory, is reduced from 2~ bits to ~1+1 bits.
A further increase in memory requirement occurs when oversampling of the input signal is employed. For example, a three . .

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~25~ 5 bit history word or input signal sequence, oversampled at a rate o-f four bits per period, would use a total of twelve bits in the same time frame. This would entail four shift registers, each three bits long and a memory capacity of 2**12 bits.
In order to reduce this requirement, some embodiments of the invention comprise an echo canceller for a digital transmission system having oversampling of -the binary input signal to the echo canceller.
Said echo canceller comprises:
a memory device having at least two sections for storing d plurality of digital words, each constituting an estimate of the echo corresponding to a unique address word;
address means for addressing each said memory section with a plurality of unique addresses each comprising a sequence of said binary input signal and a plurality of bi-ts representing the temporal position of each bit of said sequence in the corresponding bit period.
Thus, say the sequence is 101, sampled four times per bit period, giving a total sequence pattern 111100001111. Instead of twelve bits, however, the addressing means uses only five bits - the original sequence 101 plus two time-position indicator bits which in~icate which of the four possible time positions the sample bit occupies.
Brief Description of the Drawings An embodiment of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which:-Figure 1 is a schematic diagram of an echo canceller;

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Figure 2, comprising parts a and b, shows an AMI encoderand its associated waveforms;
Figure 3, comprising parts a and b, is a schematic diagram of an AMI state generator, comprising a part of the echo canceller, and its operating wave-forms;
Figure 4 is a waveform diagram for the echo canceller itself;
Figure 5, comprising parts a, b, and c, illustrates a conventional way of memory addressing in oversampled memory echo cancellers;
Figure 6 illustrates the addressing of an oversampled echo canceller according to the invention; and Figure 7 is a waveform diagram for the time position bit generator of the echo canceller.
Detailed Description of a Preferred Embodiment Referring now to Figure 1, a split-memory echo canceller is shown connected to an AMI encoder 10 which takes binary data from an outgoing binary data line 12 and codes it using alternate mark inversion (AMI) coding and applies it to the transmission line 14 going to the subscriber. The data line 12 constitutes an input to the echo canceller, in particular to a serial-to-parallel converter in the form of shift register 16 which is connected in series with a second serial-to-parallel converter in the form of second shift register 18.
The echo canceller shown in Figure 1 is for cancelling up to 16 bit periods of outgoing data echo and operating with 4 samples per bit period. Consequently~ the shift registers 16 and 18 each comprise 8 stages, the outputs of which are connected to the split memory, ~25~03~
sections of which comprise random access memories (RAMS) 20 and 22, respectively. In effect, the shift registers 16 and 18 convert the serial binary data to parallel data for addressing the RA~S 20 and 22, respectively.
Each of -the RAMS 20 and 22 comprises a 2K x 8 memory chip, for example the type HM6116 by Hitachi. RAM 20 is addressed by the most recent 8 bits of the outgoing binary (un-encoded) data stored by the sh1ft register 16. RAM or memory section 22 is addressed by the next most recent 8 bits of the outgoing data stored in shift register 18. In addi-tion, the RAMS 20 and 22 are addressed by single state bits from AMI state generators 24 and 26, respectively. The final two address inputs of RAMS 20 and 22 are addressed by the two time position indicators (comprising signals 2CLK and CLK) from the time position bit generator 28.
The AMI encoder 10, (Figure 2(a)), comprises an exclusive OR
gate 30 with one input connected to receive the binary data on line 12 and its other input connected to the Q output of a flip-flop 32. The D input of the flip-flop 32 is connected to the output of the exclusive-OR gate 30 and to the input of an inverting amplifier 34.
The input and output of the amplifier 34 serve to control switches 36 and 38, respectively. The switches 36 and 38 are connected in parallel between supply rails -V and ~V, respectively and a third switch 40. The latter is controlled by the binary data signal from line 12 and is connected to the input of an analogue buffer and driver 42. The output of the analogue buffer and driver 42 is connected to line 14.
The waveforms for the AMI encoder 10, shown in Figure 2(b), , , .

~ZS~ 35 include the clock CLK for flip-flop 32, the binary data signal, the signal at point s i.e., the output of the exclusive-OR gate 30, and the AMI encoded ou-tput.
The AllI state bit generator 24 is shown in more detail in Figure 3(a) and comprises an exclusive-OR gate 50 having its input connected to the binary data line and its output connected to the D
input of a flip-flop 52. The Q output of flip--flop 52 is connected to the second input of the exclusive-OR gate and the state bit output for the corresponding RAM 20 or 22 is taken from the output of the exclusive-OR gate.
The waveforms applied to and generated by the AMI state generator are shown in Figure 3(b) and comprise the clock, data, state bit and Q output of the flip-flop 52.
The waveforms applied to and generated by the time position bit generator, in the form of flip-flop 28, are shown in Figure 7. A
clock signal 2CLK is applied to the flip-flop 28 and also applied to the most significant of the associated two addresses of the RAMS 20 and 22, respectively. The clock signal CLK from the Q output of the divide-by-2 flip-flop is applied to the shift registers 16 and 18 and also to the next most significant address port of each of the RAMS 20 and 22.
Considering the echo canceller as a whole again, in operation, and as illustrated in timing diagram Figure 3, four echo canceller cycles, each comprising four sections, are repeated in each bit period of the binary data signal. ~ere "bit period" refers to the period of the binary data signal.
In the first section of the cycle, both memory sections i.e.

~2S~35 RAI~S 20 and 22, are dddressed by the outgoing data histories from shift registers 16 and 18, the state bits from the AMI state bit generators 24 and 26, and the sample time position indicator bits from flip-flop 28. With both RA~S in the READ mode, (signals applied to READ inputs 56 and 58 of RAMS 20 and 22 respectively), the partial echo estimate is read out from each memory. These partial estimates are added together by a summer 60 and also stored in registers 62 and 64 respectively, each of which is an 8 bit register. Such storage takes place on the rising edges of the control signals L1, L2 shown in Figure 4.
~ n the second section of the cycle the result of the addition by summer 60, comprising the total echo estimate signal is transferred to register 66. This occurs on the rising edge of the DAOLK control line (see Figure 4). This total echo estimate signal is then applied by the register 66 to a digital-to-analogue converter 68. At the conclusion of this cycle a subtracter 70 subtracts the total analogue echo estimate (from the output of the digital-to-analogue converter) from the incoming signal, which comprises far end signal and echo. The residual signal is supplied as an output from the echo canceller on line 72 to a data recovery circuit (not shown) and also is applied to a comparator 74. The comparator 74 serves to determine the sign of the residual signal and store it in a flip-flop 76 on the rising edge of control signal SCLK
(see Figure 4). This sign signal is used to determine whether the correction applied to the RAI~S 20 and 22 should be up or dGwn. The actual increment or decrement each time is a single bit. A greater number may be used if faster convergence is preferred.

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~5~35 As mentioned previously, the output from the RAMS 20 and 22 was applied to registers 62 and 64, respectively. At the beginning of the third sec-tion of the cycle the sign bit and contents oF regis-ter 62 are applied to summer 78. The incremented or decremented output of the summer 78 is applied to a tristate buffer 80. The tristate buffer 80 writes the new memory word comprising the output of summer 78 into RAM 20. More specifically, the READ/WRITE signal for RAM 20 is held low for a WRITE operation and the tristate buFfer 80 is enabled by bringing the control signal UDG1 (see Figure 1) to a low level.
In the fourth section of the cycle, a similar procedure is used to update the second memory section comprising RAM 22. In this case the old partial echo estimate is enabled from register 64, updated by adding or subtracting the sign bit and the revised or new partial echo estimate applied by means of tristate buffer 82 to RAM
22.
The same sequence of operations is repeated during the next echo canceller cycle.
So far as the reduction attributable to the AMI state bit is concerned, it should be appreciated that the contents of the memory sections, RAI~lS 20 and 22, will comprise individual unique words as the partial echo estimates, but that, for a given pattern of 8 bits and a given pair of time position bits, there will be two possible partial echo estimates from which to choose. The choice will be dependent upon the state of the AMI state generator bit applied to input A8 (as shown in Figure 1). Although the memory size is doubled by virtue of doubling the number of words for each particular sequence, the total saving is a factor of 2M-1 due to the reduction of the number of . ~ ~

~25~35 address bits from 2~ to M+1, where M is the number of history bits of the binary da-ta signal.
It should also be appreciated that the invention is not limited to AMI code but could be applied to other line codes.
The improvement or reduction in memory attributable to the use of the time position indicator means can be seen by referring to Figures 5 and 6. In both Figures, the binary data signal, shown here as 101, is sampled at four samplings per bit period as shown in Figure 5(b). The conventional arrangement shown in Figure 5 shows that the contents of the shift register (16 or 18) change sequentially as the data is clocked into it. Eventually the shift register contains the 12 bits 111100001111 which are used to address the memory. Every shif-t register word will have a corresponding memory word.
As illustrated in Figure 6, however, the echo canceller embodying the present invention uses the time position bits to encode the corresponding position in the bit period of each individual sample. Thus, in the particular example of four samples per bit period, only 2 bits are needed to designate the sample period or sampling instant. The table shown as Figure 5(c) shows the contents of the shift register, in this case shown as having only 3 bits content rather than the 8 bits content of the actual embodiment. At any sampling instant, the shift register contents comprise the actual bit of the data signal plus two time position indicator bits. These show to which sampling instant the signal applies. Thus9 in Figure 5(c) during the first four positions the shift register contents comprise the same 1 bit but the time position indicator bits change as they cycle through the four possible combinations 00, 01, 10, and 11.

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~5~5 Each address word has d unique partial echo estimate corresponding to it in the corresponding one of RAMS 20 and 22. Thus, although the binary word part of the shift register contents might remain the same for ~ bit periods, there will in effect be four distinct address words as the time position indicator bits change.
It will be appreciated that other numbers of time position indicator bits might be used to accommodate different sampling rates.

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Claims (16)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:-

1. An echo canceller, for a digital transmission system, comprising:-a memory having at least two sections, each for storing a plurality of digital words, each word comprising a partial estimate of the echo corresponding to a unique sequence of the binary signal;
address means for addressing each said memory section with a plurality of unique address words, each comprising a part of said sequence;
summing means for summing corresponding partial estimate signals from respective said memory sections;
digital-to-analogue conversion means for converting the partial echo signals to provide an echo estimate; and subtractor means for subtracting the echo estimate from an incoming said binary signal; and updating means responsive to the output of said subtractor means for increasing or decreasing the value of the corresponding digital word in the memory section.

2. An echo canceller for a digital transmission system having oversampling of the binary input signal to the echo canceller, said echo canceller comprising:
a memory device having at least two sections for storing a plurality of digital words, each constituting an estimate of the echo corresponding to a unique address word;

address means for addressing each said memory section with a plurality of unique addresses each comprising a sequence of said binary input signal and a plurality of bits representing the temporal position of each bit of said sequence in the corresponding bit period;
summing means for summing the outputs of said memory sections;
a digital-to-analogue converter for converting said outputs to provide an echo signal estimate;
subtractor means for subtracting said echo signal estimate from said binary input signal; and updating means responsive to the output of said subtractor means for increasing or decreasing the value of the corresponding digital word in the memory section.

3. An echo canceller for a digital transmission system including an encoder for converting a binary input signal to an encoded signal, said echo canceller comprising:
a memory device having two or more sections for storing a plurality of digital words, each comprising an estimate of the echo corresponding to a unique address word;
address means for addressing each said memory section with a plurality of unique addresses each comprising a sequence of said binary input signal and at least one state bit, the state of which represents the coding of the encoded signal corresponding to said sequence;
summing means for summing the outputs of said memory sections;

a digital-to-analogue converter for converting said outputs to provide an echo signal estimate;
subtractor means for subtracting said echo signal estimate from said binary input signal; and updating means responsive to the output of said subtractor means for increasing or decreasing the value of the corresponding digital word in the memory section.

4. An echo canceller as defined in claim 1, wherein said address means comprises a serial-to-parallel converter for converting sequences of said binary input signal into said address words.

5. An echo canceller as defined in claim 2, wherein said address means comprises a serial-to-parallel converter for converting sequences of said binary input signal into said address words.

6. An echo canceller as defined in claim 3, wherein said address means comprises a serial-to-parallel converter for converting sequences of said binary input signal into said address words.

7. An echo canceller as defined in claim 2, including generator means for generating a number of bits representing the temporal position in the bit period of the sampling instant to which the address word corresponds.

8. An echo canceller as defined in claim 3, including a state bit generator for generating at least one bit representing the coding of the encoded signal.

9. An echo canceller as defined in claim 8, wherein the binary input signal is alternate mark inversion (AMI) encoded, and said state generator generates a bit representing the polarity of the address word.

10. An echo canceller as defined in claim 1, for a digital transmission system having oversampling of a binary signal and an encoder for encoding said binary signal, said echo canceller comprising:-a memory having at least two sections, each for storing a plurality of digital words, each word comprising a partial estimate of the echo corresponding to a unique sequence of the binary signal;
address means for addressing each said memory section with a plurality of unique address words, each comprising a sequence of said input binary signal, a plurality of bits representing the temporal position of each bit of said sequence in the corresponding bit period and at least one state bit the state of which represents the coding of the encoded signal corresponding to said sequence;
summing means for summing corresponding partial estimate signals from respective said memory sections;
digital-to-analogue conversion means for converting the partial echo signals to provide an echo estimate; and subtractor means for subtracting the echo estimate from an incoming said binary signal; and updating means responsive to the output of said subtractor means for increasing or decreasing the value of the corresponding digital word in the memory section.

11. An echo canceller as defined in claim 10, wherein said address means comprises a serial-to-parallel converter for converting sequences of said binary signal into address words.

12. An echo canceller as defined in claim 10, further including generator means for generating a number of bits representing the temporal position in the bit period of the sampling instant to which the address word bits correspond.

13. An echo canceller as defined in claim 10, further including a state bit generator for generating at least one bit representing the coding of the binary signal.

14. An echo canceller as defined in claim 11, further including a state bit generator for generating at least one bit representing the coding of the binary signal.

15. An echo canceller as defined in claim 12, further including a state bit generator for generating at least one bit representing the coding of the binary signal.

16. An echo canceller as defined in claim 13, 14 or 15, wherein the binary signal is alternate mark inversion (AMI) coded and said state generator generates one bit representing the instant polarity of the address word.