CA1228925A - Data decoding apparatus - Google Patents
Data decoding apparatusInfo
- Publication number
- CA1228925A CA1228925A CA000447989A CA447989A CA1228925A CA 1228925 A CA1228925 A CA 1228925A CA 000447989 A CA000447989 A CA 000447989A CA 447989 A CA447989 A CA 447989A CA 1228925 A CA1228925 A CA 1228925A
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- Canada
- Prior art keywords
- data
- code
- decoding
- codes
- decoded
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T9/00—Image coding
- G06T9/005—Statistical coding, e.g. Huffman, run length coding
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/40—Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code
- H03M7/42—Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code using table look-up for the coding or decoding process, e.g. using read-only memory
- H03M7/425—Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code using table look-up for the coding or decoding process, e.g. using read-only memory for the decoding process only
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Multimedia (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Compression Of Band Width Or Redundancy In Fax (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
A data decoding apparatus decodes MH codes having different code lengths in real time and at high speed. The apparatus has an image memory, a tristate buffer group, a parallel to serial converter, code length and run length decode ROMs, and a PAL
group if desired. The tristate buffer from which the next code is to be read out can be selected immedi-ately after decoding a given code in accordance with the code length of the given code. The PAL group is used to detect an end of line if an error occurs in a given line. The error can be eliminated with one line.
A data decoding apparatus decodes MH codes having different code lengths in real time and at high speed. The apparatus has an image memory, a tristate buffer group, a parallel to serial converter, code length and run length decode ROMs, and a PAL
group if desired. The tristate buffer from which the next code is to be read out can be selected immedi-ately after decoding a given code in accordance with the code length of the given code. The PAL group is used to detect an end of line if an error occurs in a given line. The error can be eliminated with one line.
Description
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The present invention relates to a data decoding apparatus in an image file or a facsimile system. The apparatus of the invention is particularly suitable for high-speed decoding of image signals which are run-length-coded by the modified Huffman encoding method (one-dimensional compression) and stored or transmitted.
In conventional apparatus of this type, where the effective code lengths of the data vary as in MH codes, the processing speed during decoding cannot be kept cons-tant. When printing is to be performed using decodedsignals, a printer is required which is capable of changing the subscanning speed such as the paper feed speed. When decoded signals are supplied to a high-speed electrostatic printer which has a predetermined subscanning speed, the decoded signals are first stored in a one-page memory and are then supplied to the printer. Furthermore, since de-coding is performed by software processing using a micro-processor, processing speed is limited.
Since the code lengths vary, a varying code shift delay follows between decoding of one code and com-mencement of decoding of a subsequent code, as this subse-quent code is loaded into the decoder, causing a waiting time during signal processing.
Moreover, when a decoding error occurs due to a bit drop of a code or the likel colour inversion of a mono-chromatic image can be caused.
Since the apparatus must be designed for 39Z~
; processing codes having a maximum permissible length, the number of signal lines and the capacity of memory elements and the like must be increased, resulting in higher costs and other disadvantages.
The present invention has for an object to pro-vide a data decoding apparatus of simple configuration which can decode compressed codes, such as MH codes, quickly and reliably at constant speed, and without vari-able shifting delays between successive decoding operations.
It is another object of the present invention to provide a data decoding apparatus which has a capability of recovering from errors occurring during a decoding opera-tion.
It is still another object of the present inven-tion to provide a data decoding apparatus which can be directly connected to a high-speed printer which has a constant subscanning speed, so that the apparatus can de-code the input coded signals in real time and does not require a one-page memory.
According to the invention, there is provided data encoding apparatus for decoding codes obtained by cornpression, comprising memory means for continuously storing a plurality of codes to be decoded; decoding means for de-coding the codes stored in said memory means; a plurality of discriminating means for discriminating as to whether or not a specific data is stored in any one of memory locations of said memory means; and control means for controlling the decoding operation of said decoding means in accordance ,~, ~2~:8~
with the discriminating result by said plurality of dis-criminating means.
The invention extends to a data decoding appara-tus for decoding codes obtained by compression, comprising memory means for storing a plurality of codes which are to be decoded and which are of variable length; read means for reading out a predetermined amount of data from said memory means on a parallel basis, said predetermined amount of data being less than the amount of data stored in said memory means; decoding means for decoding a code contained in data read out in parallel from said memory means; and control means for controlling operation of said read means, said control means identifying code stored in said memory means and causing said read means to read out in parallel data containing the identified code from said memory means.
The invention also extends to a data decoding apparatus for decoding codes obtained by compression, comprising memory means for continuously storing a plural-ity of codes which are to be decoded and which are ofvariable length; read means for reading out a predeter-mi.ned amount of data from said memory means; decoding means for decoding a code contained in the predetermined amount of data read out from said memory means; detecting means for detecting a length of the code decoded by said decoding means; and control means for controlling opera-tion of said read means so as to read out from said memory 12~r~
means the predetermined amount of data containing code subsequent to the code decoded by said decoding means, in accordance with the length of the code detected by said detecting means.
The invention also extends to a data decoding apparatus for decoding codes obtained by compression, comprising input means for inputting the code which is to be decoded and which comprises plural binary signals;
detecting means for detecting the number of consecutive specific signals of the code input by said inputting means;
and decoding means for decoding the code input by said in-putting means in accordance with the number of consecutive specific signals detected by said detecting means and signals other than the consecutive specific signals of the code.
The invention also extends to a data decoding apparatus Eor decoding codes obtained by compression, comprising memory means for continuously storing the codes to be decoded, said codes each comprising plural binary signals; read means for reading out data stored in said memory rneans; decoding means for decoding the codes in accordance with the data read out from said memory means;
and read control means for detecting the number of conse-cutive specific signals of the code, and for controlling a out operation of said read means in accordance with a detected number of the consecutive specific signals so as to supply signals other than the consecutive specific ~Z~8~
signals of the code to said decoding means.
The invention also extends to a data decoding apparatus for decoding codes obtained by compression, comprising storage means for storing the codes which are to be decoded and which are of variable length; memory means for storing a predetermined amount of data read out from said storage means; decoding means for decoding the code contained in the data stored in said memorv means;
and control means for controlling a read out operation of the data from said storage means into said Emory means, in accordance with a length of the eode deeoded by said deeoding means.
The invention also extends to a data deeoding apparatus for decoding codes obtained by compression, eomprising inputting means for inputting data containing the codes to be decoded; memory means for storing the data input from said input means, and for outputting the data in parallel; decoding means for decoding the code eontained in the data eode output in parallel from said memory means; and control means for performing such a control that the data containing eode to be subsequently deeoded is outputted from an arbitrary location of said memory means without a waiting time after completion of the decoding operation of said deeoding means.
The above and other features of the invention will beeome apparent from the following description taken in eonjunction with the accompanying drawings, in which:
~228g25 Fig. 1 is a block diagram showing the schematic configuration of a data decoding apparatus according to the present invention; and Fig. 2 is a block diagram showing the details of a circuit for realizing the decoding apparatus shown in Fig. 1.
The preferred embodiment of the present invention is now described in detail with reference to the accompany-ing drawings.
Fig. 1 is a block diagram showing the schematic configuration of a decoding apparatus adopting the MH
method. An image memory 1 stores MH code image signals.
The image memory 1 can be an image file memory having a capacity corresponding to at least one page such as an optical or magnetic disk. The image memory 1 can be a data memory for storing image signals transmitted from a remote location through signal lines. The MH code data is read out from the image memory 1 in units of 24 bits in paral-lel. A read address counter 2 is a counter for supplying a read address to the image memory 1.
A parallel to serial converter 3 receives the 24-bit parallel data from the image memory 1 through an output data bus On. The converter 3 divides the input 24-bit parallel data into three parallel data blocks and arranges each parallel data block serially. The converter 3 includes a ternary counter 101 (Fig. 2) which increments by one the count of the read address counter 1 upon .
~22~
- 6a -shifting the 8-bit parallel data blocks every three times.
With this configuration, the time lag is avoided which would be required with a configuration using bit-wise shift registers for sequentially converting the 24-bit data into 8-bit data.
Groups of adjacent bits from the 24-bit data 14 from the parallel to serial converter 3 are applied to a group 4 of fourteen tristate buffers, each group having a one bit offset from its predecessor, each group being selectable by an offset value 15 from an offset register 9 for immediate application of its data to a run length de-code ROM 5 and a code length decode ROM 7. The offset value 15 represents a starting position in the 24-bit data 14, parallel-shifted in units of 8 bits, from which the MH
code is to be extracted, corresponding to a position at which the MH codes are segmented. The tristate buffer group 4 comprises a plurality (14) of tristate buffers which have input lines connected to the signal line 14 and outputs which are wired ORed to common output lines. When a desired tristate buffer is selected, the data it con-tains appears on the output lines. In other words, when one of the 14 tristate buffers each corresponding to one code is enabled, a continuous code data (MH code) of 13 bits or less starting from a predetermined bit of the 24-bit input data can be instantaneously extracted. Wi-th such 8-bit parallel processing, MH codes having different effective code lengths can be easily extracted at high speed.
~2~ 5 - 6b -More specifically, if a given MH code consists of the 3 low order bits of a particular tristate buffer, then the subsequent MH code is stored in the third follow"-ing tristate buffers beyond the tristate buffer storing that given MH code. This following tristate buffer can then be selected to allow instantaneous read out of the MH code without requiring a 3-bit shift operation. The MH
code supplied to the run length decode ROM 5 is converted into run length data. The run length decode ROM 5 stores a conversion look-up table, addressed by an My code for producing a corresponding run length as output data.
The run length data from the ROM 5 is counted by the run length counter 6 which produces a black or white bit number.
- 7 8~25 1 A signal ripple carry out RCO representing an end of a counting operation of a run length counter 6 is supplied to itself to load the next run length data and is also supplied to and inverts a toggle flip flop 13 which produces a signal representing whether the run length data received from the ROM 5 is black or white. In accordance with the output from the toggle flip-flop 13 and the output from the counter 6, a continuous video signal is obtained in which a black bit group and a white bit group alternately appear. The video signal from the flip-flop 13 is supplied to a high speed printer or the like. The code length decode ROM 7 stores a conversion table for converting, in a similar manner to that in the run length decode ROM 5, the MH code into an address and producing as output data the effective code length of the Mel code contained in the 13-bit data selectively supplied from the tristate buffer group I. A code length 17 from the code length decode ROM 7 is
The present invention relates to a data decoding apparatus in an image file or a facsimile system. The apparatus of the invention is particularly suitable for high-speed decoding of image signals which are run-length-coded by the modified Huffman encoding method (one-dimensional compression) and stored or transmitted.
In conventional apparatus of this type, where the effective code lengths of the data vary as in MH codes, the processing speed during decoding cannot be kept cons-tant. When printing is to be performed using decodedsignals, a printer is required which is capable of changing the subscanning speed such as the paper feed speed. When decoded signals are supplied to a high-speed electrostatic printer which has a predetermined subscanning speed, the decoded signals are first stored in a one-page memory and are then supplied to the printer. Furthermore, since de-coding is performed by software processing using a micro-processor, processing speed is limited.
Since the code lengths vary, a varying code shift delay follows between decoding of one code and com-mencement of decoding of a subsequent code, as this subse-quent code is loaded into the decoder, causing a waiting time during signal processing.
Moreover, when a decoding error occurs due to a bit drop of a code or the likel colour inversion of a mono-chromatic image can be caused.
Since the apparatus must be designed for 39Z~
; processing codes having a maximum permissible length, the number of signal lines and the capacity of memory elements and the like must be increased, resulting in higher costs and other disadvantages.
The present invention has for an object to pro-vide a data decoding apparatus of simple configuration which can decode compressed codes, such as MH codes, quickly and reliably at constant speed, and without vari-able shifting delays between successive decoding operations.
It is another object of the present invention to provide a data decoding apparatus which has a capability of recovering from errors occurring during a decoding opera-tion.
It is still another object of the present inven-tion to provide a data decoding apparatus which can be directly connected to a high-speed printer which has a constant subscanning speed, so that the apparatus can de-code the input coded signals in real time and does not require a one-page memory.
According to the invention, there is provided data encoding apparatus for decoding codes obtained by cornpression, comprising memory means for continuously storing a plurality of codes to be decoded; decoding means for de-coding the codes stored in said memory means; a plurality of discriminating means for discriminating as to whether or not a specific data is stored in any one of memory locations of said memory means; and control means for controlling the decoding operation of said decoding means in accordance ,~, ~2~:8~
with the discriminating result by said plurality of dis-criminating means.
The invention extends to a data decoding appara-tus for decoding codes obtained by compression, comprising memory means for storing a plurality of codes which are to be decoded and which are of variable length; read means for reading out a predetermined amount of data from said memory means on a parallel basis, said predetermined amount of data being less than the amount of data stored in said memory means; decoding means for decoding a code contained in data read out in parallel from said memory means; and control means for controlling operation of said read means, said control means identifying code stored in said memory means and causing said read means to read out in parallel data containing the identified code from said memory means.
The invention also extends to a data decoding apparatus for decoding codes obtained by compression, comprising memory means for continuously storing a plural-ity of codes which are to be decoded and which are ofvariable length; read means for reading out a predeter-mi.ned amount of data from said memory means; decoding means for decoding a code contained in the predetermined amount of data read out from said memory means; detecting means for detecting a length of the code decoded by said decoding means; and control means for controlling opera-tion of said read means so as to read out from said memory 12~r~
means the predetermined amount of data containing code subsequent to the code decoded by said decoding means, in accordance with the length of the code detected by said detecting means.
The invention also extends to a data decoding apparatus for decoding codes obtained by compression, comprising input means for inputting the code which is to be decoded and which comprises plural binary signals;
detecting means for detecting the number of consecutive specific signals of the code input by said inputting means;
and decoding means for decoding the code input by said in-putting means in accordance with the number of consecutive specific signals detected by said detecting means and signals other than the consecutive specific signals of the code.
The invention also extends to a data decoding apparatus Eor decoding codes obtained by compression, comprising memory means for continuously storing the codes to be decoded, said codes each comprising plural binary signals; read means for reading out data stored in said memory rneans; decoding means for decoding the codes in accordance with the data read out from said memory means;
and read control means for detecting the number of conse-cutive specific signals of the code, and for controlling a out operation of said read means in accordance with a detected number of the consecutive specific signals so as to supply signals other than the consecutive specific ~Z~8~
signals of the code to said decoding means.
The invention also extends to a data decoding apparatus for decoding codes obtained by compression, comprising storage means for storing the codes which are to be decoded and which are of variable length; memory means for storing a predetermined amount of data read out from said storage means; decoding means for decoding the code contained in the data stored in said memorv means;
and control means for controlling a read out operation of the data from said storage means into said Emory means, in accordance with a length of the eode deeoded by said deeoding means.
The invention also extends to a data deeoding apparatus for decoding codes obtained by compression, eomprising inputting means for inputting data containing the codes to be decoded; memory means for storing the data input from said input means, and for outputting the data in parallel; decoding means for decoding the code eontained in the data eode output in parallel from said memory means; and control means for performing such a control that the data containing eode to be subsequently deeoded is outputted from an arbitrary location of said memory means without a waiting time after completion of the decoding operation of said deeoding means.
The above and other features of the invention will beeome apparent from the following description taken in eonjunction with the accompanying drawings, in which:
~228g25 Fig. 1 is a block diagram showing the schematic configuration of a data decoding apparatus according to the present invention; and Fig. 2 is a block diagram showing the details of a circuit for realizing the decoding apparatus shown in Fig. 1.
The preferred embodiment of the present invention is now described in detail with reference to the accompany-ing drawings.
Fig. 1 is a block diagram showing the schematic configuration of a decoding apparatus adopting the MH
method. An image memory 1 stores MH code image signals.
The image memory 1 can be an image file memory having a capacity corresponding to at least one page such as an optical or magnetic disk. The image memory 1 can be a data memory for storing image signals transmitted from a remote location through signal lines. The MH code data is read out from the image memory 1 in units of 24 bits in paral-lel. A read address counter 2 is a counter for supplying a read address to the image memory 1.
A parallel to serial converter 3 receives the 24-bit parallel data from the image memory 1 through an output data bus On. The converter 3 divides the input 24-bit parallel data into three parallel data blocks and arranges each parallel data block serially. The converter 3 includes a ternary counter 101 (Fig. 2) which increments by one the count of the read address counter 1 upon .
~22~
- 6a -shifting the 8-bit parallel data blocks every three times.
With this configuration, the time lag is avoided which would be required with a configuration using bit-wise shift registers for sequentially converting the 24-bit data into 8-bit data.
Groups of adjacent bits from the 24-bit data 14 from the parallel to serial converter 3 are applied to a group 4 of fourteen tristate buffers, each group having a one bit offset from its predecessor, each group being selectable by an offset value 15 from an offset register 9 for immediate application of its data to a run length de-code ROM 5 and a code length decode ROM 7. The offset value 15 represents a starting position in the 24-bit data 14, parallel-shifted in units of 8 bits, from which the MH
code is to be extracted, corresponding to a position at which the MH codes are segmented. The tristate buffer group 4 comprises a plurality (14) of tristate buffers which have input lines connected to the signal line 14 and outputs which are wired ORed to common output lines. When a desired tristate buffer is selected, the data it con-tains appears on the output lines. In other words, when one of the 14 tristate buffers each corresponding to one code is enabled, a continuous code data (MH code) of 13 bits or less starting from a predetermined bit of the 24-bit input data can be instantaneously extracted. Wi-th such 8-bit parallel processing, MH codes having different effective code lengths can be easily extracted at high speed.
~2~ 5 - 6b -More specifically, if a given MH code consists of the 3 low order bits of a particular tristate buffer, then the subsequent MH code is stored in the third follow"-ing tristate buffers beyond the tristate buffer storing that given MH code. This following tristate buffer can then be selected to allow instantaneous read out of the MH code without requiring a 3-bit shift operation. The MH
code supplied to the run length decode ROM 5 is converted into run length data. The run length decode ROM 5 stores a conversion look-up table, addressed by an My code for producing a corresponding run length as output data.
The run length data from the ROM 5 is counted by the run length counter 6 which produces a black or white bit number.
- 7 8~25 1 A signal ripple carry out RCO representing an end of a counting operation of a run length counter 6 is supplied to itself to load the next run length data and is also supplied to and inverts a toggle flip flop 13 which produces a signal representing whether the run length data received from the ROM 5 is black or white. In accordance with the output from the toggle flip-flop 13 and the output from the counter 6, a continuous video signal is obtained in which a black bit group and a white bit group alternately appear. The video signal from the flip-flop 13 is supplied to a high speed printer or the like. The code length decode ROM 7 stores a conversion table for converting, in a similar manner to that in the run length decode ROM 5, the MH code into an address and producing as output data the effective code length of the Mel code contained in the 13-bit data selectively supplied from the tristate buffer group I. A code length 17 from the code length decode ROM 7 is
2~ accumulated and added in the offset register 9 through an adder group 8. When all inputs C, D and E of the adder group 8 are "0", the original offset value 15 in the offset register 9 is supplied to an input A of the adder group 8. Since an updated code length 17 is 2~ supplied to an input B of the adder group 8, upon a supply of a clock to the offset register, the updated offset value 15 is given by:
~228~5 1 updated offset value = original offset value + code length This updated offset value provides the start offset value of the MH code subsequent to the MH code currently decoded. When the selection of a tristate buffer in the tristate buffer group 4 is performed in accordance with this updated offset value, data starting immediately after the code length of the MH
code currently being coded can be instantaneously read out and this next MH code can be discriminated. In this manner, boundaries of continuously supplied MH
codes which have different code lengths can be easily discriminated and decoding of these MH codes can be performed easily.
Since the length of data which can be stored in the parallel to serial converter 3 is definite, supplementation must be performed. This means of supplementation will be described. When the offset value l5 exceeds 8, a comparator ll detects this and 2() shifts the parallel to serial converter 3 by 8-bits and sets new 8-bit data. Also, the comparator ll also supplies "-8" to an input E of the adder group 8.
Then, the updated offset value in this case is given by:
2~ updated offset value = original offset value + code length - 8 9 ~2Z~3~25 1 Then, data is shifted by 8 bits and the offset value is similarly shifted. For this reason, the relative positions of the data set in the parallel to serial converter 3 and the offset value in the offset register S 9 remain unchanged. The 8-bit shift is performed by the buffer, decoder and ternary counter as described above. Every time the count of the ternary counter reaches 2, 8-bit shift of the 24-bit data has been performed three times, and the next 24-bit data is read out from the image memory 1. In this manner, the serial data 14 as viewed from the offset register 9 appears as data of an indefinite length with no boundaries between the MH codes.
Upon completion of decoding of a given MH code, the next MH code can be loaded simultaneously or immediately thereafter. For this reason, continuous MH code decoding can be performed at high speed without waiting time. For this reason, a printer or the like which operates intermittently and synchro-2() nously with the decoding operation is not required.An EOL (End of Line) code (a sync signal representing an end of one line) which is a special type of data in the MH code is decoded by a separate special decoder.
This special decoder is an EOL decoder group 12 which receives the 24-bit data from the parallel to serial converter 3~parallel to the tristate buffer group 4.
The EOL decoder group 12 comprises fourteen 13-bit ,~
~228~
1 input PALs (Programable array Logics). The EOL decoder group 12 decodes the serial data which is shifted in units of bits. When one of the PALs detec'cs the EOL
code, a 13-input OR gate produces an EOL signal 18.
At the same time, an offset value 19 corresponding to the detected EOL code is produced. When one of the PAI,s of the EOL decoder group 12 decodes the EOL code, an EOL detection signal line 18 is set at level to reset the toggle flip-flop 13 and to produce a ~7hite video siynal for the next line input. At the same tire, the line 18 serves to cause the adder group 8 to disregard the inputs A, B and E and to add the inputs C and D. At this time, the input C of the adder group 8 receives "12" as the code length oE the EOL code, and the input D thereof receives the offset value 19 corresponding to the detected EOL code. As a result, the offset value 15 is updated as follows:
updated offset value = offset value of EOL
decoder group + 12 2n The EOL code is decoded by the special hardware for the following reason. If decoding generates an error due to a bit drop or the like, the resultant error, black and white inversion error or the like must be (confined within the current line; this error must be prevented from being extended to the entire screen.
The EOL code is decoded by the special hardware to correctly detect an end of each line to attain this.
L22~92S
1 If there is no error in the decoding operation, in the outputs to the adder group 8, during the EOL code detection the input B representing the code length is equal to the input C, and the input D representing the offset value is equal to the sum of the inputs A and E.
In this manner, since the offset register is reset, the extracting start position of the MH code of the next line is correctly given by the EOL code.
The EOL code can be given as a horizontal sync signal for the recording operation of the printer.
The configuration and mode of operation of the respective blocks of the apparatus shown in Fig. l will now be described in detail with reference to Fig. 2. Referring to Fig. 2, a signal line mark (~) represents that the corresponding signal line consists of a plurality of signal lines and the attached number shows the number of such signal lines. The same reference numerals as in Fig. l denote the same parts 2() in Fig. 2. A basic clock O is supplied to some clrcuit elements of the apparatus. Parallel output (l~word 24-bit data Do to D23) from the image memory (not shown) is latched in a D latch l00. The latching timing is when the ripple carry out of a ternary counter l0l is set at H level and the A > B output from the comparator ll is set at level. The latched data Do to D23 is divided into continuous bit data :..,~' - 12 - 12~8~2~
1 which are respectively wired-O~input to a D latch 105 through tristate buffers 102, 103 and 104. One of the tristate buffers 102 to 104 is selected by an output from a decoder 130, and the 8-bit data stored in the selected buffer is latched in the D latch 105. The 8-bit parallel data supplied to the D latches 105, 106 and 107 are parallel-to-serial converted in the form of t-hc 8-bit parallel, byte serial. The 24-bit data from the parallel to serial converter 3 is supplied to the tristate buffer group 4, and 8-bit data which are shifted in units of bits are stored in bits Do to D7, Dl to D8, D2 to Dg, and so on of tristate buffers 108, 109, 110, and so on. Of the outputs ~0 to D23, one stored in a selected one of the tristate buffers 15 108 to 111 of the tristate buffer group 4 is selected to allow selection of 8-bit data starting from a desired bit. When the tristate buffer 110, for example, is selected the outputs D2 to Dg are supplied to the run length decode ROM 5 and the code length ~() decode ROM 7. Since the maximum code length of the MH
codes is 13, theoretically a tristate buffer group consisting of 13-bit tristate buffers is required.
However, in the embodiment shown in Fig. 2, the initial signal, four or five fill bits "0"s of the MH
code are decoded by a separate circuit (this is based on the special characteristics of the MH codes).
This allows decoding of MH codes with data of less than 8 bits, thus sLmplifying the circuit.
- 13 - ~2~8~
1 A PAL 112 decodes the initial consecutive fill bits "0"s of the MH code. PAL is a tradename of U.S.A. Monolithic Memories Inc. and stands for programable array logic. Two devices "PAL18L4", for example, are combined to program with the logic as shown in Table 1 below. If there is no "0" from the start address indicated by the offset value from the offset register 9, a zero bit discrimination output "0" is produced. If there is at least one "0", a zero bit discrimination output "l" is produced. If there is four "0"s, a zero bit discrimination output "2" is produced. If there is five "0"s, a zero bit discrimination output "3" is produced. The zero bit discrimination output is supplied to a data selector 113 and is supplied as an address selection data to the two ROMs 5 and 7. Based on the input zero bit discrimination signal, the data selector 113 selects one of "0", "1", "4" and "5" (each representing a consecutive number of zeros) and produces a binary 2() number representing the selected number. The output from the data selector 113 is added to the offset value 15 by an adder 114, and the sum is supplied to an offset decoder 10. Accordingly, the buffer selected from those of the tristate buffer group 4 produces consecutive 8-bit data from a position shifted by the output from the data selector 113, that is, from the buffer one buffer to the right from the current buffer , - 14 - ~2289Z~
1 if there is one "0" in the My code. When the output from the data selector 113 is "0", the MH code consists of less than 8 bits. In this case, the addition by the adder 114 is not performed.
When the initial "0" or "0"s of the MH code are decoded by a separate circuit, the capacity of the tristate buffer group can be saved, and the number of address lines of the decode ROM can also be reduced.
When the accumulation result of the code length upon the shift operation of the tristate buffer group 4 exceeds 8, the output from the offset register 9 exceeds 8. Accordingly, the comparator 11 discrimi-nates this and renders the converter 3 operative.
; Then, the latches 105 to 107 are shifted by 8 bits.
That is, the data in the latch 105 is shifted to the latch 106, the data in the latch 106 is shifted to the latch 107. This means that the data to the tristate buffer group 4 is shifted by 8 bits. The respective buffers and latches are bit-connected such that the 2() bits 1 to 8 of the latch 107 are connected to the bits ; 1 to 8 of the buffer 108, and the bits 2 to 8 of the latch 107 and the bit 1 of the latch 106 are connected to the bits 1 to 8 of the buffer 109. For this reason, the data stored in the respective buffers in the 2~ tristate buffer sroup are also shifted by 8 bits. For example, the same 8-bit buffer data as stored in the 10th tristate buffer is stored in the second tristate buffer upon this shift operation.
- 15 - ~2~8~Zs 1 The value written in the run length decode ROM 5 assigns the address line to the run length code and the data line to the run length data. Similarly, in the code length decode ROM 7, the address line is assigned to the run length code, and the data line is assigned to the code length data. Black/white signal inputs are supplied to A10 of the PALs, the zero bit discrimination signal is supplied to A8 and A9 thereof, and the MH code is supplied to AO to A7 thereof.
Table 2 shows an example of programs stored in the run length decode ROM 5 and the code length decode ROM 7.
Since the run length of the makeup code is an integer multiple of 64, values obtained by dividing the run length of the makeup code by 64 are written in the ROM 5 and are multiplied by 64 by a 6-bit shift circuit 115 to obtain the correct run length. In other words, the output from the ROM 5 is shifted to the upper bits by 6 bits, and "O" are set in the lower bits. In the case of a terminating code, the shift 2~ operation of the shift circuit 115 is not performed, and the input data is produced from the shift circuit 115 without any modification. An output 08 from the ROM 5 is provided as a makeup code/terminating code (run length of less than 63 bits) discrimination signal 2~ output M/T. when a makeup code is produced, the signal M/T is inverted by an inverter 116, and the inverted signal renders a gate 117 inoperative so that the - 16 - ~1.228~2~;
toggle flip-flop 13 is not inverted. The toggle flip-flop 13 is cleared by a signal 18 presenting the EOL code and resets its output to "white". With this configuration, the capacity of the run length decode 5 ROM 5 can be reduced to the minimum.
The code length produced from the code length decode ROM 7 is added to the offset value by an adder 118. The sum from the adder 118 is generally supplied to the offset register 9 through a data selector 119 10 whose side A is generally selected and an adder 120.
A data selector 121 generally selects "0" and selects "-8" when the cs)mparator 11 determines that the offset value is larger than 8. Then, the adder 120 subtracts the accumulated value by 8. At the same time, a gate 15 122 is opened, and the values of the latches 105, 106 and 107 are shifted by 8 bits, respectively.
When the ternary counter 101 is incremented by one and the ripple carry out is produced, the read address counter 2 is incremented by one. The Q output 2() from the ternary counter 101 is supplied to a decoder 130 which selects one of the tristate buffers 102 to 104 to load the new 8-bit data in the D latch 105.
PALs 124 to 127 of 14 PALs decode the EOL code.
The EOL can be decoded by programming the following 25 logic using "PAL16L6".
E = /A0*/Al*/A2*/A3*/...
...*/A10*/All*/A12 ~2289Z~
1 An encoder 128 discriminates which PAL has decoded the EOL code and produces a corresponding output.
When the EOL code is detected, the encoder 128 discriminates which PAL has decoded the EOL code, and causes an adder 131 to add "12" to the output from the encoder 128 so that the offset output jumps by the data length corresponding to the EOL code. The offset output is reset through the data selector 119 which is selecting the input B in response to the EOL signal 18.
us a countermeasure against a zero run length, a FI-FO buffer of about 2 words can be incorporated in the parallel to serial converter 3, or the operation clock of the decoder can be doubled.
According to the present invention, color image coded data of B (blue), G (green), and R (red) or Y (yellow), M (magenta) and C (cyan) from a memory or the like can also be decoded in accordance with the respective colors.
In the embodiment described above, tristate buffers of the tristate buffer group can be 13-bit tristate buffers, and the processing circuit for the MH codes exceeding 8 bits can be omitted. However, in this case, the number of address lines for the decode ROM is increased, and the capacity of the ROM is also increased.
The number of tristate buffers of the tristate buffer group and that of the PALs of the EOL decoder group are not limited to 14.
- 18 - ~28~
1 A single ROM can serve as the run length decode ROM and the code length decode ROM.
The apparatus of the present invention can be applied not only to d,ecoding of MH codes but also to S other types of compressed data.
When the recording operation of a printer or the like is horizontally synchronized in accordance with the EOL code detection, recording of each line can be assured.
As described above, in accordance with a decoder of ~5H codes of the embodiment of the present invention, a single MEI code can be decoded within a l system clock which is shorter than the ME code, so that high-speed MH code decoding can be realized.
This allows a combination of an image file in which pixels are stored as compressed and a high-speed printer.
Even if the code length of the MH code is longer than the run length such as the white run lengths l, 2 and 3 and the black run length l, since the MH code can be decoded within a period of a single system clock, the decoding does not require an,y waiting time. printer or the like which must be inter-mittently operated need not be used, and image 25 reproduction based on MH codes can be realized.
; In decodina MH codes, the MH code must be generally decoded referring to 13-bit signal line.
- 19 ~8925 1 However, in the embodiment described above, the code having consecutive zeros is divided and the divided fill bits are decoded separately, so that the main decoder need only look at the 8-bit signal line and that an inexpensive conversion ROM can be used.
In the embodiment described above, an EOL
detection circuit can be incorporated to perform processing including the EOL detection, so that an adverse effect of error data on the entire screen can be prevented.
Although the present invention has been described with reference to the particular embodiment thereof, the present invention is not limited thereto.
Various other changes and modifications may be made within the spirit and scope of the present invention as defined in the appended claims.
~L~%8~25 ~3 Jo o _ _ _ --to . _ _~ _ _ _ _ a'' _ ___ ___ _ I___ _ , _ _ 20 ~~
a _ _ en _ __ _ i _ _ _ _ a _ 0 s 0 8 l --2;> O D __ = _--~22~9~5 Tabl e 2 I nput Output A1 0 Ag A8 A7A6 A5 A4 A3 A2 A1 Ao Run M/T 1 ngth 0 0 1 0 1 1 0 1 0 1 _ 0 8 _ _ _ _ _ 0 1 1 1 1 _ _ 2 0 4 _ _ _ _ _ _ _ 0 0 0 1 00 1 __ 4 0 4 _ _ _ _ _ _ , _ . . _ , , , ., , , , , , , . _ _ ,, , . . ,, _ . .. ,, _. , _ , 100 1 1 1 1 00 _ 45 0 8 o 1 Lo 1 o1 _ _ 4 6 _ O 8 . r . , _ ,: , _ , , , , 1' _ _ l l l l l l l 0 l o 1 1 0 1 1 1 1 1 1 1 1 3 1 1 1 6 . I_ _ _ X 1 0 0 0 0_¦ 0 ¦ 0 ¦ 1 1 ¦ ¦ 1 ¦ 12 EOL
15 ,1 : _ --T, , , , r l 111 ; 40 1 1 1 12 I I T r T I I I T l l 1 1 1 1 0 1 1 1 1 1 0 1 l 1 1 1 1 1 0 1 0 1 10 l 0 1 0 1 1 2 1 0 1 2 1 ~0 l I j I 1 1 43 o l 23 l LIllol1111 1 1- 1 1 1 -I
$ *
I I I I I I I I I l 2;~
~228~5 1 updated offset value = original offset value + code length This updated offset value provides the start offset value of the MH code subsequent to the MH code currently decoded. When the selection of a tristate buffer in the tristate buffer group 4 is performed in accordance with this updated offset value, data starting immediately after the code length of the MH
code currently being coded can be instantaneously read out and this next MH code can be discriminated. In this manner, boundaries of continuously supplied MH
codes which have different code lengths can be easily discriminated and decoding of these MH codes can be performed easily.
Since the length of data which can be stored in the parallel to serial converter 3 is definite, supplementation must be performed. This means of supplementation will be described. When the offset value l5 exceeds 8, a comparator ll detects this and 2() shifts the parallel to serial converter 3 by 8-bits and sets new 8-bit data. Also, the comparator ll also supplies "-8" to an input E of the adder group 8.
Then, the updated offset value in this case is given by:
2~ updated offset value = original offset value + code length - 8 9 ~2Z~3~25 1 Then, data is shifted by 8 bits and the offset value is similarly shifted. For this reason, the relative positions of the data set in the parallel to serial converter 3 and the offset value in the offset register S 9 remain unchanged. The 8-bit shift is performed by the buffer, decoder and ternary counter as described above. Every time the count of the ternary counter reaches 2, 8-bit shift of the 24-bit data has been performed three times, and the next 24-bit data is read out from the image memory 1. In this manner, the serial data 14 as viewed from the offset register 9 appears as data of an indefinite length with no boundaries between the MH codes.
Upon completion of decoding of a given MH code, the next MH code can be loaded simultaneously or immediately thereafter. For this reason, continuous MH code decoding can be performed at high speed without waiting time. For this reason, a printer or the like which operates intermittently and synchro-2() nously with the decoding operation is not required.An EOL (End of Line) code (a sync signal representing an end of one line) which is a special type of data in the MH code is decoded by a separate special decoder.
This special decoder is an EOL decoder group 12 which receives the 24-bit data from the parallel to serial converter 3~parallel to the tristate buffer group 4.
The EOL decoder group 12 comprises fourteen 13-bit ,~
~228~
1 input PALs (Programable array Logics). The EOL decoder group 12 decodes the serial data which is shifted in units of bits. When one of the PALs detec'cs the EOL
code, a 13-input OR gate produces an EOL signal 18.
At the same time, an offset value 19 corresponding to the detected EOL code is produced. When one of the PAI,s of the EOL decoder group 12 decodes the EOL code, an EOL detection signal line 18 is set at level to reset the toggle flip-flop 13 and to produce a ~7hite video siynal for the next line input. At the same tire, the line 18 serves to cause the adder group 8 to disregard the inputs A, B and E and to add the inputs C and D. At this time, the input C of the adder group 8 receives "12" as the code length oE the EOL code, and the input D thereof receives the offset value 19 corresponding to the detected EOL code. As a result, the offset value 15 is updated as follows:
updated offset value = offset value of EOL
decoder group + 12 2n The EOL code is decoded by the special hardware for the following reason. If decoding generates an error due to a bit drop or the like, the resultant error, black and white inversion error or the like must be (confined within the current line; this error must be prevented from being extended to the entire screen.
The EOL code is decoded by the special hardware to correctly detect an end of each line to attain this.
L22~92S
1 If there is no error in the decoding operation, in the outputs to the adder group 8, during the EOL code detection the input B representing the code length is equal to the input C, and the input D representing the offset value is equal to the sum of the inputs A and E.
In this manner, since the offset register is reset, the extracting start position of the MH code of the next line is correctly given by the EOL code.
The EOL code can be given as a horizontal sync signal for the recording operation of the printer.
The configuration and mode of operation of the respective blocks of the apparatus shown in Fig. l will now be described in detail with reference to Fig. 2. Referring to Fig. 2, a signal line mark (~) represents that the corresponding signal line consists of a plurality of signal lines and the attached number shows the number of such signal lines. The same reference numerals as in Fig. l denote the same parts 2() in Fig. 2. A basic clock O is supplied to some clrcuit elements of the apparatus. Parallel output (l~word 24-bit data Do to D23) from the image memory (not shown) is latched in a D latch l00. The latching timing is when the ripple carry out of a ternary counter l0l is set at H level and the A > B output from the comparator ll is set at level. The latched data Do to D23 is divided into continuous bit data :..,~' - 12 - 12~8~2~
1 which are respectively wired-O~input to a D latch 105 through tristate buffers 102, 103 and 104. One of the tristate buffers 102 to 104 is selected by an output from a decoder 130, and the 8-bit data stored in the selected buffer is latched in the D latch 105. The 8-bit parallel data supplied to the D latches 105, 106 and 107 are parallel-to-serial converted in the form of t-hc 8-bit parallel, byte serial. The 24-bit data from the parallel to serial converter 3 is supplied to the tristate buffer group 4, and 8-bit data which are shifted in units of bits are stored in bits Do to D7, Dl to D8, D2 to Dg, and so on of tristate buffers 108, 109, 110, and so on. Of the outputs ~0 to D23, one stored in a selected one of the tristate buffers 15 108 to 111 of the tristate buffer group 4 is selected to allow selection of 8-bit data starting from a desired bit. When the tristate buffer 110, for example, is selected the outputs D2 to Dg are supplied to the run length decode ROM 5 and the code length ~() decode ROM 7. Since the maximum code length of the MH
codes is 13, theoretically a tristate buffer group consisting of 13-bit tristate buffers is required.
However, in the embodiment shown in Fig. 2, the initial signal, four or five fill bits "0"s of the MH
code are decoded by a separate circuit (this is based on the special characteristics of the MH codes).
This allows decoding of MH codes with data of less than 8 bits, thus sLmplifying the circuit.
- 13 - ~2~8~
1 A PAL 112 decodes the initial consecutive fill bits "0"s of the MH code. PAL is a tradename of U.S.A. Monolithic Memories Inc. and stands for programable array logic. Two devices "PAL18L4", for example, are combined to program with the logic as shown in Table 1 below. If there is no "0" from the start address indicated by the offset value from the offset register 9, a zero bit discrimination output "0" is produced. If there is at least one "0", a zero bit discrimination output "l" is produced. If there is four "0"s, a zero bit discrimination output "2" is produced. If there is five "0"s, a zero bit discrimination output "3" is produced. The zero bit discrimination output is supplied to a data selector 113 and is supplied as an address selection data to the two ROMs 5 and 7. Based on the input zero bit discrimination signal, the data selector 113 selects one of "0", "1", "4" and "5" (each representing a consecutive number of zeros) and produces a binary 2() number representing the selected number. The output from the data selector 113 is added to the offset value 15 by an adder 114, and the sum is supplied to an offset decoder 10. Accordingly, the buffer selected from those of the tristate buffer group 4 produces consecutive 8-bit data from a position shifted by the output from the data selector 113, that is, from the buffer one buffer to the right from the current buffer , - 14 - ~2289Z~
1 if there is one "0" in the My code. When the output from the data selector 113 is "0", the MH code consists of less than 8 bits. In this case, the addition by the adder 114 is not performed.
When the initial "0" or "0"s of the MH code are decoded by a separate circuit, the capacity of the tristate buffer group can be saved, and the number of address lines of the decode ROM can also be reduced.
When the accumulation result of the code length upon the shift operation of the tristate buffer group 4 exceeds 8, the output from the offset register 9 exceeds 8. Accordingly, the comparator 11 discrimi-nates this and renders the converter 3 operative.
; Then, the latches 105 to 107 are shifted by 8 bits.
That is, the data in the latch 105 is shifted to the latch 106, the data in the latch 106 is shifted to the latch 107. This means that the data to the tristate buffer group 4 is shifted by 8 bits. The respective buffers and latches are bit-connected such that the 2() bits 1 to 8 of the latch 107 are connected to the bits ; 1 to 8 of the buffer 108, and the bits 2 to 8 of the latch 107 and the bit 1 of the latch 106 are connected to the bits 1 to 8 of the buffer 109. For this reason, the data stored in the respective buffers in the 2~ tristate buffer sroup are also shifted by 8 bits. For example, the same 8-bit buffer data as stored in the 10th tristate buffer is stored in the second tristate buffer upon this shift operation.
- 15 - ~2~8~Zs 1 The value written in the run length decode ROM 5 assigns the address line to the run length code and the data line to the run length data. Similarly, in the code length decode ROM 7, the address line is assigned to the run length code, and the data line is assigned to the code length data. Black/white signal inputs are supplied to A10 of the PALs, the zero bit discrimination signal is supplied to A8 and A9 thereof, and the MH code is supplied to AO to A7 thereof.
Table 2 shows an example of programs stored in the run length decode ROM 5 and the code length decode ROM 7.
Since the run length of the makeup code is an integer multiple of 64, values obtained by dividing the run length of the makeup code by 64 are written in the ROM 5 and are multiplied by 64 by a 6-bit shift circuit 115 to obtain the correct run length. In other words, the output from the ROM 5 is shifted to the upper bits by 6 bits, and "O" are set in the lower bits. In the case of a terminating code, the shift 2~ operation of the shift circuit 115 is not performed, and the input data is produced from the shift circuit 115 without any modification. An output 08 from the ROM 5 is provided as a makeup code/terminating code (run length of less than 63 bits) discrimination signal 2~ output M/T. when a makeup code is produced, the signal M/T is inverted by an inverter 116, and the inverted signal renders a gate 117 inoperative so that the - 16 - ~1.228~2~;
toggle flip-flop 13 is not inverted. The toggle flip-flop 13 is cleared by a signal 18 presenting the EOL code and resets its output to "white". With this configuration, the capacity of the run length decode 5 ROM 5 can be reduced to the minimum.
The code length produced from the code length decode ROM 7 is added to the offset value by an adder 118. The sum from the adder 118 is generally supplied to the offset register 9 through a data selector 119 10 whose side A is generally selected and an adder 120.
A data selector 121 generally selects "0" and selects "-8" when the cs)mparator 11 determines that the offset value is larger than 8. Then, the adder 120 subtracts the accumulated value by 8. At the same time, a gate 15 122 is opened, and the values of the latches 105, 106 and 107 are shifted by 8 bits, respectively.
When the ternary counter 101 is incremented by one and the ripple carry out is produced, the read address counter 2 is incremented by one. The Q output 2() from the ternary counter 101 is supplied to a decoder 130 which selects one of the tristate buffers 102 to 104 to load the new 8-bit data in the D latch 105.
PALs 124 to 127 of 14 PALs decode the EOL code.
The EOL can be decoded by programming the following 25 logic using "PAL16L6".
E = /A0*/Al*/A2*/A3*/...
...*/A10*/All*/A12 ~2289Z~
1 An encoder 128 discriminates which PAL has decoded the EOL code and produces a corresponding output.
When the EOL code is detected, the encoder 128 discriminates which PAL has decoded the EOL code, and causes an adder 131 to add "12" to the output from the encoder 128 so that the offset output jumps by the data length corresponding to the EOL code. The offset output is reset through the data selector 119 which is selecting the input B in response to the EOL signal 18.
us a countermeasure against a zero run length, a FI-FO buffer of about 2 words can be incorporated in the parallel to serial converter 3, or the operation clock of the decoder can be doubled.
According to the present invention, color image coded data of B (blue), G (green), and R (red) or Y (yellow), M (magenta) and C (cyan) from a memory or the like can also be decoded in accordance with the respective colors.
In the embodiment described above, tristate buffers of the tristate buffer group can be 13-bit tristate buffers, and the processing circuit for the MH codes exceeding 8 bits can be omitted. However, in this case, the number of address lines for the decode ROM is increased, and the capacity of the ROM is also increased.
The number of tristate buffers of the tristate buffer group and that of the PALs of the EOL decoder group are not limited to 14.
- 18 - ~28~
1 A single ROM can serve as the run length decode ROM and the code length decode ROM.
The apparatus of the present invention can be applied not only to d,ecoding of MH codes but also to S other types of compressed data.
When the recording operation of a printer or the like is horizontally synchronized in accordance with the EOL code detection, recording of each line can be assured.
As described above, in accordance with a decoder of ~5H codes of the embodiment of the present invention, a single MEI code can be decoded within a l system clock which is shorter than the ME code, so that high-speed MH code decoding can be realized.
This allows a combination of an image file in which pixels are stored as compressed and a high-speed printer.
Even if the code length of the MH code is longer than the run length such as the white run lengths l, 2 and 3 and the black run length l, since the MH code can be decoded within a period of a single system clock, the decoding does not require an,y waiting time. printer or the like which must be inter-mittently operated need not be used, and image 25 reproduction based on MH codes can be realized.
; In decodina MH codes, the MH code must be generally decoded referring to 13-bit signal line.
- 19 ~8925 1 However, in the embodiment described above, the code having consecutive zeros is divided and the divided fill bits are decoded separately, so that the main decoder need only look at the 8-bit signal line and that an inexpensive conversion ROM can be used.
In the embodiment described above, an EOL
detection circuit can be incorporated to perform processing including the EOL detection, so that an adverse effect of error data on the entire screen can be prevented.
Although the present invention has been described with reference to the particular embodiment thereof, the present invention is not limited thereto.
Various other changes and modifications may be made within the spirit and scope of the present invention as defined in the appended claims.
~L~%8~25 ~3 Jo o _ _ _ --to . _ _~ _ _ _ _ a'' _ ___ ___ _ I___ _ , _ _ 20 ~~
a _ _ en _ __ _ i _ _ _ _ a _ 0 s 0 8 l --2;> O D __ = _--~22~9~5 Tabl e 2 I nput Output A1 0 Ag A8 A7A6 A5 A4 A3 A2 A1 Ao Run M/T 1 ngth 0 0 1 0 1 1 0 1 0 1 _ 0 8 _ _ _ _ _ 0 1 1 1 1 _ _ 2 0 4 _ _ _ _ _ _ _ 0 0 0 1 00 1 __ 4 0 4 _ _ _ _ _ _ , _ . . _ , , , ., , , , , , , . _ _ ,, , . . ,, _ . .. ,, _. , _ , 100 1 1 1 1 00 _ 45 0 8 o 1 Lo 1 o1 _ _ 4 6 _ O 8 . r . , _ ,: , _ , , , , 1' _ _ l l l l l l l 0 l o 1 1 0 1 1 1 1 1 1 1 1 3 1 1 1 6 . I_ _ _ X 1 0 0 0 0_¦ 0 ¦ 0 ¦ 1 1 ¦ ¦ 1 ¦ 12 EOL
15 ,1 : _ --T, , , , r l 111 ; 40 1 1 1 12 I I T r T I I I T l l 1 1 1 1 0 1 1 1 1 1 0 1 l 1 1 1 1 1 0 1 0 1 10 l 0 1 0 1 1 2 1 0 1 2 1 ~0 l I j I 1 1 43 o l 23 l LIllol1111 1 1- 1 1 1 -I
$ *
I I I I I I I I I l 2;~
Claims (40)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A data decoding apparatus for decoding codes obtained by compression, comprising:
memory means for storing a plurality of codes which are to be decoded and which are of variable length;
read means for reading out a predetermined amount of data from said memory means on a parallel basis, said predetermined amount of data being less than the amount of data stored in said memory means;
decoding means for decoding a code contained in data read out in parallel from said memory means; and control means for controlling operation of said read means, said control means identifying code stored in said memory means and causing said read means to read out in parallel data containing the identified code from said memory means.
memory means for storing a plurality of codes which are to be decoded and which are of variable length;
read means for reading out a predetermined amount of data from said memory means on a parallel basis, said predetermined amount of data being less than the amount of data stored in said memory means;
decoding means for decoding a code contained in data read out in parallel from said memory means; and control means for controlling operation of said read means, said control means identifying code stored in said memory means and causing said read means to read out in parallel data containing the identified code from said memory means.
2. An apparatus according to Claim 1, wherein said read means reads out the predetermined amount of data from said memory means.
3. An apparatus according to Claim 1, wherein said decoding means comprises storage means for storing decoded data, said storage means being addressed by the data read out from said memory means to output decoded data.
4. An apparatus according to Claim 1, wherein said control means controls operation of said read means in accordance with length of a code decoded by said decod-ing means.
5. An apparatus according to Claim 1, wherein said memory means continuously stores the variable length codes without any boundary therebetween.
6. An apparatus according to Claim 1, wherein the codes are obtained by compression of image data according to a modified Huffman encoding method.
7. An apparatus according to Claim 1, further comprising detection means, separate from said decoding means, for detecting a sync code contained in data read out from said memory means.
8. A data decoding apparatus for decoding codes obtained by compression, comprising:
memory means for continuously storing a plural-ity of codes which are to be decoded and which are of variable length;
read means for reading out a predetermined amount of data from said memory means;
decoding means for decoding a code contained in the predetermined amount of data read out from said memory means;
detecting means for detecting a length of the code decoded by said decoding means; and control means for controlling operation of said read means so as to read out from said memory means the predetermined amount of data containing code subsequent to the code decoded by said decoding means, in accordance with the length of the code detected by said detecting means.
memory means for continuously storing a plural-ity of codes which are to be decoded and which are of variable length;
read means for reading out a predetermined amount of data from said memory means;
decoding means for decoding a code contained in the predetermined amount of data read out from said memory means;
detecting means for detecting a length of the code decoded by said decoding means; and control means for controlling operation of said read means so as to read out from said memory means the predetermined amount of data containing code subsequent to the code decoded by said decoding means, in accordance with the length of the code detected by said detecting means.
9. An apparatus according to Claim 8, wherein said control means controls a read location of the pre-determined amount of data from said memory means by said read means
10. An apparatus according to Claim 8, wherein said read means is adapted to read out in parallel the pre-determined amount of data from said memory means.
11. An apparatus according to Claim 8, wherein said memory means comprises a plurality of storage sections each capable of storing a predetermined amount of data, and said control means selects one of said plurality of storage sections.
12. An apparatus according to Claim 11, wherein said plurality of storage sections respectively store con-tinuous data which are shifted in units of the predeter-mined amount.
13. An apparatus according to Claim 8, wherein the codes are obtained by compression in accordance with a modified Huffman encoding method.
14. An apparatus according to Claim 8, wherein said memory means continuously stores the variable length codes without any boundary therebetween.
15. A data decoding apparatus for decoding codes obtained by compression, comprising:
memory means for continuously storing a plurality of codes to be decoded;
decoding means for decoding the codes stored in said memory means;
a plurality of discriminating means for discrimi-nating as to whether or not a specific data is stored in any one of memory locations of said memory means; and control means for controlling the decoding opera-tion of said decoding means in accordance with the discri-minating result by said plurality of discriminating means.
memory means for continuously storing a plurality of codes to be decoded;
decoding means for decoding the codes stored in said memory means;
a plurality of discriminating means for discrimi-nating as to whether or not a specific data is stored in any one of memory locations of said memory means; and control means for controlling the decoding opera-tion of said decoding means in accordance with the discri-minating result by said plurality of discriminating means.
16. An apparatus according to Claim 15, wherein the specific code discriminated by said discriminating means is a sync signal of each line.
17. An apparatus according to Claim 15, wherein said decoding means comprises storage means for storing decode data, said storage means being addressed by the code read out from said storage means to output decoded data.
18. An apparatus according to Claim 15, wherein said control means controls read out of code from said memory means in accordance with the discrimination result by said discriminating means.
19. An apparatus according to Claim 15, wherein the codes are obtained by compression in accordance with a modified Huffman encoding method.
20. An apparatus according to Claim 15, wherein said control means is adapted to perform such a control that a predetermined amount of data containing the codes to be decoded are read out in parallel from said memory means.
21. A data decoding apparatus for decoding codes obtained by compression, comprising:
input means for inputting the code which is to be decoded and which comprises plural binary signals;
detecting means for detecting the number of consecutive specific signals of the code input by said in-putting means; and decoding means for decoding the code input by said inputting means in accordance with the number of consecutive specific signals detected by said detecting means and signals other than the consecutive specific signals of the code.
input means for inputting the code which is to be decoded and which comprises plural binary signals;
detecting means for detecting the number of consecutive specific signals of the code input by said in-putting means; and decoding means for decoding the code input by said inputting means in accordance with the number of consecutive specific signals detected by said detecting means and signals other than the consecutive specific signals of the code.
22. An apparatus according to Claim 21, wherein said detecting means detects the number of specific signals at the beginning of the code.
23. An apparatus according to Claim 21, wherein said decoding means comprises storage means for storing decode data, said storage means being addressed by data representing the number of consecutive specific signals and the signals following the consecutive signals to out-put decoded data.
24. An apparatus according to Claim 21, wherein the code to be decoded is obtained by compression in accordance with a modified Huffman encoding method, and the specific signals are "O" signals.
25. An apparatus according to Claim 21, further comprising memory means for storing the code input from said input means, signals other than the consecutive speci-fic signals of the code are read out from said memory means in accordance with the number of consecutive specific signals which are detected by said detecting means.
26. A data decoding apparatus for decoding codes obtained by compression, comprising:
memory means for continuously storing the codes to be decoded, said codes each comprising plural binary signals;
read means for reading out data stored in said memory means;
decoding means for decoding the codes in accor-dance with the data read out from said memory means; and read control means for detecting the number of consecutive specific signals of the code, and for control-ling a read out operation of said read means in accordance with a detected number of the consecutive specific signals so as to supply signals other than the consecutive speci-fic signals of the code to said decoding means.
memory means for continuously storing the codes to be decoded, said codes each comprising plural binary signals;
read means for reading out data stored in said memory means;
decoding means for decoding the codes in accor-dance with the data read out from said memory means; and read control means for detecting the number of consecutive specific signals of the code, and for control-ling a read out operation of said read means in accordance with a detected number of the consecutive specific signals so as to supply signals other than the consecutive speci-fic signals of the code to said decoding means.
27. An apparatus according to Claim 26, wherein said read means reads out a predetermined amount of continuous data from said memory means.
28. An apparatus according to Claim 26, wherein said memory means has a plurality of storage sections each capable of storing the predetermined amount of data, and said control means selects one of said plurality of stor-age sections.
29. A data decoding apparatus for decoding codes obtained by compression, comprising:
storage means for storing the codes which are to be decoded and which are of variable length;
memory means for storing a predetermined amount of data read out from said storage means;
decoding means for decoding the code contained in the data stored in said memory means; and control means for controlling a read out opera-tion of the data from said storage means into said memory means, in accordance with a length of the code decoded by said decoding means.
storage means for storing the codes which are to be decoded and which are of variable length;
memory means for storing a predetermined amount of data read out from said storage means;
decoding means for decoding the code contained in the data stored in said memory means; and control means for controlling a read out opera-tion of the data from said storage means into said memory means, in accordance with a length of the code decoded by said decoding means.
30. An apparatus according to Claim 29, wherein said control means is adapted to perform such a control that the predetermined amount of data is read out in paral-lel from said storage means.
31. An apparatus according to Claim 29, wherein said control means counts a length of the code decoded by said decoding means and causes the read out operation of the data to be performed when the counted length of the code becomes a predetermined value.
32. An apparatus according to Claim 29, wherein said memory means performs a shift operation upon every decoding operation of said decoding means.
33. A data decoding apparatus for decoding codes obtained by compression, comprising:
inputting means for inputting data containing the codes to be decoded;
memory means for storing the data input from said input means, and for outputting the data in parallel;
decoding means for decoding the code contained in the data code output in parallel from said memory means;
and control means for performing such a control that the data containing code to be subsequently decoded is outputted from an arbitrary location of said memory means without a waiting time after completion of the decoding operation of said decoding means.
inputting means for inputting data containing the codes to be decoded;
memory means for storing the data input from said input means, and for outputting the data in parallel;
decoding means for decoding the code contained in the data code output in parallel from said memory means;
and control means for performing such a control that the data containing code to be subsequently decoded is outputted from an arbitrary location of said memory means without a waiting time after completion of the decoding operation of said decoding means.
34. An apparatus according to Claim 33, wherein said memory means continuously stores the codes to be de-coded, and said memory means performs at a time a data shift by a code length of the code decoded after the de-coding operation of said decoding means.
35. An apparatus according to Claim 33, wherein said control means is operable to read out the code stored in any arbitrary location of said memory means in accor-dance with the length of the code decoded by said decoding means.
36. An apparatus according to Claim 33, wherein the codes are obtained by compression in accordance with a modified Huffman encoding method.
37. An apparatus according to Claim 33, wherein said decoding means storage means in which the decoded data are stored, said storage means being addressed by data outputted in parallel from said memory means to output the decoded data.
38. An apparatus according to Claim 26, wherein said decoding means is operable to decode the code in accordance with the number of the consecutive specific signals of the code and signals other than the consecutive specific signals of the code.
39. An apparatus according to Claim 26, wherein the codes are obtained by compression in accordance with a modified Huffman encoding method, and the specific signal is "O" signal.
40. An apparatus according to Claim 29, wherein said decoding means includes means for storing the decoded data therein, said storing means is addressed by the code to produce the decoded data.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31174/1983 | 1983-02-25 | ||
| JP3117283A JPS59156073A (en) | 1983-02-25 | 1983-02-25 | Data decoding device |
| JP31172/1983 | 1983-02-25 | ||
| JP3117383A JPS59156074A (en) | 1983-02-25 | 1983-02-25 | Data decoding device |
| JP3117483A JPS59156075A (en) | 1983-02-25 | 1983-02-25 | Data decoding device |
| JP31173/1983 | 1983-02-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1228925A true CA1228925A (en) | 1987-11-03 |
Family
ID=27287230
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000447989A Expired CA1228925A (en) | 1983-02-25 | 1984-02-22 | Data decoding apparatus |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4716471A (en) |
| CA (1) | CA1228925A (en) |
| DE (1) | DE3406624A1 (en) |
| FR (1) | FR2541836B1 (en) |
| GB (1) | GB2138604B (en) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4864414A (en) * | 1985-07-03 | 1989-09-05 | Minolta Camera Kabushiki Kaishi | Image signal processing device |
| DE3632682A1 (en) * | 1986-09-26 | 1988-03-31 | Philips Patentverwaltung | CIRCUIT ARRANGEMENT FOR RECODING A DATA SIGNAL |
| US4839738A (en) * | 1987-04-22 | 1989-06-13 | Advanced Micro Devices, Inc. | Apparatus for decoding facsimile coded data to image data with coding and reference line windowing and color change detection |
| US4968135A (en) * | 1987-08-17 | 1990-11-06 | Digital Equipment Corporation | System for producing pixel image data from CCITT encoded pixel data |
| US4903269A (en) * | 1988-05-16 | 1990-02-20 | General Electric Company | Error detector for encoded digital signals |
| JP3013381B2 (en) * | 1990-03-28 | 2000-02-28 | ソニー株式会社 | Variable length data decoding device |
| JPH04373248A (en) * | 1991-06-22 | 1992-12-25 | Fuji Xerox Co Ltd | Facsimile management report output method |
| CA2063495C (en) | 1991-10-03 | 1999-03-30 | John O. G. Vieth | Method and system for compressing data in a multi-channel image processing system |
| CA2063621C (en) | 1991-10-03 | 1999-03-16 | Wayne M. Doran | Method and modular system for high speed processing of item images |
| US5390262A (en) * | 1991-10-03 | 1995-02-14 | Ncr Corporation | Method for splitting and configuring a multi-channel image processing system |
| US5245441A (en) * | 1991-12-12 | 1993-09-14 | Ruben Murray A | Document imaging processing method and apparatus |
| JP2687926B2 (en) * | 1995-05-24 | 1997-12-08 | 日本電気株式会社 | Code decoder |
| US5686915A (en) * | 1995-12-27 | 1997-11-11 | Xerox Corporation | Interleaved Huffman encoding and decoding method |
| US6133754A (en) * | 1998-05-29 | 2000-10-17 | Edo, Llc | Multiple-valued logic circuit architecture; supplementary symmetrical logic circuit structure (SUS-LOC) |
| DE69941023D1 (en) * | 1998-09-21 | 2009-08-06 | Sony Corp | CODING AND DECODING METHOD AND DEVICE |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1336317A (en) * | 1969-11-25 | 1973-11-07 | Licentia Gmbh | Communication transmission system |
| US3675212A (en) * | 1970-08-10 | 1972-07-04 | Ibm | Data compaction using variable-length coding |
| US3701111A (en) * | 1971-02-08 | 1972-10-24 | Ibm | Method of and apparatus for decoding variable-length codes having length-indicating prefixes |
| GB1332631A (en) * | 1971-02-26 | 1973-10-03 | Ibm | Data processing system |
| US3717851A (en) * | 1971-03-03 | 1973-02-20 | Ibm | Processing of compacted data |
| US3883847A (en) * | 1974-03-28 | 1975-05-13 | Bell Telephone Labor Inc | Uniform decoding of minimum-redundancy codes |
| DE2458119C3 (en) * | 1974-12-09 | 1980-08-14 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Method and arrangement for facsimile coding |
| US4099257A (en) * | 1976-09-02 | 1978-07-04 | International Business Machines Corporation | Markov processor for context encoding from given characters and for character decoding from given contexts |
| US4146909A (en) * | 1977-11-21 | 1979-03-27 | International Business Machines Corporation | Sync pattern encoding system for run-length limited codes |
| US4376933A (en) * | 1979-02-22 | 1983-03-15 | Xerox Corporation | Circuit for compacting data |
| US4494151A (en) * | 1979-07-02 | 1985-01-15 | Xerox Corporation | 4-Pixel run-length code for data compression |
| JPS5610774A (en) * | 1979-07-09 | 1981-02-03 | Ricoh Co Ltd | Facsimile device |
| JPS5771063A (en) * | 1980-10-22 | 1982-05-01 | Toshiba Corp | Conversion and storage system for picture information |
| US4399467A (en) * | 1981-10-13 | 1983-08-16 | Ncr Canada Ltd. | Method and apparatus for image data compression and decompression |
| CA1211219A (en) * | 1982-06-30 | 1986-09-09 | Hideo Kuroda | Digital data code conversion circuit for variable- word-length data code |
| JPS5937773A (en) * | 1982-08-26 | 1984-03-01 | Canon Inc | Run-length coding and decoding device |
-
1984
- 1984-02-22 CA CA000447989A patent/CA1228925A/en not_active Expired
- 1984-02-23 DE DE19843406624 patent/DE3406624A1/en active Granted
- 1984-02-24 GB GB08404879A patent/GB2138604B/en not_active Expired
- 1984-02-27 FR FR8402961A patent/FR2541836B1/en not_active Expired
-
1987
- 1987-02-25 US US07/018,868 patent/US4716471A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| GB8404879D0 (en) | 1984-03-28 |
| GB2138604B (en) | 1987-09-23 |
| DE3406624A1 (en) | 1984-09-27 |
| GB2138604A (en) | 1984-10-24 |
| FR2541836B1 (en) | 1988-08-26 |
| US4716471A (en) | 1987-12-29 |
| FR2541836A1 (en) | 1984-08-31 |
| DE3406624C2 (en) | 1989-05-11 |
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