CA1226636A

CA1226636A - Circuit arrangement for frame and phase synchronization of a local sampling clock

Info

Publication number: CA1226636A
Application number: CA000462742A
Authority: CA
Inventors: Kalman Szechenyi
Original assignee: International Standard Electric Corp
Current assignee: International Standard Electric Corp
Priority date: 1983-09-17
Filing date: 1984-09-10
Publication date: 1987-09-08
Also published as: EP0141194A3; DE3482742D1; CH665925A5; ATE54785T1; US4598413A; EP0141194B1; EP0141194A2; ES8606757A1; JPS6094552A; JPH0317424B2; DE3333714A1; ES535993A0

Abstract

Abstract of the Disclosure Circuit Arrangement for Frame and Phase Synchronization of a Local Sampling Clock With such a circuit arrangement, the sampling clock is synchronized to the frame position and the phase of the characters of a received character stream containing a "unique word"
at regular intervals. In a digital correlator (1), a cross-correlation function is generated from a unique word stored therein and from the received, sampled character stream, and a frame detection circuit (2) derives a frame clock (RT1) from those maxima of the crosscorrelation function recurring at intervals of one frame period.

To achieve synchronization at any polarity of the received character stream (i.e., even if the tip and ring wires of the subscriber line are interchanged), a second frame detection circuit (3) derives a second frame clock (RT2) from those minima of the crosscorrelation function recurring at intervals of one frame period. A clock selection circuit (8) determines which of the two frame clocks is received within a limited time interval. From this frame clock, control information for representing the phase of the sampling clock (AT) is derived in a phase synchronization circuit (10).

(Fig.2)

Description

foe K.Szechenyi 25 ircuit Arrangement for Frame and Phase Synchronization of a Local Sampling Clock The present invention relates to a circuit arrangement for synchronizing a local sampling clock to the frame position and the phase of the characters of a received character stream containing a unique word at regular time intervals, where-in a digital correlator generates a cross correlation function from the received character stream, sampled at the sampling clock rfeate, and a unique word stored at the receiving end, and wherein a frame detection circuit derives a first frame clock from those maxima of the crqsscorrelation function recurring at intervals of one frame period.

In such a circuit arrangement, the frame clock is recovered from a "unique word" by using digital correlation techniques, whereas the bit clock is recovered, in a manner not described, -from an additional bit pattern preceding the unique word (IEEE Transactions on Communication Technology, Vol. COMMA, Noah, August 1968, pp. 597 to 605). This air-cult arrangement is intended for time-division multiple-access satellite communication systems, but the problem that the frame clock and the phase of the sampling clock must be synchronized to the received digital characters also arises in TAM wire communication systems for e.g., two-wire full-duplex transmission over telephone subscriber lines. This is particularly difficult if the received dip vital characters are heavily distorted and cannot be foe K.Szechenyi 25 equalized until after determination of the appropriate phase of the sampling clock.

A prior patent application (P 32 27 151.4) has for its object to provide a circuit arrangement of the above kind which is also suitable for a heavily distorted received character stream. This object is attained by provide in a phase synchronization circuit which derives control information for adjusting the phase of the sampling clock from values of the cross correlation function in the vicinity of each detected recurrent maximum, and adjusts the phase of the sampling clock with this control information. Further-more, a clock-signal-synchronizing circuit has been pro-voided in which the deviation of a characteristic, periodical-lye recurring parameter of the received signal is measured at two different instants, and from the two measured values, the respective average of an error signal is determined.
With this error signal, the clock phase is adjusted until the error signal disappears. As the characteristic pane-meter, the envelope of the received signal is used, for example (DEMOS 27 29 312). This clock synchronization, however, is designed specifically for data communication systems using phase-shift keying and requires quite a large amount of circuitry.

The clock recovery described in the prior application no-quirks that the polarity of the received signal be known.
However, this is not always insured because it is possible, for example, that the tip wire and the ring wire of the sub-scriber line are interchanged.

The object of the invention is to derive the bit and frame clocks from a received character stream of arbitrary polarity.

I it K.Szechenyi 25 The invention is characterized in that a second frame de-section circuit derives a second frame clock from those minima of the crosscorreLation function recurring at inter-vets of one frame period, that a clock selection circuit determines which of the two frame clocks is being received within a limited time interval, and that from this frame clock, control information for representing the phase of the sampling clock is derived in a phase synchronization circuit.

Developments of the invention are characterized in the sub claims.

A principal advantage of the invention is that it improves the phase adjustment criterion.

An embodiment of the invention willow by explained with reference to the accompanying drawings, in which:
Fugue illustrates the fundamental principle of the invention with the aid of a simplified sequence of values of the cross correlation function pa: when the sampling clock is out of phase with the received character stream, and 1b: when the sampling clock is in phase with the received character stream;
Fugue is a block diagram of the circuit arrangement in accordance with the invention;
Fugue shows a phase synchronization circuit as used in the circuit arrangement of Fugue;
Fugue shows a smoothing accumulator as used in the circuit arrangement of Fugue;

I it K.Szechenyi 25 Fugue shows a clock-selection and polarity-control circuit as used in the circuit arrangement of Fugue, and Fugue shows the waveforms of the various clock signals in the circuit arrangement in accordance with the invention.

The input of the circuit arrangement in accordance with the invention is presented with the sample values of the no-ceiled character stream, consisting of ternary characters, for example, each of which is sampled once. The sample values K, following each other at the repetition rate of the sampling clock, are correlated in a digital correlator with a unique word stored at the receiving end and consist-in of, e.g., 12 binary characters to obtain values X of the cross correlation function which follow each other at the sampling rate. Mathematically, these"valu~'s can be expressed as K (j) = I Zoo- v) WOVE ), (1) v= O
where Wove ) signifies a bit of the 12-bit unique word.
Except in case of distortions, the cross correlation function X would have to assume a maximum value whenever the sample values X(i-v), to be synchronized with the unique word, are the sample values of the unique word contained in the character stream at intervals of one frame period.
A frame detection circuit then locates those relative maxima in the entire sequence X of the values of the cross-correlation function which recur at intervals of one frame period. In the example of Fugue, these are the values with the indices it and (io~108). These indices differ by 108 periods of the sampling clock because, in the example i36 K.Szechenyi 25 just described, a frame consists of 108 characters.
However, a frame may also consist of 120 characters for example. If the polarity of the received signal is known, the recurrent relative maxima thus inform the receiver of the frame clock of the received time-division-multi-pled signal. If, during the sampling process, the sampling period were made to approach zero, the simplified shape of the correlation function drawn as a solid line in Fugue would be obtained, which shows that the values X obtained by sampling at intervals of one sampling period T depend on the phase of the sampling clock. In the case of the sampling clock phase shown in Fugue, the maximum possible values of the cross correlation function cannot be determined in this manner. If, however, the phase of the local sampling clock is shifted to the position shown in Fig.1b, the detected recurrent relative maxima Kiwi) are actually the real maxima of the cross correlation function If the unique word is suitably chosen, the cross correlation function has the property of approximatively reproducing the impulse response of the transmission path, with the extreme of the cross correlation function coinciding with the extreme of the impulse response. The clock phase, giving the extreme values of the cross correlation function, also gives the extreme values of the impulse response and, thus, represents the desired clock phase for sampling the received characters.

To adjust the phase of the sampling clock, the invention uses values of the correlation function which lie in the vicinity of the recurrent maximum Kiwi). For example, use can be made of the value preceding the recurrent maximum value, i.e., the value Kiwi), and the value following 'photo K.Szechenyi 25 the recurrent maximum value, i.e., Cole). As shown in Fugue, the difference between these values, Kilo is different from zero if the value Kiwi) is not the actual maximum value. Therefore, this difference can be used as a controlled variable for adjusting the clock phase. As shown in Fig.1b, the difference kiwi) disappears if Kiwi) is the maximum possible value of the correlation function at the instantaneous sample value Zoo). Fi~q.1b thus gives the phase of the sampling clock in the phase-locked condition.

To be able to achieve frame and phase synchronization at any polarity of the received character stream, both the maxima and the minima of the cross correlation function are evaluated in accordance with the invention, as mentioned above. This will be discussed later.
t The shape of the correlation function shown in Fugue has been greatly simplified in comparison with the actual shape-In reality, the recurrent relative extreme are much more difficult to detect because of the heavy distortions of the received character stream, and a random sequence is super-imposed on the successively determined difference values K, so that the differences can be used as reliable con -trolled variables only after a smoothing process.

The circuit arrangement according to the invention contains a digital correlator 1 (Fugue) to whose input the sample values K of the received characters are applied as 8-bit words, which are continuously correlated at the character sampling rate AT with the unique word stored in the correlator to form the values X of the crosscor-relation function. These values X, which are 8-bit words Skye;

K~Szechenyi 25 like the input words, are fed to a first frame detection circuit 2 and a second frame detection circuit 3 which determine, by means of simple Logic gates, the locations of the recurrent relative maxima and minima, respectively, of the cross correlation function and, thus, a first frame clock RT1 and a second frame clock RITZ, respectively, for the received TAM signal. Each of the frame detection air-Curtis 2, 3 is connected to a mgdulo-108 counter 4, 5, whose count input is presented with the sampling clock AT
and whose count i serves to determine the frame clock. The index i is counted mud 108 because, in the embodiment being described, the unique word recurs after every 108 characters. Each output pulse of the frame detection air-cult 2, signifying a detected recurrent maximum of the cross correlation function, and each output pulse of the frame detection circuit 3, signifying a detected recurrent minimum of this function, reset the counters 4 and 5, respectively, to a predetermined count ion e.g., zero, via reset inputs R.

The output signals of the first frame detection circuit 2 and the second frame detection circuit 3 represent a first frame clock RT1 and a second frame clock RT2, respectively, which are applied to a clock selection circuit 8.

When the first frame detection circuit 2 detects a periodical-lye recurring maximum of the cross correlation function, it indicates this to the clock selection circuit 8 by a signal F1 = 1. In the absence of a periodically recurring maximum, F1 = 0. Analogously, the second frame detection circuit 3 provides a signal F2 = 1 when it detects a periodically recurring minimum of the cross correlation function.

it K.Szechenyi 25 If two frame clocks RT1 and RT2 are venerated in this manner, because the cross correlation function has both periodically recurring maxima and periodically recurring minima, only one of them can be the correct frame clock.
The latter is determined by the relationship between the waveforms of the two clocks. The clocks can be shifted with respect to each other by a limited time interval in act cordons with the actual impulse response of the transmission path, this interval having to be shorter than half a frame period. In the case of a frame consisting of 108 digital characters, the limited time interval thus can theoretically comprise a maximum of about 50 character clock periods. In practice - and also in the present embodiment -it turned out, however, that the limited time interval equals 8 clock periods at the most. The clocks can be shifted in time with respect to each other by 2 to 8 periods.
The first clock that occurs within Rosetta to eight periods is the correct frame clock. The phase relationships are apparent from Fugue, which will be explained later. Details of the clock selection circuit 8 will be explained with the aid of Fox, Andy 6.
. . .
According to the selection made, the correct frame clock RUT is transferred to one output of the clock selection circuit 8.
A second output of the clock selection circuit 8 provides a polarity signal P which can assume the value +1 or -1, assigned to it depending on the clock selection In a multiplier 9, the polarity signal P is combined with the values X of the cross correlation function, so that the correct polarity of the difference OK is ensured.

The frame clock RUT now determines which values of the cross correlation -function are selected from the set of ;Çi3~

g K~Szechenyi 25 of values X and used to form the controlled variable.
As explained with the aid of Fugue, these are the values Kiwi) and Kiwi), which lie in the vicinity of the value Kiwi) found to be the recurrent maximum. Since the counters 4, 5 are reset to zero at the instant ion the value Coffey is available when the counters 4, 5 have the count 1. All values X are applied successively from the output of the digital correlator via the multiplier 9 to a phase swanker-nauseation circuit 10 containing a subtracter 11 at its input end. This subtracter 11 is started by applying a control signal S to its control input only when either the counter 4 or the counter 5 reaches the count 1. This count is in-dilated in the clock selection circuit by a signal So or So, respectively, and converted -there into the control signal S after suitable selection At the second signal input of the subtracter 11, output values X from the digital correlator appear with a delay of two sampling periods T which is generated in a delay eye-mint 12. The functions of two multipliers 13 and 14 ahead of the two signal inputs of the subtracter 11 will be explained later.

While the positive control signal S is applied to its control input, the subtracter 11 forms the difference kiwi) between the values Kiwi) and Kiwi) of the cross correlation function. The other parts of the phase synchronization air-cult 10 and the further processing of the difference values will be explained with the aid of Fugue. It should be noted at this point, however, that the phase synchronization air-cult 10 delivers a character sampling clock AT which is phase-locked to the received character stream and is applied to the digital correlator 1 and the counters 4 and 5.

I

MU -K.Szechenyi 25 Investigations have shown that, if the signals transmitted over subscriber lines are heavily distorted, e.g., in the case of long subscriber lionizer in the presence of "bridged taps", the function used to set the sampling instant, a = Kiwi Kiwi + 1 ), can still he optimized, for the signals are sampled after the correlation maximum and, hence, after the maximum of the impulse response. This gives relatively large pro-shoots which are difficult to equalize. The equalizer co-efficient become greater than 1, so that stability problems are created. In addition, the noise amplification of the necessary preequalizer may become unacceptable. These dip-faculties can be avoided in a very advantageous manner if the phase is adjusted in accordance with the following criterion. An times greater weight is assigned to the value Kiwi 1). This gives the following compensation function:
a' = Kiwi 1) - Kiwi + 1).
The factor preferably has the value 2, 4 or 8. In the case of subscriber lines, = 4 proved very advantageous.

The values Kiwi -1) of the cross correlation function are multiplied by the factor a in a multiplier 13.

There are cases where it is more favorable to transform the foregoing function by dividing it by :
awoke Kiwi I - kiwi + 1) where = I. The values Kiwi + 1) are multiplied by the value in a multiplier 14.

In both cases, the changed weight of the values of the K.Szechenyi 25 correlation function results in the signals being sampled before the correlation maximum. As a result, the pro-shoots decrease. A slight loss in the sampled intensity of the signal maximum is more than offset by a signal-to-noise improvement.

Of the two multipliers 13 and 14, only one is present;
it is subjected to a factor different from 1.

As mentioned, the difference values kiwi), formed successively in the subtracter 11, need to be smoothed, which is done in a smoothing accumulator 16 (Fugue) lot-lowing the subtracter.

This smoothing accumulator 16, which will be explained below with the aid of Fugue, thus receives one input value Awoke) per frame period and provides at its output, at intervals equal to one frame period, control inform lotion UP which can be used directly to adjust the phase of the character sampling clock by a corresponding number of increments. The control information UP is preferably an integer, which may also be zero. For this control information UP, including its sign 5 bits are sufficient, and it is capable of con-trolling a gate circuit 17 to select the appropriate clock phase (Fugue).

At a number of parallel inputs, the gate circuit 17 receives the clock from a reference-frequency oscillator 18 with the clock period T and different clock phases. The clock phases at the individual inputs of the gate circuit differ from each other by the same increment. If, for example, the phase of the sampling clock is to be made adjustable in 128 in-cements, the reference clock from the output of the no-ference-frequency oscillator 18 will be applied to a chain ~1~2~ I

K.Szechenyi 25 of 128 delay elements eschew of which delays the phase of the clock by 128 with respect to the clock phase pro-voided by the preceding delay element in the chain. The clocks available in front of and behind the delay eye-mints 19 now form the parallel input clocks for the gate circuit 17, from which only one is selected as the phase-adjusted character sampling clock AT under control of the control information UP.

The phase adjustment in the gate circuit 17 is performed by advancing or delaying the phase by as many increments as is specified by the control information UP, including its sign. If UP is equal to I for example, the clock passing through the gate circuit 17 will be blocked, and instead, the clock delayed by three phase increments more will be allowed to pass through. If, on the other hand, the control information A =-2, changeover will be effected in the gate circuit 17 such that the latter passes the clock delayed by two phase increments less, which is then used as the adjusted character sampling clock AT in the entire circuit arrangement. This character sampling clock is applied from the gate circuit 17 to the digital correlator 1, the counters 4, 5 and to other receiving devices to be operated at the repetition rate of the received characters, e.g., the sample-and-hold circuit (not shown). The circuit arrangement in accordance with the invention thus represents a digital phase-locked loop which differs from all con-ventional digital phase-locked loops in that it establishes both frame and character synchronization.

The difference values appearing at the input of the smooth-in accumulator 16 (see Fugue, kiwi), are multiplied in a multiplier 21 by a factor a which is smaller than 1. The I

K.Szechenyi 25 multiplied values, a kiwi), are fed to an adder 1Z
whose output values Foe) are delayed in a delay element 23 by 108 periods T of the sampling clock, i.e., by one frame period. From the output of the delay element 23, the function values F are fed back to another input of the adder 22, where they are added, like in a normal accumulator, to the input values a kiwi) to obtain the new value F. The act cumulator slightly doffers from a conventional accumulator in that the values fed back, F, are multiplied by a factor of 1-2 integer in a multiplier 24, the value n being chosen so that this factor is close to 1. The values F are applied at intervals of one frame period from the output of the delay element 23 to a quantize 25, which converts them into integers Fq by rounding them off. (Input values F small for than 1 are rounded off to zero).

The output of the quantize 25 thus provides, at intervals of one frame period, integers Fq which may be positive, negative, and zero. These output values Fq are finally used as the above-explained control information UP. In addition, they are fed back to a further input of the adder 22 via a multiplier 26 in which they are multiplied by a factor b smaller than 1. The adder input is an inverting input, so that the value fed back, b UP, will be subtracted from the input value a kiwi) after each phase adjustment. (At A = O, no phase adjustment takes place). Thus, a phase adjustment is taken into account in deterring the subsequent control information UP.

The accumulation described, together with the quantization, causes the differences OK to be smoothed as desired, and derives a reliable controlled variable UP from a sequence of values OK superimposed on a random sequence. Since the phase ad-it K.Szechenyi 25 justments are made only during the period of the unique word, as described above, the unwanted phase noise as-situated with the phase adjustment is Limited to the in-tervals of the unique word and, thus, cannot cause any transmission errors.

The clock-selection and polarity-control circuit 8 con-sits of a group of switches 28 and a control circuit 29 (Figs). The group of switches 28 contains a first switch whose two inputs are presented, respectively, with the control signalsS1 and So provided by the counter 4 and 5, a second switch whose two inputs are presented, respectively, with the frame clocks RT1 and RT2 provided by the frame detection circuits 2 and 3, and a third switch to whose two inputs the voltages "-1" and "+1" are apt plied. The positions of these three switches are determined by a switch control signal STY which is produced in the control circuit 29. When this signal STY is in the "H" state, the three switches are in the positions shown in the draw-in; when the signal is in the "L" state, the switches are in the other positions.

The control circuit 29 contains an AND gate 31 whose two inputs are presented with the signal F1 from the frame de-section circuit 2 and the signal from an OR gate 32, respectively The output of the AND gate 31 provides the switch control signal ST. The two inputs of the OR gate 32 are presented, respectively, with the signal F2 from the frame detection circuit 3, which was inverted in an in-venter 33, and the output signal of an AND gate 34. One in-put of the Latter is presented with the signal F2, and the other with the output signal Q of a fLip-flop 35. The S in-put of the flip-flop 35 is presented with the output sign 3 2~Çi3~;

K.Szechenyi 25 net of an AND gate 36, which combines a first auxiliary clock To (cf. Fugue) with the frame clock signal RT2. The R input of the flip-flop 35 is presented with the output signal of a further AND gate 37, which combines a second auxiliary clock To with the frame clock signal RT1 pro-voided by the frame detection circuit I

The input signals F1, F2, To, To, RT1, and RT2, which will be explained below with the aid of Fugue, are combined in the control circuit 29 to form a switch control signal ST.
When the latter is in the H state (logic 1), the output signals of the group of switches and, thus, of the clock selection circuit 8 are:
S = So, RUT = RT1, and P = +1 When the switch control signal STY is in the L state (logic o), the output signals are:
S = So, RUT = RT2, and P = -1.

The signals To and To, illustrated in Fig 6 in the second, fourth, and sixth lines from the top, are auxiliary clocks which are generated by the frame clock signals RT1 and RT2, respectively, and define the limited time interval within which -the clock selection circuit 8 makes its decision. Their pulse lengths depend on the application, as mentioned above; in the present case, it is equal to eight clock pulse periods, i.e., 8 x T, while one frump period is equal to 108 clock pulse periods and has a duration of 1 my.

In the case A, illustrated in lines 3 and 4, the first frame clock pulse to occur within the time interval de-fined by the auxiliary clock To is a pulse of the frame Z~3~5 K.Szechenyi 25 clock RT2, so this is the frame clock recognized as eon-feat in the clock selection circuit 8.

In the case B, illustrated in lines 5 and 6, the first frame clock pulse to occur within the time interval de-fined by the auxiliary clock To is a pulse of the frame clock RT1, which is thus recognized as the correct frame clock and passed on by the clock selection circuit 8.

Claims

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. Circuit arrangement for synchronizing a local sampling clock to the frame position and the phase of the characters of a received character stream containing a unique word at regular time intervals, wherein a digital correlator generates a crosscorrela-tion function from the received character stream, sampled at the sampling clock rate, and a unique word stored at the receiving end, and wherein a frame detection circuit derives a first frame clock from those maxima of the crosscorrelation function recurring at intervals of one frame period, characterized in that a second frame detection circuit derives a second frame clock from those minima of the crosscorrelation function recurring at intervals of one frame period, that a clock selection circuit determines which of the two frame clocks is being received within a limited time interval, and that from this frame clock, control information (.DELTA.P) for representing the phase of the sampling clock is derived in a phase synchronization circuit.

2. A circuit arrangement as claimed in claim 1, character-ized in that the control information (.DELTA.P) is derived from values {K(i0 + 1), K(i0 - 1)} which the crosscorrelation function has in the vicinity of the maximum or minimum detected within the limited time interval, and is used to adjust the phase.

3. A circuit arrangement as claimed in claim 1 or 2, characterized in that the clock selection circuit produces a polar-ity signal which determines the polarity of the values {K(i)} of the crosscorrelation function fed to the phase synchronization circuit.

4. A circuit arrangement as claimed in claim 1, character-ized in that the clock selection circuit consists of:
1. a group of switches by which the frame clocks, a signal determining the polarity of the values of the cross-correlation function {K(i)} , and a control signal for forming the differences between these values are switched through, and 2. a control circuit which produces a switch control sig-nal determining the position of the group of switches.

5. A circuit arrangement as claimed in claim 4, character-ized in that the control circuit comprises logic gates in which the two frame clocks, two auxiliary clocks determining the limited time interval and derived from the two frame clocks, and two sig-nals indicating the detection of a periodically recurrent maximum by the first and second frame detection circuits, respectively, are combined to produce the switch control signal.

6. A circuit arrangement as claimed in claim 1, character-ized in that the phase synchronization circuit is preceded by an adjusting device which shifts the sampling instants ahead of the instants at which the maxima of the crosscorrelation function {K(i0)} occur.

7. A circuit arrangement as claimed in claim 6, character-ized in that the adjusting device is a multiplier with which the values of the crosscorrelation function {K(i)} fed to a delay element ahead of the input of a subtracter are multiplied by a factor (.alpha.) greater than 1.

8. A circuit arrangement as claimed in claim 6, character-ized in that the adjusting device is a multiplier with which the values of the crosscorrelation function {K(i)} fed to a second input of a subtracter are multiplied by a factor (.beta.) smaller than 1.