CA1222831A - Document processing system and equipment - Google Patents

Abstract

"DOCUMENT PROCESSING SYSTEM AND EQUIPMENT"

ABSTRACT OF THE DISCLOSURE

A document processing system including a digital image capture system, character recognition circuitry, document encoding systems, endorsers, audit trail printers and an in-line microfilm record system enable documents to be read, endorsed, encoded, digitally imaged, filmed and sorted in a single continuous pass through the document processor by way of a modular transport system.
Video data compression apparatus and method are employed for use in minimizing the amount of data necessary to store and recall a black and white video image. An image initially obtained by vertically scanning a selected document is represented by a series of consecutive vertical scans identifying particular sections or cells of the image as black or white. A plurality of consecutive scans are then temporarily stored and analyzed horizontally, analysis circuitry being utilized to identify certain consecutive black or white sections of the image, repetitions of previous sections of the image or repetitions of certain selectable patterns within the image. The coded output of the analysis circuitry is then stored and utilized to reconstruct the image.

Description

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¦i ~ACKGROUND OF Tll~ VENTION
This invention relates to document processing systems in general, more particulaxly to document processiny systerns I adapted to be utilized in the processing of ~inancial documents 1 such as checks, invoices, payment advices, vouchers, drafts, cxedit card charges and the like, and even more par-ticularly to improved document encoders, scanners, digital image processors, I and video image data compressors particularly useful in the l document processing system.
¦ Document processors which read and sort financial ¦~ documents have been in common use for some time; however, ¦l various other functions which are necessary to most financial operations have been relegated to separate sub-systems or specialized processors to prevent major bottlenecks in the 1; document processing system. Among the peripheral functions ¦l which have not, in the past, been accomplished by the primary ¦ document processor are encoding with magnetic ink, microfilming ¦'l and endorsing. Addi-tionally" state of the art document pro-Il cessors utilizing digital imaging still require manual transfer 1l of documents to other processors to accomplish traditionally l! slower speed operations such as encoding, thus resulting in j lower efficiency in processing and increased probability of errors 1i An effective document processing system desirably utilizes an eff~ctive document encoder. State of the art encoders typically fall into two general categories~ The first category of encoders includes those encoders which utiliæe , a step function to position the document to be encoded at ! a particular point. Such encoders function in a manner 1 - typically associated with typewriters or other mechanical printers and are not generally compatible with high speed document processors. A second category of document encoders, Ij including laser printers and ink jet printers, while capable of encoding continuously moving documents i5 nonetheless incom-, patible for use with modern financial document processors.

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Il Document pLocessin~ systems also desirably require i ef~ective means of image storage. ~arly attempts at image storage utilized so-called "hard copy" image storage such as microfiche, microfilm or reduced pho~ocopies. More recently, ¦ docwnent images have been obtained utilizing electronic video equipment, and still more recently, utilizing digital elec-tronic video equipment.
Typically, in a digital document image capture system, Il a moving document is repetitively scanned in one axis and Il individual sections of the documents are assigned a value as Il either a "black" or "~hite" section, as a result of a comparison i ¦¦ with an arbitrarily assigned reference value. This simplistic ¦ approach to rendering a document image into a series of "black"
¦l or "white" sections is sufficient for many applications;
~5 !I however, if the system must operate upon multihued documents, ¦l such as personal checks, it is possible that the background ¦l color of a particular document may exceed the reference Yalue r Il and therefore may result in the entire image undesirably being 1, classified as "black".
1l Further, an optical sensor is typically utilized to detect the presence of a document prior to the initiation of digitization in such known systems. This additional piece of electronic equipment provides a possible source of error, in Ij that a malfunction of the optical sensor may result in a il document passing through the system without being scanned.
Digital image processing for creating visual images from digital data is known. Typically, state of the art systems display an entire image corresponding to the digital l! values stored in memory. More sophisticated systems utilize 1l video displays with permanently established boundaries between two sections of a display and separate images assigned to each section, in order to visually compare one image to another.

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'I As the complexity of such systems increases and the demallds ¦1 upon digital image processors grow to include such state of the ¦¦ art devices as lase,r printers, the need continues to exist ¦I for more sophisticated and ~lexible digital imaye processiny Il systems, particularly in financial document processor systems.
I An effective document processor desirably includes ¦l video image data compression apparatus. Specifically, in circumstances in which it is desired to store or recall a ,,, plurality of video images, the ma~nitude of data required ~or ¦i each individual image makes data compression a highly desired ¦¦ feature. ' ¦ Known data compression schemes which are utilized in ¦ conjunction with black and white document images typically ,j involve a scan which is perpendicular to the direction of , document travel. Scan data is then analyzed and long consecu-! tive black or white sections are removed and replaced with coded substitutes. In more sophisticated data compression i' schemes, scan data is analyzed and repetitive patterns ,i containing both black and white sections may be encoded and , removèd. Present apparatus, however, is not completely , acceptable, particularly for an e~fective document processor ' system.

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i SUMM~RY OE' Tll~ INV~NTION
~ccordingly, it is a principal object of tlle present ~¦ invention to provide an improved Einancial document processox.
ll It is another object o~ the present inven~ion to I provide an improved financial document processor which utilizes ! a modular transport system and combines all required operatior)s I¦ into a single document processor.
j! It is yet another object o~ the present invention to 1ll provide an improved document encoder capable of encoding 10 1¦ continuously moving documents. I
It is another object of the present invention to provide j an improved digital document image scanning system with a ¦ variable reference value being utilized for black/white decisions It is another object of the present invention to provide 5 ¦¦ an improved digital image processing system.
I! It is another object of the present invention to provide ,~ a video data compression system which provides a higher degree of data compression than known systems.
, In accordance with these and other objects, the inven-20 il tion, briefly described, is directed to a document processing I ;
!~ system which comprises a modular transport system including a ~ digital image capture system, character reco~nition circuitry, j, document encoding systems, document endorsing systems, audit Il trail printers, an in-line microfilm record system and a high 1I speed document sorter. Associated video terminals and non-impact printers such as laser printers are utilized to provide visual images of documents processed by the system. Selected documents may be read, endorsed, encoded, annotated with an l! audit trail indicia, digitally imaged, filmed and sorted in a 30 ¦¦ single continuous pass through the document processing system ¦! of the present inven*ion. I

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j For encoding, the documents are transported between a plurality of flxed dies and a plurality of electronically controlled hammers. A magentic ink bearing ribbon is interposed ¦
I between the documents and the fixed dies and is transported at 1! the same velocity as the documents. As the docurnents *raverse the plurality of fixed dies, the electronically controlled 1~ hammers are cycled, in a selected sequence and at selected ! positions. In thos applications in which the cycle tirne of the ,1 electronically controlled hammer is too slow to allow identical 1l encoding in adjacent positions, a second plurality of fixed !I dies and associated electronically controlled hammers may be located adjacent to the irst plurality or interspersed among the first plurality of fixed dies.
Il As further described, the documents are continually !I transported across the focal plane of a stationary scanner, ¦l and repetitively scanned in a single axis. Circuitry is Il included in the digital scanner which permi~s the presence or i, absence of a document to be detected by means of an evaluation 1 of the output of the digital scanner. Additional circuitry in 20 1! the digital scanner allows a dynamic adjustment of reference levels, thereby accommodating multihued documents which may , utilize shaded backgrounds.
A digital image processing system includes an image memory and circuitry enabling the display to be partiti~ned 1 into discrete portions of variable sizes, each portion of which I¦ may be utllized either to display a selected portion of the image within the image memory or to display a plurality of alphanumeric characters. During alphanumeric character mode, 1~ coded representations of each alphanumeric character are 1! stored in thé image memory, in an appropriate section.
Alternately, selected portions of one document image may be visually compared to selected portions o a second document image by utilizing this display partitioning feature. Addi-tionaily, circuitry is provided which allows image rotation, ; mirror imaging and discrete video attribute selection within each portion o~ the display.

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i' In accordance with an i.mprovcd data compr~ssion schcme, ¦! an image is obtained by vertlcally scannlllg a selected document.
The imaye is then represented by a ~erie,s of consecutive verti ' ¦l cal scans identifying particular sections or cell.s of the irna~e ' I
S 1l as eithex black or white. A plurality of consecutive scans I j are then temporarily stored and analyzed horizontally. ~nalysis ~I circuitry is utilized to identify certain consecu-tive white or black sections of the ima~e, repetition of previous sections of the image, or repetition of certain selectable patterns within 1~ the image. The coded output of the analysis circuitry is then Il stored and may be utilized to reconstruct the image of the ¦¦ financial,doCUment.
1. According to one broad aspect of the invention, it ', comprises an apparatus for processing documents comprising:
.~' means for transporting a series of continuously moving documents '', along a selected track; means disposed adjacent to said selected track for selectively encoding machine readable data upon selected ones of said documents; means disposed I ad~acent to said selected track for reading machine readable " data encoded upon selected ones of said documents; and means disposed at ~he.end of said track for sorting said documents~

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Another broad aspect of the invention is a video data compression system for data compression of signals representative of the video image of a document, said system comprisiny: (a) means for con-tinuously transporting said document along a first dlrectional path;
(b) means for video scanning said document during said continuous transporting and in a direction transverse to said first directional path, said video scanning means producing coded signals respectively representative of black and white sections of the image of said document;
(c) said video scanning means further comprising means for producing a plurality of consecutive scans in said transverse direction, (d) means for comparing the coded signals of one scan with the coded signals of a prior scan to compare the nature of adjacent ones of said sections in an axis parallel to said first directional path~ (e) means for generating unique redundancy codes indicative of unique relationships resulting from said comparison of adjacent sectionsi and (f) means for deleting from memory those coded signals indicative of the sections having the said unique relationships and replacing said deleted signals with said unique redundancy codes.

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33~l Il, IIBRIEF DESCRIPTION F TEIE DRAWINGS
The novel f'eatures believed characteristic of the ¦¦invention are set forkh in the appended claims. The .inven-ljtion itself; however, as well as a preferred mode of use, 'ifurther objects and advantages thereof, will best be under~
stood by reference to the following detailed description of an illuskrative embodiment when read'in conjunction with the accompanying drawings, wherein:
¦¦ Figures la and lb form a yeneral block diagram of ,¦the document processing sy'stem of the present invention;
Figure 2 depicts a diagrammatic view of the docu-ment transport of the document processing system of the present invention;
`I Figure 3a depi.cts a block diagram of the encoder I!of the document processing system of the present invention;
Figure 3b depicts a diagrammatic view of'the ~encoder of the document processing system of khe present 'linven-tion;
ll Figure 4 depicts a diagrammatic view of the en-I~ldorser of the document processing system of the present ¦invention;
,j Figure 5 depicts a diagrammakic view of the camera .¦system of the documenk processor of khe present invenkion;
Il Figures 6a-6i depick a schematic View of the ¦I components of the camera buffer and inkerface'circuitry of khe document processor of the present invention;
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~L~Z2831 Flgures 7a-70 and E'igures 8a-80 depict a schematic view of the components oE the data compression system of the document processor oE the present invention;
l Figures 9a-9b depict a block diagram o~ the major ,components of the da-ta expansion system of the document I¦Processor of the present invention;
¦ Figure 10 depicts a detaile'd block diagram of the video kerminal suhsystem of the document processor of the !I present invention; and ¦¦ Figures lla-llo and Figures 12a-12q depict a ¦schematic view of the video formatter of the document ¦Iprocessor of the present invention.

I GENER~L SYSTEM DESCRIPTION , ,~1 Referring to Figures la and lb, there is depicted ! a general block diagram of tha various subsystems compri,sing ¦¦the document processing system which embodies,the present invention.
The document processlny system is controlled by 1 digital computer 100. Digi-tal computer 100 coordinates the storage and retrieval of digi'tized document images and ¦associated data which are stored, in the disclosed embodi-ment, in magnetic'disk storage. Disk controller 102 con- ¦
~ trols the actual access of digitized document images via ¦ disk drives 104, 106, and 108. Additional data, accounting information or program data may be accessed by digital computer 100 thxough tape controllex 110 which controls lZZ;~83:1L

magnetic -tape drives 112 and 114. It will be appreciated by Itllose skilled in the art that disk controller 102 and tape ¦controller 110 may control an increased or decreased number ~of disk or tape drives, as a matter of design choice.
IDigital computer 100 may selectively access either magneti~
disk storage or magnetic tape s-torage through channel se-lector 116.
Digital computer 100, in the embodiment disclosed, interfaces with a local operator via the computer I/0 bus 1 and printer interface 118. Printer interface 118 controls llne printer 120. In alternate modes of operation wherein remote communication with digital computer 100 is desired, a modem and appropriate interface circuitry may be utilized.
l Digi-tal computer lOO also controls the operation 1 oE laser printer subsystem 124, through laser printer inter-~ face 122. Laser printer subsystem-124 is utilized to provide I hard copy of selected digital images and may be utilized to generate account statements, billing statements, or other i correspondence comprising any combination of alphanumeric characters and images. The operation of laser subsystem 124 ¦ is described in greater detail herein.
Video terminal subsystem 136 is utilized in the document processing system of the present invention to provide a real time, controllable video display of selected l¦documents and alphanumeric information. The display is jlutilized to facilitate processing of information on each document. Digital computer 100 controls tho operation oi Z;;~33.~

¦Ivideo term:inal subsystem 136 through buffer interface 14~
¦and synchronous da-ta link control master 146. A plurali-ty of video display terminals may be utilized with each SDLC
I master, in a manner which will be explained in detail below.
1 High speed transport subsystem 148 is utilized to -transport individual documents through image capture sta-tions, machine readers, encoders and sorters, A plurality l of high speed transports may be utilized within each docu-i ment processlng system, thereby increasing the capacity of ¦ an individual system. High speed tran~port system 148 is I controlled utilizing buffer interface 156 and synchronous ¦ data link con-trol master 158. High speed transport system ! 148 will be explained in greater detail with respect to I Figure 2. I
¦ Digital image da-ta obtained from the digital l camera or cameras installed in each high speed transport is ¦ transferred to camera interface 160. Camera interface 160 is described in detail with reference to Figures 6a through l 6i and is utilized to couple the image data to digital image il compactor 162. Digital image compac-tor 162 is utilized to Il remove any redundancies contained in a selected image and to i encode the remaining data. In addition to the specific algorithm taught in the disclosed embodiment, the document , processing system of the present invention will function ~I with other known data compaction algorithms, such as, for example, the CCITT standard algorithm. The thus compacted digital image will require substantially less storage space i 'l 'l -7-~ !
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in the docllment processing system. Thc compac~ed imcl~3c ~1~J~n may b~ transrerrcd to storage via mult:iplexed direct m~mory access lG~ and multiplexed c3irect memory access lG6. T~;o ¦ ' ,direct memory systems are utilized in order to'provldc~
compatible interfaces between the local X bus and the di~ect memory access interface bus of digital computer 100.
Retrieval and displa~ of a compacted digital image may take place in several ways. A compacted image is trans-~,ferred to the local X bus via'direct memory access 164 and direct memory access 166. The compacted image is applied to ;digital image expander 168. The redundancies present in the ,original image are restored and the subsequent image is transferred via X bus distributor 170 or X bus distributor 172 to either laser printer subsystem 124 or video terminal jsubsystem 136 for reproduction of a hard copy or an elec-tronic image.
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DIGITAL COMPllTER
The document processing system of the preferred embodiment of the present invention utilizes' a diyital , computer 100, ~igure 1, to cont~ol the operation of the system and coordinate the storage and retrieval of document images. In a preferred embodiment of the present invent'ion, digital computer 100 was actually constructed utilizing a "Series 3200 minicomputer, manufactured by the Perkin-E1mer , .
Computer Systems Division of Oceanport, New Jersey.
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l;~ZZ837 Il Tlle Model 3242 minicomputer utilizes 32-bit j¦architecture ancl a 32-bit operating system. The main mernory -l¦stora~e, in the embodiment disclosed, contains 1536 kilobytes l¦of 150 nanosecond MOS memory. Supplernenting the computer's 1 main memory store are disc drives 104, 106 and 108, Figure 1, Model 9775 manufactured by Control Data Corporation of l Minneapolis, Minnesota, and tape drives 112 and 114, Figure i l, Model TPAC 4516, manufactured by Perkin-Elmer of Ocean-'Iport, New Jersey.
Digital computer 100 also includes a rechargeable battery backup system (not shown) to sustain the main memory jin the event of a power failure. The preferred embodiment ,jof digital computer 100 utilizes a battery rated at 320 ~! megabyte-minutes, which is capable of maintaining the memory ¦ integrity of 16 megabytes for twenty minutes.
I, I DOCUMENT TRANSPORT
jj Referring now to Figure 2, there is depicted a ildiagrammatic plan view of document transport 200. Document 'transport 200, in a preferred embodiment, is a specially ! built transport which may be modified to include additional ,equipment or to exclude undesired capabilities. The trans-port constructed and depicted in Figure 2 utilizes high ,¦speed endless belts which are driven by pinch rollers in the 1 manner well known in the art. The pinch rollers are driven i by synchronous AC motors at a nominal speed of 52 inches per !
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second in the disclosed embodiment. Sections of the trans~
port may be driven at diEferent speed~ in a mannex descrihed below.
Documents axe loaded into document transport 200 ' by means of document hopper 202. Single documents are loaded from document hopper 202 via feed drum 204. The l documents are then passed along document transport 200 ! between rollers and the endless belts (not shown).
¦ The firc.t section of document transport 200, ! reader section 206, includes an optical character reader 208 and a magnetic ink character reader 210. Those skilled in l the art will appreciate that a single model optical reader, i such as the 30-250 ips read head manufactured by Input ¦ Business Machines, Incorporated of Rockville, Maryiand, can 1 function as either an OCR reader or may be utilized to op-tically read MICR characters with appropriate control elec-¦ tronics. OCR reader 208 may b utilized in the applications ¦¦ wherein the amount field or other information is printed in j an OCR format.
0 1 The next section of document transport 200 is encoder section 212. Encoder section 212 includes hammer bank assembly 214 and die and ribbon assembly 216 and is - I utilized to encode selected documents with selectable indicia, while the document is traversing document transport 200. The operation of the encoder section will be explained in greater detail with reference to Figure 3.
Section 218 of document transport 200 i5 the endo~ser sectlon. Endorser section 218 contains ink jet .1~ '' ' '.

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printers 220 and 222 and endorser 224. Ink jet. printers 220 and 222 are standard state of the art ink jet printers that ~¦maY be utilized, in the disclosed embodiment, to print llselected indicia upon each document which passes through ,Idocument transport 200. The selected indicia may be util-¦¦ized to assist in audit trail functions or in any other ¦function desired. Endorser 224 is utilized to endorse l! documents such as checks. The structure and operation of i¦endorser 224 will be explained in greater detail with l¦respect to Figure 4.
~I The next section in document transport 200, through ! which each document is transported/ is camera section 226.
¦ Camera section 226 contains, in the en~odiment disclosed, l two digital video cameras, 228 and 234 and two illumination ~¦sources, 230 and 232. Each document which passes through !camera section 226 is scanned on both sides utilizing video ilcameras 228 and 234. The operation of camera section 226 is explained below with reference to Figures S and 6.
,j The penultimate section of document transport 200, 'Imicrofilm se.ction 236, contalns a microprocessor controlled !' microfilm recorder 238. Microfilm recorder 238 is described in greater detail belo-w, and is utilized to provide hard - l¦copy of selected documents which have been processed ~y the ~Isystem of this invention. Microfilm recorder 238 is capable 11 of accurately recording documents traveling at greater rates Ijof speed than that.present in earlier sections of document ¦Itransport 200, and as a consequence, the transport speed is . ' ' , ~IL_ ¦increased in microfilm section 236 to a nominal speed of 100 I inches per second. This transition is accompliished by I utilizing a slipping drive at ~he interface between micro-¦ ~ilm section 236 and camera section 226. Thus, while a ¦ portion of a document is still traveling at a nominal speed ¦~of 52 inches per second in camera section 226, the slipping l! drive tnot shown) in microfilm section 236 allows the ¦¦document to slip until fully released.
¦¦ The final section of document transport 200 is l¦stacker section 240. Stacker section 240, in any mannex ¦well known in the art, sorts the documents processed through ¦document transport 200 into one of several pockets. The ¦number of pockets is, of course a design choice wholly ¦¦dependent upon the application desired.
¦ As those skilled in the art will appreciate, the modularity of design employed in document transport 200 will allow great flexibility in many applications. Whole sections of document transport 200 may be deleted or rearranged to jlpermit a wide variety of custom applications. Further, the linum~er and type of devices within each module may be increased ¦or decreased as a matter of design choice.

~¦ ENCODER
1~ `With reference now to Figure 3a, there is depicted lla schematic view of encoder 300 of the present invention.
IlAn lmportant feature of the present inv~ntion is an ability '~lto encode continuously moVing documents. In kno~n document ' , `
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¦¦processiny systems document encoding prove~ to b~ the major ¦~bot~leneck to high fipeed processing. Typical so:lutions have ! included a separate slower por-tion o~ the document processor ¦~in which a document is stepped throuyh an encoder, or a j separate o~f-line encoderO Document encoder 300 is capable ¦lof encoding documents which are continuously moving at the ¦ rate of the document processiny system of the present inven tion.
Document ~ncoder 300 utilizes, in the illustrated 1 embodiment of the present invention, two identical electro-I magnetic hammer banks, hammer bank 302 and hammer bank 304.
¦ It will be apparent/ however, upon reference to the fore-l going explanation, that a fewer or greater number of hammer ! banks may be utilized in systems wherein slower or faster l transport speeds are desired. Hammer banks 302 and 304 are ~- ¦ electromagnetic hammers such as part no. CCE-05-306 manu-factured by Dataproducts, Woodland Hills, California. Each l hammer bank is controlled by a hammer driver. In the dis-; I closed embodiment, hammer driver'306 controls hammer bank ¦ 302 and hammer driver 3~8 controls hammer bank 304. Hammer ! power supply 310'provides operating power for all'hammer I ~ drivers and hammer banks.
Positioned opposite each ha~mer bank is an ap-l propriately encoded die. The selection of characters util-! ized in a particular application is strictly a design choice and may include OCR characters, MICR characters or any other de=ired clla scter pattern. The lllustrat-d embodiment . . '' '.

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¦includes two substantially identical die sets, die set 312 ¦~and die sc~t 314. Ilowever, as a matter of design choice, a i single die set may be utiliæed. Also included in the illu~:-¦trated embodiment is microprocessor control 316, which ~ provides control signals to hammer drivers 306 and 308 in Iresponse to signals from optical sensor 318. Optical sensor ! 318 is utili~ed to detect the presence of a document along , document pat.h 320. Ribbon mechanism 322 is also depicted in l Figure 3a, and will be explained in greater detail with ¦ reference to Figure 3b. ' ' Figure 3b depicts a partially diagrammatic view of the major components of document encoder 300. As explained I above, hammer banks 302 and.304 selectively strike portions . I of die sets 312 and 314, upon receipt of control signals I!generated by a microprocessor control 316 (,see Figure 3a~, ¦in conjunction with an item presence signal generated by l¦optical sensor 318.
.¦ Ribbon mechanism 322 (,Figure 3a) is shown in ilgreater detail in Figur.e. 3b and includes a ribbon supply lireel 324, ribbon takeup reel 326, ribbon tensioning arms 330 and 332 and ribbpn capstan 338. Ribbon supply reel 324 provides a fresh supply of magnetic ink ribbon 340. Such ~¦magnetic ink ribbons are typically single strike ribbons, ! that is to say the magnetic ink associated with each char-1 acter is totally removed from the ribbon during the prin ing of that character. and further attempts to print utilizing .
~the same section of ribbon 340 will result in lnvalid 1~ " ' ' , .
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~2Z~33~ 1 l¦maglletic signatures. Therefore, it is necessary to advance ¦¦maglletic inlc ribbon 340 after each character is printed, and it is advantageous, from an economy standpoint, ~o advance l ribbon 340 only while a document is present in encoder 300.
1 This is accomplished utilizing ribbon capstan 338 which i5 electronically controlled by microprocessor control 316 during those periods when a doGument is detected by optical sensor 318. For reasons which will be explained below, . ribbon 340 is driven by ribbon capstan 338 at the same speed¦ as documents on the transport. The rapid acceleration of ribbon 340 to transport speed is accomplished without l damage to ribbon 340 utilizing ribbon tensioning arms 330 I and 332. Ribbon tensioning arms 330 and 332 are pivotally .
; I mounted at point 342 and resiliently biased utilizing !
l¦ springs 334 and 336. A rapid acceleration of ribbon 340 is 'I then absorbed by ribbon tensioning arms 330 and 332 until Ij ribbon supply reel 324 and ribbon takeup reel 326 can compensate.
I In operation, encoder 300 utilizes two character ,'1 se~s to compensate for the duty cycle of the hammer bank i¦ utilized. Each individual hammer within hammer banks 3G6 Il and 308 has a duty cycle of approximately .004 seconds.
- jl Document encoding standards for MICR require individual . characters to be encoded approximately one-eighth inch ! apart, or one-tenth inch spacing.for OCR. At a nominal , transport speed of 52 inches per second, a document will travel one-eighth i~c~ in approximately .0024 secbnds. It ~L~Z~:~33~L
~should therefore be apparent that with a duty cycle o~ .004 seconds, a single hammer and die combi.nation will be unable llto repetitively strilce a single character at one-eiyhth inch ¦¦intervals. Thus, the use of multi.ple hammers and substan-lltially i~entical character sets will a:Llow full encoding at jthe present duty cycle.. Consider a possible worse case analysis, a desired encoding of eig~t consecutive identical characters. Those skilled in the art will appreciate that a llsingle hammer and die will ~e able to encode alternate digit ,Ipositions at the stated speed of operation. The second ' group of,hammers and characters allows encoder 300 to fill .
in the missing digits. More specifically! hammer bank 306 ..
and die set 312 may encode the odd'digit positions in a desired field, and hammer bank 308 and die set 314 may!
llencode the even digit positions. Thus, it should be appar-ent that increased or decreased transport speeds may be liaccommodated by utili~ing'a greater or ewer nu~ber of .
'¦hàmmer banks and die sets3 without requiring a faster duty llcycle for individual hammers. It should also be apparent that since certain portions of a particular digit field may ¦be encoded by one hammer bank while other postions may be ~encoded by a second hammer bank, it will be advantageous to , maintain rib~on 340 at the same speed as the documents.
~ passing through encoder 300. By so doing, the'used portion jof ribbon '340 associated with a particular character'wi.ll ,¦maintain its relative position directly above that partic-¦¦ular character on the document.
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~NDORSER
¦ Re~erring now to Fig~re 4, a cutaway view of the major components of endorser mechanism 400 is depicted. A
llsection oE a document 402 is shown on document path 404.
, The belt drive mechanism which transports document 402 along document path 404 is not shown.
1 Ink roller 406 is mounted in bracket 408, which ¦ j ! may be pivoted upward at pivot point 410 to allow replace-¦¦ment of ink roller-406. Additionally, pressure adjuster 412 ~ may be utilized to adjust the amount of pressure exexted by i ink roller 406 upon transfer roller 414.
!I Transfer roller 414 is mounted in tangential ¦proximity to endorser plate 416 and is utilized ~o transfer ¦ink to endorser plate 416 from ink roller 406. Transfer il roller 414, endorser plate 416 and platen 418 are all driven Ijby belt 420 and belt 422 and drive pulley 424; however, .llelectronically controlled clutch 426 is utilized to selec-l tively engage endorser plate 416. Thus, when it is desired : ¦to endorse a selected document, ink is.transferred to en-lidorser plate 416 and electronic clutch 426 is energized, !lurging endorser plate 416 into contact with platen 418 and , rotating endorser plate 416 and platen 41~ at an appropriate l speed. .
I Electronic clutch 426 is controlled, in a pre-¦ ferred embodiment, utilizing an appropriately programmed I microprocessor type device. Therefore, documents may be i -17-Z~31 lltransported through the document processing system of the ¦Present inven-tion and be selectively endorsed.

¦¦ VIDEO CAMERA
1 Figure 5 depicts a diagrammatic view of a system l, utilizing two video cameras 500 and illumination sources 502 ¦whereby the image on both sides of a document may be cap-tured. Each illumination source 502 is comprised of two 500 watt tungsten halogen bulbs, encased in a housing having o ~! cooling means and an optical focus assembly 504. Optical ¦¦focus assembly 504 comprises a plurality of lenses arranged, ~¦in any manner well known in the art, to focus a vertical bar l¦of intense light onto document plane S06. In the embodiment !l disclosed, the vertical bar is generally rectangular in ¦Ishape and is approximately six inches tall and one tenth of ¦¦an inch wide. As discussed above, documents are transported llaterally across this illuminated portion to enable video ¦image captur~.
I The light reflected from each document passes ~! through each camera lens assembly 508 and is focused on line I scanner 510. Camera lens assembly 508 is a fixed magnifi- ¦
'cation ratio lens typically utilized in fixed working dis-iltance applications such as photographic enlargers. Line i! scanner 510 is a solid state line scanner such as those Icommercially available from the Reticon Corporation of Sunnyvale, California. Line scanner 510 is a high densityr , monolithic, linea- array of silicon photodiode- with i '. . .
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inte~rated scanniny clrcuits for serial readout. The arr~y, in the embodiment disclosed, consists of a row of 768 silicon photodiodes, having a storage capacitor associated therewith llupon which may be integxated the photocurrent, and a tran-Isistor switch for periodic readout via an integrated scan-jning circuit. The individual photodiodes of line scanner 510 are one mil s~uare and are spaced center-to-center, one mil apart.
During image capture, a document is transported ; laterally across the vertical bar of light generated by each ¦illumination source sn2. Each camera lens assembly 508 focuses the reflected light from the document onto line scanner S10. Each of the 768 sillcon photodiodes contained I¦within line scanner 510 produces an electrical signal which l¦is proportional to the intensity of the incident light. The ¦¦photodiodes are then sampled at a high rate, the line ¦¦scanner utilized in the preferred embodiment may be sampled ¦at frequencies as high as ten megahertz. The combination of !~ the lateral motion of the document and the vertical action !, of sequential sampling o~ the photodiodes in line scanner 'l510 will produce a two dimensional picture of a document -Iwith a resolution within .007 of an inch.
The output of line scanner 510 is amplified and I coupled to additional circuitry as a series of pulses where-1 in the area of each pulse is proportional to the intensity of the incident light on each photodiode. This series of ~pulses is utili~ed in the camera control ~ircuitry tD sense . ', ',~'' , ' ' ~ " "' '.' . ' `I I

__ _ IL 19- 1 :~2~283~
,¦the presence of a document and to dynamically adjust the threshhold level utilized to determLne whether a particular , value is white or black. The series oE pulses is ~lso ¦ applied to the data compression system for compression, l¦storage and subsequent retrieval.
., CAMERA BUFFER AND INTERFACE CIRCUITRY
¦ With refexence now to Figures 6a-61, there is 1ldepicted a schematic view of the ma~or components of the ¦¦camera buffer and interface circuitry of the document ¦¦processor of the present invention. Wh.ile the disclosed ~¦embodiment of the present invention utilizes two video cameras, in many cases only one se of ~uffer and interface l circuitry will; be depicted. Those ordinarily skilled in the ¦ art will appreciate the simple duplication of circuitry ¦¦necessary to accomodate two video cameras.
ll Referring now to Figure 6a, osoillators 60l and I !1 602 are utilized~ in conjunction with the basic cloc~ signal !1~30.5 megahertz in a preferred embodiment) to provide the iscanning pulses to line scanner 606. Oscillators 601 and 602 are implemented, in a preferred embodiment of the pres- ¦
l'ent invention, utilizing standard 74S74 type flip-flop - 'lintegrated circuits. The control pulses necessary to oper-l¦ate line scanner 606 are applied via amplifiers 603, 604 and 1 605, which are utilized to provide level adjustments. Line scanner 606, in the illustrated embodiment, ls an RL-768C
~intcgrated c1rcuit m-nufa-tur-d by the Reticon Corporation ' . .

. 1 ' ' . ' .

283~L I

~oE Sunnyvale, California. Addil:ional cle1:ails concerning the ¦construction oE line scanner 606 are disclosed above with llrespect to the video camera description. Line scanner 606 ¦¦is scanned at a parallel rate of three megahertz. That is, llthe odd numbered cells in line scanner 606 are scanned at a ¦three megahertz rate and the even numbered cells are also scanned at a three megahertz rate. Thus, line scanner 606, with proper multiplexing of the ~ual outputs, is capable of generating video pulses at: a six megahertz rate.
1 Even cell and odd cell outputs of line scanner 606 are applied to amplifiers 611 and 610 respectively. Ampli-llfiers 611 and 610, in conjunction with capacitors 607 and 608, are utilized to capture the output of each individual scan cell. Switching transists:r 609 is utilized to alter-'Inately remove all charge accumulated on capacitors 607 and 608 between sampling times for adjacent cells of line scan-lner 606. The RESET signal accomplishes this and is applied to switching transistor ,609 through inverter 612.
!¦ The outputs of amplifiers 610 and 611, repre~ent-,1 ing the relative charge present on capacitors 608 and 607 ,j during each cell scan, are furt~er amplified by amplifiers .! 613 and 614, in a manner well known in the art. The outputs ; of amplifiers 613 and 614 are next applied to two sample and ~¦ hold circuits. The sample and hc?ld circuits are conlprised ¦ of switching transistors 617 and 6I~ and storage capacitors I 615 and 616. Thus, the charge present on capacitors 615 and . . .. ..

Il .

I
! -21-., ,1 j¦616 is indicative o~ the amount of light ~triking the cor-jlrespondirlg scanrling cells of line scanner 606 at any selec-ted t.irne. The signals are then coupled, via lines 620 and 1~621 to a final stage of amplification, consisting of ampli-I,fiers 622 and 623 (see Figure 6b).
With reference now to Figure 6b, the outputs of ~amplifiers 622 and 623 are each applie~ to two points within the dynamic threshold circuitry. Dynamic threshold adjust-llment is an important feature of the document processing ¦¦system of the present invention and allows a single system ,Ito process multicolored documents without requiring indiv-. . idual level adjustments. Il ¦ The output of amplifier 622, representing the i amplified outputs of the odd numbered cells of line scanner l 606 (See Figure 6a) is applied to one input of comparator 633 and to diode 624. Similarly, the output of amplifier 623, representlng the amplified outputs of the even numbered ~ ;
~cells of line scanner 606, is applled to one input of ¦Icomparator 634 and to diode 625.
ll Diodes 624 and 625 perform an OR function and apply the more positive of their individual inputs to ~capacitor 626. Capacitor 626 is, therefore, rapidly charged jto the level of the highest signal applied through diodes 1l624 and 625. This level is the "white" threshold and , represents a reference point fox black/light decisions. The l¦vultage lev l present on capacit~r 626 is applied through~ ¦
I
l . .. ,' ! . . .

Il -22-33~1 j~diodes 627 and 628 to the second input of comparators 633 and 634. The voltage drop across cliodes 627 and 628 as6ures llthat the signal creating charge on capacitor 626 Will be jlgreater than the resultant reference signal applied to llcomparators 633 and 634.
~! The charge present on capacitor 626 will eventual-i ly discharge slowly through resistors 629 and 630; however, a reference voltage applied through diode 632 will prevent ~ total discharge and will apply a minimum level which a cell l¦output must exceed in order to be considered "white."
'IAdditionally, the time constraints associated with capacitor ll626 and resistors 629 and 630, while chosen to be "slow"
Ijwith respect to individual cell sample times, are suffic-lliently "fast" to allow dischargP of capacitor 6Z6 ~etween ¦,adjacent documents. Thus, a totally white background lldocument, while in process, will result in a high reference jsignal being generated on capacitor 626, and result in any llsignal greater than two diode drops below that level bsing - ~¦characterized as "black." However, during the gap between jdocuments, capacitor 626 will discharge sufficiently so that ja colored background document~(blue, for example) will ~generate a lower reference level~ This system of dynamic ~reference adjustments allows a single system to process an ilentire variety of multihued documents without system ad-ljjustment, and without the possibility of losing all data ',contained on a relatively dark ~ackground document.
1~ . .

i' ~2Z;~:~33~L

For reasons of circuit design not important to the I concept, an inverted output is selected ~rom comparators 633 and 634. Tllerefore~ a particular cell in line scanner 606 ¦ which detects a "black" area will result in a logic 1 or ' "high" output of the appropriate comparator, and a cell which detects a "white" area will result in a logic 0 or l "low" output from the appropriate com~arator.
I Referring now to Figure 6c, the document detection licircuitry of the document proaesscr of the present invention 11is depicted. The odd and e~en numbered cell outputs from comparators 633 and 634 (See Figure 6bj are applied to shift ¦register 635. Shift register 635 multiplexes the dual three ,Imegahertz signals into a single six megahertz vi.deo signal.
,IOne output of shift register 635 is applied to shift re~is-ilter 636. Shift register 636 is loaded each time a "black"
'¦cell is detected and shifts each time a "white" cell.is jdetected. After eight consecutiv~ "white" cells have been ¦¦detected, the output of~shift register 636 is shifted out l¦and sets latch 640. Latch 640 is a simple JK type latch and jlis utllized to generate the signal which indicates the scan is active (ACTSCNl).
The output of shift register 635 is also applied ¦to counters 637 and 638. Counters 637 and 638 are the I¦leading edge detectors and are reset at the end of each scan through line scanner 606. Counters 637 and 638 are utilized j to count "white" cells in a single scan. If sixty-four "white" cells are detected.in a single scan, counters 637 !

~,f~
L22~3 !l j'and 638 se~ latch 639. Latch 639 i6 also a simple JK latch and is utilized to set edge detection latch 642.
The ouput of edga detection latch 642 is utiliæed Ijto generate the signal which indicates a document is present '~ TMPRS1). The output of latch 639 is also applied to counter 641-Il Counter 641 is the,trailing edge detector.
IICounter 641 is utilized to count the number o~ complete llscans in which less than sixty-four "white" cells are de-'Itected. If sixteen such scans are counted, the output of counter 641 is utilized to reset edge detection latch 642.
,Header 644 is merely a connection means ~o allow compata-;bility between systems which utilize a single video camera and s~stems which utilize two video cameras.
j¦ ,Figure 6d depicts a series of counters and re~is-,Iters utilized to provide ope,rating information to a con-jltrolling microprocessor type device. Counters 645a-645f are 'liutilized to count tha total number of active cells in a llparticular document. The number counted is latched into iregisters 646a-646c ~nd is available upon query by the ¦control device. Similarly, in applications utili~in,g two 'lvideo cameras, counters 647a 647 axe utilized to count the !¦total number of active cells in the second,side of a par-¦llticular document and registers 648a-648c store the total 1¦ count, -Figure ,6e depicts further counters and registers ~used to rro ide op~rating information. CounterF 649a-649c ll ~ l I
Il -25-1 ~LZ;22~33~L I
!l i count the tot~l number o~ l.ines scanned in a partlcular document and latch that numbex into registers 650a and 650b.
Similarly, counters 651a-651c are utilized to count the I total number of lines scanned by the ~econd camera and that ' number is latched into registers 652a and 652b. Thus, by knowing the total number of cells and the total number of scans, a control device may simply divide to calc~late the exact dimensions o'~ a particular document.
. ¦ Also depicted in Figure 6e is bus driver 653. Bus ¦ driver 653 is utilized to drlve or amplify data being read ! from any of the interface registers to permit transmittal to 'l a microprocessor type control device.
¦ Referring now to ~igure 6f, there is depicted a.
. series of input and output latches utilized to provide' ,' communications to and from a microprocessor type control device. Latches 654, 655, 656 and 657 are utilized to latch !l in in~ormation from the con~rol device'to the system.
¦~ Information and~or commands that test, clear ox arm the ,I system are received and latched into the'appropriate'latch.
!1 Information received may be utili~ed to appropriate'com-, mands, such as depicted with logic gates 658a-65~d.
!j Information; device'identification, returning test data and busy indicàtions may be latched into latcpes 659, ! 660, 661 or logic gate 662 for access by a control device.
! With reference.now to Figure 6g, there is depicted additional addr'ess and control circuitry. .Switch 666 is a multiple position DIP switch which may be set in a uniqué

"! "-` l```\ l ;~ 2~33~ 1 Il I
¦! pattern to specifically identify a particular transport and j~camera, recalling that a system may include additional ! transports as a matter oE design choice. The positions of I the various switches in switch 666 are coupled to comparator 1 664 for comp~rison with the eight address bits generated by the microprocessor type control device. Thus, it is pO5-l sible for the control device to accurately address a single i one of a plurality of devices~ If comparator 664 indicates l an address match, a valid address signal (VALAD) is gener-1 ated.
I Once a valid address has been detected, the fîrst four bits of address, A0, Al, A2 and A3 are utili~ed to address up to a maximum of sixteen addressable registers on I the addressed device. Bus driver 633 is utilized to co~ple ! these address bits to the addressable registers. Bus driver ¦665 is utilized to couple control commands and the A4 address ¦¦bit The A4 address bit is utilized, in the illustrated embodiment, in conjunction with the valid address signal, to lldesignate either of two video cameras, utiliæing logic gates `¦667d and 667e. Logic gates 667a-667c are utilized in ~on-lljunction with other decoded commands to generate interna : '! read and write commands.
ll Referring now to ~igure 6h, there are depicted six ¦¦ decoders utilized to decode command and address information 1l from the control device. Decoders ~6~ and ~72 are utilized during a memory write command to either vides camera.
Decoder 70 and C73 are util zed when thc control devlce .i . , ' ', , -27-Il , .

` ! l Il ~L2~22l33~
¦issues a memory read to either camera. Decoders 67] and 67 deco~1e the comm~lnds which acce~F ~he total cell nwllb~r ~nd total scan number registers depicted in ~igures 6d and 6e.
l Finally now, with reference to Figure 6i, there is 1 depicted the output circuitry associated with the video ! camera of the present invention. The depicted embodiment of the present lnvention utilizes eigh~ separate vldeo buses to ¦ transmit video data between various components of the sys-I tem. This group of buses is collectively referre~d to as the I X bus, and any single bus may be selected for any single ¦Idevice to utilize.
Control signals from the control device are de- I
coded utilizing decoders 675, 676, 677 and 678. Decoder I 675, 676, 677 and 678 may be implemented, in a preferred 1 embodiment, by an integrated circuit of the type 74LSl38 i manufactured by the Signetics Corporation of Sunnyvale t jCalifornia. The outputs of decoders 677 and 678 are util-ized to enable selected~three state buffers. Three'state' I, buffers 679a-679d, in the illustrated embodiment, will 1~ couple the data from one camera to one'of four video buses while three state buffers 680a-68Qd will couple't~e'data from a second camera to one of the four remaini~g video ¦ buses.

"' 11 ' ' ' ' ' ' li .
I ;' ' ,', '' " ., . .

DP~TA COMPRESS ION SYSrrE:M
With reference now to Figures 7 and 8, there is depictecl a schema'~ic representation of the circuitry o~ the ¦¦data compxession system.
Referring now to ~igure 7a, the system clock and its,complements are applied to the inputs of high speed I differential comparator 70~, which acts a's a high speed line ¦ receiver. In the disclosed'embodiment, the system clock is a 30.5 megahertz signal,generated utilizing a crystal,con-¦ trolled oscillator (not shown~. The output of comparator 701 , is applied to multivibrators 702 and 733, where the frequency ¦ is halved in a manner well known in the art.
The output of multivibrator 702 is applied to four I bit binary counter 704, where the haived clock frequellcy is , further divided into lower frequencies which are utilized throughout the syst~m.
Cross point switches 705a, 705b and 705c are utilized by a microprocessor type control device to select !¦one of eight bus lines to be coupled to the data compression llsystem. The cross point switches utilized in a preferred !~ embodiment of the present invention are Signetics type ,SD5301 switches. As previously mentioned, the eight line , bus r~ferred to as the X bus is comprised, in one embodiment ¦ of the present invention, of eight three wire bus lines.
¦ Each bus line has a ready line, a clock line and a data I line. The particular bus selected by cross point switches .. I . , .'.

~ ! . . ..

2~
~1 . ' I
l 705a, 705b and 705c is controlled by bus control reyister ! 706, in response ko commands from a microprocessor type ¦ control device.
¦ Bus control register 706 is utilized to control cross point switches 705a, 705b and 705c in conjunction with shift register 707. Shift register 707 is a parallel in-serial out (PISO) register which is ut~lized to serialize the command data from register 706 and couple that serial-l i7.ed command data to set up the cross point switches.
- ¦ Shift registers 708a and 708b are utilized in conjunction with logic gates 709a, 709b, 709c and 709d to enable cross point switches 705a, 705b and 705c and to ¦control register 706 when data is being written into regis-l¦ter 706. By controlling data into register 706 and the clocking of that data out of shift register 707, the oper-i ation of the cross point switches is carefully sequenced.

In the event that the selected X bus line is Itoccupied, or when a pause signal indicates that incoming i! data must temporarily stop, circuitry is present which will ~0 llcease data input to the dat~ compression system. A not ¦ready condition out of cross point switch 705a or an intern-I~ally generated pause signal at the input of NOR gate 710 ¦¦will generate a signal (RBUSY) which will stop the operation 11f multivibrator 703 and thence the operation of the output 25 ~ l~sec~ion.

!
.. . .,. .

` i ~.2;~2~3~L
i Also depicted in,Figure '7a is end of data clock 711. Clock 711 is a simple multivibrator which is utilized to generate the end of the ou,tput data signal.
¦ Referring now to Figure '7b, there is depicted the ¦ circuitry by which the microprocessor type control device may accurately address the data compression system and various registers within the data compression system.
Jumper wire switches 712a and 712b are utilized with various jumper wires to provide a unique address for ¦ the data compression ,system. Buffers 713a and 713b are l utilized to receive a board address and register address ! from the control device. Each board may contain up to j sixteen separate addressable registers (or thirty-two ;
including read only and write only registers) and therefore 1 four bits of address A0-A3 are utilized to select a regis-ter.
The remaining address bits are coupled to com-parators 714a and 714b where they are compared to the ad-l dress o~ the data compression system board, as determined by 1 the placement of jumper wires in ~umper wire switches 712a and 712b.
Control signals from the control device are coupled to buffer 715 and one of eight decoders 716a-716d are util-ized to decode the selected register address to determine which register will be read or written to by the current ~command.
I
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.~22z~33~
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Logic gate 717 is utilized to receive the INITI~L
signal and is utilized to gen~rate the signals which initial-ize various other portions of the data compression system.
Figures 7c and 7d, wlen placed side by side in the S I manner indicated in those two figures, depict a schemakic representation of the "spot remover" cixcuitry of the data compression system of the present invention. The spot remover circuitry is utili~ed to remove any single black Il''spot'' from the data which corresponds to a particular l¦image~ A spot is defined for these purposes as a single black cell detected by line scanner 606 (see Figure 6), that ! is surrounded by white cells.
¦¦ R~ferring now to Figures 7c and 7d, the data stream representative of a scan through a document is 1 coupled to an input o~ register 718a and then out of reg-ister 718a and into delay register 719a. Delay register 719a is, in a preferred embodiment, a 1024 bit random'access l memory that is utilizsd~in the manner of a long shift reg-! ister.
! The data out of register 718a is written into ' delay register 719a at an'address determined by address generators 720a-720c. Address generators 720a-720c are initially loaded to a number which correlates with the 1 number of cells in each scàn for a particular document or I group of documents. Address gererators 720a-720c are four bit counters which are utilized to control the addresses in delay' registers 719a and 719b. Thus, the data from register I

! -32-, 3g.

718a is written into an address of delay reyister 719a which I will result in the leading edge o~ data exiting delay regis- I

i ter 719a at the end of each scan.
l The data exiting delay register 719a is coupled to 1 register 718b and to the input of delay register 719b. As ; above, the data in delay register 719b is delayed for the leng-th of a scan and is then coupled.to register 718c.
Those skilled in the art will appreciate that this config-l uration will result in a sample of the current scan being I present in register 718a, a sample of the previous scan I being present in register 718b, and a sample of the next ! previous scan being present in register 718c.
j! It is therefore a simple matter to examine the i surrounding cells, utilizing logic gates 721a and 721b, and ! to determine whether or not a particular black cell is a "spot" that should be removed. Logic gate 723 compares the I single cell with the surrounding cells and generates the signal which removes the spot. Wire jumper 729 is provided I to allow the spot remover circultry to be disabled, if that is desired in a particular embodiment.
! r~egister 725 is a four bit, parallel access shift register which is utilized, in conjunction with ~lip flop I 726, to generate write enable signals and various system i clock signals.
2S 1 With reference now to Figures 7e and 7~, which when placed side by side in the manner indicated in the drawings, depict tbe scan memory address circuitry. The l . . !--I .
. , '' '~''.'., '.
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2~831 I
data associated with a plurality of ad~acent ~cans through a ¦¦ document must be stored and examined to permit data compres-sion, and such storage mu5t be accomplished in a precise I manner to permit later synthesis oE a document image. In 1 order to accomplish this storage in an orderly fashion, the number of scans and the number of cells in each scan must be j carefully tracked.
¦ Comparator 72S in Figurç 7f is utilized to compare I the number of cells in each scan with an incremented addressO ;
1 The number of cells in each scan is loaded into the data , compression system, ~y a control device, through registers which are not shown. The incremented address which controls the storage location of incoming data is generated by scan l memory address generators 726a, 726b and 726c. Address generators 726a, 726b and 726c are our bit binary counters which are initialized and then utilized to count to an ¦ address which corresponds to the number of cells in each scan as determined in comparator 725. When the address thus ¦ generated is equal to the number of cells in a scan, the l process is repeated.
Each time comparator 725 detects the end of a scan, the output signal is coupled to scan counter 727.
¦ Scan counter 727 is utilized to keep track of the number of i scans stored, because, as will be explained below, the data ~ compression system of the present inventio~ operates with ~ twelve scans in temporary storage in scan memory.
I

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¦ Read address generators 728a and 728b are utilized to generate the addresses which will be utilized to read the scan data from ternporary storage in the scan memory. A
separate read address generator is necessary because as will be explalned herein, the scan data in temporary storage is read out of the scan memory in a different order than the order in which it was stored.
Multivibrator 729 is utilized to initiate the ~ address generators and read address generators at the 1 beginning of operation. Parallel access Shift register 730 ¦ and multivibrator 731 are utilized to develop various clocks and reset commands utilized to operate the data compression system of the present invention. Buffers 732 and 733 are ~utilized to buffer and isolate the ciocks and reset signals so generated.
~ Figures 7g and 7h, when positioned side hy side in the manner indicated in the figuresl form a schematic diagram of the scan memory previQusly discussed. Each of ~ the memory blocks depicted, 734a-734d, 735a-735d and 736a .
1 736d are implemented utilizing a 1024 bit random access l memory. Thus, each memory block may temporarily store one i complete scan through a document, recalling that a scan may consist of up to seven hundred and sixty-eight separate cells of line scanner 606 of Flgure 6. Further, the scan 1 memory formed by the combination of memory blocks 734a-734d, 735a 735d and 736a-736d may temporarily store twelve indiv-idual scans.

, , ",,, . , ' ", ,",,', ., - ''' ~Z:Z;~ 3~
Figures 7i and 7j, when positioned as indicated in tlle figures, form a scllematic diagram o~ the address multi-l plex circuitry oE the scan memory of the present invention.
¦¦ ~ddress multiplex circuitry is necessary because, , although the data obtained from line scanner 606 (Figure 6) i is obtained and written into temporaxy storage in the scan memory in a vertical format (with respect to the document image), experimentation has shown that maximum data com-l pression will occur with analysis of that data in a horizon-¦ tal ~ormat.
l As previously discussed, the scan memory formed by il memory blocks 734a-734d, 735a-735d and 736a-736d (Figures 7g and 7h) form temporary storage for twelve complete vertical l¦scans. The data within the scan memory is analyzed horizon-¦¦ tally in groups of four scans. Therefore, the twelve memory blocks are further broken down into three groups, two of , which are being read while the third group is being written li into.
i The two groups being read are referred to as the 1¦ current data and previous data. The previous data repre-1~ sents the previous four scans prior to the current four i scans read into the system and is maintained in temporary - ¦ storage to determine what, if any, relationship exists ¦ between that data and the current data. This examination is 1 necessary to detect possible redundancies which may be I removed and replacel wieh coded equivalent~.

!
I . .
,1 -36-~L22~ 33~ 1 The descrihed system of vertical writing and l horizontal re~ding requires address m~lltiplexing to insure I proper opera~ion. Consider the subgroup oE four memory blocks into which data is being written. A memory block is 1 enabled, an address is supplied from scan memory address l generator 726a-726c (Flgure 7e), and the address is incre-! mented until comparator 725 (~igure 7f) indicates the ad-l dress has reached the end of the number of cells in a scan.
!I Next the memory block enable signal is incremented, the l¦ address generators are initialized and the process is re-l¦ peated until four scans are written into the scan memory.
,I When a subgroup of the memory blocks is being jl read, an address is generated by read address generators l 728a and 728b (Figure 7e~ and the memory block enable signal j is incremented through a four count. Next, the address is incremented and the memory block enable signal is incre-me~ted through the four memory blocks in the subgroup.
Decoder 737 acts as a one of three decoder which I enables one of the three subgroups of the scan memory at a l~ time. A subgroup of memory is enabled utilizing address l multiplexers. The first subgroup utilizes address multi-¦ plexers 738a-738d. Each address multiplexer is a quad two line to one line multiplexer. Address multiplexer 738a is ¦ utilized to provide the chip enable signal (CE) which 'il determines which of the four memory blocks within the ; subgroup is enabled. Address multiplexers 738b-d are ¦ utilized to provide the address within tbe enabled memory Il . ' ' ' .
il1 . - ~ .

,1 -37-block, and the signal which determines whethex data is being read from or written to the selected address, ~ddres~; 1, multiplexers 739a-d and 740a-d operate identically with ~ respect to the second and third scan memory subgroups.
1 Decoder 741 is a dual one of four decoder which ~s utilized to provide the read and write enable signals which serve as the inputs to address multipIexers 738a,'739a and 740a. Multiplexex 742 is a dual four line to one line ', multiplexer which is utilized to select the output of a , 1 particular subgroup c)f the scan memory to be output as the current data, and the output of a second subgroup to be output as the previous scan data.
With reference now to Figure 7k, there is depicted I the shift registers which allow, examination of the scan data 1 temporarily stored in the ,scan memory~ Current scan data is ! shifted into the sixteen bit shift reg:Lster formed by eight ¦¦ bit shift registers 743a and 743b. Data from the previous ¦I scan is simultaneously shifted into the' sixteen bit shift !I register formed by eight bit shift registers 744a and 744b.
Ij In this manner, current data may be compared to previous ¦I data and redunaancies in current data may be examined in a ,I bit by bit manner, as the data shlfts through the shift ¦¦ registers.
,I Multivibrator 745 is utilized to enable scan ¦ memory address multiplexer 738a, 739a and 740a (Fi,gure 7i) after th completion of the First SCi:A.

.1 . , . ~ .

l -38-lj ~:2283~
. . ~, i Re~erring now to Figure 71, multivibrators 746 and 747 are utilized to develop the shift enable signals (SFTEN
and SFTEN) which are utilized throughout the syst~m to ¦ enable various shift clocks and reset signals. Multivi-1 brator 748 is utilized to ~evelop the duplicate enable signal (DUPENF) which is utilized during those periods when the scan data is duplicating previous values and the re-l dwldancy may be removed. Multivibrator 749 is utilized to ! generate the BUSY signal in response to the signal indi-¦¦cating the system is armed and that data is being clocked ¦into the syste~.
Four bit binary counter 750 is utilized as a time l¦out counter. After a signal is received indicating the end ¦lof scan data, counter 750 is utilized to provide the signal 1! which shuts down the system. Elip-flop 751 and multivi-¦lbrator 752 are utilized to provide additional clock signals ¦¦after the end of data has been detected, to ensure that data l¦within the system is completely processed prior to system ~ shutdown.
1, Figures 7m and 7n, when joined in the manner lindicated in the figures, form a schematic diagram of a jsection of the redundancy removal circuitry of the data Ijcompression system of the present invention.
¦I Experimentation in the field of video image data I~compression has proven that whil~ examining horizontal sections of four s~an cells, there exist certa_n precooinant 1~ ' ' '' ' '' .

Il . . , . ' .
,1 .

Il -39-. ~LZ2Z~31 repel:itive patterns. These pa~terns are referred to herein as "Q" codes, and t:he most co~unon three codes are: a black cell ollowed by three white cells (1000 in binary repre-¦ sentation); two black cells followed by two white cells ¦ (1100 in binary representation); and, three black cells ~ollowed by a single white cell (1110 in binary represen-tation). ~
In view of the above, it will prove beneficial to l examine the scan data to determine if a series of these Q
1 codes are present. To that end, current data present in l shift registers 743a and 743b (figure 7k) is coupled to Q
!i code logic array 753O Logic array 753 is a field program-mable logic array such as the 82S100, manufactured by l Signetics of Sunnyvale, California. Logic array 753 is 1 utilized to determine irst, whether or not one of the j aforementioned three Q codes is present in the Eirst four positions of the sixteen bit logic array, and second, how many repetitions o E that code are present. It will be apparent to those skilled in the art that up to four con-li secutive four bit Q codes may be present at a single time in i¦ logic array 753.
¦ The current data present in shift registers 743a and 743b is also simultaneously coupled to black/white logic l array 754. In a manner sim1lar to the opexation of logic ¦ array 753, logic array 754 examines the first bit present to determine whether it is black or white, and secondly how many consecutive blacks or whites follow the first bit.
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j ~22~3~ 1 ¦¦ In the pre~erred embodiment, logic aJ.ray3 753 and 754 are utllized to detect the state of the data coupled thereto and to ensure that the xedundancy present is at least eight bits in length. This requirement is a design choice; however, since the redundancy to be removed m~st be replaced with an identi~ying code and an indication of the length of the redundancy ~count3, eight bits seems to be a ¦
¦¦practical minimum length.
¦¦ The state of the data in logic array 753 and 754 ; lO ¦lis coupled ~o transparent latches 755 and 756 respectively.
The output of latches 755 and 756 are coupled to latches i 757a and 757b, each of said latches formed by one half of a single twenty pin latch cirCuit~ and to the address pins of j¦count memories 75B and 7-59. Count memories 758 and 759 are 111 utilized, in con~unction with four bit binary counters 760 l and 761, to disable transparent latches 755 and 756 for a - selected period of time. Disabling circuitry is necessary to avoid various proble~s present ~uring data shifting.
hose skilled in the art will appreciate that a Q code, as previously de~ined, loses its identity if shifted one bit.
'ITherefore, if four Q codes are detected in logic array 753, it will be necessary to disable latch 755 until sixteen bits l! have been clocked through, to determine i~ additional Q
jlcodes are present. To this end, the output of latch 7~5 ¦ will address a value in count memory 758. Counter 760 will disable latch 755 and continue to do so until the selected ~count in colnt memory 758 is acnieved.

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¦ Similarly the output o~ latch 756 will be utilized ¦to address a value in count memory 759 and counter 761 will disable latch 756 to allow the identified data to be shifted j out of logic array 754. A slight difEerence in operation is 1 utili2ed if logic array 754 contains data which indicates a series of black cells in the scan. In this case, the latch l will be disabled until the last three black cells in the I previous group have been shifted to the first three posi-¦ tions in logic array 754. At this point, the data will be 1 examined to determine whether or not the last three black I cells comprise the beginning of a Q code. This operation jlrepeats until the last black cell is shifted out.
Multivibrators 76Z and 763 are utilized to enable ! latches 757a and 757b. Each time a particular redundancy 1 has been finally coded and output by the data compression system, latches 757a and 757b are enabled to latch in the ¦outputs of latches 755 and 756.
Referring now to Figure 7O, two other possible 'states of scan data may be determined. First, in the event 1l that the stream of data examined by the data compression jsystem is not wholly black or white, or comprised o~ a group ¦of consecutive Q codes, it is still possible that redundancy ¦~exists in that data. The most easily detected redundancy ¦Iwill exist when the data from the current scan, while llvarying in no discernible pattern, may entirely duplicate the data from a previous sFar. One ~ch example may be an . " '~ ' l . '' '''',' j ,1 -42-L22Z~3 I .
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intricatq but repetitive border or edge desiyn on a check or other document.
Such cases are identif:ied using logic array 764.
l Logic array 764 can simultaneously examine eight bits o~
S current data and eight bits of previous data to determine whether or not the data is duplicative. In a manner similar to that explained above with respect to black or white data, the output of logic array 764 is coupled to transparen-t latch 765. The output of transparent latch 765 is coupled ¦ to count memory 766 and is utilized to address a value which is coupled to four bit binary counter 767.
Binary counter 767 is utilized to disable latch 765 while data is being shifted through logic array 764. In ! the disclosed embodiment, as a matter of design choice, if ,I the data changes from one code to another and the duplicate code was available at the beginning of the current code, the ¦ code will be changed to a duplicate code if the data being '¦ duplicated also changes'and duplicates for at least five . .
ji additional bits. ;
~! If the duplication of previous data does not duplicate for at least five additional bits of scan data, then the data compression system will code out the old code and change to the new code and begin to encode the new values of scan data.
, After a previous red~ndancy has been identified, I coded and o~tput from tbe data compression system of the ' !l ;

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j! ~2 2Z 83 ~present lnvention, 1stch 768 is enab1ed, latchiny in tne next type of redundanc~ to be coded.
Multivibrators 770 and 771 are utilized to latch in the duplicate data mode throughout the data compression ¦ system of the present invention and to continue the dupli-cate data mode beyond a change in state of data if the duplication continues for at least five additlonal bits f scan data. -l As a last resort, if a series of Q codes, black 1 cells, white cells or duplications are not present, the data ! compression system of the present invention will store actual data, without compression. To overcome such a deter-mination (referred to herein as "mapping" or a "map" func-~ tion) a minimal amount of redundancy is required before the lS ¦ data compression system will begin encoding data. As a I matter of design choice, the dlsclosed embodiments will i cease mapping and begin to encode data if at least ele~en black or white cells arè detected, at ~east three consecu-tive Q codes are detected, or any combination of codes which 11 exceeds eleven bits. Logic array 769 is the mapping termin-ation logic array and is utilized to examine the scan data i for the previously enumerated situations which will overcome the mapping function.
I Referring now to Figures 8a and 8b, which when - ¦ joined in the manner indicated in the figures, form a ¦ schematic diagram of the count and code out circultry of the ~ daea romp ssion system of the present in.ontiol.

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Logic gates 801a, 801b and 801c are utilized in conjunction with the logic gates assoclated therewith, to encode the ou~put oE latches 7S7a and 757b of Figure 7m~ and l couple that data to quad two input multiplex 803. It should ¦ be recalled that the data in registers 75/a and 757b repre-sent the code currently being utilized in the data com-I pression system.
Similarly, logic gates 802a, 802b and 802c are l utilized, in conjunction with the logic gates associated ¦ therewith, to encode the outputs of latches 755 and 756 of j Figure 7m. Latches 755 and 756 are the transparent latches utilized to hold the data which represents the next data to be utilized in the data compression system. Thus, when a l section of data is output by the system, the next data to be coded out is switched through multiplex 803.
Those skilled in the art will appreciate that in I addition to the type of redundancy being removed from the data stream, it will be necessary to include the length of ; j the redundancy in order to allow eventual reconstruction of the redundancy. To this end, counters 804, ~05 and 806 form ~a twelve bit binary counter. The counter thus formed pro-, vides inputs to the field programmable logic array 807 which ilcontrols the coded count counters. Again, as a matter of j~design choice, the data compression system of the present ¦¦ invention includes certain maximum data counts in each type of redundancy (see Table I). The selection of a particular j ~maxlmum count is Ysed upon requirements of the code selected . ' -' '.' .' l -45-~L2ZZ83~
.

¦ and the physical liklihood that certain redundancies occur ¦¦with greater length than other redundancies. The longest count acceptable in the disclosed embodiment of -the present invention is 4096 bits in either the white cell mode or the 1 duplicate mode. Each of the other modes has a lower maximum ! count, as indicated in Table I.
When the counter formed by four bit counters 804, l 805 and 806 reaches the maximum count of 4095, rollover ¦Imultivibrator 808 is set on the next clock, and the output llof multivibrator 808 is utilized to ensure various actions.
I¦ The lower maximum counts available for black cell !j mode or Q code mode make it advisable from a data compres-l¦sion viewpoint, to operate in duplicate mode or white cell i mode if possible. Mul-tivibrator 809 is utilized, to force , the data compression system into the duplicate mode, if a code length overflow condition ls reached by counters 804, 805 and 80G in other than the white cell mode (white cell ¦¦mode maximum count being equal to duplicate mode maximum llcount), and the duplicate mode is set. The forced duplicate Imode will also occur i a code change occurs (black to white, for example) and the duplicate mode could have been 'lutilized. Multivibrator 810 is utilized, for similar pur-- !,poses, to keep track of the cell count in a mapping mode of operation. If a map count occurs which is greater than five ¦I cells and less than eight, and the duplicate mode could have been utilized at the beginning of the count, the duplicate mode will be forced, rather than allow a map ~ode.

Referring now to khe figure formed by joining Figures ~c and ad in the manner indicate~ there is depicted a schematic diagram of additional circuitry including the duplicate mode circuitry oE the data compression system of -the present invention.
Multivibrator 811 is the circuit element utiliæed to keep the da-ta compression system in the mapping mode o~
operation until one of the aforementioned special map l termination conditions occurs. Multivibrator 812 is the j circuit element utilized to enable a change to duplicate i code when tlle maximum data count occurs for a redundancy ¦jtype other than white cell (white cell maximum count being ¦¦equal to duplicate cell maximum count).
: !I The group of logic gates labeled 813 and the ll inputs associated therewith are utilized to enable logic ¦ array 814 after a suffici~nt time period has elapsed to allow the previously identified data to be clocked through.
The output of logic gates 813 is then utilized to enable ll logic array 814 the decision logic array. Logic array 814 1! is utiliæed to determine whether or not the code present should be coded out.
Logic array 81$ is utilized to control four bit counters 816 817 and 818 which are utilized to generate ¦¦ the coded count of the section of dataD Coanter 819 is the l duplicate mode load counter and is utili~ed to count the number ot tlmes the dupli~ate counter has be-n loaded.
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Quad multipLexers 820, a21 and 822 are u~ilized to ou~put the duplicate mode cell coded count or the coded count o the number o~ cells in a black or white cell count, a Q code count or a mapping count, as selected by logic gate 823.
With reference now to the figure formed by joining I Figure 8e and 8f in the manner indicated, there is depicted buffers 824 and 825. Buffers 824 and 825 are first in-first I out (FIFO) buffers that are utilized to contxol the cell i count during a mapping function, to determine how many cells I are utilized during a particular mapping function.
I Multivibrator 826 is utilized to provide addi-tional ¦ bits to fiLl up a four bit word in the FIFO da-ta buffers in ¦lorder to permit transfer of the cells stored therein.!Output li control counters 828 and 829 are four bit counters which are ~utilized to count the number of cells output from the buffers during the mapping de of operation. Comparator 827 checks l! the output of buffers 824 and 825 against a reference signal lito determine if the maximum map count was coded. Comparator - 20 ',827 is then utilized to~prevent multivibrators 831 and 832 from flushing out the remaining data stored in the map data buffer, if the mappin~ funçtion has been coded out due to a ¦maximum COUllt. If the mapping function has been terminated due to other than a maximum count (a forced duplicate mode, or a code change) multivibratoxs 831 and 832 are utilized to flush out a single four bit byte in ~he data buffer to ~indicate tl end of a m-pping function data stream.
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Logic gates 833'and multiple multivibrator 834 are utilized to ~en~rate and latch out a terminal count at ~hc end of transmitted data. This artificial count is referred to as a terminal count and is uti.lized to allow completion of -the compxession of the final bits of data.
Referriny now to Figures 8g and 8h, when joined in l the manner indicated in the figures,. there is detected ¦ multivibrator 835, which is utilized to delay the data . I enterin.y buffer 836. Buffer 836 is a four by sixteen bit 1 FIFO buffer that is utilized to temporarily store data . ~ during a mapping function. Recalling that a mapping cell' I count of greater than five cells and less than elght cells , may result in a forced duplicate mode, if duplication is .
. possible, it should be apparent to those skilled in the art ¦~ that at least eight cells'in a mapping function mode must be i examined before a map code is possible. Thus, buffer 836 is utilized to provide temporary storage until such a decision I is made. Logic gate 838 is utilized to reset buffer 836 if Il a forced duplicate mode'occurs.
:. 20 ~1 In the event that eight mapping function mode ,I cells are encountered, and the forced'duplicate mode is not . I; utilized, multivibrator 839 is utilized to dump the data ¦¦ from buffer 836 into four by sixty-four buffer 837. Buffer I 837 is utilized as..a first ln-first out buffer which stores l the data utilized during a map mode of operation.. Multi .. ' ¦ vibrator'839 will'also cause the data in buffer 836 to dump ~ . , . , ,''.
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into buEfer 837 if the clata ter~ninates prior to eight bits !¦and is coded out as a map code., ,¦ Quad multivibrator 840 is utilized in conjunction with multivibrator 834 ~see Figure 8f) to provide addit,ional I delayed terminal,count signals in the manner explained above. Multivibrator 841 is the serial out clock enable I circuit and is utilized to enable the output o~ buffer 837 ; I when it is desired to 'output the map data.
l Multivibrator 842 is the master serial output ¦¦enable latch which enables the ~arious code, count and map - ' buffer outputs. Multivibrator 843 is the load output counter Illatch which is utilized to detect the fact that data is ilpresent at the various counter control buffers, such as tbuffers 824 and 825 (see Figure 8e) and to load the counters.
lS !!Multivibrator 844 is the transfer out parallel latch which is utilized to detect the terminal count signals which , lndicate that each counter has reached the end of the count ,idesired. After' all terminai counts are detected, the data ,in storage is transferred out in paralle'l, and latch 843 is, Ithen utilized to latch in new counter control data. Multi-~lvibrator 845 is utili~ed to disable he output of multivi~
; ~¦brator 844, at logic gate 846, after the data has been lltransferred out, to ensure that only one set of data is ¦Itransferred out.
1! Multivibrator 847 is utilized to generate the sérial output clock to the code buffex and multivibrator 848 is utilize to generate thG ser~al outFut clock to the count ,1 .
~ 50-;2S31 buffer. These two multivibrators are then respon~ible for serially outputting both the speciEic code and th~ count of cells within that code.
With referellce now to Figure 8i, there is depicted a schematic representation of the count bit shi~ter circuit-ry of the present invention. Referring again'to Table I~ it can be seen that the number o bits in a particular count may vary from a maximum of eleven bits to a minimum of two I bits. In order to accurately keep track of the count in a ¦ particular code, it is necessary to keep track of the most I significant bit of the count. The least significant bit of the count is fixed and relatively easy to obtain, however, the most significant bit must be ascertained.
Logic array 852 is utilized to determine how many 1 bits are present in a particular code, The inputs to logic array 852 include the particular code encountered and t~e ` number of times the count,has been loaded. Utilizing this input data, logic array!852 is coupled to bit shifters 853-' ' ¦¦ 858, to control the position of,the most significant bit of ~¦ the count. , ' Bit 'shifters 8S3-S58 are four bit shifters with three state outputs that shift each four bit word from ~ero ¦¦to three places. Thus, under the control of logic array ! 352, it is possible,to shift the most significant bi of the count to a desired position. In the preferred-embodiment, the most signific~nt bit of the output count is shifted into ~the first bit to be s~rlally outpu~.
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Referring now to Figurec; 8j and 8k, when joined in the mann~r indicated in the figur~s orm a schematic diagram of a section of the output circuitry of the data compression system of the present invention. Logic array 859 generates the control information for ,the code and count logic arrays.
¦ The outputs of logic array 859 are coupled to four by six-! teen bit buffers 860 and 861. The data thus stored in buffers 860 and 861 i~ utilized to control four bit counters l 862 and 863 respectively. Counters 862 and 863 are utilized ¦ to generate selected terminal count signals.
¦ Lo~ic arrays 864 and 865'are also coupled to the ¦ I code and load count signals and are utilized,to generate the , , actual code to be serially output ~see Table I). The actuall! code is loaded into buffers 866-869'for serial outputting.
; 15 ¦~Buffers 866-869 are all four by sixteen bit first in-first ,lout buffer memories. Buffers 866-869 give the system the capability of utilizing up to sixteen bits of code; however, ~lin the disclosed embodiment not all bits are utilized.
¦ Buffers 870-872 are the count bufers. The count ¦ data output from bit shifters 853-858 (Figure 8i) is coupled ,Ito buffers B70-872 to be serially output from the system.
! AS above, buffers 870-872 are four by sixteen bit first in-¦Ifirst out buffer memories. Logic gates 873 are utilized, in l conjunction with certain outputs of counter 863 to generate an additional terminal count signal.
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Referring now to Figura 81, there is depicted a schematic representation of the section o~ ~he data corn-pression system that is utilized to determine the size of the document image. Four bit counters 874 and 875 are ¦ utilized to divide the coded output of the data compression system by thirty-two. ~ach time counters 874 and 8;75 reach I thirty-two, the total in four bit counters 876-879 is I incremented. Thus, the data in counters 876-B79 represents ¦how many thirty-two bit words are present in each image.
¦¦ The outputs of counters 876-879 are coupled to ¦Iregisters 880 and 881 where the control device may access ¦Ithe data. Multivibrator 882 is utilized to store the count , at the end of an image. Multivibrator 882 is reset when I its contents are read. Multivibrator 883 is utilized to , initialize the counters by ~orcing the counters to a load ¦condition until receipt of a first data clock.
Ii Referring now to Figure 8m, there is depicted a schematic representation of the logic circuitry which allows ~a coded representation to be output from the data compres-20- ~Ision system. Loyic gate 884 will allow a code out whenever a ,¦code change is allowed (CNGAL) or the end o~ data has been reached. Logic gate 885 will allow a code out during a map l¦function if the code is changed to a duplicate mode.
¦¦ Logic gate 886 will allow a code out if one of ¦ these special map mode termination sequences is encountered, i as previously discussed. Logic gate 887 is the logic gate ~ which all~w~ black cell co~es to be ternina~-d early to ,,,,",....
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begin Q code mode oE operation, as cliscussed herein. In conjuncl:ion with logic gate 887, multivibrator B88 is utilized to ensure that greater than ~even black cells have been detected prior to allowing an early termination of black cell mode of operation to code Q codes~
Multivibrator 889 is utilized to detect the over-flow condition which will xesult when the bit counters exceed the maximum count for a particular mode of operation.
In such event, the code in question is output and the system begins counting anew.
Each of the previously discussed code out signals are applied to multivibra~-or 890l which is utilized to generate the parallel load signal which is utilized to load out the current code and count. Multivibrator 891 is trig-gered along with multivibrator 890 and is utilized to select certain multiplexers which allow a look ahead function for the various logic arrays. Multivibrator 892 is utilized to genexate a buffer overflow error signai if the data compres-sion system of the present invention attempts to load additional data into the~output buffers while these buffers are full.
Referring now to Figure 8n, there is depicted the coded counters for the data compression system of the pres-, ent invention. Counter 893 is the load counter which is utilized to determine how many times counters 894a-894c have been loaded. Counters 894a-894c are utilized to generate the coded ouot of the number of cells in a current black, .. .. ..
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.1 , ~ white, Q code or mapping mode of operation. Referriny I fin~lly to.Figure 80, logic gat.e 895 and the logic gates associated therewith are utilized to generate an internal . ¦ reglster full signal in the event that any one of the first 1 in-first out buffers is full. The internal register full signal is utilized to gçnerate an error signal if additional data is loaded into a full register.
Multivibrators 896 and 897a-897d are utilized to . generate a four phase clock slgnal for utilization in the operation of the data compression sys~em. Multivibrator 896 I ~ is utilized to double the GX/2 clock from multivibrators 702 . , and 733 (Figure 7a) from 15.25 megahertz back up to 30.5 I ¦ megahertz. In turn, multivibrators 897a-897d are then j~utilized to divlde the 30.5 megahertz clock down into a.four I phase clock in a manner well known in the ar~. . .

. MICROFILM SYSTEM
¦ The document processor of the present invention .
llincorporates a microfilm recorder 238 (See Figure 2) which . Il allows selecti~e microfilming of documents during the same ¦pass in which several.other processing functions occur.

t Thus, a, particular document may be read, encoded, endorsed, ~ image captured, sorted and filmed during a single pass - . j through the document processor.
1 The microfilm system utilized within the present ¦ invention is based upon.the SMR-200B Scannermate microfilm.
recorder, m~n~fac.ured b~ the Terminal Data Corporation of ,. ~ . .

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Woodland Hills, California. It will be appreciated by those ordinarily skilled in the art that other microfilm recorders will find use in the present system, as a matter o design choice.
5 ¦ Microfilm recorder 238 films both sides of ~
document, at a speed of up to one hundred inches per second.
The film motion is synchronized with the document;transport and a document detector f stopping between documents so that interimage spacing is independent of other processing, thereby ensuring maximum film usage and format continuity.
i Microfilm recorder 238, in a preferred embodiment-, - ¦ also records a program controlled sequence number and an image count mark (commonly known as a "blip") above each l recorded image. Approximately 14,000 documents may be 1 microfiLmed on one hundred feet of 16mm. film, assuming an average document length of seven inches. The sequence ! numbers and image count marks allow rapid addressing and accessing of individual documents. The microfilmed copies l of the do~uments being processed may provide either a backup ¦ system for the digital image system, or may be utilized as l hard copy archlval storage for the documents in question.
l DATA EXPANSION SYSTEM
Referring now to Figures 9a and 9b, and the joint figure formed thereby, there is depicted a block diagram of ¦ the major components o~ the data expansion system of the pFesent in~ention~ , , , " ~ "
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l X bus receiver 901 is utilized to receive data : I from tl-e specific X bus channel seLec~ed by X bus select 902. ~rhe data thus received is coupled to serial in-par-allel out register 903, and then latched.into latch 904 and parallel in-serial out register 905. The additional latch ! and register circuitry is required to allow the receipt of IluP to eight more bits of data after the input register of ¦¦the data expansion system is ~ull. Logic gates 906 and 907 ¦are coupled to latch 904 and register 905 and are utilized ~ in conjunction with X bus select 908 and X bus transmittex 909 to stop data flow during periods when the aforementioned , latch and register are full.
¦ The data in register 905 is coupled to a sixteen bit, serial in-parallel out working register 910. The I;number of bits shifted into register 910 is controlled by .
shift counter 911. Shift counter 911 operates based upon ~he content of sixteen bit adder 912.. The initial count in . sixteen bit adder 912 is applied to ROM address generator ¦914 which is utilized to address data within code ROM 915.
'I Code ROM 915 outputs~additional data which is applied to sixteen ~it adder 9I2. The new content of ¦ sixteen blt adder 912 is utilized to control shift counter . 911, and thus control the number of bits shifted int~
. i working register 910.
¦ Examining the contents o~ Table I, it can be seen that in the discl~sed embodiment, the minimum number of bits in a code is three. Therefore, it should be apparent to . ' , ' . .
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those skilled in the artr that lf adder 912 is e~pty, that condition should cause ROM generator 914 to select a code within code ROM 915 that will cause three bits to be shifted . ¦ into recJlster 910.
1 As the contents o adder 912 are recognized as an identifiable code, code ROM 915 will generate data which I will allow the correct number of bits to be clocked into register 910, and provide the bias necessary for the correct l count. By way of example/ when the system recognizes the ¦ 1110111 code, code ROM 915 will provide data to adder 912 to allow eleven additional bits of data to enter register 910.
(see Table I, White Cell Mode) As eleven bits of count are i¦coupled to adder 912, a bias of 1024 is coupled into adder ¦l912 to be summed with the eleven bit number. The bias value ¦¦ may be coupled directly to adder 912, or, should the value j¦be higher than eight bits, by means of high bias latch 916.
i! Code ROM 915 also generates a function code based . upon the translation of~the code initially entered into . , adder 912. The function code is applied to function latch 917, where it is applied to data multiple~ 918. Data multi-.lplex 918 is utilized to select a voltage potential (black cells in this embodiment), a ground poten~ial ~white cells) a duplicate function pin, a mapping function pin, or Q code .
! register 919. Q code register 919 is a recirculating ¦ register which contains each of the three Q codes previously . discussed, and may be accessed repeatedly to provide a stream of repetitive Q codes.
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During a mapping function, no data compression was possible and the actual'data has been stored. When data multiplex 918 selects the mapping ~unction pln, data multi-' I plex 918 is coupled to the input of register 910, and re-ceives actual data received from the X bus. During a'dup-licate function data multiplex 918 is coupled to the output of duplicate buffer 920, the operation of which,will be ex-plained below.
l The ou~put of data multiplex 918, representing ¦ expanded image data, is coupled through serial in-parallel l out latch 925 and 926 onto a four bit wide data bus. The ¦limage data is then coupled simultaneously to four scan buffers 923 and 924, and four scan dupe buffer 920. , Up to ¦~eight complete scans of data are selectively stored in ¦¦buffers 923 and 924, as sequenced by the operation of multi-¦¦plexes 927 and 928. Four scan dupe buffer 920 stores the j¦most current four previous scans of data and thus permits duplication. The output'of buffer 920 is coupled back to ' data multiplex 918 by means of register 922.
, The ~ata contained in buffers'923 and 924 may now be selectively accessed by multiplex 930 to provide'at least j! two formats of data. The data stored in buffers 923 and 9?4 - ¦¦may be output in the "scan" mode, that is, in the manner in ¦ which the data was captured by the digital scanning circuitry.
¦ This method of data output is'obtained by accessing buffer 923 and reading out an e,ntire scan, then incrementing the ~scan numb~].

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¦¦ In other applications, it is more advantageous to output ima~e data in the "ladder" mode.. In the ladder mode, i data is obtained from the first acldress in each scan and the scan number is then incremented. After the first cell or address has been read out of each o the four scans in buffer 923, buffer 924 is accessed in a similar manner.
Thus, the ladder mode provides eight bits o data, each bit ¦¦from a different scan of the digital scanning circuikry.
!¦The next eight bits provided are from the next address in I each scan. The process of restoring eight scans of data, at one cell per scan resembles the structure of a ladder, and therefore is described as the "ladder" mode.
As a final variation and possible image data ~Imanipulation, latches 932 and 933 may be utilized to rev~rse llthe order o~ each byte o~ eight bits. This technique may be !, utilized to provide mirror imaging. In systems which utilized two digital cameras to capture the image of each jlside of a document, onç~side will invàriably be mirrored ; Ifrom the other. Latches 932 and 933 are utilized to correct Ithe situation when restoring the mirrored image.
,j The data out of latches 932 and 933 is coupled ¦Ithrough buffer 936 to output control circuitry 937. Output ¦control circuitry 937 is utilized to select an appropriate l! x bus channel and transmit the data. Output control circuitry 1l g37 is also utilized to control the receipt of signals from ¦ the X bus to indicate the avallability of a particular ¦ channel.
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i VIDEO T~RMINAL SUBSYSTEM
Referring now to Figure 10, there i~ depicted a l more detailed block diagram o~ video terminal subsystem 136 ¦¦(see Figure lb). Video terminal. subsystem 136 i5 utilized, ~ in the document processing system of the present invention, to provide v.ideo images of selected documents along with alphanumeric information. Video terminal subsystem 136 l provides the selected video images by means of digital image ! data captured by-the digital camera in one embodiment and 1 is utilized to allow processing of data present on documents ¦~which is not in machine readable format. For example, video ¦images may be utilized to-examine signatures, to compare two '~signatures or.to examine handwritten amount fields on docu--llments such as checks. Video terminal subsystem 136 will l¦ also find broad application in other areas wherein it is '¦desired to present a video image generated by digital data, with or without the additional of alphanumeric charactersO
;¦Digital facsimile trans~ission, d:igi~al document storage and ¦Iword processing are a few of the many uses such a system may 1! find.
I Video image data is transferred to video terminal subsystem 136 by means of X bus distributor 142. Control or ~program information is transferred to video terminal sub-!~ system 136 via synchronous data link control slave 138 and i¦ is mapped by way of direct memory access 1002 into micro-¦ processor 1004 and memory 1006. In a prefer~ed embodiment of l . ,' ,'', '' I . ' ' ' ,! ` .
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the present invention, microprocessor 1004 is a high level device capable oE addressing external memory 1006 for pro-gram instructions.
The video image data transferred via X bus dis-tributor 142 is coupled to an appropriate video formatter.
In the embodiment disclosed, up to four video formatters are utilized with each video terminal subsystem; however, additional subsystems may be utilized and/ox the number of termin~1 controllers may be modified as a matter of design choice. Each video ~ormatter contains a substantial amount of memory and is capable of storing sufficient digital data to support an entire image for the appropriate video terminal.
The detailed description of the circuitry and capability of the video formatters will be explained in greater depth with reference to Figures Ila-llo and 12a-12O. Video formatters 1008, 1010, 1012 and 1014 each correspond to a single video terminal, namely, vide~ terminals 1018, 1020, 1022 and 1024.
Each video te~minal is coupled to an appropriate video ~ormatter and keyboard by means of dual termi~al controller I/O de~ices 1016 and 1017 and terminal I/O de-vices lQl9, 1021, 1023 and 1025. Dual term1nal ~ontroller I/O devices 1016 and 1017 each differentially drive video to two terminals and provide differential receivers and serial to parallel conversion for inputs from two keyboards.
Terminal I/O devices 1019, 1021, 1023 and 1025 each receive differentially driven video for one ~erminal and provide ' ! , .' .' ' ' ., .,',, !l ,-` , Il ~2~a3l 1 parallel to serial conversion and differential drive for j data from one terminal keyboard to the appropriate dual terminAl controller I/0 port.

l With reference now to Figures lla-llo and 12a-12q, ,1 there is depicted a schematic diagram of the circuit compon-¦ ents of the video foxmatter,o,f the present invention. The ~ I video formatter of the present inven,tion is utilized to 1 provide image data and control to the video terminals of video ter~inal subsystem 136 and image data to the laser printer of laser printer subsystem 124. In alternate em-¦bodiments, the video formatter of the present invention will !Ifind wide application in various areas wherein images are I!required to be stored or manipulated in digital formatO
¦Applications such as digi,tal facsimile transmission/reception and word processing e~uipment are but a few of the many ' ¦-applications such a device will find.
Referring now particularly to Figures'lla and 11b, ,Iwhich, when joined in the manner indicated in'the figures, depict a schematic diagram of the device control registers I and memory address generation circuitry of the video for- ¦
¦ matter of the present invention. Uulti~ibrator 1101 is ! utilized to provide a power up master clear signal to ¦1 initialize the video formatter. Control register 1102 is utilized t~ receive control signals'from an appropriately !¦ programmed external control,device. The outputs of control ! .

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register 1102 are coupled to the loyic gates associated ¦¦therewith and are utilized to generate various internal ¦Icontrol signals. The control signals thus generated are I utilized throughout the system to ready the bus, select a j bank of internal memory for access by the control device, determine in what sequence,data will be transferred and.to , ! generate an interlace synchronized si~nal for image display.
. ¦ Buffer 1103 's the device identification buffer - ¦~and is utilized by the external control device to determine ' ;
¦!what type of device is coupled to the bus. Similarly, l¦buffer 1104 is utilized by the control device to test the I status of the video formatter during and before operation.
In the discussion of the video subsystem it was . , stated that the video formatter could subdivide the display , into up to nine separate display zones. Multivibrators 1105 ! throuyh 1108 are utilized to address these zones. Multi-vibrators 1105'and 1106 form the band counter, which is ~ utilized to determine a~horizontal band across.the display.
- 1I Multivibrators 1107 and 1108 form .the zone counters which il are utilized to det,ermine the address of the section within a particular band. Those s~illed in the art will recognize I that by utili~ing two bit binary numbers to characterize . I both the band,and zone address the system wii'l have the : i capability of defining up to sixteen separate æones. In- .
1, deed, although only nine zones are visible.in the disclosed I embodiment, the remaining seven zones are utilized for Il -64-Il .
horizontal and vertic~l retrace. In alternate embodiments, utilizing laser printers or other non-display d~vicefi, all sixteen zones may be utilized to provide visihle image.
Quad multivibrator 1109 is utilized simply to 1 provide a shift delay in order to coordinate with a video attribute circuit which will be discussed below.
Octal transceiver 1110 is utilized to couple data , to and from the internal memory bus and inverter buffer 1111 ! acts as a bus receiver to the internal control memory of the ! video formatter.
One of eight decoder lll2 is utilized to select a particular integrated circuit memory chip in the internal control memory and buffer 1113 is utilized to couple the I appropriate memory address to the seiected integrated cir-i, cuit control memory chip.
¦! Referring now to the joint figure formed by Fig-¦¦ ures llc and lld there is depicted a schematic representa-tion of the main timing circuitry and display memoxy timing Il circuitry of the video formatter of the present invention.
ll The main timing signal is generated by crystal !1 oscillator 1114 which provides an extremely stable 30~5 ~~ megahertz clock signal. The main clock signal is then di-¦~ vided by two utilizing multivibrator 1115. Serial in-I parallel out register 1116 lS utilized to pxovide the '¦ individual bit timing signal~ Register 1116 is operated in ! the manner of a counter, propagating a pulse through the register.

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The video ~ormatter o~ the present invention may be utilized to supply formatted vide~ to a display terminal or other device such as a laser printer. In those appli~
¦ cations in which it is desired to supply video to a remote ¦ device, it will'be necessar~ to provide the image data over l a bus, such as the aforementioned X bus. In such applica~
,! tions, it is imperative that the data'transmission begin at l, a known point, such as the upper left corner of the image in ¦ the disclosed embodiment. To that end, multivibrators 1117, ¦ and 1118 are utilized to,ensure data transmission begins at - the appropriate point. Multivibrator 1117 is utilized to enable the transmit pause as the appropriate portion of the , data approaches. Multivibrator 1118 is then utilized to l establish the synchronization of datà transmission at that I point. , ¦ Similarly, multivibrators 1119 and 1120 are util-ized to temporarily pause during transmission of image data - !¦ if the image memory,must be re~reshed or the device receiv l¦ing,the image data is not ready to receive additional data.
IlMultivibrator 1119 is utilized to'enable the clock paus,e ¦which will eventually-stop transmission of the image data.
ultivibrator 1120 then synchronizes the paused data trans-mission with fetches of data from image memory.
' ! Multivibrator 1121 is the memory timing multi-! vibrator and generates the timing signals utilized to re-¦¦trieve data from the image memory to be displayed or trans-~ mitted to a remote device. Multibrator 1122 is a slightly l , - ' ', . 1. .
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Il -66-. ~ ~22;Z ~331 ¦ Easter reacting multivibrator wh1ch i5 ut.ilized to signal ¦ the end o a byte o~ image data to the video display con-troller circuit, thus triggering the reading and displaying . ¦ of that byte of data. ~ultivibrator 1123 is the address ' 1 advance vibrator, which is utilized to load or increment the address counters which are utilized bo access image data.
¦ Referring~now to Figures lle, llf and llg, which, when joined in the manner indicated in the figures, form a ~
. schematic diagram of the,video screen format timing circuitry of the video formatter o the,prese~t invention. The circuitry thus depicted is that circuitry which allows the definition of the discrete display areas previously dis-i cussed. .Each of the display areas or zones is defined by an l operator in terms of'certain parameters. These parameters ~¦ include the zone width and height. The zone height is . I¦ defined by an arbitrary dimension called ~rows~ and each ¦¦ "row" is further defined as a particular.number of scans by !¦ the control device~' ~
!¦ Recalling that,although nine discrete display !¦ areas are possible in the disclosed embodiment, an addi-tional seven areas are also defined and are utilized for horizontal and vertical retrace in the video terminal appli-¦ cation. The data defining these 16 zones is stored in ll counter control memories.which serve to control.associated ¦ counters. Each of the counter control memories is comprised .
o~ a sixty-four bit random access'memory, organized into . .
sixteen four bit,words.
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Thus, counter control memories 1124 and 1125 are loacled with data specify~ng the number o~ scans o~ the I display system per row of height. In actual practice, the ¦ data loaded into counter control memories 1124 and 1125 ¦ represents the two~s complement of the desired number. The two' 5 COmplenlent iS utilized to permit simplified operation of four bit counters 1126 and 1127, which are loaded with ¦the two's complement number and allowed to count to a carry l condition.
1 In similar fashion, counter control memories 1128 and 1129 are loaded with data speci~ying the zone height in rows, and serve to control four blt counters 1130 and 1131.
Additionally, counter control memories 1132 and 1133 are l loaded with data specifying the width of the zone and serve 1 to control four bit counters 1134 and 1135. Those skilled in the art will appreciate that the sixteen four bit words stored in each counter control memory will serve to define sixteen separate zones.
~ Multivibrator 1136 is utilized to keep track of ' whether the current frame is odd or even in number, to permit control o~ the interlace circuitry utilized to in-crease image resolution. Four bit counter 1137 is utilized , in conjunction with the video display controller circuitry ,when alphanumeric characters are being generated. A par-ticular code specifying a selec~ed alphanumeric character is ¦ utilized to enable the video display controller circuitry to geDerate thl se1ected ch~racter: however, it is still ' ' . - .
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necessary to keep track of what scan through the display device the system is currently displaying. Individual character~, ln the disclosed embodiment o~ th~ present.
invention, are typically twelve scans ill hei~ht and the image generated to perEorm a particular character will vary with each scan. Four bit counter 1137 is thus utilized to count the number of ~cans during character generation.
Those skilled in the art will appreciate this as being standard dot-matrix character generation.
Multivibrators 1138 and 1139 are utilized to cause the initial loadlng of counters 1126, 1127, 1130, 1131, 1134, 1135 and 1137 from their respective control ¦ memories, during startup. Once operating, the aforemen-tioned counters are reloaded during each carry condition, however, initially this load must be forced as no carry existq. Multivibrator 1140 is utilized during alphanumeric character generation to ensure that an address bump by delta (explained below) does not occur until after twelve scans are complete, thus ensuring continuity o~ alphanumeric characters. Multivibrator 1141 is utili2ed to enable the address control memories during the first scan in each band of the display. Multivibrators 1142 and 1143 are coupled to the carry outputs of counters 1134 and 1135 and are utilized I to generate various zone width carry signals ~zwCRy) for utilizatio throughouc the video ormatter.

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3~1 1 Loyic gatLs 11~4a-1144d are coupled to the outputs o~ zone width counter5 1134 and 1135 and the mode select l signal ancl are ~tilized to generate wait signals to a con-¦ trol device.
S Referring now Lo Figures llh and lli, and the joint figure formed thereby, there is depicted the display address circuitry of the ~ideo formatter of the present invention.
¦ Having previously defined the-parameters of each ;
¦ of the sixteen zones ~nine of which are display zones and !l seven of which are utilized for retrace signals) in terms of !Izone width and zone height in the arbitrary dimension of ¦¦"rows" and the number o~ scans through the display per l¦"row," it is ncw necessary to provide two additional pa-~ llrameters to operate the video formatter in ths manner i¦ descrlbed.
l First, it is necessary to define a starting I I address within the imag~ memory to determine what section of l¦the image will be contained within a selected zone. Sec-11 ondly, it is likely that the zone width may n~t be suf-¦ficently wide to encompass the entire image, and therefore lisimple unitary address incrementing will not suffice. As ¦Ithe end of the zone width is reached, the address of the ¦ next byte of image data displayed must be determined by j incrementing with a selected number, which is dependent upon the width of the entire image. This selected number is re ferred o variousl, } eFein ~s the "delta ' o r "bu~p "

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increment. The bump in~rement is ~alculated by exarnining l the width of the image and determining what number must be ! added to the starting address to arrive at the start o the ¦ nex-t scan through that zone.
The starting address of each of the zones within the display may be stored withln control memories 1145-1149 I Control memories 1145-1149 are also sixty-four bit random I access memories, organized into sixteen four bit w~rds. As I a matter oE design choice, the address of image data stored 1 within image memories in the video formatter of the present invention typically contains seventeen bits. Thus, control memories 1145-1149 are capable of storing the seventeen bit ~starting address of each of the sixteen display zones as written into the control memories by a control device.
l¦ Control memories 1150-1152 are utilized in a ¦similar manner to receive and store the "delta" or "bump"
¦number by which the address of the next byte of image to be displayed is determined.l The starting address of each scan !Ithrough the zone is incremented ~y the bump increment to ¦addres,s the first bit of image necessary for the next scan through a selected zone. Quad two lnput multiplexers 1153-1155 are utilized to shift the "deIta" number and thereby l~multiply it by two. This shifting is necessary du~ing ¦linterlace in the non alphanumeric ~image) mode. Interlace Ijis utilized to increase resolution of the image~ and lS
accomplished by skipping a line of the image,and then ~utilizing the skipped image d-ta durlng the next complete '~ ' ' , ' ' .

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frame of tlle image. In order to skip a line of i~age data, the increment num~er must be t:wice the normal number to ¦ arrive at the address of the beyinning of the scan following the next scan.
¦ Having deined each zone by size and startingaddress within the image memory, and by knowing the;incre-' ment or addre,ss necessary to address the first bit'in the next scan through the zone, it is possible to display a variable window within the display which may be easily l scrolled in either axis (by incrementing the ~tarting ad-dress) or enlarged (b~ changing zone di-mensions) and may be ! utilized to visually display 'a selected portion of an image.
Further, as.will be explained below, certain zones may be ¦ dedicated to alphanumeric characters indicative o~ operating 1 parameters, prompting cues or other pertinent da~a.
Referring now to the joint figure formed by . Figures llj and llk and to Figure 111, there is depicted a . schematic diagram of the display address generation cir-¦ cuitry of the present inventionO
¦ . As discussed above, during operation o~ dis~lay i devices, as the beginning of a zone occurs, ~he previous ; I starting address must be incremented by a value.equal to that of the width of the image to ensure that appropriate , ! data is available during the next.scan through a zone (or by . twice the width of the.image iE image interlace i~ desixed).
Since this increment must take placç at the beginnin~ of., . each scan througb a zone, i.t iS co~veniont Lo co4duct such ." ''' '.
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Ij ~2;~Z83~ j ¦an incrementation at each scan, including the ~irst scan.
Since the increment would then be added to the starting address for eac}l zone, a compensation o~fset to each start-ing address is necessary.
The aforementioned compensated starting address is stored as previously discussed, in control memories 1145-114~ and is coupled to the inputs of four bit full adders I I 1156-1160. Also coupled to adders 1156-1160 are the outputs of multiplexers 1153-1155, representing the "delta" incre-I ment. Thus, adders 1156-1160 add the delta incxement to the ¦compensated starting address and coupla the sum to four bit I by four bit registers 1161-1165. The data thus stored represents the actual starting address of lmage data to be displayed in each zone.
i ~he outputs of registers 1161-1165 are coupled to ~ I four bit up counters 1166-1170. Counters 1166-1170 are four I !Ibit counters with three state outputs which are utilized to ¦increment the address data. The initial data clocked into ¦¦counters 1166-1170 is immediately clocked out onto the bus 11 and around to adders 1156-1160 to be incremented b~ the ,¦delta increment again. As the new starting address (for the next sc~n) is coupled into registers 1161-1165, counters 1166-1170 begin unitary incrementation of the previous staxting address~ It is thereEore possible, with the de-picted circuitry, to generate a starting address, increment that address until the zone boundary is reached, add a delta jinc~ement to :le previous tarting adlress to obtain the .,. ' ' '~ ' '. ' .., ', . .

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I next st~rt.ing addres's, and begin incrementing again when the ~one is next entered. Also depicted in Figure llk are buffers 1171 and 1172 which are utilized to couple the . control device into the internal bus.
Referri.ng now to the joint figure form0d by Figures llm, lln and llo, there is depicted a schematic diagram of the video generation and video display controller ¦ circuitry of the video.formatter.of the present invention.
. I Central to the video generation'and video attri-ln j bute circuitry is video generator 1173. Video generator l 1173 is comprised of, in the illustrated embodiment, an SMC

I 8002 video display controller manufactured by the SMC Micro-jlsystems corporation of Hauppauge, New ~orkt and contains a ! mask programmable, on chip, one h~mdred twenty-eight char~
¦ acter generator which utilizes a seven by eleven dot matrix block. Video generator 1173 also.includes attribute loyic , I including reverse video, character blank, character blink, ; . ¦ underline and strike-through.' Additionally, video generator : j 1173 has ~our cursor modes including.underline,,blinkingl und~rline, reverse,video and.blinking re~erse Yideo.
jl Attribute control signals are coupled to video llgenerator 1173 by means.of multiplexers 1174 and 1175.
, !¦Multiplexers.1174 an~ 1175 receive their inputs from either . ¦attribute latch 1176 or from the data bus. If a global i attribute is selectedt the correct attribute code is'written i into attribute control memories 1177 and,'ll78 by the control ~ ~device. ~.ttri~ute contro; memories 1l77 and 1178 are 1~ ' ' '' " ' ' '' ' ' .
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¦¦sixty-four bit random access memories and are utilized to store the attribute codes for each of the display zones.
! During field attribute operation (available only in the ~ alphanumeric mode), selected data from the data bus is 1 utilized to generate specific aktributes ~or selected portions (fields) of the display zone, rather than the entire zone as in global attribute operations. The selected field attribute data is applied to video generator 1173 by l means of multiplexers 1174 and 1175. Additional data from Io I the data bus is applied to pins A0~A6 of video generator 1173 and is utillzed to select a specific character from the character generator.
Logic gates 1179 and 1180, and the logic gates ll associated therewith, are utilized as a gating function for 1 the attribute capability. Logic gate 1180 is utilized to enable multiplexers 1174 and 1175 and the output of logic gate 1179 is applied to the attribute enable pin (ATTBE) of video generator 1173, thus controlling the generatlon of I video attributes. - -: 20 ll Retriggerable single shot multi~ibrato~s 1181, 1182 and 1183 are utilized in conjunction with four bit ,¦counter 118~ to time and generate horizontal and vertical ¦sync pulses. Multivibrator 1181 triggers for approximately 112.5 microseconds ater the beginning of horizontal retxa~e l!~ provide what is commonly referred to as the "front porch"
¦lof the horizontal retrace pulse. One output of multivibra-tor 1181 s utilizc ~o triSger mult1vibrator l182 wbich , Il -75-I ~ 2;~3~L
. ll provides a f.ive microseconcl horizontal sync, the remaining period o~ horlzontal retrace is the "back porch".
Multivibrator 1183 is utilized to provide inter-. lace holdoff of the vertical sync pulse. Vertical sync is 1.
delayed for approximately one-half of the horizontal sweep time to cause interlace and thereby increase image resol-ut.ion. Four bit counter llS4 is the~ utilized to generate the vertical sync pulse and the "~ront porch".and "back . porch" periods. . .
Multiv.ibratoxs 1185 and 1186 are ~tilized to provide a delay beEore the application of horizontal retrace blanking to compensate for delay encounter~d due to pipe-. . lined internal operation during character generation by . video generator 1173. Interface 1187 is provided to inter-lS connect the video formatter of the present invention to a : . video terminal interface for use in a video subsystem.Referring now to Figure 12a, there is depicted a schematic diagram of the cursor control circuitry of the I video formatter.of the present invention. Memory locations . 20 1 within the i~age memory of the vide~ formatter of the present invention are, as a matter of design choice, characterized by seventeen bit addresses. Since a typic.al microprocessor ¦ type control device utilizes an eight bit bus, three sepa-r~te write commands must be generated to load in seventeen bits. The cursor address is loaded into multivibrator 1201 .
.and eight bit registers 1204 and 120S. The additional .
. circuitry depicted is coupled to the video address bus and . ' . ' ,' ~ L~ ~

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i ! is utilized to compare the cursor address with each video address and generate the cursor signal when the correct . address is reached. .
Logic gate 1207 is utilized to compare one bit of cursor address with one bit of video address, and to enable eight bit comparators 1202 and 1203. If the comparator . I circuitry indicates a match, and the video display terminal I is not in the image mode (no cursor being utilized during ! image mode) then logic gate 1206 is utili~ed to generate the ¦ cursor signal.
. With reference now to Figures 12b and 12c, and the joint ~igure formed thereby, there is depicted a schematic diagram of the intra device addressing circuitry and run ' length counters of the video formatter of the present inven-! tion. As discussed with respect to the data compression system, it is possible to have up to sixteen separate ad-l dressable registers per system which may be directly ad-I dressed by a control device.
ll The address of a selected register is coupled from 'l a microprocessor type control device through buffers 1208 ~¦ and 1209, ~hile various control signals are coupled through ! bufer 1210. Wire strap option 1~11 is utilized to speci-¦ fically identify a particular video formatter, and the . ~I register address is applied to field programmable logic l arrays 1212 and 1213, w~ere the actual address data is decoded a~d utilized 'o Access dez~red reyister3.

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Also depicted in Fiyure 12c are the run length counters and controllers. Recalling that the video image data being generated by the data expansion circuitry may be generated in either a ladder or scan mode, it is necessary to keep track of the length of each "run" of data through the image in oxder to accurately reconstruct an original image as the data is loaded into display memory~ ' As in previous' similar circuits, the run length is loaded into counter control registërs 1214 and 1215, in two's complement form. The contents of registers 1214 and 1215 are then loaded into four bit counters 1216-1219, and counters 1216-1219 are incremented until they reach a carry condition, thus indicating the end of a run of data.
Referring now to the joint'figures formed by joining Figures 12d and 12e and by joining'Figures 12 and 12g, there `is depicted the address generation circuitry whereby image data coupled to the video formatter "is stored in image memory within the vide'o formatter. Recalling the discussion of ladder format versus scan format for image data, those skilled in the art will appreciate that cohexent storag,e o~ image data within the image memory will require that each successive byte of image data, while in the ladder ¦ format, will be stored at an address in memory which is l either greater than or less than the previous address by a value equal to the width of the image. As counters 1216-12'19 enter the carry condition, indicating the end of a run, the next byte of image data will be-stored at an address , .. . ...
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which is eit~ler greater than or less than the previous I starting address by one. Conversely, while in the scan ~ format, image data addresses will increment ox decrement by ! one, until a carry condition in counters 1216-1219 indicates the end of a run, at which time the next byte of data will be stored at an address greater tha~ or less than the pre-, vious starting address by a value equal to the width of the image. Tlle determination in either case of whether to I increment or decrement the address of the image data is ;
1 determined by the point in a document image at which the data begins.
Data bus transceiver 1220 is utilized to couple ¦ the value of the width of the image to width registers 1221 , and 1222. The two most signifi~ant bits in register 1222 ! (pins 8Q and 7Q) are utilized for the sign bits for the ¦ address increments. The outputs of width registers 1121 and 1222 are coupled to multiplexers 1223-1226. Mul~iplexers ¦ 1223-1226 are utilized to outp~t either a plus or a minus !l one, or a plus or minus width value, as determined by im~ge 11 orientation.
¦ The output of mul~iplexers 1123-1126 is then I coupled to full adders 1227a-1227f (adders 1227e and 1227f are depicted in Figure 12g) where, the address increment or I¦ decrement is added to the previous address, or preYious ¦ starting address to determine the storage address for the next byte o~ ~mage d~ta. The /esul- of th~s ~ddress ' ., ~., `, . . !
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incrementing is coupled to address registers 1228~-c (rey-ister 1228c is depicted in Figuxe 12g).
Bus transceivers 1229-1231 are utilized ~o couple the image data address to the control device. Registers 1232-1234 are utilized to temporarily store the starting address o~ each run o~ image ~ata. The starting address lS
¦ utilized when counters 1216-1219 enter a carry condition, indicating the end of a run. The next data address is l determined by incxementing the previous starting address, 1 and registers 1232-1234 are therefore utilized to retain each starting address of a run.
l Referring now to Figures 12h and 12i, and the ¦ joint figure formed thereby, there is depicted a schematic representation of certain of the timing circuits of the 1 video formatter of the present invention. Four bit counter 1235 serves as the end of data timer for the video formatter, ! counting the number of clock signals ater data reception on I ! the X bus ceases.
l As a matter of design choice, if the X bus clock 1 goes low for eight master clocks, the system will interpret I it as an end of data, causing end of data multivibratox 1236 ¦ to set. The output of multivibrator 1236 is utilized to clear multivibrator 1237, but not until the completion of any memory access in progress. Multi~ibrator 1237 also -serves to generate the busy signal when data is belng recoived.

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Dual four bit ripple counters 1238 and 1239 are I -the refresh timers which are utilized to time the periods ! between each successive refresh operation o~ the image I memory. Refresh takes place every 1.6 milliseconds, and the S ~ signal output from logic gate 1240 ~XCMMIT) is utilized to ¦ cause the incoming data on the X bus to temporarily stop.
I The refresh signal (RFRSH) is coupled to ripple counter 1241 which is utilized to cycle through the row l addresses of the image memories to accomplish refresh. The l¦ refresh addresses thus generated are latched out through the three state outputs of buffer 1242.
l Dual serial/parallel latch 1243 is the receive I latch for image data input from the X bus. Latch 1243 accepts eight bits serially off the X bus and then shifts ! the eight bits into an eight bit wide parallel output latch , where they are gated to the data bus and written into image memory while the next eight bits are being shifted into IIlatch 1243. Four bit counter 1244 is utilized to count the i input bits from the X bus to determine when an eight bit I byte has been lnput to the system. One output of counter ! 1 1244 i5 utilized to set firs byte multivibrator 1245.
- IIFirst byte multivibrator 1245 is utilized to disable the , writing of data into the image memory. Recalling the oper-ation of latch 1243, those ordinarily skilled in the art will appre ate that s a byte of data is a~cumu1ated, ch~

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i previous byte is being wxitten into memory. Since during accumulation of the first byte, no previous byte exists, the memory write is disabled Second byte multivibrator 1246 is cleared at the second byte of image data and is utilized to provide the load pulse which causes the run length to be loaded into counter control registers 1214 and 1215. (see Figure 12c) Further, since the address incrementing circuitry will not I be required for the starting address of image data, multi-~ vibrator 1246 also is utilized to disable multiplexers 1223-1226. (see Figure 12d) !I Four bit counter 1247 is the memory timing gener-ator~ which is utilized to operate the image memory independ-I ently o~ the X bus clock. Each time an eight bit byte is 1l accumulated in latch 1243, multivibrator 1248 is utilized to l! initiate a memory timing cycle, through logic gate 1250 and il muitivibrator 1249.
j Referring now to Figures 12j and 12k, and the ,¦ joint figure formed thereby, there is depicted a schematic 2Q !i representation of the display memory timing and control circuitry of the video formatter of the present invention. I
Multiplexers 1251 and 1252 are utilized to multi- ¦
! plex the video address into row and colum~ addresses. The I¦ outputs of multiplexers 1251 and 1252 are coupled to buffers il 1253 and 1254, which are utilized to drive the image memory l¦ address lines~

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j 2~3 Data is written into the image memory via write l buffer 1255 and may be read out onto the data ~us via buffer i 1256. One of eigh-t decoder 1257 is utilized to decode the j highest three bits of video address to select one of the 1 eight banks of image memory. A bank of image memory is , selected by selecting the proper column address strobe signal ~CAS). The selected bank column address strobe signal is driven by buffer 1258, whic~h is disabled during refresh by the output of logic gatë 1260, acting as an l inverter.
l Buffer 1259 is utilized to drive the write and row i address strobe signals. Shift registers 1261 and 1262 are ¦ driven by the 30.5 megahertz clock and are utilized to ! generate timing signals for the image memory. Wire strap ` 15 il options 1264 and 1265 are utilized to vary the timing signals generated to accomodate various types of integrated circuit ; I memories which may be utilized in the image memory. Multi-¦I vibrator 1263 is cleared by the outFut o~ logic gate 1266 during a read, write or refresh action, and serves to control 1 shift registers 1261 and 1262.
Referring now to the joint figure formed by joining Figures 121, 12mj 12n and 120, there is depicted a schematic Il representation of the image memory of the video fo~matter of !¦ the present invention. Image memory integrated circuits ¦ 1266a-h, lZ67a-h, 1268a-h, 125~a-h, 1270a-~, 1271a-h, 1272a-h and 1273a-h are each, in a pref~rreu embodimenc, a 16K bit 1~
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~ 9~3~ i i dynamic random access memory, such as the TMS 411G manu-! factured by Texas Instruments, Incorporated of Dallas, Texas. The eight banks of memory form a 128K byte image ¦ memory which contains sufficient image data to accurately portray an entire display image. Further, in addition to ¦limage data, alphanumeric character codes may be stored ¦within the image memory for character generation by means of video generator 1173 (see Figure lln).
Il Finally no~, re~erring to the joint figures formed 1 by joining Figures 12p and 12q in the manner indicated in I the figures, there is depicted a schematic diagram of the I interace circuitry which couples the video formatter of the ! present invention to the other subsystems in the document lprocessor by means of the X bus.
l~ X bus control reglster 1274 is an internal video ¦formatter register which is directly addressable by the external control device in the manner described herein. The data input to X bus control register 1274 is utilized to I;select a particular one of the eight X bus channels, and also specifies whether the video formatter will receive data ,or transmit data.
The upper four bits in X bus control register 1274 specify a receive condition and are applied to one of ten lldecoder 1275. The output of one of ten decoder 1275 is 1¦ applied to inverter buffer 1276 and is then utilized to select one of the eight X bus transceivers 1278a-h.

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In the transmit mode, the lower ~our bits of X bus control register 127~ are utili~ed and specify a transmit condition. The lower four bits are applied to one of ten decoder 1277, the output of which is utilized to select one of eight X bus transceivers 1278a-h.
During transmission of data from the video for-matter, eight bit wide bytes of data are coupled to parallel in-out shift register 1279 for serlali2ation and application to X bus transceivers 1278a-h.
Multivibrator 1280 is utilized to temporarily pause transmission of data during the refresh cycle, and is gated to ensure that the pause takes place at the end of a clock pulse, to prevent possible split clocks. Multivibra-tor 1281 is set and holds the clock low when the end of image data is encountered. After the last bit of data in the sixteen display zone has been transmitted, multivibrator 1281 is set and remains set until cleared by the external - control device. This provides the end of data signal to the receiving device.
~' l LASER PRINTER SUBSYSTEM
An important feature of the document processing ¦ system of the present invention is the ability to produce a 1 facsimile image of the entire image of a processed document, l any portion thereof, or m~ultiple poxtion$ thereof, for inclusion in a statement, letter, or other document. With reference again to Flgure 1, the document images for a ' ' ' ,', . ...

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plurality o~ documents are storecl, in one pre~erred embodi-ment, in magne-tic disk storage. Digital computer 100 accesses a selected plurality of digital images via disk controller 102 and channel selector 116.
The selected digital images are transferred thxough multiplexed direct memory access 166, a sixteen channel direct memory access designed to be compatible with digital computer 100. The selected digital images are then transferred to local X bus through multiplexed direct memory access 164, a four channel direct memory access desi~ned to be compatible with the microprocessor utilized in the local subsystems. If the image data selected is in compacted form, it is transferred via local X bus to digital image expander 162 or expansion. The resultant expanded data is transferred through X bus distributor 170 and X bus dis-tributor 132 into a video formatter 134 for formatting and interfacing into the sequence required by the specific laser printer system. Video ~ormatter 134 utilizes identical circuitry to that utilized in video formatters 1008, 1010, 1012 and 101~ o Figure 10, and that circuitry is explained ¦ in greater depth with reference to Figures lla-llo and 12a-12q. The properly formatted image data is temporarily stored in image memory 128, and selectively applied to laser printer 130 by printer controller 126.
Video formatter 134 may also be utilized to gen-erate alphanumeric characters for use in addition to the dig~tal image data, ln those applications wherein a single . ." '',, '' . .
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documellt is required to have an image and alphanwner1c information. In such app1ications, the image and data required for the alphanumeric characters are both stored in image memory 128.
I.aser printer 130, in the embodiment disclosed, i6 a Model ND2 high speed printer manufactured by the Siemens Corporation of Cherry Hill, New Jersey. Laser printer 130 emp~oys laser technology and electrophotographic techniques.
The digital image data is utilized to control a laser which exposes selected por~ions o a rotating, photocond~ctor surfaced drum. Toner will adhere to the exposed portions of ¦ the drum and will then be transfexred to paper in the ¦ manner well known in the art.
l It should be appreciated by those skilled in the ¦ art that ink jet or other state of the art printing systems may be utilized with the document processing system of the present invention.
lthough the invention has been described with reference to a specific embodiment, this description is not ~0 meant to be construed in a limiting sense. Various modifi-cations of the disclosed embodiment as well as alternative embodiments of the invention will become apparent to persons skilled ln the art upon reference to the description of the invention. It is therefore contemplated that the appended claims will cover any such modifications or embodiments that ~ fall w hin the true sccpe of the inventlon.
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Claims (3)

WHAT IS CLAIMED IS:

1. A video data compression system for data compression of signals representative of the video image of a document, said system comprising:
(a) means for continuously transporting said document along a first directional path;
(b) means for video scanning said document during said continuous transporting and in a direction transverse to said first directional path, said video scanning means producing coded signals respectively representative of black and white sections of the image of said document;
(c) said video scanning means further comprising means for producing a plurality of consecutive scans in said transverse direction;
(d) means for comparing the coded signals of one scan with the coded signals of a prior scan to compare the nature of adjacent ones of said sections in an axis parallel to said first directional path;
(e) means for generating unique redundancy codes indicative of unique relationships resulting from said comparison of adjacent sections, and (f) means for deleting from memory those coded signals indicative of the sections having the said unique relationships and replacing said deleted signals with said unique redundancy codes.

2. The system as defined by claim 1 further comprising means for generating said redundancy codes in response to consecutive scans indicating a black section followed by three adjacent white sections;
two adjacent black sections followed by two adjacent white sections; or three adjacent black sections followed by an adjacent white section.

3. The system as defined by claim 1 further comprising means for generating said redundancy codes in response to consecutive scans indicating identical data.