CA1215455A - Digital span frame detection circuit - Google Patents
Digital span frame detection circuitInfo
- Publication number
- CA1215455A CA1215455A CA000455920A CA455920A CA1215455A CA 1215455 A CA1215455 A CA 1215455A CA 000455920 A CA000455920 A CA 000455920A CA 455920 A CA455920 A CA 455920A CA 1215455 A CA1215455 A CA 1215455A
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- Prior art keywords
- digital
- digital span
- detection circuit
- frame detection
- flip
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
- H04J3/0605—Special codes used as synchronising signal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/06—Time-space-time switching
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Time-Division Multiplex Systems (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
A DIGITAL SPAN FRAME DETECTION CIRCUIT
ABSTRACT OF THE DISCLOSURE
In a telecommunications switching system, which has a switching network connected to a number of asynchronous digital spans, a digital span frame detection circuit continuously monitors the framing of each of the digital spans. The digital span frame detection circuit checks for both proper framing and super framing, TS bits and FS bits. An ordered exami-nation of each of the number of digital spans will occur. Any digital span which lacks proper framing or super framing will be marked for subsequent processing.
These markings will be scanned and submitted for refram-ing in an ordered fashion.
ABSTRACT OF THE DISCLOSURE
In a telecommunications switching system, which has a switching network connected to a number of asynchronous digital spans, a digital span frame detection circuit continuously monitors the framing of each of the digital spans. The digital span frame detection circuit checks for both proper framing and super framing, TS bits and FS bits. An ordered exami-nation of each of the number of digital spans will occur. Any digital span which lacks proper framing or super framing will be marked for subsequent processing.
These markings will be scanned and submitted for refram-ing in an ordered fashion.
Description
"` lZ~ S
A DIGITAL SPI~N FRAMR DET~CTION CIRCUIT
CROSS-REFERENCE TO RELATED APPLICATIONS
The present application is related to copending Canadian patent application sarlal number 455,921-5, having the same inventive entity and being assigned to the same assignee.
B~CKGROUND OF THE INVENTION
The present invention pertains to data transmission between telecommunications switching systems via digital spans and more particularly to a circuit within a telecommunications switching system for detecting proper framing and super framing for a number of digital spans.
In modern telecommunications switching, it is necessary to transmit large amounts oE data rapidly between switching systems. To this end, digital spans are utilized to connect switching systems and to transmit this data. These digital spans may be T1 or T2 carriers using DSl or DS2 data formats, respectively. These digital spans transmit data at high speeds, serially. The data is transmitted by one switching system and received by another. Since a particular switching system may be connected to a number of others, each switching system may have a number of digital spans from which it receives data.
These digital spans contain framing and synchronizing information. Since high frequency signals are subject to drifting, periodically the digital spans may lose proper framing and synchronization. This problem is magnified when a switching system must maintain proper framing and synchronization for a number of digital spans.
In addition, the Federal Communications Commission provides regulations which mandate the time duration that a digital span may be without proper framing and synchronization.
Accordingly, it is the object of the present invention to provide an ef-ficient and quick operating circuit for digital span frame detection.
SUMMARY OF THE INVENTION
In a telecommunications switching system which has a switching network, a plurality of digital spans are connected to the switching network. Each of these digital spans asynchronously transmits PCM data to the switching networX. A digital span frame detec-tion circuit is connected between each of the digital spans and the switching network for detecting a loss of proper framing for any of the digital spans.
The digital span frame detection circuit includes a monitor which is connected to each of the digital spans. The monitor produces a frame check signal for detection of a framing bit (S-bit) for each of the digital spans. An initial addresser is connected to the switching network and to the monitor. This initial addresser operates to collect and to transmit a first set of address signals. A first memory is con-nected to the initial addresser and operates in re-sponse to the first set of address signals to transmit a data word representing the error status of one particular digital span which is indicated by the first set of address signals.
A second addresser is connected to the first memory and it operates to transmit a second set of address signals in response to the error status word of the first memory. A second memory is connected to the 3Q second addresser. The second memory operates in re-sponse to the second set of address signals, which must include at least three bits being equal to a predefined value, to produce an error signal of a first logic value. If less than three bits are equal to the prede-fined value, the second memory will produce an errorsignal of a second logic value.
., The first memory is also connected to the second addresser. And the firsk memory is operated to store the second set of address signals for each partic-ular digital span.
The monitor is connected to the second memory and operates in response to the error signal of the first logic value to produce an alarm signal for a particular digital span. Latches, which are connected to the monitor, are operated to store an indication representing the alarm signal for each digital span. A
scanner is connected between the monitor and the latches.
The scanner operates to examine each of the stored alarm signals for the digital spans and to produce output signals9 which identify one digital span which has a corresponding alarm signal indicating a loss of framing.
DESCRIPTION OF THE DRAWINGS
Figure 1 is a block diagram of a telecommuni-cations switching system which embodies the present invention.
Figure 2 is a bit map of a channel, a frame, and a super -frame of a Tl digital span.
Figure 3 is a state diagram of a frame detec-tion and reframing circuit of the present invention.
Figure 4 is a schematic diagram of a portion of the digital span frame detection re-framing circuitry.
Figure 5 is a schematic diagram of the alarm indication circuitry.
Figures 6A9 6B and 6C are schematic diagrams of a portion of the digital span frame detection and reframing circuitry.
Figures 7A and 7B are schematic diagrams of a portion of digital span frame detection and reframing circuitry.
4~
DESCRIPTION OF TIIE PREFER~ED EMBODIMENT
Referring to Figure 1, a -time-space-time digital switching network along with the corresponding common control is shown. Telephone subscribers, such as subscribers 1 and 2, are shown connected to analog line unit 13. Analog line unit 13 is connected to both copies of the analog control unit 14 and 14'. Originat-ing time switches 20 and 20' are connected to duplex pair of space switch units 30 and 30' which are in turn connected to the terminating time switch 21 and 21'.
Time switch and control units 21 and 21' are connected to analog control unit 14 and 14' and ultimately to the telephone subscribers 1 and 2 via analog line circuit 13.
Digital control units 15 and 15' connect the digital spans to the switching network. Digital span equipment may be implemented using a model 9004 Tl digital span manufactured by GTE Lenkurt Inc. Simi-larly, analog trunk unit 16 connects trunk circuits to the digital switching network via analog control units 17 and 17'.
A peripheral processor CPU 70 controls the digital switching network and digital and analog control units. Analog line unit 13 and a duplex pair of analog control units 14 and 14' interface to telephone sub-scribers directly. A duplicate pair of digital control units 15 and 15' control the incoming PCM data from the digital spans. Similarly~ the analog trunk unit 16 and a duplex pair of analog control units 17 and 17' inter-face to trunk circuits. The analog and digital controlunits are each duplicated for reliability purposes.
The nature of a Tl data and its format is shown in Figure 2. Each voice sample consists of eight bits, PCMO-PCM7. PCM0 is a sign bit. PCMl-PCM7 give the magnitude of the voice sample. PCMl may also be used to convey alarm indications. PCM7 is used to carry supervision information during frames 6 and 12.
Twenty-four voice samples are organized together with an S bit to form a frame. Each voice sample in the frame is associated with one channel of voice (or data). The channels are numbered 0-23. The S bit carries a periodic pattern which, when detected, is used to identify the beginning of each frame of data. Twelve frames of data are organized to form a "super rame". During frames 6 and 12 of the super frame, PCM7 is used to carry supervision information associated with each of the 24 channels. The periodic pattern of data carried by the S bit also makes it possible to identify the individual frames within a super frame.
I`he pattern carried on the S bit is as follows (the first bit is associated with frame 0):
"100011011100". It can be seen that during the odd numbered frames, the S bit forms an alternating pattern of "l"s and "O"s, i.e., "101010". This alternating pattern is referred to as the TS pattern and is used to identify the starting position of the frames. During the even numbered frames the S bit carries the pattern "001110", where the first "1" indicates the beginning of frame 6. This pattern is referred to as the FS
pattern and is used to identify the position within a super frame.
Every time a TS bit occurs, a frame detector compares it with the value that it expects to see (ones during frames 1, 5, and 9; zeroes during frames 3, 7, and 11). If the TS bit disagrees with the expected value, it is considered an error. If three errors occur during any five consecutive examinations of TS
bits for a digital span (T-carrier), then that digital span is considered to be out of frame. An alarm condi-tion is operated. Eventually, an attempt will be made to reframe that T-carrier.
Lxamination of FS bits is an analogous proce-dure to that of the TS bits, except for the fact that no check is made for FS blts occurring during frames Z
and 8.
When reframing is attempted for a digital span, the frame detector examines each bit position for a period of 16 frames. If any bit position has con-sistently toggled during alternate frames, then that bit position is assumed to be the correct framing bit position, and the contents of a write vector will be updated to reflect the new S bit position.
If the TS pattern is properly aligned, but the FS pattern is in error, the frame detector will increment a write vector by four frame positions. This will occur every time the FS pattern is in error until eventually the write vector is properly aligned with the incoming FS pattern.
Referring to Figures 4 through 7 taken col-lectively, when the signal FLAGB is sent by a digital span, the write vector (MRVCTO-MRVCT7), is set, it indicates that an S bit has been received and is avail-able for frame checking. Signal FLAGB is constantly monitored by programming logic array (PLA) 761. This indicates that a particular digital span (T-carrier) is requesting a frame check operation. If no other digital span is requesting a frame check operation, PLA 761 and D type flip-flop 765 will p~oduce a signal FRMCHK, which indicates that this particular digital span now has a pending frame check request.
Simultaneously, PLA 761 will generate a signal RSTFLGB which resets the frame check request FLAGB fro~ the digital span. Additionally, PLA 761 will generate a strobe frame check signal STBFRMCHK
through flip-flop 765 and NAND gate 769. Signal STBFRMCHK will cause hex flip-flop 605 to latch the following information: first, the three least signif-icant bits of the write vector (MRVCTO-MRVCT2), which identify the particular digital span whose FLAGB signal will set; second, the odd/even frame bit (ODD/ENFR)which indicates whether the S bit is a TS bit or an FS
bit; third, the BADT/FS signal, generated by data selector 322, which indicates whether the F/TS bit agrees with the expected value for that frame; and fourth, and a NOCHECK signal generated ~y data selector 322, which is true during frames 2 and 8. As mentioned above, the FS bits occurring during frames 2 and 8 are not checked.
Multiplexers 614 and 615 select either of two address sources for accessing memory 622. Memory 622 is a 256 by 4 bit RAM memory. During the frame checking operation, the contents of flip-flops 605 are selected to provide the address for access to memory 622. The memory contents of the address selected by flip-flops 605 contain the error history for the F/TS bit for the particular digital span being checked. The four bits read from the memory location are transmitted along with the BADT/FS signal to flip-flops 607. Ihe outputs from flip-flops 607 are used as an address to access PROM memory 627. PROM memory 627 is an 32 by 8 bit memory device.
PROM memory 627 is arranged such that, if the address bits contain three or more ones, the ERROR
output signal of PROM 627 will be true. The outputs of flip-flops 607 are also selected by selectors 616 and 617 and are written as data inputs to memory 622. In addition, the most recent value of BADT/FS bit is stored as one of the four bits of history data in memory 622. The four most recent values of the BADT/FS
signal are written into memory 622 and will be available for the next succeeding frame check.
In response to the ERROR signal, PLA 761 will provide an 80 microsecond negative going pulse via NAND
gate 773 on the FRCHKSTB lead, which will cause the circuitry (8 bit adder latches 501 and 502 and 8 bit data selector 50~) to set an alarm indication for the 'ss particular digital span that has been determined to be in error.
If an error is detected while checking for the FS bit, PLA 761 operates via flip--flop 765 to produce the SRESYNC signal. As a result, flip-flop 716 will be set. While f]ip--flop 716 is set~ the content of flip-flops 605 will remain s-table, identifying which digital span requires resynchronization.
Next time the write vector for that particular digital span is accessed, four bit magnitude comparator 766 will generate a true signal on the SYNCMATCH lead.
As a result, AND gate 726 will generate a RFSYNC signal.
When the BUFFEMTY signal and SYNCMATCH signal occur simultaneously, AND gate 704 generates a reset to flip-flop 716.
Synchronous ~-bit binary counter 710 and 4-bit magnitude comparator 722 form an 8 bit scanner, which constantly scans the outputs of the alarm bits via the FALMFOUND lead of data selector 50~. When a frame alarm is detected, counter 710 is disabled from counting and its outputs identify the particular span which has the frame alarm. As a result, PLA 761 is informed that a reframing operation must be performed.
In addition, signal FDTMATCH produced by comparator 722 will be true when the write vector of the particular digital span being reframed is accessed.
Comparator 712, PLA 761 and flip-flop 765 form a finite state machine, which controls the sequenc-ing of the reframing procedure. The major reframing states are shown in the state diagram of Figure 3.
Initially, all digital spans are in frame as reframing circuitry is in the idle/initialize state 1.
When a frame alarm is detected, the reframing circuitry remains in this state for four frames of incoming data.
During this time, data from the digital span in error will be written into memory 622. In addition, for every data bit that is written, a logic l will be written into a corresponding position, called the still possible bit position.
At the completion of this task, the reframing circuitry will enter the update state. During the update state, the bits received from the digital span undergoing reframing are compared with the bits received two frames previously. If they are the same, the corresponding still possible bit is reset; if they are different~ the corresponding still possible bit is left unchanged. This process is repeated for 16 frames of data~ Counter 712 is incremented once for each compari-son so that its CRY output indicates the completion of the 16 frame interval period.
At this time, the reframe circuitry enters the check state. During this interval the still possi-ble bits are examined. If a still possible bit is set, then the corresponding bit position is a possible framing bit position. When such a possible framing bit position is detected, flip-flop 638 and counter 711 are loaded with the proper data to ensure that reframing will take place. Then, the reframing circuitry enters the super frame update state.
During the super frame update state, the additional span should have proper terminal synchroniza-tion. At the completion of the super frame updatestate, a signal FRCHKSTB will be generated. As a result, the frame alarm will be reset via adder latches 501 and 502. The frame alarm scanner counters 710 and 722 will then resume scanning for another frame alarm on another digital span.
Whenever a particular digital span passes an eight bit PCM sample to the circuit via the PCMXD0 through PCMXD7 leads, flip-flop 318 is set indicating that PCM data is available for processing during the next time frame detector cycle. The contents of the PCM sample are latched into flip-flop 608 and value of the write vector is latched into flip-flops 606.
~..if~ 5 At the beginning of the next frame detector cycle, the REFRMREQ signal causes flip-flop 326 to be set, generating a reframe grant signal REFRMGRT. The reframe grant signal reserves the frame detector cycle for use in re:framing operations only. Any pending frame check request will be deferred until the begin-ning of the next frame detector cycle.
The REFRMGRT signal causes selectors 614 and 615 to enable address information stored in flip-flops 606. During the first 324 nanoseconds, the contents of memory 622 are read out and "exclusive-ored" with PCMXD0-PCMXD3 via selectors 616 and 617. The output of the exclusive-or gates 629-632 is stored in flip-flop 637. During the next 324 nanosecond period, the four corresponding still possible bits are read from memory 622, "anded" with the contents of flip-flop 637 and stored in flip-flop 649, whose outputs are then gated by selectors 616 and 617 to be written back into memory 622. In this fashion, the still possible bits are updated. During the initialization state, signal RSTSTLPOS will constantly clear the contents of flip-flop 637 so that the data written back into the still possible bit positions will be all ones.
During the third and fourth intervals of 324 nanoseconds in the frame detector cycle, similar opera-tions are performed with PCM data bits PCMXD4 through PCMXD7. During the second hal-f of the frame detector cycle, the SCAN signal will be true, causing a different set of addresses to be accessed in memory 622.
Gates 328 and 640 generate the control signals from multiplexers 616 and 617. When the frame detector has completed the 16 frames of update operation, it enters the check state. During the check state, the frame detector cycles in the same manner in which it cycled during the update state; however, each time the still possible bits are read out of memory 622, they are used to address PROM memory 627. The PROM contents .5~
are arranged such that, if any of the still possible bits are set the one present ONEYRES signal will be true. This indicates that a framing bit position has been detected. The signals POSNA and POSNB indicate which of the four still possible bits was set (if more than one bit position is set, they will indicate the first bit position set). In response to the ONEPRES
signal, the PLA 761 will set -flip-flop 638 and will load this position information into counter 711.
Flip--flop 638 and its associated circuitry is arranged so that the next time the write vector is accessed for the particular digital span, the REFRAME
signal will be true. Thereby, the write vector is forced to be set to channel 3. Counter 711, flip-flop 716, NAND gates 718 and 723 are arranged to insert a number of skip commands each time the particular digital span is accessed. The number of skips is determined by the bit position of the still possible bit that was detected. This position information is loaded into counter 711, which then inserts skip commands until it has counted up to a value of binaTy 1000, at which time the output of NAND gate 718 goes to a 0 and counter 711 stops counting.
Although the preferred embodiment of the invention has been illustrated, and that form described in detail, it will be readily apparent to those skilled in the art that various modifications may be made therein without departing from the spirit of the inven-tion or from the scope of the appended claims.
A DIGITAL SPI~N FRAMR DET~CTION CIRCUIT
CROSS-REFERENCE TO RELATED APPLICATIONS
The present application is related to copending Canadian patent application sarlal number 455,921-5, having the same inventive entity and being assigned to the same assignee.
B~CKGROUND OF THE INVENTION
The present invention pertains to data transmission between telecommunications switching systems via digital spans and more particularly to a circuit within a telecommunications switching system for detecting proper framing and super framing for a number of digital spans.
In modern telecommunications switching, it is necessary to transmit large amounts oE data rapidly between switching systems. To this end, digital spans are utilized to connect switching systems and to transmit this data. These digital spans may be T1 or T2 carriers using DSl or DS2 data formats, respectively. These digital spans transmit data at high speeds, serially. The data is transmitted by one switching system and received by another. Since a particular switching system may be connected to a number of others, each switching system may have a number of digital spans from which it receives data.
These digital spans contain framing and synchronizing information. Since high frequency signals are subject to drifting, periodically the digital spans may lose proper framing and synchronization. This problem is magnified when a switching system must maintain proper framing and synchronization for a number of digital spans.
In addition, the Federal Communications Commission provides regulations which mandate the time duration that a digital span may be without proper framing and synchronization.
Accordingly, it is the object of the present invention to provide an ef-ficient and quick operating circuit for digital span frame detection.
SUMMARY OF THE INVENTION
In a telecommunications switching system which has a switching network, a plurality of digital spans are connected to the switching network. Each of these digital spans asynchronously transmits PCM data to the switching networX. A digital span frame detec-tion circuit is connected between each of the digital spans and the switching network for detecting a loss of proper framing for any of the digital spans.
The digital span frame detection circuit includes a monitor which is connected to each of the digital spans. The monitor produces a frame check signal for detection of a framing bit (S-bit) for each of the digital spans. An initial addresser is connected to the switching network and to the monitor. This initial addresser operates to collect and to transmit a first set of address signals. A first memory is con-nected to the initial addresser and operates in re-sponse to the first set of address signals to transmit a data word representing the error status of one particular digital span which is indicated by the first set of address signals.
A second addresser is connected to the first memory and it operates to transmit a second set of address signals in response to the error status word of the first memory. A second memory is connected to the 3Q second addresser. The second memory operates in re-sponse to the second set of address signals, which must include at least three bits being equal to a predefined value, to produce an error signal of a first logic value. If less than three bits are equal to the prede-fined value, the second memory will produce an errorsignal of a second logic value.
., The first memory is also connected to the second addresser. And the firsk memory is operated to store the second set of address signals for each partic-ular digital span.
The monitor is connected to the second memory and operates in response to the error signal of the first logic value to produce an alarm signal for a particular digital span. Latches, which are connected to the monitor, are operated to store an indication representing the alarm signal for each digital span. A
scanner is connected between the monitor and the latches.
The scanner operates to examine each of the stored alarm signals for the digital spans and to produce output signals9 which identify one digital span which has a corresponding alarm signal indicating a loss of framing.
DESCRIPTION OF THE DRAWINGS
Figure 1 is a block diagram of a telecommuni-cations switching system which embodies the present invention.
Figure 2 is a bit map of a channel, a frame, and a super -frame of a Tl digital span.
Figure 3 is a state diagram of a frame detec-tion and reframing circuit of the present invention.
Figure 4 is a schematic diagram of a portion of the digital span frame detection re-framing circuitry.
Figure 5 is a schematic diagram of the alarm indication circuitry.
Figures 6A9 6B and 6C are schematic diagrams of a portion of the digital span frame detection and reframing circuitry.
Figures 7A and 7B are schematic diagrams of a portion of digital span frame detection and reframing circuitry.
4~
DESCRIPTION OF TIIE PREFER~ED EMBODIMENT
Referring to Figure 1, a -time-space-time digital switching network along with the corresponding common control is shown. Telephone subscribers, such as subscribers 1 and 2, are shown connected to analog line unit 13. Analog line unit 13 is connected to both copies of the analog control unit 14 and 14'. Originat-ing time switches 20 and 20' are connected to duplex pair of space switch units 30 and 30' which are in turn connected to the terminating time switch 21 and 21'.
Time switch and control units 21 and 21' are connected to analog control unit 14 and 14' and ultimately to the telephone subscribers 1 and 2 via analog line circuit 13.
Digital control units 15 and 15' connect the digital spans to the switching network. Digital span equipment may be implemented using a model 9004 Tl digital span manufactured by GTE Lenkurt Inc. Simi-larly, analog trunk unit 16 connects trunk circuits to the digital switching network via analog control units 17 and 17'.
A peripheral processor CPU 70 controls the digital switching network and digital and analog control units. Analog line unit 13 and a duplex pair of analog control units 14 and 14' interface to telephone sub-scribers directly. A duplicate pair of digital control units 15 and 15' control the incoming PCM data from the digital spans. Similarly~ the analog trunk unit 16 and a duplex pair of analog control units 17 and 17' inter-face to trunk circuits. The analog and digital controlunits are each duplicated for reliability purposes.
The nature of a Tl data and its format is shown in Figure 2. Each voice sample consists of eight bits, PCMO-PCM7. PCM0 is a sign bit. PCMl-PCM7 give the magnitude of the voice sample. PCMl may also be used to convey alarm indications. PCM7 is used to carry supervision information during frames 6 and 12.
Twenty-four voice samples are organized together with an S bit to form a frame. Each voice sample in the frame is associated with one channel of voice (or data). The channels are numbered 0-23. The S bit carries a periodic pattern which, when detected, is used to identify the beginning of each frame of data. Twelve frames of data are organized to form a "super rame". During frames 6 and 12 of the super frame, PCM7 is used to carry supervision information associated with each of the 24 channels. The periodic pattern of data carried by the S bit also makes it possible to identify the individual frames within a super frame.
I`he pattern carried on the S bit is as follows (the first bit is associated with frame 0):
"100011011100". It can be seen that during the odd numbered frames, the S bit forms an alternating pattern of "l"s and "O"s, i.e., "101010". This alternating pattern is referred to as the TS pattern and is used to identify the starting position of the frames. During the even numbered frames the S bit carries the pattern "001110", where the first "1" indicates the beginning of frame 6. This pattern is referred to as the FS
pattern and is used to identify the position within a super frame.
Every time a TS bit occurs, a frame detector compares it with the value that it expects to see (ones during frames 1, 5, and 9; zeroes during frames 3, 7, and 11). If the TS bit disagrees with the expected value, it is considered an error. If three errors occur during any five consecutive examinations of TS
bits for a digital span (T-carrier), then that digital span is considered to be out of frame. An alarm condi-tion is operated. Eventually, an attempt will be made to reframe that T-carrier.
Lxamination of FS bits is an analogous proce-dure to that of the TS bits, except for the fact that no check is made for FS blts occurring during frames Z
and 8.
When reframing is attempted for a digital span, the frame detector examines each bit position for a period of 16 frames. If any bit position has con-sistently toggled during alternate frames, then that bit position is assumed to be the correct framing bit position, and the contents of a write vector will be updated to reflect the new S bit position.
If the TS pattern is properly aligned, but the FS pattern is in error, the frame detector will increment a write vector by four frame positions. This will occur every time the FS pattern is in error until eventually the write vector is properly aligned with the incoming FS pattern.
Referring to Figures 4 through 7 taken col-lectively, when the signal FLAGB is sent by a digital span, the write vector (MRVCTO-MRVCT7), is set, it indicates that an S bit has been received and is avail-able for frame checking. Signal FLAGB is constantly monitored by programming logic array (PLA) 761. This indicates that a particular digital span (T-carrier) is requesting a frame check operation. If no other digital span is requesting a frame check operation, PLA 761 and D type flip-flop 765 will p~oduce a signal FRMCHK, which indicates that this particular digital span now has a pending frame check request.
Simultaneously, PLA 761 will generate a signal RSTFLGB which resets the frame check request FLAGB fro~ the digital span. Additionally, PLA 761 will generate a strobe frame check signal STBFRMCHK
through flip-flop 765 and NAND gate 769. Signal STBFRMCHK will cause hex flip-flop 605 to latch the following information: first, the three least signif-icant bits of the write vector (MRVCTO-MRVCT2), which identify the particular digital span whose FLAGB signal will set; second, the odd/even frame bit (ODD/ENFR)which indicates whether the S bit is a TS bit or an FS
bit; third, the BADT/FS signal, generated by data selector 322, which indicates whether the F/TS bit agrees with the expected value for that frame; and fourth, and a NOCHECK signal generated ~y data selector 322, which is true during frames 2 and 8. As mentioned above, the FS bits occurring during frames 2 and 8 are not checked.
Multiplexers 614 and 615 select either of two address sources for accessing memory 622. Memory 622 is a 256 by 4 bit RAM memory. During the frame checking operation, the contents of flip-flops 605 are selected to provide the address for access to memory 622. The memory contents of the address selected by flip-flops 605 contain the error history for the F/TS bit for the particular digital span being checked. The four bits read from the memory location are transmitted along with the BADT/FS signal to flip-flops 607. Ihe outputs from flip-flops 607 are used as an address to access PROM memory 627. PROM memory 627 is an 32 by 8 bit memory device.
PROM memory 627 is arranged such that, if the address bits contain three or more ones, the ERROR
output signal of PROM 627 will be true. The outputs of flip-flops 607 are also selected by selectors 616 and 617 and are written as data inputs to memory 622. In addition, the most recent value of BADT/FS bit is stored as one of the four bits of history data in memory 622. The four most recent values of the BADT/FS
signal are written into memory 622 and will be available for the next succeeding frame check.
In response to the ERROR signal, PLA 761 will provide an 80 microsecond negative going pulse via NAND
gate 773 on the FRCHKSTB lead, which will cause the circuitry (8 bit adder latches 501 and 502 and 8 bit data selector 50~) to set an alarm indication for the 'ss particular digital span that has been determined to be in error.
If an error is detected while checking for the FS bit, PLA 761 operates via flip--flop 765 to produce the SRESYNC signal. As a result, flip-flop 716 will be set. While f]ip--flop 716 is set~ the content of flip-flops 605 will remain s-table, identifying which digital span requires resynchronization.
Next time the write vector for that particular digital span is accessed, four bit magnitude comparator 766 will generate a true signal on the SYNCMATCH lead.
As a result, AND gate 726 will generate a RFSYNC signal.
When the BUFFEMTY signal and SYNCMATCH signal occur simultaneously, AND gate 704 generates a reset to flip-flop 716.
Synchronous ~-bit binary counter 710 and 4-bit magnitude comparator 722 form an 8 bit scanner, which constantly scans the outputs of the alarm bits via the FALMFOUND lead of data selector 50~. When a frame alarm is detected, counter 710 is disabled from counting and its outputs identify the particular span which has the frame alarm. As a result, PLA 761 is informed that a reframing operation must be performed.
In addition, signal FDTMATCH produced by comparator 722 will be true when the write vector of the particular digital span being reframed is accessed.
Comparator 712, PLA 761 and flip-flop 765 form a finite state machine, which controls the sequenc-ing of the reframing procedure. The major reframing states are shown in the state diagram of Figure 3.
Initially, all digital spans are in frame as reframing circuitry is in the idle/initialize state 1.
When a frame alarm is detected, the reframing circuitry remains in this state for four frames of incoming data.
During this time, data from the digital span in error will be written into memory 622. In addition, for every data bit that is written, a logic l will be written into a corresponding position, called the still possible bit position.
At the completion of this task, the reframing circuitry will enter the update state. During the update state, the bits received from the digital span undergoing reframing are compared with the bits received two frames previously. If they are the same, the corresponding still possible bit is reset; if they are different~ the corresponding still possible bit is left unchanged. This process is repeated for 16 frames of data~ Counter 712 is incremented once for each compari-son so that its CRY output indicates the completion of the 16 frame interval period.
At this time, the reframe circuitry enters the check state. During this interval the still possi-ble bits are examined. If a still possible bit is set, then the corresponding bit position is a possible framing bit position. When such a possible framing bit position is detected, flip-flop 638 and counter 711 are loaded with the proper data to ensure that reframing will take place. Then, the reframing circuitry enters the super frame update state.
During the super frame update state, the additional span should have proper terminal synchroniza-tion. At the completion of the super frame updatestate, a signal FRCHKSTB will be generated. As a result, the frame alarm will be reset via adder latches 501 and 502. The frame alarm scanner counters 710 and 722 will then resume scanning for another frame alarm on another digital span.
Whenever a particular digital span passes an eight bit PCM sample to the circuit via the PCMXD0 through PCMXD7 leads, flip-flop 318 is set indicating that PCM data is available for processing during the next time frame detector cycle. The contents of the PCM sample are latched into flip-flop 608 and value of the write vector is latched into flip-flops 606.
~..if~ 5 At the beginning of the next frame detector cycle, the REFRMREQ signal causes flip-flop 326 to be set, generating a reframe grant signal REFRMGRT. The reframe grant signal reserves the frame detector cycle for use in re:framing operations only. Any pending frame check request will be deferred until the begin-ning of the next frame detector cycle.
The REFRMGRT signal causes selectors 614 and 615 to enable address information stored in flip-flops 606. During the first 324 nanoseconds, the contents of memory 622 are read out and "exclusive-ored" with PCMXD0-PCMXD3 via selectors 616 and 617. The output of the exclusive-or gates 629-632 is stored in flip-flop 637. During the next 324 nanosecond period, the four corresponding still possible bits are read from memory 622, "anded" with the contents of flip-flop 637 and stored in flip-flop 649, whose outputs are then gated by selectors 616 and 617 to be written back into memory 622. In this fashion, the still possible bits are updated. During the initialization state, signal RSTSTLPOS will constantly clear the contents of flip-flop 637 so that the data written back into the still possible bit positions will be all ones.
During the third and fourth intervals of 324 nanoseconds in the frame detector cycle, similar opera-tions are performed with PCM data bits PCMXD4 through PCMXD7. During the second hal-f of the frame detector cycle, the SCAN signal will be true, causing a different set of addresses to be accessed in memory 622.
Gates 328 and 640 generate the control signals from multiplexers 616 and 617. When the frame detector has completed the 16 frames of update operation, it enters the check state. During the check state, the frame detector cycles in the same manner in which it cycled during the update state; however, each time the still possible bits are read out of memory 622, they are used to address PROM memory 627. The PROM contents .5~
are arranged such that, if any of the still possible bits are set the one present ONEYRES signal will be true. This indicates that a framing bit position has been detected. The signals POSNA and POSNB indicate which of the four still possible bits was set (if more than one bit position is set, they will indicate the first bit position set). In response to the ONEPRES
signal, the PLA 761 will set -flip-flop 638 and will load this position information into counter 711.
Flip--flop 638 and its associated circuitry is arranged so that the next time the write vector is accessed for the particular digital span, the REFRAME
signal will be true. Thereby, the write vector is forced to be set to channel 3. Counter 711, flip-flop 716, NAND gates 718 and 723 are arranged to insert a number of skip commands each time the particular digital span is accessed. The number of skips is determined by the bit position of the still possible bit that was detected. This position information is loaded into counter 711, which then inserts skip commands until it has counted up to a value of binaTy 1000, at which time the output of NAND gate 718 goes to a 0 and counter 711 stops counting.
Although the preferred embodiment of the invention has been illustrated, and that form described in detail, it will be readily apparent to those skilled in the art that various modifications may be made therein without departing from the spirit of the inven-tion or from the scope of the appended claims.
Claims (11)
1. In a telecommunications switching system having a switching network, a plurality of digital spans connected to said switching network and each said digital span asynchronously transmitting PCM data to said switching network, a digital span frame detection circuit connected between each said digital span and said switching network for detecting a loss of proper framing for any of said digital spans, said digital span frame detection circuit comprising:
monitor means connected to each said digital span and being operated to produce a frame check signal for detection of an S-bit of any one particular digital span;
first means for addressing connected to said switching network and to said monitor means, said first means for addressing being operated to collect and transmit a first address;
first memory means connected to said first means for addressing and being operated in response to said first address to transmit a data word representing an error status of said one particular digital span, indicated by said first address;
second means for addressing connected to said first memory means and being operated to transmit a second address in response to said error status word;
second memory means connected to said second means for addressing and being operated in response to said second address, including at least three bits equal to a redefined value, to produce an error signal of a first value or alternatively to produce an error signal of a second value;
said first memory means connected to said second means for addressing and being further operated to store said second address for said one particular digital span;
said monitor means connected to said second memory means and being operated in response to said error signal of a first value to produce an alarm signal for said one particular digital span;
latching means connected to said monitor means and being operated to store an indication repre-senting said alarm signal for each of said digital spans; and means for scanning connected to said monitor means and to said latching means, said means for scanning being operated to examine said stored alarm signals for each said digital span and means for scanning being further operated to produce a plurality of output signals for identifying one said digital span, having a correspond-ing alarm signal indicating loss of framing.
monitor means connected to each said digital span and being operated to produce a frame check signal for detection of an S-bit of any one particular digital span;
first means for addressing connected to said switching network and to said monitor means, said first means for addressing being operated to collect and transmit a first address;
first memory means connected to said first means for addressing and being operated in response to said first address to transmit a data word representing an error status of said one particular digital span, indicated by said first address;
second means for addressing connected to said first memory means and being operated to transmit a second address in response to said error status word;
second memory means connected to said second means for addressing and being operated in response to said second address, including at least three bits equal to a redefined value, to produce an error signal of a first value or alternatively to produce an error signal of a second value;
said first memory means connected to said second means for addressing and being further operated to store said second address for said one particular digital span;
said monitor means connected to said second memory means and being operated in response to said error signal of a first value to produce an alarm signal for said one particular digital span;
latching means connected to said monitor means and being operated to store an indication repre-senting said alarm signal for each of said digital spans; and means for scanning connected to said monitor means and to said latching means, said means for scanning being operated to examine said stored alarm signals for each said digital span and means for scanning being further operated to produce a plurality of output signals for identifying one said digital span, having a correspond-ing alarm signal indicating loss of framing.
2. A digital span frame detection circuit as claimed in claim 1, said monitor means including:
a programming logic array;
first-flip flop means connected to said programming logic array;
first gating means connected between said first flip-flop means and said first means for address-ing; and second gating means connected between said programming logic array and said latching means.
a programming logic array;
first-flip flop means connected to said programming logic array;
first gating means connected between said first flip-flop means and said first means for address-ing; and second gating means connected between said programming logic array and said latching means.
3. A digital span frame detection circuit as claimed in claim 2, said first means for addressing including:
second flip-flop means connected to said switching network and to said programming logic array;
and multiplexer means connected to said second flip-flop means.
second flip-flop means connected to said switching network and to said programming logic array;
and multiplexer means connected to said second flip-flop means.
4. A digital span frame detection circuit as claimed in claim 3, said first memory means including random access memory means connected to said multiplexer means.
5. A digital span frame detection circuit as claimed in claim 4, said second means for addressing including third flip-flop means connected to said switching network, to said means for scanning and to said second memory means.
6. A digital span frame detection circuit as claimed in claim 5, said second memory means including programmable read only memory means connected to said third flip-flop means and to said programming logic array.
7. A digital span frame detection circuit as claimed in claim 5, said second means for addressing further including first data selection means connected between said third flip-flop means and said random access memory means for transmitting a modified error status word to said random access memory means for storage for each said digital span.
8. A digital span frame detection circuit as claimed in claim 7, said latching means including:
binary adder latch means connected to said second gating means and to said means for scanning; and second data selection means connected to said binary adder latch means and to said means for scanning.
binary adder latch means connected to said second gating means and to said means for scanning; and second data selection means connected to said binary adder latch means and to said means for scanning.
9. A digital span frame detection circuit as claimed in claim 8, said means for scanning including:
binary counter means connected to said switch-ing network; and magnitude comparator means connected to said binary counter means and being operated to produce a frame detection match signal for a digital span having a corresponding alarm signal stored in said latching means.
binary counter means connected to said switch-ing network; and magnitude comparator means connected to said binary counter means and being operated to produce a frame detection match signal for a digital span having a corresponding alarm signal stored in said latching means.
10. A digital span frame detection circuit as claimed in claim 9, said binary counter means includ-ing a plurality of outputs providing for frame alarm address signals indicating an identity of said digital span, which lacks proper framing.
11. A digital span frame detection circuit as claimed in claim 10, said means for scanning includ-ing fourth flip-flop means connected to said switching network and to said magnitude comparator means to provide a reframing grant signal for initiating a reframing operation.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/506,571 US4507780A (en) | 1983-06-22 | 1983-06-22 | Digital span frame detection circuit |
| US506,571 | 1983-06-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1215455A true CA1215455A (en) | 1986-12-16 |
Family
ID=24015161
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000455920A Expired CA1215455A (en) | 1983-06-22 | 1984-06-05 | Digital span frame detection circuit |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US4507780A (en) |
| CA (1) | CA1215455A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4545053A (en) * | 1984-03-21 | 1985-10-01 | At&T Information Systems Inc. | Time slot interchanger |
| US4674088A (en) * | 1985-03-07 | 1987-06-16 | Northern Telecom Limited | Method and apparatus for detecting frame synchronization |
| EP0262478B1 (en) * | 1986-09-29 | 1991-08-21 | Siemens Aktiengesellschaft | Method for frame synchronization of an exchange of a pcm-tdm telecommunication network |
| US4740960A (en) * | 1986-10-30 | 1988-04-26 | Gte Communication Systems Corporation | Synchronization arrangement for time multiplexed data scanning circuitry |
| US4754454A (en) * | 1986-11-17 | 1988-06-28 | Gte Communication Systems Corporation | Synchronization circuitry for duplex digital span equipment |
| US5513173A (en) * | 1994-03-16 | 1996-04-30 | Xel Communications, Inc. | Data link access unit for T1 spans supporting the extended superframe format (ESF) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR1518764A (en) * | 1967-01-23 | 1968-03-29 | Labo Cent Telecommunicat | Channel synchronization circuit in a pulse code modulation transmission network |
| JPS4943809B1 (en) * | 1968-10-25 | 1974-11-25 | ||
| FR2281686A1 (en) * | 1974-08-05 | 1976-03-05 | France Etat | DIGITAL TRANSMISSION NETWORK WITH INDEPENDENT TRANSMITTED FRAME PHASES |
-
1983
- 1983-06-22 US US06/506,571 patent/US4507780A/en not_active Expired - Fee Related
-
1984
- 1984-06-05 CA CA000455920A patent/CA1215455A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| US4507780A (en) | 1985-03-26 |
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