CA1206619A - Electronic postage meter having redundant memory - Google Patents
Electronic postage meter having redundant memoryInfo
- Publication number
- CA1206619A CA1206619A CA000419915A CA419915A CA1206619A CA 1206619 A CA1206619 A CA 1206619A CA 000419915 A CA000419915 A CA 000419915A CA 419915 A CA419915 A CA 419915A CA 1206619 A CA1206619 A CA 1206619A
- Authority
- CA
- Canada
- Prior art keywords
- data
- microprocessor
- random access
- postage meter
- memories
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G07—CHECKING-DEVICES
- G07B—TICKET-ISSUING APPARATUS; FARE-REGISTERING APPARATUS; FRANKING APPARATUS
- G07B17/00—Franking apparatus
- G07B17/00185—Details internally of apparatus in a franking system, e.g. franking machine at customer or apparatus at post office
- G07B17/00362—Calculation or computing within apparatus, e.g. calculation of postage value
-
- G—PHYSICS
- G07—CHECKING-DEVICES
- G07B—TICKET-ISSUING APPARATUS; FARE-REGISTERING APPARATUS; FRANKING APPARATUS
- G07B17/00—Franking apparatus
- G07B17/00185—Details internally of apparatus in a franking system, e.g. franking machine at customer or apparatus at post office
- G07B17/00362—Calculation or computing within apparatus, e.g. calculation of postage value
- G07B2017/00395—Memory organization
- G07B2017/00411—Redundant storage, e.g. back-up of registers
Abstract
ELECTRONIC POSTAGE METER HAVING REDUNDANT MEMORY
ABSTRACT OF THE DISCLOSURE
An electronic postal meter has an accounting unit with redundant nonvolatile random access memories controlled by a microprocessor system. The redundant random access memories have separate groups of address and data lines to minimize identical errors in data stored therein. The data transfer may occur at different times to and from the memories, with respect to any given byte of data. The system may incorporate redundant microprocessors, and critical parameters may be checked at periodic intervals in the main program of the accounting microprocessor system.
ABSTRACT OF THE DISCLOSURE
An electronic postal meter has an accounting unit with redundant nonvolatile random access memories controlled by a microprocessor system. The redundant random access memories have separate groups of address and data lines to minimize identical errors in data stored therein. The data transfer may occur at different times to and from the memories, with respect to any given byte of data. The system may incorporate redundant microprocessors, and critical parameters may be checked at periodic intervals in the main program of the accounting microprocessor system.
Description
`` ~L2~
This invention relates to electronic accountlng systems, and is especially directed to an electronic postage meter having a microprocessor controlled electronic account-ing unit with nonvolatile random access mernory.
An electronic postage meter having an accounting unit with a microprocessor, and nonvolatile memory for storing accounting data, is disclosed, for example, in U. S.
Patent No. 4,301,507, issued November 17, 1981, and assigned to the assignee of the present application. In this system the accounting data is stored in the random access memory and retrieved from the random access memory by way of common address and data lines of the microcomputer system.
While in most instances it can be assured that the account-ing data stored in the memory will be correct, there are certain conditions that can occur that can result in non-detectable errors in the data.
In order to overcome such problems, it has been proposed to employ redundant memories. The microprocessor program for the postal meter thus includes a subroutine for com-paring the data stored in the redundant memories, to providean error indication if the stored data in the two memories is different. While this technique increases the reliability of the stored data, there are certain conditions in which even this type of a redundant system will not enable the determination of an error. It must, of course, be emphasized that, in a postage meter, it is essential that the highest degree of reliability of the accounting data be obtained.
The present invention is therefore directed to the provision of an electronic postage meter having redundant memory in the nonvolatile accounting memory wherein the possibility of error conditions that are not detectable is minimized.
'i'~'~
Briefly stated, in accordance with one aspect of the invention, redundant nonvolatile memories are provided in the accounting unit of an electronic postage meter, the accounting unit having a microprocessor controlled to store accounting data redundantly in the two memories. In order to minimize the possibility of nondetectable errors, the two redundant mPmories are interconnected with the microprocessor, iOe., the microcomputer bus, by way of entirely separate groups of data and address lines As a result of the complete separation of the addressing and data, various error conditions, such as the shorting of a pair of address lines~ will not result in the erroneous addressing of both of the memoriesO
15 Accordingly, under such conditions, the shorting of a pair of address lines will not result in the storage of the same data in both of the memories, so that a comparison of stored data will result in the detection of the error condition.
In accordance with a further embodiment of the invention, corresponding data is applied redundantly to the redundant memories at different times. This may be effected by separately applying the data sequentially to the two memories. Alternatively, data may be 25 simultaneously applied to or retrieved from the two memories, with the data transferred at any ins~ant with respect to the two memories corresponding to different information. As a resùlt, instantaneously occurring transients on the transmission lines will not be likely 30 to affect the corresponding data stored in the two memories in the same fashion. This system thereby minimizes the possibility of nondetectable and/or noncorrectable errors resulting from transients.
In accordance with a still further embodiment of 35 the invention, the redundancy of the accounting system may be increased by also employing redundant microprocessors for controlling the two memories.
Other aspects of the invention are as follows:
In an electronic postage meter system having a micro-processor connected to a plurality o-f address lines, to a plurality of data lines, and to control line means, and 5 random access memory means connected to said address and data lines and to said control line means to enable storage of data in said memory means and reading of data from said memory means under control of said microprocessor, said microprocessor being arranged to selectively corltrol 10 said address and data lines; the improvement wherein said .random access memory means comprises first and second random access memories each connected to separa-te groups of said address lines and separate groups of said data lines, whereby data may be transferred to and from said 15 first and second random access memories independently of any common interconnection.
In an electronic postage meter having a micro-processor with a plurality of address lines, with a plurality of data lines, and with control line means, the 20 microprocessor being arranged to selectively con-trol said addre.ss and data lines, and random access memory means connected to said address and data lines and control line means to enable transfer of data between said random access memory means and microprocessor, sald postage 25 meter having a printer connected to be controlled by said microprocessor, and feedback means for signalling the setting of the printing means to the microprocessor' the improvement wherein said random access memory com-prises first and second random access memories, and means 30 independently responsive to feedback from said feedback means to update the accounting data in each of said first and second random access memories.
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In an electronic postage meter having a printing unit and an accoun-ting unit, the improvement wherein sald postage~meter comprises first and second microprocessor, first and second accounting registers connected to be separately controlled by said first and second micro-processors, said first and second rnicroprocessor having programs for separately updating their respective accounting registers, to account for the printing of postage by said meter, and means for comparing the accounting results in said first and second accounting registers for disabling said postage meter in the absence of a coincidence of data in said first and second registers.
In an electronic postage meter having a micro-processor, memory means coupled to said microprocessorfor storing postage accounting data and operational condition data, and a plurality of sensors for detecting operation conditions in said posage meter, the improve-ment wherein said microprocessor comprises means for checking said sensors periodically on a time-shared basis, said time sharing including at least verification of said stored accounting data, said checking being effected between successive operations of said meter by said microprocessor, said meter operation being in response to external operational inputs, said means for checking sensors including means for comparing data, said microprocessor presenting in said means for com-paring a unique pattern of said stored operational condition data for comparison with a pat-tern of actual operational condition data from said sensors, and means responsive to an absence of said unique pattern in the outputs of said sensors for indicating an error condition.
-3b-A microprocessor system including an address bus having a plurality of address l.ines, a data bus having a plurality of data lines, and a control bus having a plurality of control lines, a microprocessor connected to each of the address lines and data lines of said address and data bus, respectively, and coupled to said control bus, first and second random access memories, each of said first and second random ac~ess memories being connected to different lines of said address bus and different lines of said data bus, whereby said random access ~emories may be separately addressed.
r In order to still further minimize the possibility of printing postage without accounti.ng, the program of the microprocessor may be directed to the periodic testing of various critical parameters within the microprocessor, as part of a main routine, the testing routine only being interrupted, if necessary, during a conventional postage printing operation such as the prin~ing of postage and accounting therefor. As a consequence, the routine of the postage meter enables the continuous ~esting of such parameters, so that the postage meter may be disabled as soon as a condition exists that threatens the integrity of the accounting data. The error checking on a periodic basis may test not only the physical parameters, such as positions of various mechanical elements, but also may effect the comparison of the data stored in the two memories, as well as performing control sum checks to determine if the data stored in each memory is in accordance with determined relationships.
In order that the invention will be more clearly understood, it will no~ be disclosed in greater detail with reference to ~he accompanying drawings, wherein:
Fig. 1 is a block diagram of one embodiment of an electronic postage meter in accordance with the invention;
Fig. 2 is a time diagram illustrating the sequence of addressing the redundant memories in accordance with another embodiment of the invention;
Fig. 3 is a time diagram illustrating another sequence for addressing the redundant memories in accordance with the invention;
Fig. 4 is a block diagram of a portion of a modification of the system of Fig. 1;
Fig. S is a block diagram of a further modification of a portion of the system Gf Fig. l; and Fig. 6 is a block diagram of a further modification of the invention.
ReEerring now ~o the drawings, and more in particular to Flg. 1, therein is illustrated an electronic accounting system, such as may be employed in an electronic postage meter.
The system incorporates a central processing unic 10, such as a microprocessor, and a read only memory 11 storing programs ~or operation of the system. The central processing uni. 10 is coupled ~o one or more peripherals, such as, for example, the printing uni~ 12 and con~rol uni_ 13 of an electronic postage meter such as disclosed in aforesaid U. S. patent 4,301,507. In the system of Fig. 1 a secured housing 14 surrounds various components of the system, such as the central processin~! unit 10 and printin~ unit 12. As a consequence, it is necessar~ to provide ports between the central proces~ing unit and external control ~nit 13, in order to enable two-way communication between these units.
Preferably, the ports are in the for~ of a pair of one-way tranmission paths with opto couplers 15 and 16 at the secure housing, in order to inhibit the application of any electric potentials to the accounting unit witlout showing evidence of attempts to damage the unit. The opto couplers prererably provide for two-way ~.erial intercommunication be~ween the units on a bit-by-bit basis, in order to minimize the number of ports necessary in the housing.
In addition, it is desirable, as discussed in afore-mentioned U. S. patent 4,301,501 to enable in~ercommunicatlon between the prin~ing unit and central processing unit 10 by way of a similar pair of OptO coupling devices 17 and 18, these OptO
couplers preferably enabling serial two-way transmission on a bit-by-bit basis.
The printing unit, as well as the control unit may, if desired, have separate microprocessors incorporated therein, enabling the use of a plurality of dedicated mlcroprocessor systems. This not only enhances the security of the system, but also increases its reliability by restricting the required tasks of each microprocessor to a specific portion of the overall operation of the system. For example, the possibility of conflicting program requirement is thereby greatly reduced.
As illustrated in Fig. 1, a pair of random access memories 20, 21 is also provided within the secure housing. The random access memories 20 and 21 are preferably nonvolatile memories of conventional nature, so that accounting data may be stored therein withou~
105s even though external power to the system may be lost. For example only, the random access memories may be of the type employing battery back-up, EAROM or EPROM.
In accordance with the invention, the random access memory 20 is connected to the central processing unit 10 by way of a plurality of address lines 22 and a plurality of data lines 23. The random access memory is coupled to the central processing unit 10 by way of 25 another pluxality of address lines 24, and another plurality of data lines 25. In accordance with the invention it is necessary that both the address lines and the data lines coupled to the random access memories be different. For example, address lines A0 -30 A7 are of a conventional microprocessor system and maybe coupled to the random access memory 20l while address lines C0 - C7 are coupled to the random access memory 21. Similarly, conventional data lines B0 B3 may be coupled to the random access memory 20, with 35 data lines D4 - D7 being coupled to the random access memory 21.
In an accounting system that requires both security and reliability, it is desirable to provide redundancy. A
certain degree of redundancy may be obtained if the random access memories are connected to the central processing unit by separate data iines, although employing the same address lines. In such a system, the same data may be stored or retrieved from the two random access memories by way of their respective separate data lines, either simultaneously or at different times under control of the respective chip enable signals. While in many instances such an arrangement will enable the detection of errors, upon comparison of data in the two memories, there are in fact possibilities of error that cannot be detected. For example, if two o~-the address lines are inadvertently shorted together, either in the microprocessor itself or externally thereof,; ~hé same erroneous data will be stored in the tWQ random access memories, so that comparison of the data stored ln the two memories will not reveal an error condition.
The present invention overcomes this problem by employing an entirely different set of address lines of the address bus for addressing the two random access memories.
Preferably, of course~ the number of address lines, and the number of data linesl connected to each of the random access memories is the same. If, now, two address lines of the system are shorted together, for example, there is little likelihood that t~e resultant data stored in the two memories will be the same, so that the reliability of the ~ystem, in detection of errors, is greatly increased.
While the two random access memories may be simultan-eously addressed, employing their separate address lines, for the storage or recovery of the same information, this may also g ~ i6~
result in errors that could not be detectable or correctable. For example, it is possible tha~ a transient on the bus lines could interfere, in the same manner, with the simultaneously transmitted data.
Accordingly, in accordance with a further feature of the invention, as illustrated in Fig. 2~ the two memories are addressed, with respect to the same data, in a sequential manner. For example, all of the sequential bytes of a message may be first applied to, or received, from the first memory~ i.e., memory 1.
Following the transfer of this message, with respect to the first memory, the same message is then transmitted with respe~t to the second memory. It will, of course, be apparent that the term "byte" herein refers to data of a length equal to the number of data lines connected to each memory.
In order ~o reduce the time necessary for updating or reading the memory, each memory may be updated or read simultaneously but with different data being transmitted to or from each memory at any instant, as illustrated in Fig. 3.
Figs. 2 and 3 hence illustrate two techniques for minimizing the occurrence of undetectable errors resulting from the occurrence, for example, of transient pulses. It is apparent that it would be unlikely for the same interference to occur with sequentially transmitted data.
In a still further embodiment of the invention, the data may be stored in the two memories in a 30 different form. For example, the data stored in one or both of the memories may be coded, in order to further minimize the occurrence of errors undetectable by comparison of the data stored in the two memories. For example, as illustrated in Fig. 4, a coder/decoder 30 35 may be employed to code and decode the data stored in the random access memory 20, applied to and received from .
the data bus 23. A coder/decoder 31 may optionally be provided for coding and decoding data in the random access memory 21. If such an additional coder/decoder is employed, it is preferably that it have a different coding than that of the coder/decoder 30. -It is, of course, apparent that tne programs of the microprocessor have appropriate subroutines to determine, when a comparison be tween the da ta shows an i ncons i s tency, wh i ch memory bears the greater likelihood of correctness. In addition, ~urther routines may be provided in the event of an inability of the system to determine which of the data entries are error free, ~o provide an error indication that inhibits further operation of the system.
In the embodiment of the invention illustrated in Figs. 2 and 3, the two memories are addressed under the control of a fixed program responsive, for example, to a determined condition in the system. As a consequence, a determined relation-ship necessarily exists between the addre~sing times for the two memories. As a further modification, when separate memory units ~0 are provided, each memory unit may be made independently responsive to determined conditions. For example, when the accounting system is interconnected as il~ustrated in Fig. 1 to form a postage meter, the two memories may be independently responsive to each feedback of a printer setting, in order to update the separate memories, with an overriding subroutine being provided for cross-checking, i.e., comparing the data stored in the two memories. ~he independent control may be, for example, in the form of a memory controller. By thus making the two memory units operable more independently from one another, the chances of a greater error-free operation are substantially enhanced.
In order to insure proper operation, and thereby to maintain the integrity of the accounting information stored therein, electronic postage meters are provided with a plurality of sensors, such as ~he sensors 50, 51 and 52 illustrated coupled ~o the central processing uni~ 10 in Fig. 1. These sensors may be employed for checking a number of conditions within the meter, such as the position of a shuttex bar blocking operation of the meter, the positions of various interposers controlling operation of the posta~e meter, and various other condition sensors such as temperature and humidity. In non-electronic postage meters of the type employing microprocessors for control, such as disclosed in U.S. Patent 3,978,457 (case B-200), certain of these sensors are interrogated by a software routine upon the initial application of power to the meter. The positions of the various shutter bars and interposers, for example only, are also determined by software routines initiated by various externally originating conditions, such as, for example, manually controlled operations for initiating the printing of postage. The error checking routines for checking such sensors, as well as for checking additional conditions such as the correctness of data stored in the memories, are hence invoked only when specifically requested in response to external stimuli. Thus, even though a condition may have occurred between operations of the postage meter, that would eventually 23 cause it to cease operation, i.e., upon the next call for printin~ of postage the meter may still deceptively appear externally to be operable.
In accordance with a further feature of the invention, a program for the microprocessor effects the checking of the registers of the random access memory, as well as the various sensors, which may be optical switches, and all other critical data indicators at regular times during the course of operation of the postal meter, rather than simply checking these parameters at startup of the meter and uncalled for by external stimuli. By thus providing periodic checks, the possibility of error-free e~ operation is even more greatly enhanced. In otheYwords, the main routine of the postage meter, to which it always returns following the completion of, for example, a postage printing operation, includes software subroutines that periodically check critical parameters, such as the proper positioning of mechanical elements in the meter and the co~rect compa~ison of data in memories, as well as the correctness of the ~ata in accordance with control sum data. This technique enables the additional advantageous periodic checking of further sensors mounted, for example, to detect mechanical violation of the security of the ho~sing.
For this purpose, as illustrated in Fig. 5, the ; sensors 50, 51 and 52 may be connected to set a ~lurality of stages of a shift LegiSter 55. It will, o course, be under-/~U/~L stood that the number of such sensorsmay be greater than the three illustrated. The shift register 55 is coupled to the address and read out by the central processing unit 10 at determined times in the main program. A coded bit pattern is provided in the read only memo~ry 11, corresponding to the correct error-free conditions of the sensors. At the times during the program when the sensors are to be tested, the shift register, under control of the central processin~ unit, shifts out the existing bit pattern for comparison with the stored bit pattern in the read only memory 11. Thus, the status of the various sensors in the meter may be continually determined, so that the meter may be disabled as soon as a condition exis~s that threatens the integrity of the meter.
13 ~2~
The shift register may be~ of course, shifted under the control of the microprocessor, by the conventional clock source ln the system.
Alternatively, the shift register may be preprogrammed, in accordance with a deterrnined unique pattern, so that the output of the shift register may be compared with a predetermined "good'l condition. The information available from an eight or 16 bit pattern code, in accordance with this embodiment of the invention, may thus provide a very large degree of sophistication for the determination of any appropriate error checking for diagnostic purposes, using signature analysis techniques. This form of error checking may be imposed upon various system constraints for both diagnostic and possible error correction on an automatic basis.
In the system illustrated in Fig. 1, as discussed above, the printing unit 12 and control unit 13 may include dedicated microprocessors for controlling the specific functions of these units, thereby enabling the use of a dedicated system for the accounting unit including the central processing unit 10, read only memory 11 and random access memories 20 and 21. In further embodiments of the invention, the printing unit 12 may further incorporate a random access memory 60, and/or the control unit 13 may include a nonvolatile random access memory 61.
In a further embodiment of t~,e invention, as illustrated in Fig. 6, the nonvolatile random access memories 20, 21 of the accounting system are intercoupled with separate microprocessors 60 and 61, each of the microprocessors having S a separate read only memory 62, 63 respectively, for storing the operating programs for the respective microprocessor. It will, of course, be apparent in the arrangement of Fig. 6, as well as in the arrangement of Fig. 1, that the read only memory, as well as other components of the system, may be incorporated in the same integrated circuit as the microprocessor.
Since the two microprocessors are separately controlled, and have separate address and data lines 64, 65 respectively, the two random access memories are thereby entirely independently controlled. The two mieroprocessors separately communicate with the control unit 13 and printer 12 by way of separate selecting switehes 7~ and 71 addressed by the respective microprocessors 60 and 61. As a consequence, each of the microprocessors may receive signals from the printer and control unit, and each of them may also transmit messages. In addition, data processed in the two microprocessors may be compared by means of a data latch 72 controllable by either of the micro-processors.
In the arrangement of Fig. 6, input data received, for example, from the keyboard 73 or other peripheral device coupled to the control unit 13, is applied by way of the opto couplers 15 and 16 and the selecting switches 70 and 71 to the two micro-processor systems. Alternatively, of course, the data may be input-to the two microprocessors in response to an interrupt signal. The two microprocessors, in response to the input information, perform the necessary accounting procedures independently of one another, with respect to the data stored in
This invention relates to electronic accountlng systems, and is especially directed to an electronic postage meter having a microprocessor controlled electronic account-ing unit with nonvolatile random access mernory.
An electronic postage meter having an accounting unit with a microprocessor, and nonvolatile memory for storing accounting data, is disclosed, for example, in U. S.
Patent No. 4,301,507, issued November 17, 1981, and assigned to the assignee of the present application. In this system the accounting data is stored in the random access memory and retrieved from the random access memory by way of common address and data lines of the microcomputer system.
While in most instances it can be assured that the account-ing data stored in the memory will be correct, there are certain conditions that can occur that can result in non-detectable errors in the data.
In order to overcome such problems, it has been proposed to employ redundant memories. The microprocessor program for the postal meter thus includes a subroutine for com-paring the data stored in the redundant memories, to providean error indication if the stored data in the two memories is different. While this technique increases the reliability of the stored data, there are certain conditions in which even this type of a redundant system will not enable the determination of an error. It must, of course, be emphasized that, in a postage meter, it is essential that the highest degree of reliability of the accounting data be obtained.
The present invention is therefore directed to the provision of an electronic postage meter having redundant memory in the nonvolatile accounting memory wherein the possibility of error conditions that are not detectable is minimized.
'i'~'~
Briefly stated, in accordance with one aspect of the invention, redundant nonvolatile memories are provided in the accounting unit of an electronic postage meter, the accounting unit having a microprocessor controlled to store accounting data redundantly in the two memories. In order to minimize the possibility of nondetectable errors, the two redundant mPmories are interconnected with the microprocessor, iOe., the microcomputer bus, by way of entirely separate groups of data and address lines As a result of the complete separation of the addressing and data, various error conditions, such as the shorting of a pair of address lines~ will not result in the erroneous addressing of both of the memoriesO
15 Accordingly, under such conditions, the shorting of a pair of address lines will not result in the storage of the same data in both of the memories, so that a comparison of stored data will result in the detection of the error condition.
In accordance with a further embodiment of the invention, corresponding data is applied redundantly to the redundant memories at different times. This may be effected by separately applying the data sequentially to the two memories. Alternatively, data may be 25 simultaneously applied to or retrieved from the two memories, with the data transferred at any ins~ant with respect to the two memories corresponding to different information. As a resùlt, instantaneously occurring transients on the transmission lines will not be likely 30 to affect the corresponding data stored in the two memories in the same fashion. This system thereby minimizes the possibility of nondetectable and/or noncorrectable errors resulting from transients.
In accordance with a still further embodiment of 35 the invention, the redundancy of the accounting system may be increased by also employing redundant microprocessors for controlling the two memories.
Other aspects of the invention are as follows:
In an electronic postage meter system having a micro-processor connected to a plurality o-f address lines, to a plurality of data lines, and to control line means, and 5 random access memory means connected to said address and data lines and to said control line means to enable storage of data in said memory means and reading of data from said memory means under control of said microprocessor, said microprocessor being arranged to selectively corltrol 10 said address and data lines; the improvement wherein said .random access memory means comprises first and second random access memories each connected to separa-te groups of said address lines and separate groups of said data lines, whereby data may be transferred to and from said 15 first and second random access memories independently of any common interconnection.
In an electronic postage meter having a micro-processor with a plurality of address lines, with a plurality of data lines, and with control line means, the 20 microprocessor being arranged to selectively con-trol said addre.ss and data lines, and random access memory means connected to said address and data lines and control line means to enable transfer of data between said random access memory means and microprocessor, sald postage 25 meter having a printer connected to be controlled by said microprocessor, and feedback means for signalling the setting of the printing means to the microprocessor' the improvement wherein said random access memory com-prises first and second random access memories, and means 30 independently responsive to feedback from said feedback means to update the accounting data in each of said first and second random access memories.
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In an electronic postage meter having a printing unit and an accoun-ting unit, the improvement wherein sald postage~meter comprises first and second microprocessor, first and second accounting registers connected to be separately controlled by said first and second micro-processors, said first and second rnicroprocessor having programs for separately updating their respective accounting registers, to account for the printing of postage by said meter, and means for comparing the accounting results in said first and second accounting registers for disabling said postage meter in the absence of a coincidence of data in said first and second registers.
In an electronic postage meter having a micro-processor, memory means coupled to said microprocessorfor storing postage accounting data and operational condition data, and a plurality of sensors for detecting operation conditions in said posage meter, the improve-ment wherein said microprocessor comprises means for checking said sensors periodically on a time-shared basis, said time sharing including at least verification of said stored accounting data, said checking being effected between successive operations of said meter by said microprocessor, said meter operation being in response to external operational inputs, said means for checking sensors including means for comparing data, said microprocessor presenting in said means for com-paring a unique pattern of said stored operational condition data for comparison with a pat-tern of actual operational condition data from said sensors, and means responsive to an absence of said unique pattern in the outputs of said sensors for indicating an error condition.
-3b-A microprocessor system including an address bus having a plurality of address l.ines, a data bus having a plurality of data lines, and a control bus having a plurality of control lines, a microprocessor connected to each of the address lines and data lines of said address and data bus, respectively, and coupled to said control bus, first and second random access memories, each of said first and second random ac~ess memories being connected to different lines of said address bus and different lines of said data bus, whereby said random access ~emories may be separately addressed.
r In order to still further minimize the possibility of printing postage without accounti.ng, the program of the microprocessor may be directed to the periodic testing of various critical parameters within the microprocessor, as part of a main routine, the testing routine only being interrupted, if necessary, during a conventional postage printing operation such as the prin~ing of postage and accounting therefor. As a consequence, the routine of the postage meter enables the continuous ~esting of such parameters, so that the postage meter may be disabled as soon as a condition exists that threatens the integrity of the accounting data. The error checking on a periodic basis may test not only the physical parameters, such as positions of various mechanical elements, but also may effect the comparison of the data stored in the two memories, as well as performing control sum checks to determine if the data stored in each memory is in accordance with determined relationships.
In order that the invention will be more clearly understood, it will no~ be disclosed in greater detail with reference to ~he accompanying drawings, wherein:
Fig. 1 is a block diagram of one embodiment of an electronic postage meter in accordance with the invention;
Fig. 2 is a time diagram illustrating the sequence of addressing the redundant memories in accordance with another embodiment of the invention;
Fig. 3 is a time diagram illustrating another sequence for addressing the redundant memories in accordance with the invention;
Fig. 4 is a block diagram of a portion of a modification of the system of Fig. 1;
Fig. S is a block diagram of a further modification of a portion of the system Gf Fig. l; and Fig. 6 is a block diagram of a further modification of the invention.
ReEerring now ~o the drawings, and more in particular to Flg. 1, therein is illustrated an electronic accounting system, such as may be employed in an electronic postage meter.
The system incorporates a central processing unic 10, such as a microprocessor, and a read only memory 11 storing programs ~or operation of the system. The central processing uni. 10 is coupled ~o one or more peripherals, such as, for example, the printing uni~ 12 and con~rol uni_ 13 of an electronic postage meter such as disclosed in aforesaid U. S. patent 4,301,507. In the system of Fig. 1 a secured housing 14 surrounds various components of the system, such as the central processin~! unit 10 and printin~ unit 12. As a consequence, it is necessar~ to provide ports between the central proces~ing unit and external control ~nit 13, in order to enable two-way communication between these units.
Preferably, the ports are in the for~ of a pair of one-way tranmission paths with opto couplers 15 and 16 at the secure housing, in order to inhibit the application of any electric potentials to the accounting unit witlout showing evidence of attempts to damage the unit. The opto couplers prererably provide for two-way ~.erial intercommunication be~ween the units on a bit-by-bit basis, in order to minimize the number of ports necessary in the housing.
In addition, it is desirable, as discussed in afore-mentioned U. S. patent 4,301,501 to enable in~ercommunicatlon between the prin~ing unit and central processing unit 10 by way of a similar pair of OptO coupling devices 17 and 18, these OptO
couplers preferably enabling serial two-way transmission on a bit-by-bit basis.
The printing unit, as well as the control unit may, if desired, have separate microprocessors incorporated therein, enabling the use of a plurality of dedicated mlcroprocessor systems. This not only enhances the security of the system, but also increases its reliability by restricting the required tasks of each microprocessor to a specific portion of the overall operation of the system. For example, the possibility of conflicting program requirement is thereby greatly reduced.
As illustrated in Fig. 1, a pair of random access memories 20, 21 is also provided within the secure housing. The random access memories 20 and 21 are preferably nonvolatile memories of conventional nature, so that accounting data may be stored therein withou~
105s even though external power to the system may be lost. For example only, the random access memories may be of the type employing battery back-up, EAROM or EPROM.
In accordance with the invention, the random access memory 20 is connected to the central processing unit 10 by way of a plurality of address lines 22 and a plurality of data lines 23. The random access memory is coupled to the central processing unit 10 by way of 25 another pluxality of address lines 24, and another plurality of data lines 25. In accordance with the invention it is necessary that both the address lines and the data lines coupled to the random access memories be different. For example, address lines A0 -30 A7 are of a conventional microprocessor system and maybe coupled to the random access memory 20l while address lines C0 - C7 are coupled to the random access memory 21. Similarly, conventional data lines B0 B3 may be coupled to the random access memory 20, with 35 data lines D4 - D7 being coupled to the random access memory 21.
In an accounting system that requires both security and reliability, it is desirable to provide redundancy. A
certain degree of redundancy may be obtained if the random access memories are connected to the central processing unit by separate data iines, although employing the same address lines. In such a system, the same data may be stored or retrieved from the two random access memories by way of their respective separate data lines, either simultaneously or at different times under control of the respective chip enable signals. While in many instances such an arrangement will enable the detection of errors, upon comparison of data in the two memories, there are in fact possibilities of error that cannot be detected. For example, if two o~-the address lines are inadvertently shorted together, either in the microprocessor itself or externally thereof,; ~hé same erroneous data will be stored in the tWQ random access memories, so that comparison of the data stored ln the two memories will not reveal an error condition.
The present invention overcomes this problem by employing an entirely different set of address lines of the address bus for addressing the two random access memories.
Preferably, of course~ the number of address lines, and the number of data linesl connected to each of the random access memories is the same. If, now, two address lines of the system are shorted together, for example, there is little likelihood that t~e resultant data stored in the two memories will be the same, so that the reliability of the ~ystem, in detection of errors, is greatly increased.
While the two random access memories may be simultan-eously addressed, employing their separate address lines, for the storage or recovery of the same information, this may also g ~ i6~
result in errors that could not be detectable or correctable. For example, it is possible tha~ a transient on the bus lines could interfere, in the same manner, with the simultaneously transmitted data.
Accordingly, in accordance with a further feature of the invention, as illustrated in Fig. 2~ the two memories are addressed, with respect to the same data, in a sequential manner. For example, all of the sequential bytes of a message may be first applied to, or received, from the first memory~ i.e., memory 1.
Following the transfer of this message, with respect to the first memory, the same message is then transmitted with respe~t to the second memory. It will, of course, be apparent that the term "byte" herein refers to data of a length equal to the number of data lines connected to each memory.
In order ~o reduce the time necessary for updating or reading the memory, each memory may be updated or read simultaneously but with different data being transmitted to or from each memory at any instant, as illustrated in Fig. 3.
Figs. 2 and 3 hence illustrate two techniques for minimizing the occurrence of undetectable errors resulting from the occurrence, for example, of transient pulses. It is apparent that it would be unlikely for the same interference to occur with sequentially transmitted data.
In a still further embodiment of the invention, the data may be stored in the two memories in a 30 different form. For example, the data stored in one or both of the memories may be coded, in order to further minimize the occurrence of errors undetectable by comparison of the data stored in the two memories. For example, as illustrated in Fig. 4, a coder/decoder 30 35 may be employed to code and decode the data stored in the random access memory 20, applied to and received from .
the data bus 23. A coder/decoder 31 may optionally be provided for coding and decoding data in the random access memory 21. If such an additional coder/decoder is employed, it is preferably that it have a different coding than that of the coder/decoder 30. -It is, of course, apparent that tne programs of the microprocessor have appropriate subroutines to determine, when a comparison be tween the da ta shows an i ncons i s tency, wh i ch memory bears the greater likelihood of correctness. In addition, ~urther routines may be provided in the event of an inability of the system to determine which of the data entries are error free, ~o provide an error indication that inhibits further operation of the system.
In the embodiment of the invention illustrated in Figs. 2 and 3, the two memories are addressed under the control of a fixed program responsive, for example, to a determined condition in the system. As a consequence, a determined relation-ship necessarily exists between the addre~sing times for the two memories. As a further modification, when separate memory units ~0 are provided, each memory unit may be made independently responsive to determined conditions. For example, when the accounting system is interconnected as il~ustrated in Fig. 1 to form a postage meter, the two memories may be independently responsive to each feedback of a printer setting, in order to update the separate memories, with an overriding subroutine being provided for cross-checking, i.e., comparing the data stored in the two memories. ~he independent control may be, for example, in the form of a memory controller. By thus making the two memory units operable more independently from one another, the chances of a greater error-free operation are substantially enhanced.
In order to insure proper operation, and thereby to maintain the integrity of the accounting information stored therein, electronic postage meters are provided with a plurality of sensors, such as ~he sensors 50, 51 and 52 illustrated coupled ~o the central processing uni~ 10 in Fig. 1. These sensors may be employed for checking a number of conditions within the meter, such as the position of a shuttex bar blocking operation of the meter, the positions of various interposers controlling operation of the posta~e meter, and various other condition sensors such as temperature and humidity. In non-electronic postage meters of the type employing microprocessors for control, such as disclosed in U.S. Patent 3,978,457 (case B-200), certain of these sensors are interrogated by a software routine upon the initial application of power to the meter. The positions of the various shutter bars and interposers, for example only, are also determined by software routines initiated by various externally originating conditions, such as, for example, manually controlled operations for initiating the printing of postage. The error checking routines for checking such sensors, as well as for checking additional conditions such as the correctness of data stored in the memories, are hence invoked only when specifically requested in response to external stimuli. Thus, even though a condition may have occurred between operations of the postage meter, that would eventually 23 cause it to cease operation, i.e., upon the next call for printin~ of postage the meter may still deceptively appear externally to be operable.
In accordance with a further feature of the invention, a program for the microprocessor effects the checking of the registers of the random access memory, as well as the various sensors, which may be optical switches, and all other critical data indicators at regular times during the course of operation of the postal meter, rather than simply checking these parameters at startup of the meter and uncalled for by external stimuli. By thus providing periodic checks, the possibility of error-free e~ operation is even more greatly enhanced. In otheYwords, the main routine of the postage meter, to which it always returns following the completion of, for example, a postage printing operation, includes software subroutines that periodically check critical parameters, such as the proper positioning of mechanical elements in the meter and the co~rect compa~ison of data in memories, as well as the correctness of the ~ata in accordance with control sum data. This technique enables the additional advantageous periodic checking of further sensors mounted, for example, to detect mechanical violation of the security of the ho~sing.
For this purpose, as illustrated in Fig. 5, the ; sensors 50, 51 and 52 may be connected to set a ~lurality of stages of a shift LegiSter 55. It will, o course, be under-/~U/~L stood that the number of such sensorsmay be greater than the three illustrated. The shift register 55 is coupled to the address and read out by the central processing unit 10 at determined times in the main program. A coded bit pattern is provided in the read only memo~ry 11, corresponding to the correct error-free conditions of the sensors. At the times during the program when the sensors are to be tested, the shift register, under control of the central processin~ unit, shifts out the existing bit pattern for comparison with the stored bit pattern in the read only memory 11. Thus, the status of the various sensors in the meter may be continually determined, so that the meter may be disabled as soon as a condition exis~s that threatens the integrity of the meter.
13 ~2~
The shift register may be~ of course, shifted under the control of the microprocessor, by the conventional clock source ln the system.
Alternatively, the shift register may be preprogrammed, in accordance with a deterrnined unique pattern, so that the output of the shift register may be compared with a predetermined "good'l condition. The information available from an eight or 16 bit pattern code, in accordance with this embodiment of the invention, may thus provide a very large degree of sophistication for the determination of any appropriate error checking for diagnostic purposes, using signature analysis techniques. This form of error checking may be imposed upon various system constraints for both diagnostic and possible error correction on an automatic basis.
In the system illustrated in Fig. 1, as discussed above, the printing unit 12 and control unit 13 may include dedicated microprocessors for controlling the specific functions of these units, thereby enabling the use of a dedicated system for the accounting unit including the central processing unit 10, read only memory 11 and random access memories 20 and 21. In further embodiments of the invention, the printing unit 12 may further incorporate a random access memory 60, and/or the control unit 13 may include a nonvolatile random access memory 61.
In a further embodiment of t~,e invention, as illustrated in Fig. 6, the nonvolatile random access memories 20, 21 of the accounting system are intercoupled with separate microprocessors 60 and 61, each of the microprocessors having S a separate read only memory 62, 63 respectively, for storing the operating programs for the respective microprocessor. It will, of course, be apparent in the arrangement of Fig. 6, as well as in the arrangement of Fig. 1, that the read only memory, as well as other components of the system, may be incorporated in the same integrated circuit as the microprocessor.
Since the two microprocessors are separately controlled, and have separate address and data lines 64, 65 respectively, the two random access memories are thereby entirely independently controlled. The two mieroprocessors separately communicate with the control unit 13 and printer 12 by way of separate selecting switehes 7~ and 71 addressed by the respective microprocessors 60 and 61. As a consequence, each of the microprocessors may receive signals from the printer and control unit, and each of them may also transmit messages. In addition, data processed in the two microprocessors may be compared by means of a data latch 72 controllable by either of the micro-processors.
In the arrangement of Fig. 6, input data received, for example, from the keyboard 73 or other peripheral device coupled to the control unit 13, is applied by way of the opto couplers 15 and 16 and the selecting switches 70 and 71 to the two micro-processor systems. Alternatively, of course, the data may be input-to the two microprocessors in response to an interrupt signal. The two microprocessors, in response to the input information, perform the necessary accounting procedures independently of one another, with respect to the data stored in
2~
~he respective random access memories. I`he programs of the two microprocessors enable interchange of accounting data for comparison, for example, on a contention basis, by way of the data latch 72. The programs of the two microprocessors may enable, for e~ample, only one of the microprocessors to control the display 75 coupled to the control unit 13, and/or to control the printer 12. Alternatively, of course, redundant control may be employed, whereby the control of a printer function, or the control of a display, may require the common occurrence of the output function from the two micro~rocessors.
This may be effected, for example, in the manner disclosed in aforementioned U. S. patent 4,301,507, by controlling a pair of s~ries transistors separately by the two microprocessors, whereby the common output of the series transistors effects the desired control. It is, of course, apparent that other techn~ques may be employed ~or this purpose.
`~ The arrangement of Fig. 6 thereby increases the redundancy of the system, so that even a failure in a micro-~0 processor will enable the determination, with great reliability, the occurrence of an error condition that may require the disabiing of the meter.
In the system of ~ig. 6, the printer 12 is more completely shown as comprised of a microprocessor 80 coupled to the opto couplers 17 and 18, and controlling a print setter 81. The print setter 81 sets the printwheels in a printer 82, the setting of the printwheels being fed back to the micro-processor 80 by way of a feedback path 83. This feedback enables the printer unit to determine if an error has occurred in the setting of the printwheels, and ~hereby to disable the 16 ~ 3~ ~
meter in the event of an erroneous setting The feedback setting may be applied from the microprocessor 80 to the opto couplers 17 and 18, thereby enabling the ~wo microprocessors in the accounting system to be separately responsive to the feedback signals, for accounting for postage to be printed.
It is, of course, apparent that suitable control lines are provided connected to the microprocessor and xandom access m~mories, in the disclosed systems of the invention, in the conventional manner, for controlling the systems The function of disabling the meter, in the illustrated embodiments of the invention, may be ~ffected by inhibiting, under program control, operation of the mechanical elements of the meter.
Alternatively, the existence of an error requiring disabling of the meter may direct the routines of the microprocessor to perform an endless loop. Errors that do not require disabling of the meter may be displayed, 20 under control of the microprocessor, by means of the display 73 coupled to the external control unit.
While the invention has been disclosed and described with reference to a limited number of embodiments~ it will be apparent that variations and 25 modifications may be made therein, and it is intended in the ollowing claims to cover each such variation and modification as falls within the true spirit and scope of the invention.
Other types of memory can, of course, be employed 30 instead of RAM such as serial memory~
~he respective random access memories. I`he programs of the two microprocessors enable interchange of accounting data for comparison, for example, on a contention basis, by way of the data latch 72. The programs of the two microprocessors may enable, for e~ample, only one of the microprocessors to control the display 75 coupled to the control unit 13, and/or to control the printer 12. Alternatively, of course, redundant control may be employed, whereby the control of a printer function, or the control of a display, may require the common occurrence of the output function from the two micro~rocessors.
This may be effected, for example, in the manner disclosed in aforementioned U. S. patent 4,301,507, by controlling a pair of s~ries transistors separately by the two microprocessors, whereby the common output of the series transistors effects the desired control. It is, of course, apparent that other techn~ques may be employed ~or this purpose.
`~ The arrangement of Fig. 6 thereby increases the redundancy of the system, so that even a failure in a micro-~0 processor will enable the determination, with great reliability, the occurrence of an error condition that may require the disabiing of the meter.
In the system of ~ig. 6, the printer 12 is more completely shown as comprised of a microprocessor 80 coupled to the opto couplers 17 and 18, and controlling a print setter 81. The print setter 81 sets the printwheels in a printer 82, the setting of the printwheels being fed back to the micro-processor 80 by way of a feedback path 83. This feedback enables the printer unit to determine if an error has occurred in the setting of the printwheels, and ~hereby to disable the 16 ~ 3~ ~
meter in the event of an erroneous setting The feedback setting may be applied from the microprocessor 80 to the opto couplers 17 and 18, thereby enabling the ~wo microprocessors in the accounting system to be separately responsive to the feedback signals, for accounting for postage to be printed.
It is, of course, apparent that suitable control lines are provided connected to the microprocessor and xandom access m~mories, in the disclosed systems of the invention, in the conventional manner, for controlling the systems The function of disabling the meter, in the illustrated embodiments of the invention, may be ~ffected by inhibiting, under program control, operation of the mechanical elements of the meter.
Alternatively, the existence of an error requiring disabling of the meter may direct the routines of the microprocessor to perform an endless loop. Errors that do not require disabling of the meter may be displayed, 20 under control of the microprocessor, by means of the display 73 coupled to the external control unit.
While the invention has been disclosed and described with reference to a limited number of embodiments~ it will be apparent that variations and 25 modifications may be made therein, and it is intended in the ollowing claims to cover each such variation and modification as falls within the true spirit and scope of the invention.
Other types of memory can, of course, be employed 30 instead of RAM such as serial memory~
Claims (21)
1. In an electronic postage meter system having a microprocessor connected to a plurality of address lines, to a plurality of data lines, and to control line means, and random access memory means connected to said address and data lines and to said control line means to enable storage of data in said memory means and reading of data from said memory means under control of said microprocessor, said microprocessor being arranged to selectively control said address and data lines; the improvement wherein said random access memory means comprises first and second random access memories each connected to separate groups of said address lines and separate groups of said data lines, whereby data may be transferred to and from said first and second random access memories independently of any common interconnection.
2. The electronic postage meter system of claim 1 further comprising permanent memory means for storing postage meter programs for controlling said microprocessor, said routines addressing said first and second random access memories time sequentially for transfer of identical data thereto.
3. The electronic postage meter system of claim 1 further comprising permanent memory means having postage meter programs for controlling said microprocessor, said programs addressing said first and second random access memories with time overlap, to transfer the identical data to and from said first and second random access memories respectively whereby identical data is transferred to and from said first and second random access memories at different times while both of said random access memories are addressed in a plurality of successive addressing cycles of said microprocessor.
4. In an electronic postage meter having a microprocessor with a plurality of address lines, with a plurality of data lines, and with control line means, the microprocessor being arranged to selectively control said address and data lines, and random access memory means connected to said address and data lines and control line means to enable transfer of data between said random access memory means and microprocessor, said postage meter having a printer connected to be controlled by said microprocessor, and feedback means for signalling the setting of the printing means to the microprocessor; the improvement wherein said random access memory comprises first and second random access memories, and means independently responsive to feedback from said feedback means to update the accounting data in each of said first and second random access memories.
5. In an electronic postage meter having a printing unit and an accounting unit; the improvement wherein said postage meter comprises first and second microprocessors, first and second accounting registers connected to be separately controlled by said first and second microprocessors, said first and second microprocessors having programs for separately updating their respective accounting registers, to account for the printing of postage by said meter, and means for comparing the accounting results in said first and second accounting registers for disabling said postage meter in the absence of a coincidence of data in said first and second registers.
6. The electronic postage meter of claim 5 wherein said routines of said first and second microprocessors store data in their respective accounting memories with different coding.
7. The electronic postage meter of claim 5 wherein said printing unit comprises a further microprocessor having a postage printing program for controlling printing of said postage meter.
8. In an electronic postage meter having a microprocessor, memory means coupled to said microprocessor for storing postage accounting data and operational condition data, and a plurality of sensors for detecting operation conditions in said postage meter, the improvement wherein said microprocessor comprises means for checking said sensors periodically on a time-shared basis, said time sharing including at least verification of said stored accounting data, said checking being effected between successive operations of said meter by said microprocessor, said meter operation being in response to external operational inputs, said means for checking sensors including means for comparing data, said microprocessor presenting in said means for comparing a unique pattern of said stored operational condition data for comparison with a pattern of actual operational condition data from said sensors, and means responsive to an absence of said unique pattern in the outputs of said sensors for indicating an error condition.
9. A microprocessor system including an address bus having a plurality of address lines, a data bus having a plurality of data lines, and a control bus having a plurality of control lines, a microprocessor connected to each of the address lines and data lines of said address and data buses, respectively, and coupled to said control bus, first and second random access memories, each of said first and second random access memories being connected to different lines of said address bus and different lines of said data bus, whereby said random access memories may be separately addressed.
10. The microprocessor system of claim 9 further including a program memory for controlling the operation of said microprocessor and having a program for addressing said first and second random access memories to store the same data therein.
11. The microprocessor system of claim 10 wherein said program addresses corresponding storage locations of said first and second memories, wherein corresponding data is stored in or read therefrom at different times.
12. The microprocessor system of claim 11 wherein said program simultaneously stores different data in said first and second memories at noncorresponding address locations, whereby instantaneously occurring errors affect the data stored to said first and second memories in different manners.
13. The microprocessor system of claim 3 wherein said random memories are nonvolatile memories.
14. The microprocessor system of claim 13 further comprising means responsive to differences in data stored in first and second memories for disabling further operation of said microprocessor.
15. The electronic postage meter of claim 8 wherein said sensors are arranged to sense physical conditions of said meter.
16. The electronic postage meter of claim 8 wherein one of said sensors is arranged to sense the position of a shutter bar which blocks the operation of said meter.
17. The electronic postage meter of claim 8 wherein one of said ssensors is connected to sense temperature.
18. The electronic postage meter of claim 8 wherein one of said sensors is connected to sense humidity.
19. The electronic postage meter of claim 8 wherein said postage meter has a memory, and said means for checking said sensors periodically checks the correctness of data stored in said memory.
20. The electronic postage meter of claim 8 wherein said memory means includes a pair of memories for storing postage meter data and said means for checking said sensors periodically compares information stored in said memories.
21. The electronic postage meter of claim 8 wherein said meter operation is responsive to randomly timed external operational inputs.
Applications Claiming Priority (2)
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|---|---|---|---|
| US34387782A | 1982-01-29 | 1982-01-29 | |
| US343,877 | 1982-01-29 |
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| CA1206619A true CA1206619A (en) | 1986-06-24 |
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| JP (1) | JPH0797417B2 (en) |
| CA (1) | CA1206619A (en) |
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| JPS6162161A (en) * | 1984-08-22 | 1986-03-31 | ピツトネイ・ボウズ・インコーポレーテツド | Non-volatile memory having real time and power down data memory capacity for electronic postage meter |
| CA1247254A (en) * | 1985-03-12 | 1988-12-20 | Peter C. Digiulio | Postage meter with a non-volatile memory security circuit |
| JPS62168292A (en) * | 1985-10-15 | 1987-07-24 | ピツトネイ・ボウズ・インコ−ポレ−テツド | Dual redundant electronic postage meter |
| DE3685191D1 (en) * | 1985-10-16 | 1992-06-11 | Pitney Bowes Inc | SYSTEMS FOR THE NON-VOLATILE STORAGE OF DATA AND MACHINE SYSTEMS. |
| US4817004A (en) * | 1985-10-16 | 1989-03-28 | Pitney Bowes Inc. | Electronic postage meter operating system |
| US4805109A (en) * | 1985-10-16 | 1989-02-14 | Pitney Bowes Inc. | Nonvolatile memory protection arrangement for electronic postage meter system having plural nonvolatile memories |
| US4845632A (en) * | 1985-10-16 | 1989-07-04 | Pitney Bowes Inc. | Electonic postage meter system having arrangement for rapid storage of critical postage accounting data in plural nonvolatile memories |
| ATE175512T1 (en) * | 1986-09-02 | 1999-01-15 | Pitney Bowes Inc | TRANSACTION SYSTEM WITH MODULAR PRINTER |
| FR2620259B1 (en) * | 1987-03-31 | 1989-11-24 | Smh Alcatel | DEVICE FOR COUPLING NON-VOLATILE MEMORIES IN AN ELECTRONIC MACHINE AND POSTAGE MACHINE USING THE SAME |
| WO1989011134A1 (en) * | 1988-05-09 | 1989-11-16 | Ascom Hasler Ag | Electronic computing and storage system for franking machines |
| GB8819647D0 (en) * | 1988-08-18 | 1988-09-21 | Alcatel Business Systems | Franking machine |
| US5661808A (en) | 1995-04-27 | 1997-08-26 | Srs Labs, Inc. | Stereo enhancement system |
| GB9601588D0 (en) * | 1996-01-26 | 1996-03-27 | Neopost Ltd | Postage meter |
| DE59710554D1 (en) | 1996-01-31 | 2003-09-18 | Francotyp Postalia Ag | franking machine |
| US5970152A (en) * | 1996-04-30 | 1999-10-19 | Srs Labs, Inc. | Audio enhancement system for use in a surround sound environment |
| US5912976A (en) | 1996-11-07 | 1999-06-15 | Srs Labs, Inc. | Multi-channel audio enhancement system for use in recording and playback and methods for providing same |
| GB2319217B (en) * | 1996-11-18 | 2001-07-25 | Neopost Ltd | Postage meter and postage indicia printed thereby |
| DE29913639U1 (en) * | 1999-07-30 | 2000-01-13 | Francotyp Postalia Gmbh | Franking and franking machine |
| US7277767B2 (en) | 1999-12-10 | 2007-10-02 | Srs Labs, Inc. | System and method for enhanced streaming audio |
| US9088858B2 (en) | 2011-01-04 | 2015-07-21 | Dts Llc | Immersive audio rendering system |
| US9164724B2 (en) | 2011-08-26 | 2015-10-20 | Dts Llc | Audio adjustment system |
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| US3544777A (en) * | 1967-11-06 | 1970-12-01 | Trw Inc | Two memory self-correcting system |
| US3978457A (en) | 1974-12-23 | 1976-08-31 | Pitney-Bowes, Inc. | Microcomputerized electronic postage meter system |
| JPS5227979A (en) * | 1975-07-18 | 1977-03-02 | Mitsubishi Electric Corp | Signal transmitter device |
| US4404647A (en) * | 1978-03-16 | 1983-09-13 | International Business Machines Corp. | Dynamic array error recovery |
| US4253015A (en) * | 1979-03-28 | 1981-02-24 | Pitney Bowes Inc. | Electronic postage meter having an accounting system independent of power failure |
| DE2916840A1 (en) * | 1979-04-26 | 1980-11-06 | Postalia Gmbh | ELECTRONICALLY CONTROLLED FRANKING MACHINE |
| CA1160744A (en) * | 1979-05-09 | 1984-01-17 | Jesse T. Quatse | Electronic postage meter having improved security and fault tolerance features |
| DE2939935A1 (en) * | 1979-09-28 | 1981-04-09 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | SECURE DATA PROCESSING DEVICE |
| US4301507A (en) * | 1979-10-30 | 1981-11-17 | Pitney Bowes Inc. | Electronic postage meter having plural computing systems |
| JPS56130613A (en) * | 1980-03-19 | 1981-10-13 | Hitachi Ltd | Automated device for periodic inspection |
| DE3024370C2 (en) * | 1980-06-27 | 1987-01-02 | Siemens AG, 1000 Berlin und 8000 München | Redundant tax system |
| GB2079223B (en) * | 1980-07-09 | 1984-03-14 | Roneo Alcatel Ltd | Postal franking meter |
-
1983
- 1983-01-20 CA CA000419915A patent/CA1206619A/en not_active Expired
- 1983-01-25 EP EP92114140A patent/EP0513880B1/en not_active Expired - Lifetime
- 1983-01-25 DE DE3382835T patent/DE3382835D1/en not_active Expired - Lifetime
- 1983-01-25 DE DE1983100639 patent/DE85385T1/en active Pending
- 1983-01-25 DE DE19833382810 patent/DE3382810T2/en not_active Expired - Lifetime
- 1983-01-25 EP EP96110413A patent/EP0736846B1/en not_active Revoked
- 1983-01-25 DE DE19833382744 patent/DE3382744T3/en not_active Expired - Lifetime
- 1983-01-25 EP EP83100639A patent/EP0085385A3/en not_active Withdrawn
- 1983-01-28 JP JP58012585A patent/JPH0797417B2/en not_active Expired - Lifetime
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| DE85385T1 (en) | 1985-12-05 |
| DE3382810T2 (en) | 1997-05-22 |
| EP0513880A3 (en) | 1993-01-13 |
| EP0085385A2 (en) | 1983-08-10 |
| DE3382744T3 (en) | 2002-09-05 |
| EP0736846A2 (en) | 1996-10-09 |
| EP0736846B1 (en) | 2000-10-25 |
| DE3382835D1 (en) | 2000-11-30 |
| JPS58144989A (en) | 1983-08-29 |
| EP0513880B1 (en) | 1997-01-02 |
| JPH0797417B2 (en) | 1995-10-18 |
| EP0085385A3 (en) | 1984-11-14 |
| EP0513880A2 (en) | 1992-11-19 |
| DE3382810D1 (en) | 1997-02-13 |
| DE3382744T2 (en) | 1994-09-01 |
| EP0736846A3 (en) | 1996-10-16 |
| DE3382744D1 (en) | 1994-05-19 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |