CA1200326A - High-power dual-gate field-effect transistor - Google Patents

High-power dual-gate field-effect transistor

Info

Publication number
CA1200326A
CA1200326A CA000439975A CA439975A CA1200326A CA 1200326 A CA1200326 A CA 1200326A CA 000439975 A CA000439975 A CA 000439975A CA 439975 A CA439975 A CA 439975A CA 1200326 A CA1200326 A CA 1200326A
Authority
CA
Canada
Prior art keywords
gate
electrodes
terminal
pellet
carrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000439975A
Other languages
French (fr)
Inventor
Franco N. Sechi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RCA Corp
Original Assignee
RCA Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by RCA Corp filed Critical RCA Corp
Application granted granted Critical
Publication of CA1200326A publication Critical patent/CA1200326A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
    • H01L29/8124—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate with multiple gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12033—Gunn diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Wire Bonding (AREA)

Abstract

Abstract of -the Disclosure HIGH-POWER DUAL-GATE FIELD-EFFECT TRANSISTOR
An FET pellet containing a plurality of each of source, gate and drain electrodes in an array, normally combined with a carrier to create a single-gate power FET, is combined with a special carrier having a source terminal, a drain terminal, and first and second gate terminals to create a dual-gate FET with relatively high power handling capabilities. In the dual gate FET some of the drain electrodes are connected to the source terminal, some of the gate electrodes are connected to the first gate terminal, and some of the gate electrodes are connected to the second gate terminal. Respective sets of source electrodes are connected together by the carrier.
Some source electrodes retain the characteristics of source electrodes and other source electrodes have the characteristics of drain electrodes.

Description

f'~
-1- RCA 77,333 HIG~-POWER DUAL-GATE FIELD-EFFECT TRANSISTOR
This invention is concerned with dual-gate field-effect transistors (FET) and more particularly with dual-gate FETs which produce high power ou-tput.
Known dual-gate FETs have the desirable property of high gain at high frequencies, such as at Ku-band.
Furthermore, the gain can be varied by varying the bias voltage on the second gate. Known dual-gate FETs have the undesirable property of producing low output power of approxlmately -ten milliwatts.
Known single~gate FETs, particularly of the type described in U. S. Patent No. 3,993,515 which are "flip chip" mounted, desirably can produce hundreds of milliwatts of output power but cannot produce controlled high gain at high frequency.
In accordance with a preferred embodimen-t of the invention; an FET pellet has at least a drain pad and a source pad and multiple electrodes connected to each of said pads, has at least two gate pads and multiple gate electrodes connected to each gate pad, and has multiple other electrodes, and a transistor carrier comprises an electrically insulative thermally conductive substrate and, mounted thereon, a source terminal, a drain terminal, a first gate terminal, a second gate terminal, and an additional terminal. The carriex and pellet are arranged such that: the drain pad of -the pellet is elec-tr~cally connected to the drain -terminal of the carrier, the source pad of the pellet is electrically connected to the source terminal of the carrier, one of said ga-te pads of the pellet is electrically connected to the firs-t gate terminal of the carrier, another one of the gate pads of the pellet is electrically connected to -the second gate terminal of the carrier, and the o-ther electrodes of the pellet are electrically connected to the additional terminal of the carrier.
FIGURE 1 is a plan view of an FET pellet conventionally used to crea-te a single gate power FET;

6~3~q~
-2- RCA 77,333 FIGURE 2 is a cross section elevatlon view along lines 2 2 of the FIGURE 1 FET pellet;
FIGURE 3 is a plan view of a single-gate power FET carrier above which is positioned the FET pellet of FIGURE 1, illustrated in phantom, in accordance with the prior art;
FIGURE 4 is a cross section elevation view along lines 4-4 of the FIGURE 3 carrier and the FIGURE 1 pelle-t in accordance with the prior ar-t;
FIGURE 5 is an electrical schematic of a single gate power FET constructed as in FIGURES 3 and 4 in accordance with the prior art;
FIGURE 6 is a plan view of a dual-gate power FET
carrier above which is positioned the FET pellet of FIGURE
1, illustrated in phantom, in accordance with a preferred embodiment of the present invention;
FIGURE 7 is a cross section elevation view along lines 7-7 of khe FIGURE 6 carrier and the FIGURE 1 pellet in accordance with a preferxed embodiment of the present invention; and FIGURE 8 is an electrical schematic of a dual-gate power FET constructed as in FIGURES 6 and 7 in accordance wi-th a preferred embodiment of the pr~sent i.nven-tion.
Referring now to FIGIJRES 1 and 2 there is illustrated, in plan view and cross sectional elevation view respectively, an FET pelle-t intended for use in fabricating a single~gate power F~T. The pellet 10 comprises a semiconductor substrate 12 of gallium arsenide (GaAs) material upon which i5 deposited n-doped layer 14 approximately 0.3 micrometers thick of GaAs ma-terial. On the layer 14 is a pattern of electrodes and pads -to be described hereinafter. Although the physical layout of the pads and electrodes is the same in the prior art single-gate application and the inventive dual-gate application, the use made of the electrod~s and pads is different~

3f~
-3- RCA 77,333 Thus in FI~URES 1 and 2 the let-ters S (source), D (drain) and G ~gate) which are not in parentheses, (), refer to the invention use of the pads and electrodes;
while the same letters enclosed in parentheses refer to the prior art use for those electrodes and pads. A11 electrodes, S, D and G extend between lines 16~16 and 18-18 in FIGURE 1. There are our pads, 20, 22, 24, and 26 illustrated in FIGURE 1. ~ll electrodes and pads are typically made of gold and deposited on substrate 14.
In the prior art there are two drain pads 20, 22 by way of example. The (D~ pad 20 is connec-ted to two (D) electrodes 20a and 20b. Likewise, in the prior art there are two ga-te pads 24 and 26. By way of example, (G) pad 26 is connected to four (Ç) electrodes 26a, 26b, 26c, and 26d. Referring to FIGURE 2, it will be noted that the upper surface of all five prior art (S3 elec-trodes 30, 32, 34, 36 and 38 are elevated above layer 14 relative -to all four (D) electrodes 20a, 20b, 22a and 22b. The eight (G) electrodes (no-t nun~ered in FlGURE 2 because of their small size) and depressed into voids in the layer 14 for purposes of easy manufacture. The five (S) electrodes are not connected to any source pads but rather in accordance with the prior ar-t, are elec-trically connected together by a carrier to be hereinafter described. Although not indicated in FIGURE 2, the upper surface of pads 20, 22, 24 and 26 are at the same elevations as the upper surface of the (S) electrodes.
In a typical prior art pellet, the elec-trode and pad pattern illustrated in FIGURES 1 and 2 less one end (S) electrode (for example, 38) may be repeated. That is, a set of pads and electrodes extending between and including elec-trodes 30 and 26d are positioned to the left of electrode 30. Since the repeated set electrodes are not necessary to the present invention, they are not illustrated.
In accordance with the invention, the use of the various pads and electrodes is much differen-t tha-t the prior art use. For example, with reference to FIGURE 1, 3~
-4- RCA 77,333 electrodes 22a and 22b are treated as source electrodes, no-t drain electrodes as in the prior art. Likewise pad 22 connected to electrodes 22a and 22b is treated as a source pad, not a drain pad. Electrodes 30, 32 and part of 34 are treated as drain elec-trodes, not source electrodes.
Finally the gate electrodes connec-ted to gate pad 24 are treated as gate 1 electrodes and the gate electrodes connected to gate pad 26 are treated as gate 2 electrodes of the dual-gate FET, no-t simply gate electrodes of the single-gate FET.
In the prior art, FET pellet 10 is flip chip (turned over and) mounted to a carrier 50 as illustrated in plan view iIl FIGURE 3 and in cross section view in FIGURE 4, to which attention is now direc-ted. Thus FIGURES 3 and 4 illustrate mechanically and FIGURE 5 illustrates electrically a single-gate power FET. With regard to FIGURE 3, the pellet 10 is only shown in phantom so the shape of the carrier can more easily be seen.
Further, since the scale of FIGURES 3 and 4 are smaller than that of FIGURES 1 and 2, only the gate and drain pads~ not electrodes are illustrated and source electrodes are simply illustrated as one long block ra-ther -than individual electrodes. Parentheses are used on the designations G, D and S to be consistent with FIGURES 1 and 2.
Carrier 50 includes an inverted T-shape (as viewed in FIGURE 4) membex 52 made of copper for heat conduction and for an electrical connection to all of the source electrodes (S). For good heat dissipation characteristics the vertical portion 52a of the T is typically trapezoidal in cross section as illus-trated in FIGURE 4. Carrier 50 also contains two ceramic risers 54 and 56 parallel to and flanking portion 52a. On each ceramic riser is a copper layer 58 and 60 respectively.
Short lengths of bond wire 62 and 64 are connected between pellet gate pads 24 and 26 respectively and copper layer 58. Similarly, short lengths of bond wire 66 and 68 are coImected between pellet drain pads 20 and 22 respectively 3~
,
-5- RCA 77,333 and a copper layer 60. Thus, gate pads 24 and 26 are elec-trically connected together by copper layer 58, drain pads 20 and 22 are electrically connected together by layer 60, and the source electrodes are electrically connected together by the T-shaped area 52a which also dissipates heat produced in -the source electrodes and other parts of pellet 10. Layer 58 is the transistor gate connec-tion designated by -the lower case letter g in FIGURE
3. Layer 56 is the transistor drain connection designated by the lower case let-ter d in FIGURE 3, and T-shaped member 52 is the transistor source connection as designated by the lower case let-ter s in FIGURE 3.
FIGURE 5 illustrates in elec-trical schematic form the transistor which is mechanically illustrated in FIGURES 3 and ~. The letters in parentheses () are prior art D, G and S designations corresponding wi-th th~ pelle-t designations in FIGURES 1 and 2 while the lower case d, g and s terminal designations are for consis-tency with the equivalent designations in FIGURE 3.
FIGURES 6, 7 and 8 to which attention is directed, illustrate how the pellet of FIGURES 1 and 2, originally designated for use as a single-gate power FET, is used to make a dual-gate FET with power handling capacity ~reater than that of a conventional dual-ga-te FET. FIGURE 6 is a plan view of a dual-gate FET in accordance wi-th the invention. The FET comprises a carrier 70 and, illustrated in phantom as was -true in FIGURE 3, the FET pellet 10 of FIGURES 1 and 2. As with FIGURE 3, only the gate and drain (one used as a source) pads and in the general source (drain) area are illustrated. FIGURE 7 is a cross section elevation view along lines 7 7 of FIGURE 6 but with FET pellet 10 in place.
Carrier 70 comprises a substra-te 72 preferably made of beryllium oxide (BeO) on which is deposited a conductive pattern typically of copper and gold. The BeO
material is known to be a good electrical insulator and a good thermal conductor. The conductive pattern includes a 32~
-6- RCA 77,333 drain pad 74 in line with and electrically connected to drain pad 20 of pelle~ 10, a source pad 76 in line with and electrically connected to source pad 22 (a drain pad in the prio~ art), a first gate pad 78 in line with and elec~rically connec-ted to the G1 gate pad 24 of pelle-t 10 and a second gate pad 80 in line with and electrically connected to -the G2 gate pad 26 of pellet 10. The conductive pattern also includes a pad 82 in line with and electrically connected to all of electrodes 30, 32, 34, 36 and 38. The various pads and elec-trodes on pellet 10 are soldered to their associated pads on carrier 70. The heat generated in pellet 10 when it is conducting power also passes by means of the various pads to BeO substrate 72 and then to other parts of the circuit (no-t shown) for ultimate dissipation into the atmosphere.
The pads 74, 76, 78 and 80 are the dual-gate transistor terminals and are so indicated by lower case letters which correspond to the same letters in the dual-gate FET transistor electrical schematic of FIGURE 8.
That is, pad 74 is the transistor drain pad d, pad 76 is the transistor source pad s, which is typically grounded as illustrated in FIGURE 8, pad 78 is the transistor gate gl terminal and pad 80 is the transistor g2 gate pad terminal.
Although as illustrated in FIGURES 6, 7 and 8 there is no connection to the outside world f.rom -the source S2/D1 pad 82, in some applications a connec-tion from this pad to other circuit elements (not shown) may be desirable and is easily accomplished by simply adding the desired circuitxy on BeO substrate 7~ in-terconnected as appropriate with pad 82.
By reviewing FIGURES 1 and 2 and FIGURES 6, 7 and 8 it will be understood that in accordance wi-th the invention, electrodes which are conventionally used as sources are in accordance with the invention used as drains, electrodes 30, 32 and 34 (FIGURE 1) being examples thereof, electrodes which are conventionally used as drains are in accordance with the invention used as
-7- RCA 77,333 sources, ~lectrodes 22a and 22b being examples thereof and the various gate electrodes which normally are electrically connected -together (see FIGURE 3) are electrically split into two gates, G1 and G2.
It will be understood that by using an FET pellet 10, FIGURE 1, conventionally used in making a single-gate power FET in combination with a novel carrier which interconnects the pellet electrodes differen-tly -than with the prior art carrier and provides different external connections, as illustrated in FIGURES 6 and 7, a dual-gate FET capable of handling power many times that of a conventional dual-gate FET is realized. Fu.rthermore, other circui-ts and circuit elements (not shown) may also be placed on the BeO substrate 72 and coupled to pads 74, 76, 78 and 80, as appropria-te.

Claims (4)

WHAT IS CLAIMED IS:
1. A combination operative as a dual-gate FET;
said combination comprising:
an FET pellet having at least a drain pad and a source pad, and multiple electrodes connected to each of said pads, having at least two gate pads and multiple gate electrodes connected to each of said gate pads, and having multiple other electrodes;
a carrier comprising an electrically insulative, thermally conductive substrate and mounted thereon a source terminal, a drain terminal, a first gate terminal, a second gate terminal, and an additional terminal;
said carrier and pellet arranged such that said drain pad of said pellet is electrically connected to said drain terminal of said carrier, said source pad of said pellet is electrically connected to said source terminal of said carrier, one of said gate pads of said pellet is electrically connected to said first gate terminal of said carrier, another one of said gate pads of said pellet is electrically connected to said second gate terminal of said carrier, and said other electrodes of said pellet are electrically connected to said additional terminal of said carrier.
2. The dual gate FET as set forth in Claim 1 wherein said substrate is beryllium oxide.
3. The dual gate FET as set forth in Claim 2 wherein said other electrodes of said pellet serve as additional source and drain electrodes, all connected to said carrier additional terminal and not connected to any of said pellet pads.
4. The dual gate FET as set forth in any one of Claims 1, 2, and 3 wherein said electrodes are in an elongated line.
CA000439975A 1982-11-26 1983-10-28 High-power dual-gate field-effect transistor Expired CA1200326A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US44472582A 1982-11-26 1982-11-26
US444,725 1982-11-26

Publications (1)

Publication Number Publication Date
CA1200326A true CA1200326A (en) 1986-02-04

Family

ID=23766084

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000439975A Expired CA1200326A (en) 1982-11-26 1983-10-28 High-power dual-gate field-effect transistor

Country Status (5)

Country Link
JP (1) JPS59108336A (en)
CA (1) CA1200326A (en)
DE (1) DE3343030A1 (en)
FR (1) FR2536910A1 (en)
GB (1) GB2131228B (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2137807B (en) * 1983-04-05 1987-08-12 Plessey Co Plc A semiconductor component and method of manufacture
JPH0425031A (en) * 1990-05-16 1992-01-28 Nec Corp High-output monolithic microwave integrated circuit
JPH07505016A (en) * 1992-12-22 1995-06-01 ヒューズ・エアクラフト・カンパニー FET chip with a bridge to remove heat
DE4444808B4 (en) * 1993-12-17 2005-12-15 Denso Corp., Kariya Semiconductor device
US7299459B1 (en) 2000-01-19 2007-11-20 Sabio Labs, Inc. Parser for signomial and geometric programs
US6802050B2 (en) * 2002-04-07 2004-10-05 Barcelona Design, Inc. Efficient layout strategy for automated design layout tools
US7093205B2 (en) 2002-04-10 2006-08-15 Barcelona Design, Inc. Method and apparatus for efficient semiconductor process evaluation

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4048646A (en) * 1975-02-26 1977-09-13 Nippon Electric Company, Limited Dual-gate schottky barrier gate fet having an intermediate electrode and a method of making same
US3993515A (en) * 1975-03-31 1976-11-23 Rca Corporation Method of forming raised electrical contacts on a semiconductor device
US4104673A (en) * 1977-02-07 1978-08-01 Westinghouse Electric Corp. Field effect pentode transistor
US4161740A (en) * 1977-11-07 1979-07-17 Microwave Semiconductor Corp. High frequency power transistor having reduced interconnection inductance and thermal resistance
FR2455785A1 (en) * 1979-05-02 1980-11-28 Thomson Csf ELECTRICAL INSULATOR SUPPORT, WITH LOW THERMAL RESISTANCE, AND BASE OR HOUSING FOR POWER COMPONENT, INCLUDING SUCH SUPPORT

Also Published As

Publication number Publication date
JPS59108336A (en) 1984-06-22
GB2131228A (en) 1984-06-13
DE3343030A1 (en) 1984-05-30
GB2131228B (en) 1986-06-04
FR2536910A1 (en) 1984-06-01
GB8331225D0 (en) 1983-12-29

Similar Documents

Publication Publication Date Title
US5025296A (en) Center tapped FET
US3969745A (en) Interconnection in multi element planar structures
US3986196A (en) Through-substrate source contact for microwave FET
CA1232364A (en) Wafer-scale-integrated assembly
US4276558A (en) Hermetically sealed active microwave integrated circuit
JPH098064A (en) Semiconductor device
US4764802A (en) Semiconductor devices
JP2001028425A (en) Semiconductor device and manufacture thereof
US4161740A (en) High frequency power transistor having reduced interconnection inductance and thermal resistance
US6777791B2 (en) Multiple ground signal path LDMOS power package
CA1200326A (en) High-power dual-gate field-effect transistor
US5901042A (en) Package and semiconductor device
US3479570A (en) Encapsulation and connection structure for high power and high frequency semiconductor devices
US3864727A (en) Semiconductor device
JPS5931042A (en) Semiconductor device with high frequency and output
US6776399B2 (en) Chip-scale package
JPH08213614A (en) Mos-technology power-device chip and package assembly
KR860000971B1 (en) Microwave field effect transistor
JP2884577B2 (en) Field effect transistor
US3710202A (en) High frequency power transistor support
KR940002769B1 (en) Device and manufacturing method of semiconductor with overlapping conducting layer
US6706967B2 (en) Lead-less semiconductor device with improved electrode pattern structure
DE69727788T2 (en) SEMICONDUCTOR ARRANGEMENT WITH SPECIAL EMITTER CONNECTION
JPS6327859B2 (en)
JPS63202974A (en) Semiconductor device

Legal Events

Date Code Title Description
MKEX Expiry