CA1196407A - Data transmission systems for full duplex communication - Google Patents
Data transmission systems for full duplex communicationInfo
- Publication number
- CA1196407A CA1196407A CA000415498A CA415498A CA1196407A CA 1196407 A CA1196407 A CA 1196407A CA 000415498 A CA000415498 A CA 000415498A CA 415498 A CA415498 A CA 415498A CA 1196407 A CA1196407 A CA 1196407A
- Authority
- CA
- Canada
- Prior art keywords
- signal
- local
- main
- station
- clock signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/14—Two-way operation using the same type of signal, i.e. duplex
- H04L5/1423—Two-way operation using the same type of signal, i.e. duplex for simultaneous baseband signals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Dc Digital Transmission (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
Disclosed is a full duplex communication system con-necting by a two wire link a main station and a local station.
Both the main station and the local station has a clock pulse generator. The local clock pulse generator is switchable be-tween a pulse rate which corresponds to that of the main clock and another pulse rate which defers about a fixed value. A
comparator compares the phase of the incoming signal with the local clock signal and switches the local clock generator when its output is out of phase with the received signals.
Disclosed is a full duplex communication system con-necting by a two wire link a main station and a local station.
Both the main station and the local station has a clock pulse generator. The local clock pulse generator is switchable be-tween a pulse rate which corresponds to that of the main clock and another pulse rate which defers about a fixed value. A
comparator compares the phase of the incoming signal with the local clock signal and switches the local clock generator when its output is out of phase with the received signals.
Description
~196407 1 The present invention relates in general to a duplex communication system and in particular to a duplex transmission system employing a two-wire link between a main station and a local station, the main station generating a clock signal where-by the coded data signal is transmitted during one half period of the main clock signal from the main station to the local sta-tion and during the other half period the coded data signal is transmitted from the local station to the main station.
A data transmission system of this type is known from the German patent 2,453,628. Such systems are employed for sig-nal transmission over short distances and for a short duration of transmission. The two-wire link transmits in rapid direction exchange alternately from the main station to the local one and vice versa informat on contained in a single signal step such as one bit, one dibit, or one tribut. The data transmission code is selected such that in the local station the rate of period of the main clock signal can be detected so that the local station is synchronized with the main station.
; In the prior system according to the German patent 25 53 628 no active clock generator is present in the local sta-tion. As a consequence in the event of an interruption in the link, the local station is without clock signals.
Moreover, in the prior art system, the main station ~transmits to the local station a bipolar RZ (return to zero) signal and from the local station to the main station a uni-polar RZ signal is transmitted. Most transmitted signals are scanned or sensed as to their timing by means of NRZ (non-return to zero) signals. In the RZ signals thexe is no possibility to achieve a transmission without direct current components.
A general ob~ect of the present invention is to overcome
A data transmission system of this type is known from the German patent 2,453,628. Such systems are employed for sig-nal transmission over short distances and for a short duration of transmission. The two-wire link transmits in rapid direction exchange alternately from the main station to the local one and vice versa informat on contained in a single signal step such as one bit, one dibit, or one tribut. The data transmission code is selected such that in the local station the rate of period of the main clock signal can be detected so that the local station is synchronized with the main station.
; In the prior system according to the German patent 25 53 628 no active clock generator is present in the local sta-tion. As a consequence in the event of an interruption in the link, the local station is without clock signals.
Moreover, in the prior art system, the main station ~transmits to the local station a bipolar RZ (return to zero) signal and from the local station to the main station a uni-polar RZ signal is transmitted. Most transmitted signals are scanned or sensed as to their timing by means of NRZ (non-return to zero) signals. In the RZ signals thexe is no possibility to achieve a transmission without direct current components.
A general ob~ect of the present invention is to overcome
-2- ~
119640~
1 the disadvantages of prior-art systems of this kind.
More particularly, it is an object of this inv~ntion to provide an improved duplex transmission system of the afore-described kind in which the local station generates clock pulses independently from the main station whereby the rate or period of the received signals is promptly synchronized with the clock signals in the main station.
In keeping with these objects and others which will be-come apparent hereinafter, one feature of the invention resides in providing the local station with a separate local clock pulse generator which is switchable to generate a first local clock signal at a period corresponding to that of the main clock sig-nal, and a second local clock signal the period of which dif-fers from the rate of the main signal about a fixed amount, means for comparing the phase of the received coded data signal with one of the local clock signals, and means for switching over the local pulse generator when the received data signal is out o phase with the one local clock signal.
By virtue of the active clock signal generator in the local station it is insured that corresponding terminal apparatus in the local station is always properly clocked.
r~uring the reception of the main data signal it is synchronized with the main clock signal and in the case of an interruption of the transmission link it is still timed by a clock signal which may differ from that of the main station but which im-mediately upon the receipt of the main signal is promptly synchronized with the latter.
The novel features which are considered as charac-teristic for the present invention are set forth in particular in the appended claims. The invention itself, however, both as 1196~07 1 to its construction and its method of operation, together with additional objects and advantages thereof, will be best under~
stood from the following description of specific embodiments when read in connection with the accompanying drawings.
FIG. l is a block diagram of a data transmission system according to this invention; and FIG. 2 is a time plot of respective signals occurring in the system of FIG. l.
Referring firstly to FIG. 1, a terminal apparatus 1 is associated with a main station 2 and the terminal apparatus
119640~
1 the disadvantages of prior-art systems of this kind.
More particularly, it is an object of this inv~ntion to provide an improved duplex transmission system of the afore-described kind in which the local station generates clock pulses independently from the main station whereby the rate or period of the received signals is promptly synchronized with the clock signals in the main station.
In keeping with these objects and others which will be-come apparent hereinafter, one feature of the invention resides in providing the local station with a separate local clock pulse generator which is switchable to generate a first local clock signal at a period corresponding to that of the main clock sig-nal, and a second local clock signal the period of which dif-fers from the rate of the main signal about a fixed amount, means for comparing the phase of the received coded data signal with one of the local clock signals, and means for switching over the local pulse generator when the received data signal is out o phase with the one local clock signal.
By virtue of the active clock signal generator in the local station it is insured that corresponding terminal apparatus in the local station is always properly clocked.
r~uring the reception of the main data signal it is synchronized with the main clock signal and in the case of an interruption of the transmission link it is still timed by a clock signal which may differ from that of the main station but which im-mediately upon the receipt of the main signal is promptly synchronized with the latter.
The novel features which are considered as charac-teristic for the present invention are set forth in particular in the appended claims. The invention itself, however, both as 1196~07 1 to its construction and its method of operation, together with additional objects and advantages thereof, will be best under~
stood from the following description of specific embodiments when read in connection with the accompanying drawings.
FIG. l is a block diagram of a data transmission system according to this invention; and FIG. 2 is a time plot of respective signals occurring in the system of FIG. l.
Referring firstly to FIG. 1, a terminal apparatus 1 is associated with a main station 2 and the terminal apparatus
3 is connected to a local station 4. The terminal apparatus in each station may be for example a Teletex device. The main station 2 is connected to the local station 4 by a two wire link 5 which is relatively short, for example within the range of a building.
The main station2 is provided with a clock pulse gen-erator Pl controlled by a quartz oscillator Ql to generated a main transmission clock signal a, which is applied to a coder Cl and to a decoder Dl. Coder Cl receives from the te;rminal apparatus 1 data s:ignal _ (Fig. 2b) to be transmitted and con-verts the same into a coded transmission signal c (Fig~ 2c) which is supplied to a transformer Ul connected at one end of the two wire links 5. The transformer Ul is also connected to the input of the decoder Dl which decodes received signal and supplies the decoded data to the terminal apparatus 1.
The local station 4 has also a coder C2 which processes data signals from the terminal apparatus 3 in the same manner as coder Cl in the main station and generatas a local data transmission i (Fig. 2i) which is applied to the other transformer U2 at the transforming end of the link 5. According 6~V~
to this invention, local station 4 is provided with its own clock generator which in this example includes a quariz oscil-lator Q2 operating at a nominal frequency of 4.6 megacycles for instance; the output of oscillator Q2 is connected to time clock generator T2 which includes a switchable diYider of the incoming signal. The divider divides the frequency by n-l or n+l depending on the signal at its switching input 6 and the resulting reception clock signal _ (Fig. 2h) is ap-plied to the output 7. _ indicates the ratio between frequencies of the local oscillator Q2 and the local clock signal h. The local or reception clock signal _ is inverted in inverter J and is applied as a local transmission clock signal g to the coder C2.
The local station 4 further includes two comparators KOMP 1 and KOMP 2 connected in parallel to the transformer U2. One of the comparators rectifies and limits in amplitude the positive components, and the other comparator the negative components of the received coded signal _. Differentiators DIF1 and DIF2 are connected to the outputs of corresponding com-parators and the output signals from the differentiators are ap-pIied to inputs of an A~D-gate 8. The output of AND-gate 8 thus produces a zero par,sage signal e (Fig. 2e) which is applied to one input of comparator 9. The other input of comparator 9 is supplied with comparison clock signals f (Fig. 2f) produced in a delaying circuit 11 from reception clock signal _. The output c\f phase comparator 9 is connected to the switching input 6 of the clock pulse generator T2. If now the received signal _ is present or if signals e and f do not coincide in time, then the signal generated at the ouput of comparator 9 switches the local clock pulse generator T2 to a divlding ratio n+l or al-ternatively when the signal e and f coincide, to a ratio n-l.
.~
1:1964V~
1 The output 7 of local clock pulse generator 2 is di-rectly connected to the terminal apparatus 3. Comparator KOMP2 together with an additional delay stage 11 and step feeler 12 from a decoder D2 of the local station 4. The step feeler 12 is controlled by the reception clock signal from the output 7 via the additional delay stage 11. The sensed step values from the output of feeler 12 are applied to a set input of a flip-flop 13 which is controlled by the reception clock signal _.
The operation of the duplex system of this invention is as follows:
The main transmission clock signal a has a rate or clock period TA and a key or step ratio of 50%. During the high (H) or "l" signal steps of the signal a coder Cl is active and decoder Dl is blocked. Vice versa, during the low (L) or "0"
signal steps coder l is closed and decoder l is active.
Fig. 2b shows by way of an example an NRZ-signal "0,1,1,0,1" representing information to be transmitted. The data b during the "1" stage of the main clock signal a are con-~` verted in coder Cl in the coded transmission signal _ which has no DC component. In the coded signal c, each period of :
the signal c thus consists of a negative and a positive signal component whereby in the case of a "0" information in signal b the negative component trails the positive component; in the case of "1" information in signal d the positive component is behind the negative component (Fig. 2c).
The main coded transmission signal c after passage through the two wire link 5 is received in the local station as a recept signal d from which the zero passage signals e are derived in the manner described before. As it will be seen from Fig. 2e the period of signals e is the same as that 119~407 1 of the main clock signal a. The reception clock signal h the momentary rate or clock period of which is indicated as PH is to be synchronized with the zero passage signals ~. For this purpose a comparison clock signal f is derived from the recep-tion clock signal _ by means of the delay stage 10 and the phase of the falling flank of the signal r is compared with the rising flank of the zero passage signal e. The rising flank of the signal e is delayed about a quarter of clock period TA with respect to the rising flank of the main clock signal a. In order to compensate for this phase difference the falling flank of the comparison signal f is delayed about the same amount in delay stage 10 so that the proper relation-ship with respect to the zero passage signal e be established.
If signal f overlaps the signal e, then the divider T2 is switched over to divide by the ratio n-l whereby n is 384 for example. If no overlap is present between signals _ and f, ` then the dividing ratio of clock generator T2 is switched over to n+l. Consequently, the falling flank of the comparison signal f oscillates about the rising flank of the signal e until the clock signal of the local station 4 at the output 7 catches the main clock signal a of the main station 2. The local transmission signal g is inverted relative to the re-ception clock signal _ and thus to the main transmission clock signal a. Accordingly, if coded signal 1 to be transmitted is coded with information derived from the terminal apparatus 3 which may be for example "1,0,0,1,1" then the signal is trans-mitted when coder Cl in the main station is blocked and decoder Dl is active.
The delay stage 11 delays the reception clock signal _ about ~ of the clock pulse period TH so as to insure an optimum 1196~07 1 step sensing operation of the sensor 12, that means at larger time gaps.
As long as no received signal d is present at the local station 4, the local clock signal generator ~2 operates at a dividing ratio n+l. As a consequence, a relatively large deviation of the clock period TH relative to the main clock period TA is produced. The phase of the comparison clock pulse signal f for a very short time is out of phase as to the per-iod TA. As soon as a signal d is received and the zero passage signals e are generated, a time point is promptly reached at which the falling flank of the signal s coincides with the ris-ing flank of the signal e and the desired synchronization between the main and local clock signals is achieved.
It will be understood that each of the elements de-scribed above, or two or more together, may also find a useful application in other types of constructions differiny from the types described above.
While the invention has been illustrated and described ~ as embodied in a specific example of a full duplex communication ZO system, it is not intended to be limited to the details shown, since various modi~Eications and structural changes may be made without departing in any way ~rom the spirit of the present in-vention.
Without further analysis, the foregoing will so fully reveal the gist of the present invention that others can, by ap-plying current knowledge, readily adapt it for various applica-tions without omitting features that, fxom the standpoint of prior art, fairly constitute essential characteristics of the generic or specific aspects of the present invention.
The main station2 is provided with a clock pulse gen-erator Pl controlled by a quartz oscillator Ql to generated a main transmission clock signal a, which is applied to a coder Cl and to a decoder Dl. Coder Cl receives from the te;rminal apparatus 1 data s:ignal _ (Fig. 2b) to be transmitted and con-verts the same into a coded transmission signal c (Fig~ 2c) which is supplied to a transformer Ul connected at one end of the two wire links 5. The transformer Ul is also connected to the input of the decoder Dl which decodes received signal and supplies the decoded data to the terminal apparatus 1.
The local station 4 has also a coder C2 which processes data signals from the terminal apparatus 3 in the same manner as coder Cl in the main station and generatas a local data transmission i (Fig. 2i) which is applied to the other transformer U2 at the transforming end of the link 5. According 6~V~
to this invention, local station 4 is provided with its own clock generator which in this example includes a quariz oscil-lator Q2 operating at a nominal frequency of 4.6 megacycles for instance; the output of oscillator Q2 is connected to time clock generator T2 which includes a switchable diYider of the incoming signal. The divider divides the frequency by n-l or n+l depending on the signal at its switching input 6 and the resulting reception clock signal _ (Fig. 2h) is ap-plied to the output 7. _ indicates the ratio between frequencies of the local oscillator Q2 and the local clock signal h. The local or reception clock signal _ is inverted in inverter J and is applied as a local transmission clock signal g to the coder C2.
The local station 4 further includes two comparators KOMP 1 and KOMP 2 connected in parallel to the transformer U2. One of the comparators rectifies and limits in amplitude the positive components, and the other comparator the negative components of the received coded signal _. Differentiators DIF1 and DIF2 are connected to the outputs of corresponding com-parators and the output signals from the differentiators are ap-pIied to inputs of an A~D-gate 8. The output of AND-gate 8 thus produces a zero par,sage signal e (Fig. 2e) which is applied to one input of comparator 9. The other input of comparator 9 is supplied with comparison clock signals f (Fig. 2f) produced in a delaying circuit 11 from reception clock signal _. The output c\f phase comparator 9 is connected to the switching input 6 of the clock pulse generator T2. If now the received signal _ is present or if signals e and f do not coincide in time, then the signal generated at the ouput of comparator 9 switches the local clock pulse generator T2 to a divlding ratio n+l or al-ternatively when the signal e and f coincide, to a ratio n-l.
.~
1:1964V~
1 The output 7 of local clock pulse generator 2 is di-rectly connected to the terminal apparatus 3. Comparator KOMP2 together with an additional delay stage 11 and step feeler 12 from a decoder D2 of the local station 4. The step feeler 12 is controlled by the reception clock signal from the output 7 via the additional delay stage 11. The sensed step values from the output of feeler 12 are applied to a set input of a flip-flop 13 which is controlled by the reception clock signal _.
The operation of the duplex system of this invention is as follows:
The main transmission clock signal a has a rate or clock period TA and a key or step ratio of 50%. During the high (H) or "l" signal steps of the signal a coder Cl is active and decoder Dl is blocked. Vice versa, during the low (L) or "0"
signal steps coder l is closed and decoder l is active.
Fig. 2b shows by way of an example an NRZ-signal "0,1,1,0,1" representing information to be transmitted. The data b during the "1" stage of the main clock signal a are con-~` verted in coder Cl in the coded transmission signal _ which has no DC component. In the coded signal c, each period of :
the signal c thus consists of a negative and a positive signal component whereby in the case of a "0" information in signal b the negative component trails the positive component; in the case of "1" information in signal d the positive component is behind the negative component (Fig. 2c).
The main coded transmission signal c after passage through the two wire link 5 is received in the local station as a recept signal d from which the zero passage signals e are derived in the manner described before. As it will be seen from Fig. 2e the period of signals e is the same as that 119~407 1 of the main clock signal a. The reception clock signal h the momentary rate or clock period of which is indicated as PH is to be synchronized with the zero passage signals ~. For this purpose a comparison clock signal f is derived from the recep-tion clock signal _ by means of the delay stage 10 and the phase of the falling flank of the signal r is compared with the rising flank of the zero passage signal e. The rising flank of the signal e is delayed about a quarter of clock period TA with respect to the rising flank of the main clock signal a. In order to compensate for this phase difference the falling flank of the comparison signal f is delayed about the same amount in delay stage 10 so that the proper relation-ship with respect to the zero passage signal e be established.
If signal f overlaps the signal e, then the divider T2 is switched over to divide by the ratio n-l whereby n is 384 for example. If no overlap is present between signals _ and f, ` then the dividing ratio of clock generator T2 is switched over to n+l. Consequently, the falling flank of the comparison signal f oscillates about the rising flank of the signal e until the clock signal of the local station 4 at the output 7 catches the main clock signal a of the main station 2. The local transmission signal g is inverted relative to the re-ception clock signal _ and thus to the main transmission clock signal a. Accordingly, if coded signal 1 to be transmitted is coded with information derived from the terminal apparatus 3 which may be for example "1,0,0,1,1" then the signal is trans-mitted when coder Cl in the main station is blocked and decoder Dl is active.
The delay stage 11 delays the reception clock signal _ about ~ of the clock pulse period TH so as to insure an optimum 1196~07 1 step sensing operation of the sensor 12, that means at larger time gaps.
As long as no received signal d is present at the local station 4, the local clock signal generator ~2 operates at a dividing ratio n+l. As a consequence, a relatively large deviation of the clock period TH relative to the main clock period TA is produced. The phase of the comparison clock pulse signal f for a very short time is out of phase as to the per-iod TA. As soon as a signal d is received and the zero passage signals e are generated, a time point is promptly reached at which the falling flank of the signal s coincides with the ris-ing flank of the signal e and the desired synchronization between the main and local clock signals is achieved.
It will be understood that each of the elements de-scribed above, or two or more together, may also find a useful application in other types of constructions differiny from the types described above.
While the invention has been illustrated and described ~ as embodied in a specific example of a full duplex communication ZO system, it is not intended to be limited to the details shown, since various modi~Eications and structural changes may be made without departing in any way ~rom the spirit of the present in-vention.
Without further analysis, the foregoing will so fully reveal the gist of the present invention that others can, by ap-plying current knowledge, readily adapt it for various applica-tions without omitting features that, fxom the standpoint of prior art, fairly constitute essential characteristics of the generic or specific aspects of the present invention.
Claims (3)
1. A data transmission system for a full duplex communication via a two wire link between a main station and a local station, the main station generating a main clock signal whereby during one half period of the main clock signal a coded data signal is transmitted from the main station to the local one and during the other half period the coded data signal is transmitted from the local station to the main station, said local station comprising a separate local clock pulse generator switchable to generate a first local clock signal having a peri-od corresponding to that of the main clock signal, and a second local clock signal the period of which differs from that of the main signal about a fixed amount; means for comparing the phase of the received coded data signal with one of the local clock signals and for switching over the local pulse generator when the received coded data signal is out of phase with the one local clock signal.
2. A data transmission system as defined in claim 1, wherein said local clock pulse generator includes an oscillator and a divider controlled by said cooperating means to switch over from a dividing ration n+l to a dividing ratio n-l.
3. A data transmission system as defined in claim 1, wherein said comparing means include zero passage detector of the received signal and a delay stage connected to the output of said local clock pulse generator to compare the phase of zero passages of the received signal with the local clock signal.
_9_
_9_
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DEP3145126.8 | 1981-11-13 | ||
| DE19813145126 DE3145126A1 (en) | 1981-11-13 | 1981-11-13 | DATA TRANSFER SYSTEM FOR FULL DUPLEX TRANSFER |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1196407A true CA1196407A (en) | 1985-11-05 |
Family
ID=6146319
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000415498A Expired CA1196407A (en) | 1981-11-13 | 1982-11-12 | Data transmission systems for full duplex communication |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP0079527B1 (en) |
| JP (1) | JPS58130653A (en) |
| CA (1) | CA1196407A (en) |
| DE (2) | DE3145126A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2536309A (en) * | 2015-03-09 | 2016-09-14 | Cirrus Logic Int Semiconductor Ltd | Low power bidirectional bus |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4825450A (en) * | 1987-03-12 | 1989-04-25 | The Boeing Company | Binary data communication system |
| US4823364A (en) * | 1987-03-12 | 1989-04-18 | The Boeing Company | Receive coupler for binary data communication systems |
| CA1311033C (en) * | 1988-03-19 | 1992-12-01 | Shinji Ohta | Circuit for obtaining accurate timing information received signal |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1401436A (en) * | 1971-10-14 | 1975-07-16 | Gen Electric Co Ltd | Pulse transmission systems |
| JPS5321963B2 (en) * | 1973-11-12 | 1978-07-06 | ||
| US3983498A (en) * | 1975-11-13 | 1976-09-28 | Motorola, Inc. | Digital phase lock loop |
| GB1566223A (en) * | 1978-01-17 | 1980-04-30 | Standard Telephones Cables Ltd | Digital duplex transmission system |
-
1981
- 1981-11-13 DE DE19813145126 patent/DE3145126A1/en not_active Withdrawn
-
1982
- 1982-11-04 DE DE8282110146T patent/DE3264446D1/en not_active Expired
- 1982-11-04 EP EP82110146A patent/EP0079527B1/en not_active Expired
- 1982-11-11 JP JP57196857A patent/JPS58130653A/en active Pending
- 1982-11-12 CA CA000415498A patent/CA1196407A/en not_active Expired
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2536309A (en) * | 2015-03-09 | 2016-09-14 | Cirrus Logic Int Semiconductor Ltd | Low power bidirectional bus |
| GB2536309B (en) * | 2015-03-09 | 2017-08-02 | Cirrus Logic Int Semiconductor Ltd | Low power bidirectional bus |
| US9935786B2 (en) | 2015-03-09 | 2018-04-03 | Cirrus Logic, Inc. | Low power bidirectional bus |
| US10218535B2 (en) | 2015-03-09 | 2019-02-26 | Cirrus Logic, Inc. | Low power bidirectional bus |
Also Published As
| Publication number | Publication date |
|---|---|
| EP0079527A2 (en) | 1983-05-25 |
| DE3145126A1 (en) | 1983-07-14 |
| EP0079527B1 (en) | 1985-06-26 |
| JPS58130653A (en) | 1983-08-04 |
| EP0079527A3 (en) | 1983-06-29 |
| DE3264446D1 (en) | 1985-08-01 |
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