CA1187177A - Serial-parallel-serial charge coupled device and method of transferring charge therein - Google Patents
Serial-parallel-serial charge coupled device and method of transferring charge thereinInfo
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- CA1187177A CA1187177A CA000397790A CA397790A CA1187177A CA 1187177 A CA1187177 A CA 1187177A CA 000397790 A CA000397790 A CA 000397790A CA 397790 A CA397790 A CA 397790A CA 1187177 A CA1187177 A CA 1187177A
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Abstract
SERIAL-PARALLEL-SERIAL CHARGE COUPLED DEVICE MEMORY AND
METHOD OF TRANSFERRING CHARGE THEREIN
Abstract of the Disclosure An SPS CCD memory using two phase clocking in the serial registers and ripple clocking in the parallel registers with interlacing transfer of charge in the parallel registers to the output serial registers. First alternate parallel registers are coupled to the output register through first transfer gates and rirst storage gates, and second alternate parallel registers are coupled to the output register through second transfer gates and second storage gates. Third storage gates are provided with each third storage gate alternately receiving charge from a first storage gate and a second storage gate with the third gate delivering the charge to the same storage gate of the output register in response to the high speed clock signals of the output serial register.
By linearly staggering the endmost gates of the first alternate parallel registers and the second alternate parallel registers, the interlacing of charge occurs at the endmost gate of the parallel registers.
METHOD OF TRANSFERRING CHARGE THEREIN
Abstract of the Disclosure An SPS CCD memory using two phase clocking in the serial registers and ripple clocking in the parallel registers with interlacing transfer of charge in the parallel registers to the output serial registers. First alternate parallel registers are coupled to the output register through first transfer gates and rirst storage gates, and second alternate parallel registers are coupled to the output register through second transfer gates and second storage gates. Third storage gates are provided with each third storage gate alternately receiving charge from a first storage gate and a second storage gate with the third gate delivering the charge to the same storage gate of the output register in response to the high speed clock signals of the output serial register.
By linearly staggering the endmost gates of the first alternate parallel registers and the second alternate parallel registers, the interlacing of charge occurs at the endmost gate of the parallel registers.
Description
~ 7 50.3982 ~ , SERIAL-PARALLEL-SERIAL C~ARGE COUPLED DEVICE MEMORY AND
MET~OD OF TRANSF'ERRING C~RGE THEREIN
This invention relates generally to charge coupled devices tCCD's), and more particularly the invention relates to CCD memories e~ploying a serial-parallel-serial (SPS) arrangement~
A two phase serial-parallel-serial charge-coupled device memory ~SPS CCD) is disclosed by Varshney, Venkateswaran, and Amelio in U.S. Patent No. 4,165,541O The memory has a group of parallel shit registers with an input serial shift regi~er at one end of the group and an output serial shiEt register at the opposite end of the group.
Data are supplied to tlle input serial register at the rate of the two phase clock signals, and after the register is filled a serial to parallel transfer operation loa~s the lS data in the parallel shiEt registers. The data are transerred through the parallel shift registers, usin~
ripple clocking, and a parallel to serial transfer oeration then loads the data into the ol1tput serial shi~
register.
The memory uses a convention~l interlacing technique in whlch one.pa.rallel shift register is provided for each element o the input or output serial shift registers.
~sing the two phase electrode structure for the input and output registers the data are transferred to or from the ,", .: ~
parallel registers at the cor~ect phase s.o that charges are alternately transEerred to or from alternate parallel regi.sters.
Heretofore, transEer of charge ~rom the parallel registers to the output serial register has required an intermediate voltage level applied to the last storage gate~ This intermediate voltage level ensures that the data in alternate parallel channels are transfer-red to the serial gates which are at a high potential (E.G. either ~1 or ~2) r and the data from other alternate parallel channels are not transferred due to the intermediate voltage level at the last storage gates being higher than the potential of the serial gates where charge transfer is not wanted. Not only is the intermediate voltage level required, but timing is critical since charge from the parallel registers is transferred and interlaced directly into the fast transfer operation of the serial register.
A general object of the present invention is an im-roved SPS CCD memory.
In accordance with one aspect of the invention a two phase SPS CCD memory array includes means for transEerring charge Erom parallel registers to a serial output register comprising a 2a first transfer gate associated with each Eirst alternate parallel register, a second trans:Eer gate associated with each second alternate parallel register, a first storage gate associated with each first transfer gate, a second storage gate associated with each second transfer gate, a third storage gate associated and shared with each first storage gate and each second storage gate whereby charge from a Eirst storage gate and from a second storage gate are alternately loaded into said third ?~
storage gate, and means for controlling said first trans~er gates and said second transfer gates whereby charge from said first alternate parallel registers is trans~erred through said first storage gates and said third storage gates to said serial output register in response to a serial register clock sign~l and then charge from said second alternate parallel registers is trans-ferred through said second storage gates and said third storage gates to said serial output register in response to a serial register clock si.gnal.
Another aspect of the invention includes a two phase SPS CCD memory array, a method of transEerring charge Erom paral-lel registers to a serial output register using clock signals of said serial output register comprising the steps of a) trans-ferring first charge from first alternate parallel registers to first storage gates, b) transerring said first charge from said first storage gates to shared storage gates~ c) transferring said first charge from said shared stroage gates to said serial output register in response to a clock signal of said serial output register, d) transferring second charge from second a].ternate parallel register to second storage gates, e) transferring said second charge from said second storage gates to said shared storage gates, and f) transferring said second charge from said third storage gates to said serial output register in response to a clock signal of said serial output register.
A further aspect of the invention comprises a two phase SPS CCD array, charge transfer means comprising a firs-t ~7~
endmost storage element of a first parallel register, a second endmost storage element of a second parallel register, a first transfer element associated with said Eirst endmost storage element, a second transfer element associated with said second endmost storage elemen-t, a first lntermediate storage element associated with said first trans~er element, a second intermediate storage element associated with said second transfer element, and a common storage element associated with said first and second intermediate storage elements whereby charge from said first endmost storage element is transferred through said first transfer element and said first intermediate storage element to said common storage element r and then charge from said second endmost storage element is transferred through said second transfer element and said second intermediate storage element to said common element.
The invention and objects and features thereof will be more readily apparent from the following detailed description and appended claims when taken with the drawing, ln which: Figure 1 is a schematic of a prior art SPS CCD arra~.
Figure 2A-2D are illustrations oE charge transer in the array of Figure 1.
-3a-~ 7 7 r ``. ~ ' .!
Figure 3 is a schematic of one embodiment of an SPS CCD
array in which the present invention can be employed.
Figures 4A-4D are illustrations of charge transfer in the array of Figure 3.
Figure 5 is a more detailed schematic of a portion of th~
SPS CCD array o~ Figure 3 in accordance with one embodiment of the present invention.
Figures 6A-6C are a timing diagram for the charge transfer in the array of Figure 3.
Figure 7 is an electrical schematic of two adjacent parallel channels of the SPS CCD array of Figure 5.
Figures 8-15 illustrate the transfer of charge in accordance with the timing diagram of Figure~ 7.
Referring now to thP drawings, Figure 1 is a schematic of an SPS CCD array as disclosed in U. S. Patent No. 4,165,541.
The CCD memory array 10 i5 arranged as a serial-parallel-serial memory and includes interlacing of data to and from the parallel registers and ripple clocking of the parallel shift registers to incxease the bit storage capacity.
parallel shift register of the block shown includes nine groups of eight electrodes, to which ripple clock signals Rl, ---RB, respectively, are applied, each group being capable o storing seven hits o~ information~ An inpu~ serial register 12 includes 32 electrodes associated with each o the 01 and ~ clock signals for a total of 64 elec~rodes.
In operation/ data are supplied to serial input shift regis-t~r 12 which is driven by clock signals ~1 and 0~. The data are stepped across the serial shift register in a conventional two phase CCD mannex. As soon as the serial shit regist~r is filled with one bit stored beneath every other electrode, a signal 0TI is supplied to allow these bits of information, represented by charge packets stored beneath the serial register electrodes, to be transferred into the input elec-trode of every other parallel shift register 14. Then, additional data are stepped into the serial shift register by application of signals 01 and 02. Once the data are stored under every other elec~rode in the input serial shift register, this time residing under electrodes not used in the previous transfer, signal ~Tl is again supplied to allow the charges under the electrodes to be transferred into the input elemen~ of the remaining unused alternate parallel shift registers n Once this is complete, ripple clock signals Rl, R2 R8 are applied to the groups of elements of the parallel shif~ registers to ~ransfer the data along the parallel registers. When the input electrode of each o~ the parallel shift registers is vacant, new data from the input lS serial shift regiq~er are transferred and the process is repeated.
The application of the ripple clock ~ignals results in the rippling movement of ~4 bit~ of data in the parallel shift registers. That is, a blank potential well is moved backward in each group of eight electrodes of the parallel shift registers, thereby transferring the data forward one electrode for each eight electrodes thàt the blank moves backward.
Signal 0T~ is applied to cause a trans~er of the data from the output electxode of every other one of the 64 parallel shift registers to be transferred into corresponding alter~
nating electrodes of the output serial shift re~ister.
These data are then stepped out of the output serial register by the application of signals 01 and 02. As soon as the output serial register is vacant, another transfer from the parallel shift register is initiated.
To perform the charge transfer from alternate parallel registers 14 to the output serial register 16~ an additional gate 18, is provided. Signal Vcc is applied ~o electrode 18 to provide an intermediate ~oltage level between the high level of 01 ~or 02) and the low level of 02 ~or ~1) to 7~7~
J
selectively block charge transfer to the low level clock 02 (or ~1) Figures 2A-2D illustrate c.harge ~ransfer from the parallel registers 14 to the output sexial register 16 of th~ array of Figure 1. In Figure 2A the stored charge, designated by xls, under the Vcc electrodes 18 of ~he parallel registers are aligned awaiting transfer. In Figure 2B the charges in the 01 registers are transferred to the output serial register 16 through the transfer gates 22 when 01 is high and ~2 is low.
As above described, the Vcc voltage on ëlectrodes 18 prevents the transfer of charge to the low 02 electrodes of output register 16. After the 01 charges are removed from the out-put register, the 02 charges under the electrodes 18 are then transferred to the serial re~ister 16 while 02 is hi~h and 01 is low as shown in Figure 2C. In Figure 2D the transferred charges are loaded in the output register ready for transfer from the array.
Figure 3 is a schematic of one embodiment of an SPS CCD array in which the present invention ca.n be employed. The array is similar to the array.of Figure 1 and the same reference numerals are used for like elementsO However, the endmost electrodes`20 of the parallel registers 14 a.re linearly off-set with transfer gates 30 ~or transferring charge f.rom the01 columns to the output register being closer to the output register than the transfex gates 32 which transfer charge from the 02 columns of the parallel registers to the output register 16. As will be described further hereinbelow, the transfer gates 3Q respond to a signal RB, and the transfer gates 32 respond to a signal R~ whereby charges from.the 01 and 02 oolumns are selectively transferred through storage gates 34 and transfer gates 36 to the storage gates 37. The storage gates 34 are controlled by a signal RC and ~he trans~
~ex and storage gates 36 and 37 are controlled by a signal RD. Transfer ~o the storage gates of the output serial register 16 is controlled by the serial gate 01. Importantly, the interlaciny of data from the parallel registers to the ~ 7-- .
registers. Since charge is transferred to the serial register 16 from storage electrodes 37 in response to the serial register ~1 clock, critical timing is not required.
Figures 4A-4D illustrate the transfer of charge from the parallel registers to the output serial register in the array of Figure 3. As illustrated in Figure 4A the charge in the 01 parallel registers is offset from the charye in the 02 registers due to charge in the ~1 columns residing under storage gates 34 and charge in the ~2 columns being under electrodes 20. In Figure 4B, charge in the 01 columns is transferred from the storage gates 34 to the 01 electrodes of the output register 16. After this charge is moved from the output register, the charge in the 02 columns is trans~
erred through the storage electrodes 37 to the serial register 16. This charge could be trans~erred to the 02 electrodes of register 16, by separate storage gates, ~ut by sharing the storage gates 37 the charge can be transferred to the 01 electrodes, as will be described with reference to Figure S. After the charge is transferred to the register 16, as shown in Figure 4D, the charge can be removed from the output register by the two phase clocking. Importantly, the intermediate voltage Vcc is eliminated and the interlacing of the charge occurs iIl the slow transfer regîon o~ the parallel registers rather than at the fast transfer regions of the output serial register 16. Further, critlcal timing in the charge transfer to the serial output register is eliminated by using the serial register 01 clock for charge transfer.
Figure 5 is a more detailed schematic of a portion of the array of Figure 3 in accordance with one embodiment of the present invention and further illustrating the endmost electrodes 20 of the parallel registers, the transfer gate 3s electrodes 30 for the ~1 channels, the transfer electrode 32 for the ~ channels, the storage electrode 34, the transfer electrode 36 and .the storage electrodP 37. The structures are similar to the semiconductor structures in U. S. Paten~
7~
No. 4,165,541, with the parallel channels defined by channel stop implant or by field oxlde 40 and the doped barriers between electrodes in the parallel registers and the output serial register indicated by cross hatching 42. The transfer gates 30 and 32 are polycrystalline silicon, or polysilicon, electrodes overlying the barriers in the 01 channels and the 02 channels, respectively. Storage electrodes 34 are polysilicon overlying the ~1 channels between the barriers 43 and the barriers 45 and overlying the 02 channels ~etween the barriers 44 and the barriers 45. The charge from the storage gates 34 in the 01 and 02 columns can be respecti~ely transferred through separate transfer gates to the serial output register 16. However, in this embodiment one storage gate 37 is used for two adjacent 01 and 02 columns whereby charge rom the two columns are alternately transferred throug~ the storage gate 37 to the 01 gates of the serial output register. The transfer gates 36 have a polysilicon electrode comprising polysilicon 48 overlying the doped barrier 45 and the storage gates 37 ~0 comprises polysilicon overlying the charge storage region.
The 01 electrodes of the serial output register overlap barriers 52 between the storage gates 37 and the serial register.
Detailed operation of the SPS CCD array is illustrated in Figures 8-15 and will be described with reerence to the timing diagram given in Figures 6A-6C and the electrical schematic of adjacent 01 and 02 columns shown in Figure 7O
As shown in Figure 7, the endmost electrodes 20 of the two parallel columns are controlled by voltage Rl. The transfer gates 30 and 32 are controlled by voltages RA and RB, respectively. Storage gate 34 is controlled by a voltage Rc, and the transfer gate 36 and storage gate 37 are controlled by a voltage RD. Charge is transferred into a gate of the output serial regis~er 16.
Xefexring now to Figure 6, the ~1 2nd ~2 signals for trans-ferring charge in the serial registers are giYen along with by a voltage RD. Charye is transferred into a gate of the output serial register 16.
Referring now to Figure 6, the 01 and 02 signals for trans-fexring charge in the serial xegisters are given along with the ripple voltages Rl-R~ for transferring charge in the parallel registers. The control voltages RA, RB, Rc, and RD are then shown in time sequence with respect to the 01 and 02 voltages and the Rl-~8 ripple voltages.
Referring now to Figures 8-15 the transfex of charge from the parallel registers to the output serial registPr is illustrated at times tl-tl2 (as shown in Figures 6A-6C).
In E'igure 8 at time tl charges are present under the endmost electrodes of the parallel registers. In Figure 9 at times t2, t3, and t4 charges are transferred from the ~1 channels to the storage gate 34 in response to R~ and Rc.
In Figure 10 at time t5 the charges in the storage gates 34 are transferred through the transfer gate 36 to the storage gate 37 in response to RD. In Figure 11 charges are trans-ferred to the output sexial register from the parallel register in response to the serial register clock 01 during the time period t6. The charges are then clocked out of the ~5 serial register beginning with time period t7, as shown in Fi~ure 12.
As shown in Figure 13 at times t8, t9, and tlO while the charges in the output serial register are being clocked out, the charges in the 02 channels of parallel registers- are transferred to the storage gates 34 in response to RA and Rc. At time tll the charges in the storage gates 34 are then transferred to the storage gate 37 in response to RD
for loading in the serial output register 16. Finally r at time tl~ the charges in the storage gate 37 are transferred into the output register 16 in response to the ~1 voltage.
By interlacing the charge at the endmost electrodes of the parallel registers and transferring the charge through shared s-torage gates in accordance with the invention, charge transfer -timing is not cri~ical and the use of an intermediate voltage is not required. Moreover, the struc-ture can be used.with CCD devices operating at lower voltagesthan presently used. Importantly, transfer to the serial shift register is obtained by the use of the serial clock 01. While the invention has been described with reference to a specific embodiment, the description is illustrative of the invention and is not to be construed as limiting the invention4 Various modifications and applications may occur to those skilled in the art without departing from the true spixit and scope of the invention as defined by the appended claims.
MET~OD OF TRANSF'ERRING C~RGE THEREIN
This invention relates generally to charge coupled devices tCCD's), and more particularly the invention relates to CCD memories e~ploying a serial-parallel-serial (SPS) arrangement~
A two phase serial-parallel-serial charge-coupled device memory ~SPS CCD) is disclosed by Varshney, Venkateswaran, and Amelio in U.S. Patent No. 4,165,541O The memory has a group of parallel shit registers with an input serial shift regi~er at one end of the group and an output serial shiEt register at the opposite end of the group.
Data are supplied to tlle input serial register at the rate of the two phase clock signals, and after the register is filled a serial to parallel transfer operation loa~s the lS data in the parallel shiEt registers. The data are transerred through the parallel shift registers, usin~
ripple clocking, and a parallel to serial transfer oeration then loads the data into the ol1tput serial shi~
register.
The memory uses a convention~l interlacing technique in whlch one.pa.rallel shift register is provided for each element o the input or output serial shift registers.
~sing the two phase electrode structure for the input and output registers the data are transferred to or from the ,", .: ~
parallel registers at the cor~ect phase s.o that charges are alternately transEerred to or from alternate parallel regi.sters.
Heretofore, transEer of charge ~rom the parallel registers to the output serial register has required an intermediate voltage level applied to the last storage gate~ This intermediate voltage level ensures that the data in alternate parallel channels are transfer-red to the serial gates which are at a high potential (E.G. either ~1 or ~2) r and the data from other alternate parallel channels are not transferred due to the intermediate voltage level at the last storage gates being higher than the potential of the serial gates where charge transfer is not wanted. Not only is the intermediate voltage level required, but timing is critical since charge from the parallel registers is transferred and interlaced directly into the fast transfer operation of the serial register.
A general object of the present invention is an im-roved SPS CCD memory.
In accordance with one aspect of the invention a two phase SPS CCD memory array includes means for transEerring charge Erom parallel registers to a serial output register comprising a 2a first transfer gate associated with each Eirst alternate parallel register, a second trans:Eer gate associated with each second alternate parallel register, a first storage gate associated with each first transfer gate, a second storage gate associated with each second transfer gate, a third storage gate associated and shared with each first storage gate and each second storage gate whereby charge from a Eirst storage gate and from a second storage gate are alternately loaded into said third ?~
storage gate, and means for controlling said first trans~er gates and said second transfer gates whereby charge from said first alternate parallel registers is trans~erred through said first storage gates and said third storage gates to said serial output register in response to a serial register clock sign~l and then charge from said second alternate parallel registers is trans-ferred through said second storage gates and said third storage gates to said serial output register in response to a serial register clock si.gnal.
Another aspect of the invention includes a two phase SPS CCD memory array, a method of transEerring charge Erom paral-lel registers to a serial output register using clock signals of said serial output register comprising the steps of a) trans-ferring first charge from first alternate parallel registers to first storage gates, b) transerring said first charge from said first storage gates to shared storage gates~ c) transferring said first charge from said shared stroage gates to said serial output register in response to a clock signal of said serial output register, d) transferring second charge from second a].ternate parallel register to second storage gates, e) transferring said second charge from said second storage gates to said shared storage gates, and f) transferring said second charge from said third storage gates to said serial output register in response to a clock signal of said serial output register.
A further aspect of the invention comprises a two phase SPS CCD array, charge transfer means comprising a firs-t ~7~
endmost storage element of a first parallel register, a second endmost storage element of a second parallel register, a first transfer element associated with said Eirst endmost storage element, a second transfer element associated with said second endmost storage elemen-t, a first lntermediate storage element associated with said first trans~er element, a second intermediate storage element associated with said second transfer element, and a common storage element associated with said first and second intermediate storage elements whereby charge from said first endmost storage element is transferred through said first transfer element and said first intermediate storage element to said common storage element r and then charge from said second endmost storage element is transferred through said second transfer element and said second intermediate storage element to said common element.
The invention and objects and features thereof will be more readily apparent from the following detailed description and appended claims when taken with the drawing, ln which: Figure 1 is a schematic of a prior art SPS CCD arra~.
Figure 2A-2D are illustrations oE charge transer in the array of Figure 1.
-3a-~ 7 7 r ``. ~ ' .!
Figure 3 is a schematic of one embodiment of an SPS CCD
array in which the present invention can be employed.
Figures 4A-4D are illustrations of charge transfer in the array of Figure 3.
Figure 5 is a more detailed schematic of a portion of th~
SPS CCD array o~ Figure 3 in accordance with one embodiment of the present invention.
Figures 6A-6C are a timing diagram for the charge transfer in the array of Figure 3.
Figure 7 is an electrical schematic of two adjacent parallel channels of the SPS CCD array of Figure 5.
Figures 8-15 illustrate the transfer of charge in accordance with the timing diagram of Figure~ 7.
Referring now to thP drawings, Figure 1 is a schematic of an SPS CCD array as disclosed in U. S. Patent No. 4,165,541.
The CCD memory array 10 i5 arranged as a serial-parallel-serial memory and includes interlacing of data to and from the parallel registers and ripple clocking of the parallel shift registers to incxease the bit storage capacity.
parallel shift register of the block shown includes nine groups of eight electrodes, to which ripple clock signals Rl, ---RB, respectively, are applied, each group being capable o storing seven hits o~ information~ An inpu~ serial register 12 includes 32 electrodes associated with each o the 01 and ~ clock signals for a total of 64 elec~rodes.
In operation/ data are supplied to serial input shift regis-t~r 12 which is driven by clock signals ~1 and 0~. The data are stepped across the serial shift register in a conventional two phase CCD mannex. As soon as the serial shit regist~r is filled with one bit stored beneath every other electrode, a signal 0TI is supplied to allow these bits of information, represented by charge packets stored beneath the serial register electrodes, to be transferred into the input elec-trode of every other parallel shift register 14. Then, additional data are stepped into the serial shift register by application of signals 01 and 02. Once the data are stored under every other elec~rode in the input serial shift register, this time residing under electrodes not used in the previous transfer, signal ~Tl is again supplied to allow the charges under the electrodes to be transferred into the input elemen~ of the remaining unused alternate parallel shift registers n Once this is complete, ripple clock signals Rl, R2 R8 are applied to the groups of elements of the parallel shif~ registers to ~ransfer the data along the parallel registers. When the input electrode of each o~ the parallel shift registers is vacant, new data from the input lS serial shift regiq~er are transferred and the process is repeated.
The application of the ripple clock ~ignals results in the rippling movement of ~4 bit~ of data in the parallel shift registers. That is, a blank potential well is moved backward in each group of eight electrodes of the parallel shift registers, thereby transferring the data forward one electrode for each eight electrodes thàt the blank moves backward.
Signal 0T~ is applied to cause a trans~er of the data from the output electxode of every other one of the 64 parallel shift registers to be transferred into corresponding alter~
nating electrodes of the output serial shift re~ister.
These data are then stepped out of the output serial register by the application of signals 01 and 02. As soon as the output serial register is vacant, another transfer from the parallel shift register is initiated.
To perform the charge transfer from alternate parallel registers 14 to the output serial register 16~ an additional gate 18, is provided. Signal Vcc is applied ~o electrode 18 to provide an intermediate ~oltage level between the high level of 01 ~or 02) and the low level of 02 ~or ~1) to 7~7~
J
selectively block charge transfer to the low level clock 02 (or ~1) Figures 2A-2D illustrate c.harge ~ransfer from the parallel registers 14 to the output sexial register 16 of th~ array of Figure 1. In Figure 2A the stored charge, designated by xls, under the Vcc electrodes 18 of ~he parallel registers are aligned awaiting transfer. In Figure 2B the charges in the 01 registers are transferred to the output serial register 16 through the transfer gates 22 when 01 is high and ~2 is low.
As above described, the Vcc voltage on ëlectrodes 18 prevents the transfer of charge to the low 02 electrodes of output register 16. After the 01 charges are removed from the out-put register, the 02 charges under the electrodes 18 are then transferred to the serial re~ister 16 while 02 is hi~h and 01 is low as shown in Figure 2C. In Figure 2D the transferred charges are loaded in the output register ready for transfer from the array.
Figure 3 is a schematic of one embodiment of an SPS CCD array in which the present invention ca.n be employed. The array is similar to the array.of Figure 1 and the same reference numerals are used for like elementsO However, the endmost electrodes`20 of the parallel registers 14 a.re linearly off-set with transfer gates 30 ~or transferring charge f.rom the01 columns to the output register being closer to the output register than the transfex gates 32 which transfer charge from the 02 columns of the parallel registers to the output register 16. As will be described further hereinbelow, the transfer gates 3Q respond to a signal RB, and the transfer gates 32 respond to a signal R~ whereby charges from.the 01 and 02 oolumns are selectively transferred through storage gates 34 and transfer gates 36 to the storage gates 37. The storage gates 34 are controlled by a signal RC and ~he trans~
~ex and storage gates 36 and 37 are controlled by a signal RD. Transfer ~o the storage gates of the output serial register 16 is controlled by the serial gate 01. Importantly, the interlaciny of data from the parallel registers to the ~ 7-- .
registers. Since charge is transferred to the serial register 16 from storage electrodes 37 in response to the serial register ~1 clock, critical timing is not required.
Figures 4A-4D illustrate the transfer of charge from the parallel registers to the output serial register in the array of Figure 3. As illustrated in Figure 4A the charge in the 01 parallel registers is offset from the charye in the 02 registers due to charge in the ~1 columns residing under storage gates 34 and charge in the ~2 columns being under electrodes 20. In Figure 4B, charge in the 01 columns is transferred from the storage gates 34 to the 01 electrodes of the output register 16. After this charge is moved from the output register, the charge in the 02 columns is trans~
erred through the storage electrodes 37 to the serial register 16. This charge could be trans~erred to the 02 electrodes of register 16, by separate storage gates, ~ut by sharing the storage gates 37 the charge can be transferred to the 01 electrodes, as will be described with reference to Figure S. After the charge is transferred to the register 16, as shown in Figure 4D, the charge can be removed from the output register by the two phase clocking. Importantly, the intermediate voltage Vcc is eliminated and the interlacing of the charge occurs iIl the slow transfer regîon o~ the parallel registers rather than at the fast transfer regions of the output serial register 16. Further, critlcal timing in the charge transfer to the serial output register is eliminated by using the serial register 01 clock for charge transfer.
Figure 5 is a more detailed schematic of a portion of the array of Figure 3 in accordance with one embodiment of the present invention and further illustrating the endmost electrodes 20 of the parallel registers, the transfer gate 3s electrodes 30 for the ~1 channels, the transfer electrode 32 for the ~ channels, the storage electrode 34, the transfer electrode 36 and .the storage electrodP 37. The structures are similar to the semiconductor structures in U. S. Paten~
7~
No. 4,165,541, with the parallel channels defined by channel stop implant or by field oxlde 40 and the doped barriers between electrodes in the parallel registers and the output serial register indicated by cross hatching 42. The transfer gates 30 and 32 are polycrystalline silicon, or polysilicon, electrodes overlying the barriers in the 01 channels and the 02 channels, respectively. Storage electrodes 34 are polysilicon overlying the ~1 channels between the barriers 43 and the barriers 45 and overlying the 02 channels ~etween the barriers 44 and the barriers 45. The charge from the storage gates 34 in the 01 and 02 columns can be respecti~ely transferred through separate transfer gates to the serial output register 16. However, in this embodiment one storage gate 37 is used for two adjacent 01 and 02 columns whereby charge rom the two columns are alternately transferred throug~ the storage gate 37 to the 01 gates of the serial output register. The transfer gates 36 have a polysilicon electrode comprising polysilicon 48 overlying the doped barrier 45 and the storage gates 37 ~0 comprises polysilicon overlying the charge storage region.
The 01 electrodes of the serial output register overlap barriers 52 between the storage gates 37 and the serial register.
Detailed operation of the SPS CCD array is illustrated in Figures 8-15 and will be described with reerence to the timing diagram given in Figures 6A-6C and the electrical schematic of adjacent 01 and 02 columns shown in Figure 7O
As shown in Figure 7, the endmost electrodes 20 of the two parallel columns are controlled by voltage Rl. The transfer gates 30 and 32 are controlled by voltages RA and RB, respectively. Storage gate 34 is controlled by a voltage Rc, and the transfer gate 36 and storage gate 37 are controlled by a voltage RD. Charge is transferred into a gate of the output serial regis~er 16.
Xefexring now to Figure 6, the ~1 2nd ~2 signals for trans-ferring charge in the serial registers are giYen along with by a voltage RD. Charye is transferred into a gate of the output serial register 16.
Referring now to Figure 6, the 01 and 02 signals for trans-fexring charge in the serial xegisters are given along with the ripple voltages Rl-R~ for transferring charge in the parallel registers. The control voltages RA, RB, Rc, and RD are then shown in time sequence with respect to the 01 and 02 voltages and the Rl-~8 ripple voltages.
Referring now to Figures 8-15 the transfex of charge from the parallel registers to the output serial registPr is illustrated at times tl-tl2 (as shown in Figures 6A-6C).
In E'igure 8 at time tl charges are present under the endmost electrodes of the parallel registers. In Figure 9 at times t2, t3, and t4 charges are transferred from the ~1 channels to the storage gate 34 in response to R~ and Rc.
In Figure 10 at time t5 the charges in the storage gates 34 are transferred through the transfer gate 36 to the storage gate 37 in response to RD. In Figure 11 charges are trans-ferred to the output sexial register from the parallel register in response to the serial register clock 01 during the time period t6. The charges are then clocked out of the ~5 serial register beginning with time period t7, as shown in Fi~ure 12.
As shown in Figure 13 at times t8, t9, and tlO while the charges in the output serial register are being clocked out, the charges in the 02 channels of parallel registers- are transferred to the storage gates 34 in response to RA and Rc. At time tll the charges in the storage gates 34 are then transferred to the storage gate 37 in response to RD
for loading in the serial output register 16. Finally r at time tl~ the charges in the storage gate 37 are transferred into the output register 16 in response to the ~1 voltage.
By interlacing the charge at the endmost electrodes of the parallel registers and transferring the charge through shared s-torage gates in accordance with the invention, charge transfer -timing is not cri~ical and the use of an intermediate voltage is not required. Moreover, the struc-ture can be used.with CCD devices operating at lower voltagesthan presently used. Importantly, transfer to the serial shift register is obtained by the use of the serial clock 01. While the invention has been described with reference to a specific embodiment, the description is illustrative of the invention and is not to be construed as limiting the invention4 Various modifications and applications may occur to those skilled in the art without departing from the true spixit and scope of the invention as defined by the appended claims.
Claims (6)
1. In a two phase SPS CCD memory array, means for transferring charge from parallel registers to a serial output register comprising a first transfer gate associated with each first alternate parallel register, a second transfer gate associated with each second alternate parallel register, a first storage gate associated with each first transfer gate, a second storage gate associated with each second transfer gate, a third storage gate associated and shared with each first storage gate and each second storage gate whereby charge from a first storage gate and from a second storage sate are alternately loaded into said third storage gate, and means for controlling said first transfer gates and said second transfer gates whereby charge from said first alternate parallel registers is transferred through said first storage gates and said third storage gates to said serial output register in response to a serial register clock signal and then charge from said second alternate parallel registers is transferred through said second storage gates and said third storage gates to said serial output register in response to a serial register clock signal.
2. Means for transferring charge as defined by Claim 1 wherein said first and second transfer gates are linearly offset to prevent concurrent charge transfer from said first alternate parallel registers and said second alternate parallel registers.
3. In a two phase SPS CCD memory array, a method of transferring charge from parallel registers to a serial output register using clock signals of said serial output register comprising the steps of a) transferring first charge from first alternate parallel registers to first storage gates, b) transferring said first charge from said first storage gates to shared storage gates, c) transferring said first charge from said shared storage gates to said serial output register in response to a clock signal of said serial output register, d) transferring second charge from second alternate parallel register to second storage gates, e) transferring said second charge from said second storage gates to said shared storage gates, and f) transferring said second charge from said third storage gates to said serial output register in response to a clock signal of said serial output register.
4. The method of transferring charge as defined by Claim 3 wherein each of said shared storage gates alternately receives first charge from a first storage gate and second charge from a second storage gate and alternately transfers said first charge and said second charge to a storage gate of said serial output register in response to clock signals of said serial output register.
5. In a two phase SPS CCD array, charge transfer means comprising a first endmost storage element of a first parallel register, a second endmost storage element of a second parallel register, a first transfer element associated with said first endmost storage element, a second transfer element associated with said second endmost storage elements a first intermediate storage element associated with said first transfer element, a second intermediate storage element associated with said second transfer element, and a common storage element associated with said first and second intermediate storage elements whereby charge from said first endmost storage element is transferred through said first transfer element and said first intermediate storage element to said common storage element, and then charge from said second endmost storage element is transferred through said second transfer element and said second intermediate storage element to said common element.
6. Charge transfer means as defined by Claim 5 wherein said common storage element is associated with a storage element of an output serial register whereby charge from said first endmost storage element and charge from said second endmost element are alternately transferred from said common storage element of said output serial register in response to a clock signal of said output serial register.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US24177581A | 1981-03-09 | 1981-03-09 | |
| US241,775 | 1981-03-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1187177A true CA1187177A (en) | 1985-05-14 |
Family
ID=22912131
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000397790A Expired CA1187177A (en) | 1981-03-09 | 1982-03-08 | Serial-parallel-serial charge coupled device and method of transferring charge therein |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS57210496A (en) |
| CA (1) | CA1187177A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL8105397A (en) * | 1981-11-30 | 1983-06-16 | Philips Nv | LOAD-COUPLED DEVICE. |
| US4873760A (en) * | 1986-12-29 | 1989-10-17 | Ishikawajima-Harima Heavy Industries Co., Ltd. | Vessel lid mounting and demounting apparatus |
| US4862235A (en) * | 1988-06-30 | 1989-08-29 | Tektronix, Inc. | Electrode structure for a corner turn in a series-parallel-series charge coupled device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2836080B1 (en) * | 1978-08-17 | 1979-10-11 | Siemens Ag | Charge shift memory in serial-parallel organization with strictly periodic clock control |
-
1982
- 1982-03-08 CA CA000397790A patent/CA1187177A/en not_active Expired
- 1982-03-09 JP JP3595282A patent/JPS57210496A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57210496A (en) | 1982-12-24 |
| JPH0415560B2 (en) | 1992-03-18 |
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