CA1185713A - Digital data packet transmission system - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

A digital data packet transmission system especially -but not exclusively- useful in videotex transmission uses a continuous transmission carrier. Data packets are individually included in transmission blocks which are periodically transmitted, with dummy packets being used to fill the blocks, if necessary. The period of the transmission blocks are exactly equal or a little longer than the maximum length of the transmission blocks. The beginning of each transmission block has a synchronization pattern which is constituted by a "bit sync" byte followed by a "byte sync" byte. The signals (except for the synchronizing pattern) are scrambled before transmission and descrambled upon receipt and recognization of the synchronizing pattern.

Description

The present invention relates to a digital data multiplex system for digital data to ~e transmitted or broadcasted through telecommunication satellites and/or ground stations. More generally, the multiplex system may be used with any transmission and/or recor-5 ding means~
The transmission of digital sound information and the transmis-sion of digital data intended for various serviccs by using satellite broadcasting means or ground broadcasting networks contitue a neh broadcasting or transmission service that causes to provide a new lO broadcasting system the implementation of which should not disturb the operation of existing receiver sets as long as they have not totally been replaced by new standard receiver sets.
Some of those new services require large capacity channels, particularly with respect to the digital transmission of at least 1~ four high monophonic quality "sound~' channels, ot any other similar cornbination of hih quality stereophonic or monophonic sounds. Other services require lower bit rate channels, particularly for trans-mitting teletext data, captioning data, telecopier data, etc. Indeed, a 2 ~qbit channel must be provided together with a simple flexible 20 procedure for multiplexing the various services using that channel.
hs ~ar as such a channel is concerned, two types of structures are well known: first continuous rate channels transmitting digital network multiplex and more particulaly 2.048 ~bit/s multiplex of level TN1 as defined in the recommendation G732 of the CCITT; second, 25 packet channei transmission. Those two-structures have advantages and drawbacks when applied to broadcasting. Both have a common advantage, that is they have been successfully experienced and even exploited for several years.
Continuous rate channels, well known in the transmission field, 30 are used for transmitting sound or voiced signals. The capacity of such 2.048 Mbit~s channels is of five or six high quality monophnonic channels depending on the utilized coding process. They have two draw-backs. On the one hand; they provide easy multiplexing for signals having rates that multiple of 64 kbit/s. On the other hand, 64 k~it/s 35 is the minimum rate for direct insertion, without need of an addi-tional multiplexing level.

1`~

7~ 3 ~ acket transmission has the follo~Jing advantaces. It is simple 5 to perform. It malces the insertion of ~synchronous channels easy. It requires no specific values and more particularly no minimum limit for entering rates. ~acket multiplexing being based on transmitted packet identification, demultiplexing process is performed in a very simple manner in the receivers. Ressourcc sharing is programmable and changeable without imposing requirements in receivers. Demultiplexing and coupling to terminal units may be embodied with integrated circuits.
On the opposite, packet broadcasting has the following draw-backs. At the receiver end, packet selection process causes packets to be lost in the case of degraded signals, ~hich results in a major degradation of the quality of the service. ~t has been experienced that loss rate of packets is usually low as well in satellite broadcasting as ground station broadcasting for usual propagation conditions. However such a phenomenon, when it occurs, should not Zo cause a substantial degradation of service. hs a result the use of packet multiplexing for sound broadcasting limits the useful capacity of a 2.048 Mbit/s channel at the equivalent of four high quality rnonophonic sounds.
In )tnown continuous carrier data packet transmission systems, data are transmitted to a modulator which inserts specific trans-mission block start and stop signals which are used in the demodu-lator to provide a correct operation thereof, that is possibly to restore the carrier wave and particularly to regenerate the bit clock. ~hen considering the most usual case of a transparent modula--tor, those specific start and stop signals are transmitted irres--pective of the packet structure of the data flow. Otherwise said t those specific may be located within a packet and there may be several packets between two specific signals. In the field, with bad transmission condition, the loss of entire packet at the reception end causes less trouble than packet mutilation.
A purpose of the present invention is to provide a transmission system overcoming the above mentioned drawbacks and wherein data packets are periodically transmitted.
Such a system has already been described in the French patent

2,44~,370 ~herein there is provided a data signal made of packs or }~

01 _ 3 _ 02 packets each including a synchronization signal (SI) followed by 03 a field of data (CD). In that French patent, each field of data 04 (CD) is not a so-called data packet.
05 A packet transmission system is also known which serves 06 to broadcast data within a TV channel. Such a system is 07 described particularly .in the U.S. patent 4,058,830.
08 In accordance with one embodiment of the invention, a 09 system is provided for transmitting digital data pac]cets comprising transmitter apparatus for periodically transmitting 11 blocks of data in a form of data packets, the period for 12 transmitting the blocks of data containing I clock pulses which 13 define a period which is at least as long as a block of data, 14 apparatus for filling each transmission period wi-th dummy packets if the period is not otherwise filled with the digital packets, 16 and apparatus for defining the beginning of each transmission 17 block of data by a distinctive synchronization pattern of pulses 18 including a bit synchronization pulse followed by a byte 19 synchroniæation pulse~
In accordance with another embodiment of the invention, ~:l. a system is provided for transmitting digital data packets 22 comprising transmitter apparatus for periodically txansmitting ~3 blocks o:E data in a form of data packets, the period for transmitti.ng the blocXs of data containing I clock pulses which 7.~ deEine a period which is at least as long as a block of data, 2~ apparatus :Eor filling each transmission period with dummy packets ~1 i ~he period i9 not otherwise filled with the digital packets, 2~ apparatus for defining the beginning of each transmission block 29 oE data by a distinctive synchronization pattern of pulses including a bit synchronization pulse followed by a byte 31 synchronization pulse, at least one data packet receiver 32 apparatus including a memory for storing the synchronization 33 pattern, a shift register circuit for storing two successive 34 bytes, a demodulator circuit including a clock for demodulating the block of data signals and for applying the demodulating 36 signals to the signal input of the shift register. A comparator 37 circuit has first inputs connected to the output of the memory 01 - 3a -02 and second inputs connected in parallel to the output of the 03 shift register, an OR gate circult having a first input connected 04 to an output of the compara~or, first and second counter 05 circuits having a capacity of (I - 1) bits, having a clock pulse 06 input which is connected -to the demodulator clock, and having an 07 overflow output connected, on -the one hand, to a second input of 08 the OR gate ~ircuit and on ~he other hand to an initialization 09 input of the second counter circui-t. The second counter circuit has a capacity of about two bytes and has a clock pulse input 11 connected rom a comparator circuit enable input. The output of 12 the OR gate circuit is connected to an initialization input of 13 the first counter, and the output of the second count~r delivers 14 a validation signal for the transmission block of data.
Reference is now made to the drawings, which should be 16 referred to for a consideration of both prior art and the present 17 invention, in which:
18 Fig. 1 is a schematic diagram showing a sequence of l9 packe-ts, according to the known system of the U.S. Patent ~0 4,058,830, ~1 Fig. 2 is a schematic diagram showing a sequence of -transmission blocks according to this inven-tion, ~3 Fig. 3 is a block-diagram of a transmission equipment ~4 for use in the system according to this invention, and associated ~S -to the known system of the U.S. Patent 4,058,830, ~6 Fig. 4 i6 a block-diagram of a reception equipment for 27 use in the system according to this invention, and associated to 28 -the known system of the U.S. Patent 4,058,830, 29 Fig. 5 is a diagram of the adapter used in the reception equipment shown in Fig. 4, 31 Fig. 6, which appears out of consecutive order on the 32 same page as Fig. 4, shows waveforms illustrating the operation 33 of the adap-ter shown in Fig. 5, 34 Figs. 7 and 8 are block-diagrams of alternatives of the transmission and reception equipments respectively shown in 36 Figs. 3 and 4, 37 Fig. 9 is the diagram of an embodiment of -the adapter 01 - 3b -02 used in the reception equipment shown in Fig. 8, and 03 Fig. 10 is an organigram illus-trating the operation of 04 the adapter shown in Fig. 9.
05 In attached Fig. 1 there is shown a sequence of data 06 packets Pl-P4, ... , which are built as the packets described in 07 the U.S. Patent 4,058,830. Each packet Pi includes a packet 08 prefix Ek~ and a field of data Dkj, with 1 indicating the number 09 of the packet broadcasted through the system, k indicating the number of the data source originating the data packet and 11 indicating the number of the packet -transmitted from the 12 concerned data source. In each packe~ prefix and each data 13 field, data are assembled in bytes or octe~s. The packet prefix 14 comprises the flrst eight bytes of the packet and the data field may include up to 32 bytes, that is a maximum as far as the 16 French TV standards are concerned.
17 Within the packet prefix, the first two bytes 1 and 2 lB are proposed for the "bit" synchronization and each are composed 1~ of the bit sequence 10101010, byte 3 is purposed for the "byte"
synchronization and may correspond to the bit sequence 11100111;
~L bytes ~, 5 and 6 are alloted to the service identification, that is the source identiEication; byte 7 indicates the packet index and permits to recognize i.n the receiver equipment whether or not a pack~ has been lost; finally byte 8 indicates the data field ~'; eormat, i.e. the length of the data field expressed by the number ~6 0 e the last byte having a meaning.
~7 Each packet shown in Fig. 1 is carried on a TV picture ~B llne ln a TV channel. Packets may be transmitted on any TV
29 channel picture line or only some of them in a well known manner.
In other words, in the system described in the UOS.
31 patent 4,058,830 the data packet broadcasting involves a time 32 sharing multiplexing that may be divided into two levels. As 33 ~hown in Fig. 1, there i5 a multiplexing of the data from a 34 plurality of sources, each source being described by the contents of bytes 4-6, which creates as many data channels as sources.
36 The packets are inserted in every TV picture line or in 37 some of them only. Of course, TV picture lines carrying digital 38 data are not visible on the ~V receiver screen.
In thc system described in the ~.S. patent 4,058,830, as shown in Figs. 1 and 6 accompanying the specification thereof, reception circuits comprise a TV receiver set which delivers ~rom its video out 5 put video signals to the properly said processing equipment, which comprises a demodulator (or demodulation portion 61) and a demultiple-xer (or logic portion 62). The demodulator derives the digital multi-plex from the video signals and delivers to the demultiplexer the se-rially arranged digital data DS, correctly phased bit clock HD and a 10 validation signal VAL indicating to the multiplexer that a data pa--cket is present in the processed TV line. From the prefix information the demultiplexer selects a digital channel, i.e. the desired source, and delivers the useful data to utilization means.
To be noted that in that known system the beginning of each pa-15 cket is preceded by the line sync signal of the ~V signal. Thereforethere is no ambiguity for identitifying the first bytes of each packet.
A purpose of this invention is to provide a transmission system operating with a continuous transmission carrier - contrary to a TV
20 signal that is a pulsed carrier - wherein use is made of a packet organization similar to that described in the U.S~ patent 4,058,830 and a modulation suitable for the -transmission carrier.
According to a feature of this invention, there is provided a a digital data packet transmission system using a continuous transmis-25 sion carrier wherein data packets are individually included in trans-mission blocks which are periodically transmitted, with transmission blocks containing dummy packets if necessary, for instance on a carrier modulated at 2.048 Mbit/s with MSK modulation, the period of the transmission blocks, every I clock pulses, being exactly equal or 30 a little longer than the maximum length of the transmission blocks, the beginning of each transmission block comprising a synchronization pattern constituted by a "bit sync" byte followed by a "byte sync"
byte, the above mentioned rate value as well as the modulation type being, of course, given by way of example.
In the system according to this invention, the structure nf the transmission blocks is very similar to that of the packets described in the U.S. patent 4,058,830 so that each receiver equipment also includes a demodulator, for instance operating with the used r~s~

. 3 modulation and delivering the above mentioned signals DS, HD and VAL, and a demultiplexer as described in the said U.S. patent. Hereafter in the demodulator consideration will be separately given to the properly said demodulation circuits and the adapter that delivers signals DS, HD and VAL.
The main purpose of the adapte- is to detect the synchroniza-tion pattern before each packet prefix, such a synchronization pat-tern being constituted by the "bit sync" byte and the "byte sync"
byte, and to deliver the signal VAL to the demultiplexer.
Indeed the synchronization pattern is used as a time reference for processing the following packet. In other words, the synchroniza-tion pattern fulfills the fonction of the TV line sync signal in the system described in the U.S. patent 4,058,830. To be noted that the "byte sync" byte cannot alone constitute the synchronization pattern because it might be confused with another byte of the data field or of the packet prefix.
The confusion of the "byte sync" byte with a byte of the data field is not too troublesome. Indeed as the data usually change from a field to another one, permanent false synchronization would be avoided. On the opposite, such a confusion with a byte belonging to the packet prefix Gan entirely disturb the communication. As a matter of fact, in a packet prefix data are much less changing than in the following field of data, particularly in the case of a multiplex comprising no more than one or a few digital channels. With a sequence of two bytes of the Hamming code, it would be sufficient to indepenaently select the last four bits of the first byte and the first four bits of the second byte to rebuild the "byte sync" byte and then causes such a trouble. Certain configurations of identifiers X, Y, Z cause false synchronizations which may be stable.
According to this invention, instead of the "byte sync" byte alone, use is made of a sequence of 16 bits comprising the "bit sync"
byte, or at least the last one, with the "byte sync" byte. In order to preclude false synchronizations on bytes of the packet bytes, every configuration of triplets of compatible synchronization pat-35 terns represented in hexadecimal notation by E7, 21, B4 and E7, 2D, 84 have been examined. Each synchronization pattern made of lOlOlOlC) followed by the ~'byte sync" byte has successively ceen compared with the first 16 configurations obtained by shifting the sequence of 32 bits composed of:

7~3 - the last three "byte sync" byte bits, in direct order and in reverse orderj - sixteen configurations for each of the following three bytes belonging to the Hamming code, i.e. in hexade-cimal:
A~, 40, 92, 7A, 26, CE, lC, F4, 0~, E3, 31, D9, 85, 6D, BF, 57, - five bits randomly selected in order to complete the 32 configurations.
In the hereafter included table, there is mentioned the lists of the sequences which might result in at least one identity with the searched sequence. No identity has been found out for bytes B4 and 2D.
A byte cannot be used in the synchronization pattern if there is at least one identity with the last byte nil. Indeed, in that 15 case, an identity is encountered in the first three bytes and the utilization of some address configurations may cause a false trans-mission block synchronization.
Thus bytes 21 and 84 cannot be used. On the opposite bytes E7, as in the ~.S. patent 4,058,830, plus ~4 and 2D can be used.
20 Associated to the "bit sync" byte, they can be used as synchroniæa-tion patterns.
In some types of demodulators, as differential or coherent demo-dulators, a sign ambiguity systematically occurs in the demodulated signal. In known systems ambiguity is removable by using a specific 25 encoding. According to a feature of this invention, removing sign ambiguity is performed by detecting the sign of the "byte sync" byte and using the detection result either for reversing or not the data polarities in the receiver.
according to another feature, in a data packet receiver used in 30the system according to this invention, there is provided a memory storing the synchronization pa~tern, a shift register capable to store two successive bytes, the demodulated binary signals being applied to the said shift register serial input, a comparator whose first inputs are connected from the said memory outputs and second 35inputs are connected from the said shift register parallel outputs, the comparator output being connected to the first input of an OR
gate, a first cow~ter having a capacity of (I - 1) bits whose clock input is connected from the demodulator bit clock and overflow output o o o o o o o o o o o o o o o o o o ~ ~ ~ ~ ~ ~ ~ ~ ~r ~ ~ ~ ~
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V Ln Ln Ln Ln Ln Ln Ln Ln Ln Ln Ln Ln Ln Ln Ln Ln Ln Ln Ln Ln Ln Ln Ln Ln Ln Ln Ln Ln Ln Ln Ln Ln ~ Ln a Ln Q Ln a Ln a Ln a Ln L:~ Ln a Ln a m a Ln a Ln a Ln a Ln a Ln a Ln a Ln a r . 0 ~D 0 lD 0 ID 0 ~D 0 LD 0 LD 0 ~ 0 ID 0 (S~ 0 ID 0 ID 0 ID 0 ID 0 LD 0 ID 0 ID
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a ~ ~ r ~ n~ t~ t~ r.~ N t~ V ~ ~I r~ rSl r~ t~ ~ a a 0 0 ~D ~D m m Ln Ln .3 is connected, on the one hand, to the second input of the said OR
gate and, on the other hand, to the initialization input of a second counter having a capacity of about two bytes whose clock input is connected from comparator enable input, output of the OR gate being connected to the initialization input of the first counter, output of the second counter delivering a validation signal for the trans-mission block.
According to another feature, the said memory is comprised of a first and a second memory, the said comparator is comprised of a first and a second comparator, and the shift register is comprised of a first one-byte shift register serially connected to a second one-byte shift register, the first memory storing byte 10101010 and the second memory storing the "byte sync" byte, the said receiver also comprising a hird comaparator whose the first inputs are con-nected from outputs of the first memory through inverters and hesecond outputs are connected from the first shift register, the enab].e input of the third comparator being connected from the second counter outpu-t, outputs of the first and second comparators being connected to the inputs of an AND gate whose output is connected to the ~i.rst input of the OR gate, the third comparator output being connected to the input of an inverting circuit for inverting the polarities of the received bits, the inverting circuit output being connected to the serial input of the first shift register.
In addition, it has been experienced that, when transmitting 2S data packets on a carrier, errors may occured at the demodulation end when data to be trjansmitted have peculiar structures, such as for ins-tance in the case of no binary transition, or for sequences of data causing consecutive phase shifts of 9O, or for periodic binary configurations, and so on. Indeed in those cases, the spectrum of the transmitted signal does not uniformely cover the transmission channel frequency band, but is a line spectrum which disturbs the carrier restoration, because the restoration circuits tend to tune on a line, than on another line, and so on.
it is known - see the French technical book TELEINFOR~ATIQ~E by C. Macchi and J.-F. Guilbert, published by Dunod in lg79, pages 55 and 56, paragraph "Brouillage" (Scrambling) - to avoid the transmis-sion of line spectrum signal to perform, at the transmitting end, a 7 ~
modulo-2 addition of the binary da~a train and a pseudo-random sequence and, at the receiving end, to perform a second modulo-2 addition of the received train and a pseudo-random sequence identical to the first one.
In the following description, that modulo-2 addition will be called a data scrambling operation, when it is performed at the transmitting end, and a data descrambling operation, when it is performed at the receiving end.
According to another feature, a data scrambling is performed in each transmission block, the synchronization pattern being excluded, and a data descrambling is performed in the same conditions, the pseudo-random sequences being, at both transmitting and receiving ends, generated by identical random sequence generators, the receiver random sequence generator being triggered as soon as each synchronization pattern has been recognized in each transmission block.

7~
01 The transmission equipment shown in Fig. 3 comprises a 02 "managing" unit 11, a plurality of couplers 12.1-12.n supplied 03 with data from a plurality of data sources 13.1-13.n, an interface 04 14, a modulator circuit 15, a transmitter 16, an antenna coupler 05 17 and an antenna 18. All those circuits may be entirely identical 06 to those described in Figs. 3 and 4 of U.S. Patent 4,058,830.
07 The equipment shown in Fig. 3 still comprises a second 08 "managing" unit 19, a plurality of couplers 20.1-20.n supplied 09 with data from a plurality of data sources 21.1-21.n, a coupler ~2 connected to a source 23l an interface 24, a time base 25, a 11 modulator 26, a frequency mixer 27, and a power amplifer 28 12 whose output is connected to the input of coupler 17.
13 The modulation performed in modulator 26 is a MSK
14 modulation and modulator may be of the type described in the French patent application publication 2,428,345 filed on June 6th, 1978 16 and entitled "Modulator for coherent phase shift modulation of 17 indicia 1/2 with continuity of the modulated signal phase". The 18 carrier frequency may be of about 10 MHz. The carrier is L9 transposed at the transmission of the transmitter 16 in the mixer 27 and amplified in the power amplifier 28.
2l Circuits 26, 27 and 28 are considered as well known 22 and will not be hereafter Eurther described.
~3 The modulator 15 has one input connected from a TV
picture signal source 65.
~5 Source 23 is a dummy signal generator. It is constituted by a memory that stores a constant sequence of bits ~7 which is so selected as to fit with the utilized modulation to 2B render the hit clock restoration easier.
29 Time base 25 delivers bit clock through managing circuit 18 and interface 24 to the couplers 20.1-20.n, and to 31 modulator 26. In addition it delivers the periodic block 32 starting signal of period I to the managing circuit.
33 The reception equipment shown in FigO 4 comprises an 34 antenna 29 connected to the input of a frequency mixer 30 having two outputs r one output being connected to the input of a IF
36 amplifier 31 and the other one being connected to the input of a 37 sound amplifier 32~ Output of amplifier 31 is connected to the 38 input of a detector 33 . .
.
,.~ ....

whose video output is connected, on the one hand, ~o . ~j~eodcr and display circuit 34, and, on the other hand, to a dcmodu1ator 35 who~e output is parallel connected to inputs of dernultiplexers 36 and 37.
The demodulator 35 and demultiplexers 36 and 37 altogether form a reception equipment as described in the U.S. Patent 4,058,830. De-multiplexers 36 and 37 may be associated to units, not shown, such as ANTIOPE teletext terminals.
Output of amplifier 32 is connected to the input of a detector 38 whose sound output is connected to the input of a di~ital demodula-tor 39, which delivers the restored bit clock and the data.
Output of demodulator 39 is connected to the input of anadapter 40 whose output is parallel connected to corresponding inputs of demultiplexers 41nl~41 .n which also may be associated to ANTIOPE
teletext terminals, or sound terminals.
~he reception equipment shown in Fig. 4 further comprises a key board 42 available to the user, whose output is connected to the input of a control circuit 43 whose output is connected to control inputs of demultiplexers 35, 36 and 41.1-41.n.
Pr~tically, MSK signal dem~dulator 39 has two outputs 4~ and 4S, output 44 delivering the bit clock and output 45 delivering the train ol binary data. As shown in the detailed diagram of Fig. 5, out-put 44 of demodulator 39 is parallel connected to the clock inputs of two down-counters 46 and 47. Output "O" Or down-counter 46 is connec-ted, on the one hand, to the load input of down-counter 47 and, on the other hznd, to one input of a two-input OR gate 48. The parallel inputs of down-counter 46 are connected from the parallel outputs of a memory 49 storing;the digital value of the period 1, less one.
Parallel inputs of down-counter 47 are connected from parallel out-puts of a memory 50 storin~ the value of n pulses. Output "O" of down-counter 47 is connected to the input of an inverter 51 whose outputis connected, on the one hand, through wire S2 to the enable inputs of demultiplexers 41.1-41.n and, on the other hand, to the ena~le inputs of comparators 53, 54 and 55.
Output 45 of demodulator 39 is connected to one input of al~ ex.-clusive-OR gate 56 whose output is connected tc~ the input of a shift register 57 whose output is connected to the input of a shift register 58 whose output is parallel connected throu~h wire 59 to data inputs of demultiplexers 41.141.n. Shift registers S7 and S8 are * T.rade ~rk both byte registers~ The eigh~ parallel outputs of shift register 58 are connected to the first eight parallel inputs o~ comparator 53.
the eight parallel outputs of shift register 57 are respectively connected to the first eight parallel inputs of comparators 54 and 55. the second eight inputs of comparator 53 are connected from outputs of a byte memory 60. The second eight inputs of comparator 54 are connected from the output of a byte memory 61 and the second eight outputs of comparator 55 are respectively connected from the outputs of eight inverters 62 whose inputs are respectively connected 10 fro~ outputs of byte memory 61.
Output of` comparator 53 is connected to one input of a two-input AND gate 63 whose the other input is connected from output of comparator 54 and output is connected to the second input of OR gate 48. Output of comparator 55 is connected to input "H" (clock input) 15 of a D flip-flop 64 whose output Q is connected to the second input exclusive-OR gate 56 and output Q is connected to its input "~".
Output of OR gate 48 is connected to load control input of down-counter 46.
Assuming that the value of the block transmission period is I
20 clock pulses, down-counter 46 is so designed as to cyclically count from ~I-1) down to nil, unless it is earlier reloaded by output of` OR
gate 48.
Down-counter 47 is so designed as to cyclically count down n pulses, i.e. 2 pulses, for instance.
In Fig. 6, there is shown the waveform A o~ output signal from inverter 51 wh;ch constitutes the validation signal VAL. Indeed, output of down-counter 47 is at level "l" as long as that counter is counting down, which means that width of signal VAL is of n pulses.
~'ave~orm B of output signal from down-counter 45 is ahead with 30 respect to the beginning of each period since down-counter 46 counts (I-1) pulses only. Waveform C represents the output signal from AND
gate 63. Output signal C is delivered when respective outputs of comparators 53 and 54 are coinciding which means a posi-tive compa-rison that occurs when the two bytes of the synchronization pattern 35 are simultaneously recognized in 53 and 54. As a result, when a synchronization pattern has been recognized just after signal B, down-counter 46 is again reset. Thus, when synchronization is nor-mally present 9 down-counter 46 delivers every I pulses an output ~ 13 signal to 47.
In Fig. 6, waveform D represents the signal VAL delivered at the period which follows the transmission of signal A, assuming that the synchronization pattern has ~een correctly recognized. Thus wave-form D is identical to signal A. It will now be assumed that during the next period the expected coincidence in 53 and 54 does not occur.
Then waveform E shows that the next signal VAL is still ahead by one pulse with respect to signal A. Waveforms F and G illustrate the condition when the synchronization pattern had not already been recognized at the preceding transmission block, which causes a shift ahead by one pulse at each period. If the coincidence occurs before signal V~L has been shifted ahead by _ pulses, the condition of signals A, B and C is restored. If not, it occurs at the end of a transmission block.
It i9 possible to demonstrate that the wldth n of the strobe signal VAL may be determined as a function of a given probability of an out-of-synchronization condition within a predetermined time dura-tion.
When the byte corresponding to the "byte sync" byte appears in the shift register 57, but with a reverse polarity, while signal VAL
is delivered from 47, through 51, comparator 55 delivers a positive comparisorl signal that is applied to the input "H" (clock input) of flip-flop 64 whose output Q condition changes. As a result, there is a change of polarity at the output of exclusive-OR gate 56. That polarity change permits to expect a positive comparison at the beginning of the next period.
In the adapter shown in Fig. S, as far as the functions are con-cerned, there are a circuit 66 intended for picking up the transmis-sion block synchronization and operating as a digital lock loop, a circuit 67 intended for reading synchroni~ation patterns of transmis-sion blocks, and an ambiguity removing circuit 68. Circuit G6 compri-ses down-counters 46 and 47, QR gate 48, memories 49 and 50, and inverter 51. Circuit 67 comprises comparators 53 and 54, shift registers 57 and 58, memories 50 and 61, and AND gate 63. Circuit 68 CGmprises comparator 55, inverter 62, flip-flop 64 and exclusive-OR
gate 56.
In the transmission equipment shown in Fig. 3, it is implicitly assumed that the rough packets delivered from couplers 20.1-20.n and 22 were transmitted without modification through the managing circuit 18 to the modulator 26 wherein the transmission block synchronization pattern was inserted in front of each packet. In Fig. 7, there is shown an alternative of that transmission equipment wherein there is provided within the managing circuit 19 a scrambling circuit 69 performing a binary scrambling, the data input of which is connected from data output of interface 24 and the data output of which is connected to the data input of a binary-to-signal modulation circuit 70 of the modulator 26. Another input of circuit 70 is connected from the output of a circuit 71 which periodically delivers the synchroni~ation for each transmission block. Output of modulation circuit 70 is connected to the input of a ~ilter circuit 72 for reducing the power spectrum, the output of which is connected to the frequency mixer 27. The time base 25 delivers the c]ock signals 15 needed to control and operate all those circuits. Indeed the scram-bling circuit 69 comprises a pseudo-random sequence generator 73 and an exclusive-OR gate 74 whose one input is connected from output of interface 24 and the other input is connected from output of pseudo--random sequence generator 73 and whose output is connected to the 20 corresponding input of modulator circuit 70. The pseudo-random se-quence generator 73 operates with a polynomial (x + x ~ 1) and delivers a longer sequence than packet length. The generator 73 has a triggering input 75 that is connected to a corresponding output of the time base 25.
2S The reception equipment shown in Fig. 8 is provided for receiving transmission blocks processed by the circuits shown in Fig 7. It still includes.the detector 38, demodulator 39, adapter 40 and dernultiplexers 41.1-41.n. However in this embodiment, the adapter ~G
includes a circuit 76 provided for picking up the transmission block 30 synchronization and operating a digital closed loop, a circuit 77 intended for reading synchronization patters of transmission blocks, an ambiguity removing circuit 78, a descrambling circuit 79 and a time base 80. ~ithin demodulator 39, there is also shown a circuit 81 used for restoring the bit synchroni~ation. The descrambling circuit 35 79 includes a pseudo-random sequence generator ~2, identical to the generator shown in Fig. 7, and an exclusive-OR gate 83 whose one input is connected from output of pseudo-random sequence generator 82 and the other input is connected from output of ambiguity removing circuit 78 and whose output delivers the data pac~ets to the said demultiplexers.

The adapter 40 and the circuit 81 are shown with more details in Fig. 9. The circuit 76 includes a synchronous down-counter 84, a memory 8S, a four-stage binary counter 86, a PROM memory 87 and an OR
gate 88. The memory stores the length N of the transmission blocksl that is the number of bits in each packet, plus the synchronization pattern, plus a predetermined number of bits filling the gap between the end of the packet and the next synchronization pattPrn. In the described embodiment, that predetermined gap corresponds to one bit, but may be changed. The memory 85 is obviously changeable if the transmission system is modified in this respect. Output of memory 85 is connected to the load input of down-counter 84. Output "O" of down counter 84 is connected to one input of an OR gate 88 whosc output is connected to the load enable input of down-counter 84.
Output "O" of 84 is also connected -to an address input A5 of PROM
memory 87. Clock input of down-counter 84 is connected from bit clock output H of circuit 81.
Binary counter 86 has its four outputs QO-Q3 respective]y connected to four address inputs AO-A3 of PROM memory 87. Three outputs DO-D2 of 87 are respectively connected to reset (RAZ) input, clock input and load input CH of counter~86. A fourth output D3 of PROM memory 87 is connected to the second input of OR gate 88.
Finally input A4 of PROM memory 87 is connected from output of an AND
gate 89, in circuit 77.
The operation of the digital lock loop 76 ~ill be hereafter described in conjunction with the organigram shown in Fig. lt), wherein the contents of the circles correspond to the conditions of counter 86 and the variable A is defined as follows:
- for each condition "0"-"12" and -"14" and "15", the value of A is that of A4, when A5 is at level "11', and 30- for condition "13", the value of A is that of A4, irres-pective of the value of A5.
Input A4 is at level "1" each time the synchronization pattern or the reciprocal thereof is recognized in circuit 77 while input A5 is at "1" for each zero crossing of down-counter 84.
35Condition "O" of counter 86 corresponds to a correct syn-chronous operation with A4 and A5 conditions simultaneously being "1"
at each beginning of each transmission block. Assuming that, when A5 , is ~ 9 A4 is no longer "1", i.e. A = O, a clock pulse is delivered from output Dl of PROM 87 to clock input of 86 which changes to condition "1". At t~e next period of down-counter 84, when A5 is "1", if A4 is "1", output DO of 87 resets counter 86, but if A4 sis "O"
again, output D1 delivers another pulse which causes counter 86 to change to condition "2", and so on, up to the time either counter 86 reaches condition ~'12~ or is reset to "O". When count "12'i has been reached in counter 86 and when A5 is "1", A4 is "1", counter 86 is reset, but if A4 is "O", output D2 delivers a load signal to counter which is set tc condi*ion "13". Synchronization is considered as lost and the digital lock loop starts to operate in search mode. From that time, each time input A4 is at le~el "1", irrespective A5, PROM B7 causes counter 86 to step to condition "14" and, through D3, causes down-counter 84 to be loaded. In condition "14", when A5 is "li', if 15 A4 is "O", PROM 87 reloads counter 86 at "13", but if A4 is also "1'~, it causes 86 to step to "15". At the next period, counter 86 steps to "O" or is reloaded down to "13", as shown in the organigram.
Circuit 77 includes two serially connected shift registers 90 and 91, and two PRO~; memories 92 and 93, as well as an OR gate 94 and 20 an AND gate 89.
Shift register 90 has its serial input connected from digital data output of demodulator 39 and its serial output connected to the serial input of ~hift register 91. Parallel outputs of shift register 90 are connected to address inputs of PROM memory 92, while parallel 25 outputs of shift register 91 are connected to address inputs of PROM
memory 93. PROM memory 92 has two outputs D4 and D5 which are respectively at level "1" depending on the byte being in shift register 90 which either directly corresponds to the "byte synchroni-zation" byte or the reverse thereof. PROM memory 93 has an output D6 30 which at level "1" for both cases of the byte being in shift register 91 and corresponding to the "bit synchronization" byte and its reverse. Outputs D4 and D5 are respectively connected to the two inputs of DR gate 94 whose output is connected to one input of AND
gate 89. Output D6 of PR~M memory 93 is connected to the other input 35 of AND gate 89.
The ambiguity removing circuit 78 includes a flip-flop 95 and an exclusive OR gate 96. Flip-flop 95 is a RS-type flip-flop whose .

~ 7 input R i5 connected from output D4 of PROM memory 92 while input P
is connected from output D5 of PROM m~mory 92. Enabl~ input EN of flip-flop 95 is connected from output DO of PROM memory 87, in 76, and its output ~ is connGcted to one input of exclusive-OR gate 96, the other input of which is connected from serial output of shift register 9l.
When the two bytes of the synchronization pattern are res-pectively being in shift registers 90 and 9l, respective outputs D6 and D4 of PROM memories 93 and 92 are at level "l". Thus output of OR
lO gate 94 and output of AND gate 89 are at level "l", which resul*s in A4 = l. If the byte corresponding to the "byte synchronization" byte, but with a reverse polarity, appears in shift register gO, while the reverse of the "bit synchroniæation" byte is being in shift register 9l, outputs D6 and D5 of 93 and 92 change to level "l", which again 15 results in A4 = l. I~ addition, input P of flip-flop 95 is "l", so that output Q of 95 changes its condition, when output DO of 86;
connected to input EN of 95 is at level "l", i.e. at the beginning of a transmission block. As a result, there is a polarity reversal at the output of exclusive-OR gate 96. Such a polarity reversal permits 20 to expect a positive comparison at the beginning of the next period.
Time base 80 includes an eight-stag~ binary counter 97 and a PROM rnen1ory 98. Clock input of counter 97 is connected from bit clock out;put H of circuit 81. Reset (RAZ~ input of 97 is connected from a predetermined output D7 of down-counter 84. Parallel outputs of 97 25 are connected to address inputs of PROM memory 98. In a preferred embodiment, output D7 of 84 corresponds ;to count '14011. Thus, counter 97 is reset five bytes before the end of each block. That number of five bytes could be reduced to three or increased, however it seems reasonable. Output MAX of 97 is connected to its input EN so as to 30 stop the counting as soon as it has reached 256 bits, since it is useful only at the beginning of each transmission block.
PROM memory 98 has two outputs D8 and D9 connected to circuit 81, an output DlO connected to the wire VAL and an output Dll connected to the triggering input of the pseudo random sequence 85 generator 82.
The bit clock restoration circuit 81 includes an analog switch 99 wnose data input is connected to output of detector 38 and output is connected to input of a narrow band one-pole ~ilter 100. Output of filter 100 is connected to the first input of a comparator 101 whose second input is connected from output D9 of PROM memory 98~ Output of comparator 101 is connected to the phase set input of a frequency divider 102 whose signal input is connected from ~I crystal controlled oscillator 103. The frequency of oscillator 103 is n times the bit frequency. Comparator 101 may be an operational amplifier one input of which is connected from output of filter 100 and the other input is connected from D9~ Output D9 applies all the-time a blocking poten-tial to comparator 101> save during a short duration which corres-ponds to the last bits of the "bit sync!' byte of the synchronization pattern of each transmission block, that is when the envelope of the signal delivered from filter 100 should have exceeded a predetermined threshold. Output signal from comparator 101 thus is a strobe for frequency divider 102 which is loaded during the strobe as soon as the first zero-crossing of the output signal of filter 100 has occured, which provides the phasing.
Moreover, filter 100 must be quiet during the useful portion of the packet so as to do not disturb its response when the "bit sync"
20 burst occurs. Therefore the analog switch 99 has its control input connected from output D8 of PROM memory 98, that output D8 being at level "1" only a few bits before the end of a packet.
Output D11 is at level "1" at a predetermined time after the beginning of a block so as to trigger the pseudo-radom sequence 25 generator 82 which must start to deliver its sequence on the time the 17th bit of occurs at the corresponding input of exclusive-OR gate 83. Output D10 is at level "1" at a predetermined time so as to deliver the signal VAL to the demultiplexers. The divider 102 deli--vers the bit clock on wire H.
Of course, the program of PROM memory 98 permits to selec1t those predetermined times for enabling outputs D8-Dll so as to obtain the most efficient operation.

Claims (9)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A system for transmitting digital data packets comprising transmitter means for periodically transmitting blocks of data in a form of data packets, the period for transmitting said blocks of data containing I clock pulses which define a period which is at least as long as a block of data, means for filling each transmission period with dummy packets if said period is not otherwise filled with said digital packets, and means for defining the beginning of each transmission block of data by a distinctive synchronization pattern of pulses including a bit synchronization pulse followed by a byte synchronization pulse.

2. A digital data packet transmission system according to claim 1, wherein the "bit sync" byte is 10101010 and the "byte sync" byte is B4 or 2D in hexadecimal notation.

3. A system for transmitting digital data packets comprising transmitter means for periodically transmitting blocks of data in a form of data packets, the period for transmitting said blocks of data containing I clock pulses which define a period which is at least as long as a block of data, means for filling each transmission period with dummy packets if said period is not otherwise filled with said digital packets, means for defining the beginning of each transmission block of data by a distinctive synchronization pattern of pulses including a bit synchronization pulse followed by a byte synchronization pulse, at least one data packet receiver means including memory means for storing the synchronization pattern, shift register means for storing two successive bytes; demodulator means including a clock means for demodulating said block of data signals and for applying the demodulating signals to the signal input of said shift register means; comparator means having first inputs connected to the output of said memory means and second inputs connected in parallel to the output of said shift register means;

OR gate means having a first input connected to an output of said comparator means; first and second counter means, said first counter means having a capacity of (I - 1) bits, having a clock pulse input which is connected to the demodulator clock means, and having an overflow output connected, on the one hand, to a second input of said OR gate means and, on the other hand, to an initialization input of said second counter means, said second counter means having a capacity of about two bytes having a clock pulse input connected from a comparator means enable input; the output of the OR gate means being connected to an initialization input of the first counter means, and the output of the second counter means delivering a validation signal for the transmission block of data.

4. A digital data packet tansmission system according to claim 1, wherein the "bit sync" byte is 10101010 and the "byte sync" byte is B4 or 2D in hexadecimal notation, at least one data packet receiver means including memory means for storing the synchronization pattern, shift register means for storing two successive bytes; demodulator means including a clock means for demodulating said block of data signals and for applying the demodulating signals to the signal input of said shift register means; comparator means having first inputs connected to the output of said memory means and second inputs connected in parallel to the output of said shift register means; OR gate means having a first input connected to an output of said comparator means; first and second counter means, said first counter means having a capacity of (I - 1) bits, having a clock pulse input which is connected to the demodulator clock means, and having an overflow output connected, on the one hand, to a second input of said OR gate means and, on the other hand, to an initialization input of said second counter means, said second counter means having a capacity of about two bytes having a clock pulse input connected from a comparator means enable input; the output of the OR gate means being connected to an initialization input of the first counter means, and the output of the second counter means deliverying a validation signal for the transmission block of data.

5. A digital data packet transmission system according to claim 1 or 2, and data scrambling means in the transmitter means for scrambling the signals in each block of data prior to the transmission thereof, said scrambling excluding the synchronization pattern, and data descrambling means in the receiver means for descrambling the receiver signals for restoring the blocks of data to the same conditions that they had prior to the start of said transmission, means for generating pseudo-random sequences at both the transmitting and receiving ends of said system, the pseudo-random sequences being generated by identical random sequence generator means, the receiver pseudo-random sequence generator means being triggered responsive to each recognization of the synchronization pattern of signals in each transmission of a block of data signals.

6. A digital data packet transmission system according to claim 3 or 4, wherein each data packet receiver includes two PROM memory means associated with two serially connected shift register means, said shift register means having parallel outputs respectively connected to address inputs of said two associated PROM memory means, two outputs of the two PROM
memory means being respectively connected to the inputs of said AND gate, third PROM memory means, an output of said AND gate being connected to an address input of said third PROM memory means, binary 2P-stage counter means, OR gate means, said third PROM memory means having a first set of outputs respectively connected to reset, clock and load inputs of said binary 2P-stage counter means, a second output of said third PROM
memory being connected to a first input of said OR gate, the outputs of the binary 22-stage counter being connected to corresponding address inputs of said third PROM memory means, down-counter means having loading inputs, packet length memory means, the output of said OR gate being connected to a load input of said down-counter means, the loading inputs of said down counter means being connected from outputs of said packet length memory, and a zero output connected to the second input of the OR gate and to an address input of said third PROM memory means, and base time circuit means, said down-counter having a predetermined output connected to said base time means to deliver a base time validation signal.

7. A digital data packet transmission system according to claim 3 or 4, wherein each data packet receiver includes two PROM memory means associated with two serially connected shift register means, said shift register means having parallel outputs respectivly connected to address inputs of said two associated PROM memory means, two outputs of the two PROM memory means being respectively connected to the inputs of said AND
gate, third PROM memory means, an output of said AND gate being connected to an address input of said third PROM memory means, binary 2P-stage counter means, OR gate means, said third PROM
memory means having a first set of outputs respectively connected to reset, clock and load inputs of said binary 2P-stage counter means, a second output of said third PROM
memory being connected to a first input of said OR gate, the outputs of the binary 22-stage counter being connected to corresponding address inputs of said third PROM memory means, down-counter means having loading inputs, packet length memory means, the output of said OR gate being connected to a load input of said down-counter means, the loading inputs of said down counter means being connected from outputs of said packet length memory, and a zero output connected to the second input of the OR gate and to an address input of said third PROM memory means, and base time circuit means, said down-counter having a predetermined output connected to said base time means to deliver a base time validation signal, and further including an exclusive OR gate, said receiver means further includes pseudo-random sequence generator means having a trigger input connected from an output of said time base means and an output connected to one input of said exclusive OR gate means, and a second input of said exclusive OR gate being connected from a serial output of the second shift register means, said exclusive OR gate having an output which delivers a useful output data packet.

8. A digital data packet transmission system according to claim 1, and a second two input OR gate, the first PROM memory means associated with the first shift register means having two outputs which are respectively enabled depending upon the polarity of the "byte sync" byte in the first shift register means, both of said two outputs of said first shift register means being connected to the two inputs of said second OR gate, the output of said second OR gate being connected to an input of said AND gate, a flip-flop, one of said two outputs being connected to an input R of said flip-flop and the second one of said two outputs being connected to input P of said flip-flop, an enable input of said flip-flop being connected from an output of said third PROM memory means, a second exclusive OR gate, and an output Q of said flip-flop being connected to one input of said second exclusive OR gate, a second input of said second exclusive OR gate being connected to the serial output of said second shift register means and an output of said second exclusive OR gate being connected to a second input of said first exclusive OR gate.

9. A digital data packet transmission system according to claim 3 or 4, and at least one data packet receiver means including memory means for storing the synchronization pattern;
shift register means for storing two successive bytes;
demodulator means including a clock means for demodulating said block of data signals and for applying the demodulating signals to the signal input of said shift register means; comparator means having first inputs connected to the output of said memory means and second inputs connected in parallel to the output of said shift register means; OR gate means having a first input connected to an output of said comparator means; first and second counter means, said first counter means having a capacity of (I -1) bits, having a clock pulse input which is connected to the demodulator clock means, and having an overflow output connected, on the one hand, to a second input of said OR gate means, and on the other hand, to an initialization input of said second counter means, said second counter means having a capacity of about two bytes having a clock pulse input connected from a comparator means enable input; the output of the OR gate means being connected to an initialization input of the first counter means, and the output of the second counter means delivering a validation signal for the transmission block of data, and wherein the said memory means is comprised of first and second memory means, said comparator means is comprised of first and second comparator means, and the shift register means is comprised of a first one-byte shift register means serially connected to a second one-byte shift register means, the first memory means storing byte 10101010 and the second memory means storing the "byte sync" byte, said receiver means also comprising third comparator means having first inputs connected to outputs of the first memory means via inverters and second outputs connected to the first shift register means, an enable input of the third comparator means being connected to the output of the second counter means, AND gate means outputs of the first and second comparator means being connected to the inputs of said AND gate means having an output connected to the first input of the OR
gate means, the third comparator means having an output connected to the input of an inverting circuit means for inverting the polarities of the received bits, and the inverting circuit means having an output connected to the signal input of the first signal register means.