CA1162642A - Digital video signal encoding and decoding system - Google Patents
Digital video signal encoding and decoding systemInfo
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- CA1162642A CA1162642A CA000356138A CA356138A CA1162642A CA 1162642 A CA1162642 A CA 1162642A CA 000356138 A CA000356138 A CA 000356138A CA 356138 A CA356138 A CA 356138A CA 1162642 A CA1162642 A CA 1162642A
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Abstract
ABSTRACT OF THE DISCLOSURE
The system encodes a high rate digital video signal conveying the picture elements into a low rate digital signal conveying words representative of some picture elements. It comprises a frame store, a movement detector for detecting the movement area in one frame with respect to the preceding one, a predictor, a bit distributing circuit for selecting the picture elements to be transmitted, a PCM encoder , which encodes the DPCM words of the selected elements according to a quantization law and an interpolating circuit The number of bits NB allocated to each line in the low rate digital signal is made constant. The movement detector detects the two ledge elements defi-ning each line moving area and thereby deduces the maximum number NP and average bit number B of the element words to be encoded and transmitted.
The bit distributing circuit down-counts the bits which remain for allocation to the line and the element words which remain likely to be encoded and compares these down-count totals for selectively controlling the encoding of moving area element word. A transmitted and encoded word represents the level number with respect to the quantization law associated with the line.
The system encodes a high rate digital video signal conveying the picture elements into a low rate digital signal conveying words representative of some picture elements. It comprises a frame store, a movement detector for detecting the movement area in one frame with respect to the preceding one, a predictor, a bit distributing circuit for selecting the picture elements to be transmitted, a PCM encoder , which encodes the DPCM words of the selected elements according to a quantization law and an interpolating circuit The number of bits NB allocated to each line in the low rate digital signal is made constant. The movement detector detects the two ledge elements defi-ning each line moving area and thereby deduces the maximum number NP and average bit number B of the element words to be encoded and transmitted.
The bit distributing circuit down-counts the bits which remain for allocation to the line and the element words which remain likely to be encoded and compares these down-count totals for selectively controlling the encoding of moving area element word. A transmitted and encoded word represents the level number with respect to the quantization law associated with the line.
Description
~ ~ 62642 ~ he present in~ention r~lates to a dlgltal video signal encoding and decodlng system in which the diyital video signal delivered from the camera with a given high rate is constituted of words having a predetermined number of bits and representing picture elements and is encoded into a PCM encoded signal transmitted along a low rate digital transmission medium conveying words re-presenting certain picture elements. More particularly, the invention relates to a digital video system for transmitting videotelephone signals.
In the transmitter of a videotelephone system for a speaker, the videotelephone signal is delivered from the monitoring means associated with the camera through analog-to-digital converting means in a PCM
digital wave-form having a high rate, such as approxima-tely 16 to 18 Mbits/s, depending on the adopted videostandard. Each word representing of a picture line element comprises 8 bits, which corresponds to 256 quantization levels between white and black. After DPCM differential encoding in the encoding device of the transmitter, the digital videosignal is transmitted on the digital transmission medium at a low rate equal to
In the transmitter of a videotelephone system for a speaker, the videotelephone signal is delivered from the monitoring means associated with the camera through analog-to-digital converting means in a PCM
digital wave-form having a high rate, such as approxima-tely 16 to 18 Mbits/s, depending on the adopted videostandard. Each word representing of a picture line element comprises 8 bits, which corresponds to 256 quantization levels between white and black. After DPCM differential encoding in the encoding device of the transmitter, the digital videosignal is transmitted on the digital transmission medium at a low rate equal to
2 Mbits/s approximately. Reduction in the binary rate by a factor of approximately 8 corresponds on average to a transmission of a bit per element.
However, to obtain satisfactory picture recons-- titution in the decoding device of the receiver of the distant speaker, a minimum of 3 bits per picture element (pel) must be transmitted, thereby implying that the encoding device comprises means for selecting certain pels with a view to transmitting these only after putting them into DPCM code and that the decoding device at least comprises means for interpolating the untransmitted elements in terms of the transmitted and decoded elements so as to reconstitute the entire picture.
In this respect, it will be noted that the scope of the invention does not ' take in the digltal video enaodin~ and decoding systems in which all the pels are retransmitted in the form of differential PCM encoded words, each of which has a predetermined number of bits (equal to three, for example) and for which the out-going binary rate lies approximately in the ratio betweenthe incoming binary rate and this predetermined bit number (see, for instance, UK Patent Application published under n 2,003,001 on February 28, 1979).
In order to solve the above problem, so-called systematic replenishment encoding systems were first of all put forward, as described, for example, in paragraph II of the published article by M. DEVIMEUX, M. JOLIVET and J.P. TEMIME in '-Journees d'Etudes of 30th November and 1st December 1977, of the French Society of Electricians, Electronicians and Radio-electricians in Rennes. Systematic replenishment encoding consist of transmitting a constant 'number of data bits allocated to a limited number of ele-ments on successive pictures, generally with every third field on the picture encoded at 3 bits/pel. In this case, the encoding device transmits all the 3-b~ts pel words in DPCM code related to every third frame on the digital transmission medium. In the receiver, the decoding system reconstitutes the pairs of missing fields by interpolation between the adjacent transmitted fields. With this in mind, it comprises a field buffer which is read at the pel frequency. Such an encoding and decoding system introduces in particular temporal and spatial resolution losses and a very marked -jerk'- effect, especially in the case of significant displacements of the moving area of the picture (generally, the speaker's face) on the fixed background.
These losses stem from the fact that the frequency of the transmitted fields is one third of that of the real fields and it naturally follows from this that the alternation of the even and odd frames necessitates an interpolation . ~ .
~ ~62642 of the missing both temporal and spatla:L E~.elds.
Other more performiny encoding and decoding systems are known but are far more complex. They are called conditional replenishment systems. These comprise a movement detector for detecting the movement o~ each vi~eo picture with a view to controlling pel word seleckion means to dis-criminate between the pel words to be transmitted and encoded or not depending on internal criteria. Such conditional replenishment systems are disclosed, inter alia, in the following documents:
- article by M. DEVIMEUX et al., already mentioned, paragraph III;
- article by J.C. CANDY, M.A. FRANKE, B.G. HASKELL
and F.W. MOUNTS in "The Bell System Technical Journal'', vol.
50, July-August 1971, New York, Pages 1889 to 1917;
- article by R.C. NICOL, '-Conference on Digital Processing of Signals in Communication', Loughborough University of Technology, September 1977;
- article by B.G. HASKELL and R.L. SCHMIDT in -The Bell System Technical Journal , vol. 50, no. 8, October 1975, pages 1475 to 1495;
- article by von GERT BOSTELMANN in Frequenz , vol. 33, no. 1, January 1979, Berlin, pages 2 to 8; and - U.S. Patent no. 4,027,331.
The internal discrimination criteria in the movement detector are based on the detection of the elements of the visual portion of each frame whose amplitudes or levels have varied in excess of a certain threshold, generally variable in terms of the pel words which may be transmitted, with respect to those of the previous picture elements. The -stationary-- areas of the present picture which correspond to ampliture differences coming below the variable threshold remain unchanged in the frame store, except in the event of interpolation. On the other hand, , ~
~ ~62642 the moving areas are replenish~!dl i.e. flll up the Erame store in lleu oE the corresponding areas of the previous frame.
It turns out that such criteria are quite suitable when dealing with video pictures where the displacements of the moving areas of the picture are relatively restricted.
The movement detection threshold drops when the number of modified elements to be encoded and transmitted increases so as to allow suitable reconstitution in the decoding device of the receiver. It is conceivable from this that the encoding must be regulated in order to adapt the variable number of modified element words to be encoded to the constant rate of the digital transmission medium.
This regulation is achieved using an -elastic-- buffer in which the selected encoded element words are written in asynchronism ~and are read in sychronism at the transmission medium rate.
Given that this buffer store is never full or empty, its contents make it possible to determine the regulation parameters of the encoder such that the average incoming bit-rate in the buffer store be equal to that of the transmission medium. Indeed, the number of bits, or more exactly, of the pel words, generally with 4 bits after DPCM encoding, is variable from frame to frame. For each frame, DPCM words representing the amplitudes of the variable picture elements as well as the start and end address words of the clusters of these variable elements are thus transmitted. When the buffer store overflows, due to significant variable element clusters is imminent, temporal subsampling of every second field and/or spatial subsampling of one pel out of two for each line systematically occurs (modes 1 and 2 according to the afore-mentioned article by HASKELL and SCHMIDT). In the first above mode, the missing field, even for example, is not transmitted by the transmitter and is replaced at the receiver by a field resulting an interpolation of the two previous and upcoming adjacent odd fields, thus reducing the vertical resolu-tion oE the picture by a Eactor of two.
In the second mode, -the untransmitted pels are obtained from their transmitted adjacen-t elemen-ts by interpolation.
Conditional replenishment encoding and decoding systems, such as these, present the following drawbacks:
- the optimization and the production of the encoding device are complex as a result of the various operating modes depending on the fullness of the -elastic--buffer store and consequently on the movement;
- multiplexing in the digital transmission medium of a variable number of element and element cluster address data words and, therefore, of variable duration;
- as a result of the variable number and duration of the transmitted pel words for each picture, need at the receiver for resynchronizing means employing variable lock on the transmitted synchronization words and an -elastic-buffer store analogous to that at the transmitter;
- in the event of significant movements, reduction of the temporal or spatial resolution by the spatial or temporal subsampling.
To avoid the interpolation problems according to the conditional replenishment, KITSUTARO AMANO and consorts teaches in U.S. Patent no. 3,940,555 an encoding of a picture signal for which all the variable MICD encoded level words representative of pel level exceeding a predetermined threshold are transmitted in the low rate digital signal and for which the number of bits allocated to each -line-- of the - low rate digital signal is constant. Encoding is an intra-image encoding. Each MICD word indicates the difference between the levels of a present picture element of a horizontal, vertical or diagonal line and the corresponding present picture element of an adjacent line of same type.
The bit number allocated to each line is composed of a line synchronization word, an addressing bit for each pel of the line, the state of which indicates the presence or absence of a change on the pel level, and MICD
-,- - 4a -.... i j .
__ = - ~, ., .. , .. ~ . _.. __.. _ ... . .. .. . . ... _ .... .. . .. . . .. ._ . . ... _ . _ . _ _ .. _ ._ 1 1 626~2 level words corresponding to chantJcd pel~.. The bit number of ~ICP words is always ~ss than or equal to a predetermined integer, such as four, so as to fit the number of DPCM words to be transmitted to the predeter-mined blt number allocated to each line.
However, this encoding and decodiny system has the drawback that the bit number allocated to each line may be reduced to the unity, when the number of line pels to be transmitted, the levels of which have varied, is high. In fact, since an interpolation and, consequently, a subsam~ling are not provided, the picture spatial resolution is very reduced considerably. This encoding and decoding system is used when the ratio between the outgoing and incoming binary rates is relatively low, such as 1/4.
It is therefore an object of this invention to provide an encoding and decoding system free, in particu-lar, of the complexity of the regulation means, the elastic buffers and the resynchronizing means of the conditional replenishment; systems.
Another object of the invention is to allocate to selected pel words of the moving picture parts to be decoded and transmit-ted on the digital transmission medium a constant duration for each frame which is indepen-dent of the variable number of modified elements from one frame to the next.
A further object of the invention is to fix once and for all the number of bits allocated to each line in the low rate digital signal.
Yet another of this invention is to transmit the data relative to the lines in synchronism with the line frequency and, consequently, to eliminate the element cluster addressing problems. The qualities of the recons-tituted picture at the receiver are wholly comparable with those of known conditional replenisnment systems.
t J626~
For achieving the a:Eorementioned objects and according to the present invention as broadly claimed in the appended claims, there is provided a digital video system having an encoding device in the transmitter for encoding a digital video signal at a high given rate constituted of PCM words which have a predetermined bit number and which are represen-tative of consecutive picture elements of a scannecl pi.cture, into a digital encoded si~nal transmitted on a low rate digital trans-mission medium conveying words which are representativeof present picture elements, the levels of which have varied relative to those corresponding to the previous picture. The encoding device of the digital video system comprises:.
- picture storing means for storing the trans-mitted picture eIement words after interpolating;
- means for detecting the moving area of the - present picture with respect to the previous stored picture by means of comparison of the word difference between two words representative of two corresponding elements of the present picture and the previous stored .picture with a predetermined threshold;
- the data bit number NB allocated to each line of a.picture in said digital transmission medium being constant and the average bit number B allocated to each encoded signal word of a line being greater than or e~ual to a first predetermined integer' - said moving area detecting means producing for each line of a picture the coordinates of the two ledge picture elements defining the moving area of said present picture with respect to the corresponding line of said previous picture so as to deduce thereby the number NP of picture elements in said moving area of the line likely to be encoded ana said average bit number B, - a linear predicting means for delivering DPCM
1 1 626~ 2 predicted p.icture element worcl;Erom th~ ~ored plcture element words and presen-t picture element wordsi - firs-t and second clown-counting means controlled by said movement area detecting means and having their counts C1, C2, set to NB and NP at the start of the moving area of each present picture line :Eor down-counting the number of bits remaining -to be allocated to said line and the number of picture element words remaining likely to be encoded at the line element frequency;
- means connected to down-counting means for comparing the counts of said first and second down-count-ing means to select the DPCM words representing the picture element to be transmitted each time Cl/B ~ C2, - means receiving said DPCM words and controlled by comparing means for encoding, according to a predeter-mined quantization law, said selected DPCM words in order to multiplex said selected DPCM words in said digital transmission medium; and - means connected to said encoding means for - 20 linearly interpolating the PCM unselected picture element words.
According to an advantageous characteristic of the present invention and, in order to reduce the data quantity to be transmitted, the encoding means of the encoding device transmits on the digital transmission medium, not the amplitude of the DPCM quantization level of each selected modified element, but rather a B-bit PCM word representing the ~uantification lever number.
Preferably,two identical decoding means are included in the transmitter encoding device and the receiver decoding device respectively and restore a word represen-tative of said level so that the transmitter and receiver frame store.identical words for each pel o~f the moving area of a line after interpolatinq and low-pass filtering, if required. In ,~ .~
~ ~ 626~2 accordance with a Eirst p~efcrrecl cmhod~ment of the encodlng device,lneans are provided for calcula-ting the maxi~u~ 3~
and average D values of the DPCM encoded words of all the elements in the moving area of_a line such that the DPCM
encoding means can select a 2 B level quantization law peculiar to the moving area of the line. This enables the variation characteristics of the incoming video signal to be reduced as much as possible. A quantization law associated with a line may be reconstitu-ted in the decoding device of the receiver, since D and DMAX are included in the data preamble which is assigned to the line and which precedes the selected level words of the line. In accordance to a second preferred embodiment, which is less complex than the first preferred embodiment, the level numbers of a plurality of quantification laws are stored in the encoding means of the encoding device.
For each line, a stored quantification law is selected as function of the average number B alloca-ted to selected and transmitted level words of the line.
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention as illustrated in the accompanying drawings, in which:
- Fig. 1 is a schematic diagram showing the moving area of a picture displayed on the screen of a videotelephone;
- Fig. 2 is a block diagram of the encoding device of the transmitter according to the first embodiment and partlv to the second embodiment;
- Fig. 3 is a detailed block diagram of the movement detector of the transmitter which includes an arithmetic unit for calculating B and NP analogous to the that of the decoding device illustrated in Fig. 13, Flg. 4, which is disposed on the same sheet of I ~ 626~2 drawings as Flgure 1, i5 a clatailed block diagram o~ the bl-t distributing clrcuit whish selec-ts the changed pel to be transmitted, - Fig. 5 is a detailed block diagram of the arithmetic unit for calculating DMAX and D, - Fig. 6 is a detailed block diagram of the PCM
encoder of the -transmitter according to the firs-t embodi-mentz Fig. 7 is a detailecl block diagram of the PCM
decoder of the transmitter or receiver according to -the first embodiment;
Fig. 8 is a detailed block diagram of the PCM
coder of the transmitter according to the second embodi-ment~
- Fig. 9 is a detailed block diagram of the PCM
decoder of the transmitter or receiver according to the second embodiment;
- Fig. 10 is a detailed block diagram of a linear interpolating circuit, - Fig. 11 is a detailed block diagram of a conditional spatial filtering circuit;
- Fig. 12 is a diagram illustrating the sub-sampling in the moving area of a line; and - Fig. 13 is a block diagram of the decoding device of the receiver according to the first embodiment and partly to the second embodiment.
. .
9 ~ 62642 Reference will be made :Ln this description, for example purposes, to a standard videotelephone the functional features of which are as follows:
Definition of a picture displayed by a videotelephone:
- 313 l:ines, 288 of which are used the visible picture portion and 25 of which are allocated to the field (or half-frame) synchronizing and blanking signal;
- each line contains 284 elements, 53 of which are allocated to the line synchronizing and bIanking signal and 231 of whiGh are visible picture elements (pels);
- frequency of the field synchronizing signal equals to 50 Hz i.e. 25 frames per second with two interlacing;
- frequency of the line synchronizing signal :
7.825 kHz ;
- frequency of the elements: 7.825 x 284 = 2.2223 MHz.
After sampling of the video signal which is trans-mitted by the camera of the videotelephone, the encoding device of the transmitter receives a digital signal having a frequency of 8 x 2.2223 = 17.778 M bits/s in which each element is sampled over 256 level values between white (l volt) and black (0.3 volts) and takes up a time-slot T = 450 nsec corresponding to an 8-bit word.
After encoding the video digital signal is conveyed on a digital link which is connected to the output of the transmitted is of the TNl type in accordance with international recommendations. It has a rate equal to 30 2.048 Mbits/s and transmits a repeating frame having 32 eight-bit bytes (octets) whose time intervals TI0 and TIl6 are reserved, inter alia, for frame alignment, signaling and stuffing indication purposes. An 8-bit time interval of the link frame is allocated to a 64kbit/s digital channel . _ . . . _ _ .. .. .. . . . . . . . .. .. , .. . . . . .. . . . .... __ . .
whlch conveys the addltlonal data such as the sound. Con-sequently, 29 time intervals in a 2.048 Mbit/s digital frame are occupied by the video signal produced by the transmitter, namely a video bit-rate at the output of the transmitter equal to:
2.048 x 29/32 = 1.856 Mbit/s In accordance with the invention, the encoding device makes its possible to reduce the picture-carrying video signal rate from 17.778 Mbits/s to 1.856 Mbits/s by assigning a constant number of bits N in the outcoming encoded digital signal to each useful line amongst 288 of a frame which is equal, as per the foregoing parameters, to:
N = 1.856 x 106/(288 x 25) : 258 bits per picture line It will be assumed in what follows that, amongst - these 258 bits, the first 27 are given over to a preamble which contains words intended, in particular, for the line synchronization and certain discriminations inherent in the invention-orientated encoding. It follows from this that NB = 258 - 27 = 231 bits remain which are truly allocated to the transmission of the visible portion of a picture line. These NB bits are generally split into words of at least three bits. Each word indicates the amplitude of a particular line element selected as per DPCM encoding accor-ding to the invention, the principle of which is described hereinafter in reference to Fig. 1.
On this figure, we have schematically shown the contour of the moving picture on a videotelephone screen, such that the speaker's (S) face (shaded area) stands out against a fixed background area BA which is generally unicolour, or more exactly has a uniform colorimetric level.
Each line can be divided into an area BAl, BA2 or two areas BAl and BA2 which represent the background BA and which vary from one frame to the next only in terms of i 1 62642 camera noise, and/or a c~ntral. or lateral area S~ whlch is essentially moving and represents the moving speaker S or the suddenly uncovered background. In this way, for lines Ll, L2, L3, L4 above area S, at the speaker's face level, at the speaker's neck level and at the speaker's shoulder level when fully filmed respectively, as shown in Flg. 1, the area distribution is given by table I below:
TABLE I
Area BAl SA A2_ _ line Llfixed empty empty line L2fixed moving fixed line L3empty moving fixed line L4empty moving empty For each line, these areas are marked ofE by two picture elements Ml and M2 of coordinates X, and X2, or more precisely, the moving area SA of the speaker pictures is defined with respect to the background BA by pairs of elements Ml, M2. Since the video signal representative of the back-ground has a constant amplitude variation on each line, only the pels on picture area SA are of any interest when re-producing the picture in the videotelephone system receiver.
For example, the area Ml M2 of the line L2 is small, the area-Ml M2 of the line L3 occupies the major portion of the 25 left hand side of the screen and the area Ml M2 of the line L4 occupies the whole screen. Since the number of bits NB
allocated to a line is constant, the encoding device transmits the frame data of a line area Ml M2 by reducing the real contents of this received data to 8-bit words at 17.778 Mbits/s in accordance with certain criteria which are based, on the one hand, on the temporal redundancy of the frame or handing only those frame areas which are moving and, on the other hand, on the spatial redundancy with a view to cutting down the range of the transmitted signal by differential pulse .d, -' .
~ .1 82642 cod.ing (DPC~
The various transmitter encoding devlce circuits are illustrated in Fig. 2 and will be described below as we come to them in the processing of the 17.778 Mbit/s digital video signal leaving the camera and the associated sampler.
The encoding device essentially comprises a frame store 1 which momorizes the odd field followed by the even field of one and the same frame, a movement detector 2, a bit distributing circuit 3, a lineas predictor 4, an arithmetic unit 5 which produces digital values D~X and D
which characterize the reducing of the incoming video signal, a PCM encoder 6, a PCM decoder 7, an interpolating circuit 8 and a conditional spatial filtering circuit 9. It further comprises two shift registers (or line delay circuit) Rl and R2 which are connected in series and each having 231 x 8 stages, as well as a digital subtractor 41 and a digital adder 42, an input of each of which is connected to the out-put 40 of the predictor 4. The input I of the encoding device receives only 8-bit words P (F, L) at the binary rate of 17.778 Mbits/s which are representative of the 231 visible elements of a line L of a frame F. Filtering and separating means (not shown) are inserted up line of the input I, in order to separate the video information from the frame and line synchronizing and blanking information. These devices are well known in prior art and do not come within the scope of this invention. Likewise, the multiplexing and transmit-ting circuits connected to the outputs of the encoding device for making up the 2.048 Mbit/s outcoming digital signal shall not be described. In addition, it will be noted that the various links depicted on the drawings are simple connections of bus-bars and that the logic circuits are referred to here-below by their unction and generally comprise a number of such elementary circuits in parallel. The numerical references at the inputs and outputs of blocks in Fig. 2 (and Fig. 13) 1 ~ 626~ 2 designate terminals or inpu~ Ol ou-tput components which may come up in corresponding detailed block diagrams of other figures.
First and foremost, in order to process the area of the moving picture relating to a line L, we must detect the above- defined elements Ml and M2. This function is ful-filled by movement detector 2 shown in Fig. 3. In this detector 2, a digital subtractor 20 receives through its direct input (+) a pel word P (F, L) of a line L in the frame F to be processed which is transmitted by the input I, and through its inverse input (-) a pel word P (F-l,, L) of the line L of the preceding frame (F-l) which is transmitted from the output 10 of the frame store 1.
In accordance with the invention, detection of the movement is based on the element-to-element comparison of the edge zones at elements Ml and M2 (Fig.l) between the frame F being received at the input I and the previous one F-l stored in the frame store 1. In this respect, the frame store 1 (Fig.2) stores all the pel words P' (F, L) of a frame, i.e. 288 x 231 8-bit words. These words P' (F, L) are in fact formed after encoding, as will be seen here-after. The store 1 is, for instance, made up of 34 modules with a capacity equal to 16 kbits. It is of the random access type (RAM) and is written in and read out at a period which is substantially lower than the time slot occupied by a pel word P (F, L). It will moreover be noted that, in the drawings, we have not shown the time base of the encoding device which delivers by means of a clock, such as phase locking loop set at a line frequency of 7.825 kHz, the various monitoring signals peculiar to the monitoring component circuits 1 to 9.
Each element P (F, L) of the present frame F and the corresponding element P' (F-l, L) of the previous frame (F-l) are transmitted into two buffer registers 210 and 220 of the movement detector 2, whlch ar~ .rcspectively inter-connec-ted between the direct input (-~) of the subtractor 20 and the input I and between the i.nverse input (-) of the subtractor 20 and the output 10 of frame store 1. The out-put of the subtractor 20 provides a word representative of difference P (F,L) - P' (F-l, L) which is applled to the inputs of two arithmetic units 211 and 221. The first, 211, transmits a word indicating the absolute value of the difference /P (F, L) - P' (F-l, L)/ to one of the inputs of a digital comparator 23, the other input of which receives a threshold signal T. This threshold T is, for example, equal to the gap between two or three successive levels of the 256 equidistributed levels corresponding to the sampling of the incoming video signal. If /P (F, L) - P' (F-l, L)j> T, the output of comparator 23 isin.state 1 and is in state O otherwise. The second arithmetic unit 221 delivers a 1 if the difference /P (F, L) - P (F-l,L)/ is positive and a O otherwise. The output of comparator 23 and the arithmetic unit 221 are connected to AND gates 213 and 223 respct-ively, having for example three inputs. One of inputs 214, 224 of an AND gate 213, 223, is directy connected to the output of the comparator 23, respectively of the unit 221.
Each of the other two inputs of these gates are connected to the latter input 214, 224 via one delay line 215, 216, two delay lines 215, 216, 225, 226, respectively. These delay lines introduce a delay equal to T and ensure that the.amplitude of three consecutive elements of a line of the present frame have fluctuated with a magnitude differeNce greater than the threshold T and have the same sign with respect to the corresponding elements of the previous frame (F-l). If the sign is positive, then the output of the AND gate 223 applies a 1 to one input of an AND gate 26.
If the sign is negative,.the output of a NOR gate 24, the three inputs of which are connected in parallel to those 1 ~ 62642 of the AND ga-te 223, applles a 1 to the above lnput of the yate 26. The two inputs oE the ya-te 26 are connected to the outputs of the AND gate 213 and, via an OR gate, 25, to the outputs of AND gate 223 and NOR gate 24. In this way, as soon as the output of the AND gate 26 is state 1 at the start of the line processing operation, this indicated the detection of the element Ml. After the transmission of the other moving-picture elements of the major portion of the area SA (Fig. 1) which is modified beyond the threshold T
from one frame to the next, when-the output of the AND gate 26 reverts to state O , this indicates the detection of the element M2. The criterion implicated in movement detector 2 is thus founded on the displacement of the transition or contour between the areas BAl and BA2 on the one hand and the area SA on the other, namely on the inter-frame difference in the amplitudes of the moving elements.
This criterion also distinguishes the moving elements from camera noise by the choice of a suitable value for threshold T.
The output Pf the AND gate 26 is connected to a logic circuit 27 which delivers the coordinates Xl, X2 of the detected elements Ml and M2. The circuit 27 comprises two monostable flip-flops 271 and 272 which are connected directly and via an inverter 270 to the output of the AND
gate 26. The outputs of the flip-flops 271, 272 are con-nected to two AND gates 273 and 274. The other inputs of the AND gates 273, 274 are connected to the output of an element counter 277. This counter 277 is triggered after the end of the line synchronizing signal following the first 53 elements and is reset to zero and held after the 231st following element. The output of the counter 277 thus transmits the successive coordinates 1 to 231 of the line elements. Buffer registers 275 and 276 connected to the outputs of the AND gates 273 and 274 store the Xl and X2 i 1 62642 coordinates of the detec-ted elements Ml and M2.
It will be noted, as will be explained later on, that the detection of elements Ml and M2 by means of the movement detector 2 is performed over a line transmission period equal to 1/7.825 second. Throughout this detection, the 231 8-bit pel words P (F, L) of the line L are delayed in series in the first shift register Rl connected to the input I. Reading of the Xl and X2 coordinates from the registers 275 and 276 is controlled at the start of the following line L + 1 received at the input I. The various delays lasting one line L or two lines 2L for carrying out the various operations inherent in the encoding are indicated in the drawing by blocks representing line synchronizing signal delay circuits.
Referring now to Fig. 4, bit distributing circuit 3 delivers, upon reception of the-second next line L + 2-at the input I, the average number of bits s allocated to each pel cf line L to be transmitted and selects in accordance with distribution criteria the elements that will be really transmitted in order to adapt the 17.778 Mbits/s incoming rate to the 1.856 Mbits/s outgoing rate, i.e. to the real rate of 2.048 Mbits/s after multiplexing. The distribution criteria are as follows:
a) each pel to be transmitted is so indicated by a word having at least three bits as to obtaining a DPCM encoding giving adequate picture qualities in the receiver; the number of bits in a transmitted pel word is preferably restricted by a high limiting value equal to six for instance;
b) since the frequency pass band is reduced in the moving area SA (Fig. 1), due in particular to the blurring inherent to integration in camera, subsampling of the moving elements ~.r can be perEormed; ln o~h~r words, certain el~ments of a line in area S are neither encoded nor transmitted and will be reconsti-tuted upline of the frame store, both in the transmitter encoding device (Fig. 2) and in the receiver decodin~ dev;lce (Fig. 13) by means of interpolating and filtering circuits such as 8 and 9;
c) when the total number of bits NP ~ B of the NP pel words in the SA area is less than the number of bits NB reserved for a line, i.e.
- when the SA area or X2 - Xl is very small, then filling bits without sense and/or eventually additional data words, such as pel PCM words, can be mixed with the NP x B bits to come up to NB bits.
Bit distribution and sample selection mainly depend on the width of the area SA equal to X2 - Xl on the line L. With this in mind, the movement detector 2 shown in Fig. 3 includes an arithmetic unit 28 which calculates the number of elements NP of the SA area lying between M
and M2, including the latter, and the average number of bits B to be assigned to each element to be transmitted.
Under control of the synchronizing signal of the following line L + 1 prior to the start of line L pel word transfer from register Rl to register R2, shown in Fig. 2, the X
and X2 coordinates are read in the registers 275 and 276 via reading AND gates 28I and 282. They are transmitted, on the one hand, to inputs 510 and 520 of the arithmetic unit 5 (Fig.5) and, on the other hand, to the inverse (-) and direct (+) inputs of a digital subtractor 283, respectively.
The difference (X2 - Xl) is added to unity in an adder 284 to deliver X2 - Xl + 1 = NP to a register 285 and to the input of an divide -by- NB devider 286. The divider 286 I 1 62~2 performs the integer division: integer part (NB/NP) =
b = average number of bits. The number b delivered by the divider 286 is compared with three and six in a comparator 287. If 6 > b ~ 3, then an output 2871of the comparator 287 opens an AND gate 2880 so as to transmit the number of bits allocated to each pel after encoding, such that b =
s, from the output of the divider 286 to a register 289, via an OR gate 2881. If b < 3, then an output 2873 of the comparator 287 applies the lower limiting integer value of the average bit number B equal to 3 to the register 289 via the OR gate 2881. Finally, if b > 6, then an output 2876 of the comparator 287 applies the upper limiting integer value of the average bit number B equal to 6 to the register 289 via the OR gate 2881.
The bit distribution circuit 3 shown in Fig. 4 comprises two down-counters 31 and 32 which have their counts initially set to NB and NP respectively by reading a read-only memory (not shown) and the register 285 (Fig.3) controlled by the line synchronization signal. The count of a down-counter 30 is also initially set to xl by reading the register 275 (Fig. 3) so that, once its count reaches zero it triggers counting in down-counters 31 and 32 at the element frequency l/t, simultaneously with the series transmission of the pel words P (F, L) of the line L from register R2 to the input 600 of the encoder 6 via the sub-tractor 41 (Fig. 2). The counts in down-counters 31 and 32 are delivered on output buses 310 and 320, at the element frequency of 1/l = 2.2223MHz, to two digital multiplying circuits 33 and 34 by NP and NB, respectively. The outputs of the circuits 33 and 34 are connected to the direct (~) and inverse (-) inputs of a digital comparator 35. When the difference of the compared words in the comparator 35 is positive, its output 350 is in state 1 and controls the opening of an AND gate 36, the other input of which receives the average number oE bits B kransm:Lt-ted by the regist~r 289 (Fig. 3) at each period ~. Coun-ting input 311 of the down-counter 31 is connected to the outpwt of AND gate 36 and down-counting input 321 of the down-counter 32 receives a 1 at each period ~ corresponding to the NP elements of moving area SA of the line L.
It can be seen rom the bit distributing circuit
However, to obtain satisfactory picture recons-- titution in the decoding device of the receiver of the distant speaker, a minimum of 3 bits per picture element (pel) must be transmitted, thereby implying that the encoding device comprises means for selecting certain pels with a view to transmitting these only after putting them into DPCM code and that the decoding device at least comprises means for interpolating the untransmitted elements in terms of the transmitted and decoded elements so as to reconstitute the entire picture.
In this respect, it will be noted that the scope of the invention does not ' take in the digltal video enaodin~ and decoding systems in which all the pels are retransmitted in the form of differential PCM encoded words, each of which has a predetermined number of bits (equal to three, for example) and for which the out-going binary rate lies approximately in the ratio betweenthe incoming binary rate and this predetermined bit number (see, for instance, UK Patent Application published under n 2,003,001 on February 28, 1979).
In order to solve the above problem, so-called systematic replenishment encoding systems were first of all put forward, as described, for example, in paragraph II of the published article by M. DEVIMEUX, M. JOLIVET and J.P. TEMIME in '-Journees d'Etudes of 30th November and 1st December 1977, of the French Society of Electricians, Electronicians and Radio-electricians in Rennes. Systematic replenishment encoding consist of transmitting a constant 'number of data bits allocated to a limited number of ele-ments on successive pictures, generally with every third field on the picture encoded at 3 bits/pel. In this case, the encoding device transmits all the 3-b~ts pel words in DPCM code related to every third frame on the digital transmission medium. In the receiver, the decoding system reconstitutes the pairs of missing fields by interpolation between the adjacent transmitted fields. With this in mind, it comprises a field buffer which is read at the pel frequency. Such an encoding and decoding system introduces in particular temporal and spatial resolution losses and a very marked -jerk'- effect, especially in the case of significant displacements of the moving area of the picture (generally, the speaker's face) on the fixed background.
These losses stem from the fact that the frequency of the transmitted fields is one third of that of the real fields and it naturally follows from this that the alternation of the even and odd frames necessitates an interpolation . ~ .
~ ~62642 of the missing both temporal and spatla:L E~.elds.
Other more performiny encoding and decoding systems are known but are far more complex. They are called conditional replenishment systems. These comprise a movement detector for detecting the movement o~ each vi~eo picture with a view to controlling pel word seleckion means to dis-criminate between the pel words to be transmitted and encoded or not depending on internal criteria. Such conditional replenishment systems are disclosed, inter alia, in the following documents:
- article by M. DEVIMEUX et al., already mentioned, paragraph III;
- article by J.C. CANDY, M.A. FRANKE, B.G. HASKELL
and F.W. MOUNTS in "The Bell System Technical Journal'', vol.
50, July-August 1971, New York, Pages 1889 to 1917;
- article by R.C. NICOL, '-Conference on Digital Processing of Signals in Communication', Loughborough University of Technology, September 1977;
- article by B.G. HASKELL and R.L. SCHMIDT in -The Bell System Technical Journal , vol. 50, no. 8, October 1975, pages 1475 to 1495;
- article by von GERT BOSTELMANN in Frequenz , vol. 33, no. 1, January 1979, Berlin, pages 2 to 8; and - U.S. Patent no. 4,027,331.
The internal discrimination criteria in the movement detector are based on the detection of the elements of the visual portion of each frame whose amplitudes or levels have varied in excess of a certain threshold, generally variable in terms of the pel words which may be transmitted, with respect to those of the previous picture elements. The -stationary-- areas of the present picture which correspond to ampliture differences coming below the variable threshold remain unchanged in the frame store, except in the event of interpolation. On the other hand, , ~
~ ~62642 the moving areas are replenish~!dl i.e. flll up the Erame store in lleu oE the corresponding areas of the previous frame.
It turns out that such criteria are quite suitable when dealing with video pictures where the displacements of the moving areas of the picture are relatively restricted.
The movement detection threshold drops when the number of modified elements to be encoded and transmitted increases so as to allow suitable reconstitution in the decoding device of the receiver. It is conceivable from this that the encoding must be regulated in order to adapt the variable number of modified element words to be encoded to the constant rate of the digital transmission medium.
This regulation is achieved using an -elastic-- buffer in which the selected encoded element words are written in asynchronism ~and are read in sychronism at the transmission medium rate.
Given that this buffer store is never full or empty, its contents make it possible to determine the regulation parameters of the encoder such that the average incoming bit-rate in the buffer store be equal to that of the transmission medium. Indeed, the number of bits, or more exactly, of the pel words, generally with 4 bits after DPCM encoding, is variable from frame to frame. For each frame, DPCM words representing the amplitudes of the variable picture elements as well as the start and end address words of the clusters of these variable elements are thus transmitted. When the buffer store overflows, due to significant variable element clusters is imminent, temporal subsampling of every second field and/or spatial subsampling of one pel out of two for each line systematically occurs (modes 1 and 2 according to the afore-mentioned article by HASKELL and SCHMIDT). In the first above mode, the missing field, even for example, is not transmitted by the transmitter and is replaced at the receiver by a field resulting an interpolation of the two previous and upcoming adjacent odd fields, thus reducing the vertical resolu-tion oE the picture by a Eactor of two.
In the second mode, -the untransmitted pels are obtained from their transmitted adjacen-t elemen-ts by interpolation.
Conditional replenishment encoding and decoding systems, such as these, present the following drawbacks:
- the optimization and the production of the encoding device are complex as a result of the various operating modes depending on the fullness of the -elastic--buffer store and consequently on the movement;
- multiplexing in the digital transmission medium of a variable number of element and element cluster address data words and, therefore, of variable duration;
- as a result of the variable number and duration of the transmitted pel words for each picture, need at the receiver for resynchronizing means employing variable lock on the transmitted synchronization words and an -elastic-buffer store analogous to that at the transmitter;
- in the event of significant movements, reduction of the temporal or spatial resolution by the spatial or temporal subsampling.
To avoid the interpolation problems according to the conditional replenishment, KITSUTARO AMANO and consorts teaches in U.S. Patent no. 3,940,555 an encoding of a picture signal for which all the variable MICD encoded level words representative of pel level exceeding a predetermined threshold are transmitted in the low rate digital signal and for which the number of bits allocated to each -line-- of the - low rate digital signal is constant. Encoding is an intra-image encoding. Each MICD word indicates the difference between the levels of a present picture element of a horizontal, vertical or diagonal line and the corresponding present picture element of an adjacent line of same type.
The bit number allocated to each line is composed of a line synchronization word, an addressing bit for each pel of the line, the state of which indicates the presence or absence of a change on the pel level, and MICD
-,- - 4a -.... i j .
__ = - ~, ., .. , .. ~ . _.. __.. _ ... . .. .. . . ... _ .... .. . .. . . .. ._ . . ... _ . _ . _ _ .. _ ._ 1 1 626~2 level words corresponding to chantJcd pel~.. The bit number of ~ICP words is always ~ss than or equal to a predetermined integer, such as four, so as to fit the number of DPCM words to be transmitted to the predeter-mined blt number allocated to each line.
However, this encoding and decodiny system has the drawback that the bit number allocated to each line may be reduced to the unity, when the number of line pels to be transmitted, the levels of which have varied, is high. In fact, since an interpolation and, consequently, a subsam~ling are not provided, the picture spatial resolution is very reduced considerably. This encoding and decoding system is used when the ratio between the outgoing and incoming binary rates is relatively low, such as 1/4.
It is therefore an object of this invention to provide an encoding and decoding system free, in particu-lar, of the complexity of the regulation means, the elastic buffers and the resynchronizing means of the conditional replenishment; systems.
Another object of the invention is to allocate to selected pel words of the moving picture parts to be decoded and transmit-ted on the digital transmission medium a constant duration for each frame which is indepen-dent of the variable number of modified elements from one frame to the next.
A further object of the invention is to fix once and for all the number of bits allocated to each line in the low rate digital signal.
Yet another of this invention is to transmit the data relative to the lines in synchronism with the line frequency and, consequently, to eliminate the element cluster addressing problems. The qualities of the recons-tituted picture at the receiver are wholly comparable with those of known conditional replenisnment systems.
t J626~
For achieving the a:Eorementioned objects and according to the present invention as broadly claimed in the appended claims, there is provided a digital video system having an encoding device in the transmitter for encoding a digital video signal at a high given rate constituted of PCM words which have a predetermined bit number and which are represen-tative of consecutive picture elements of a scannecl pi.cture, into a digital encoded si~nal transmitted on a low rate digital trans-mission medium conveying words which are representativeof present picture elements, the levels of which have varied relative to those corresponding to the previous picture. The encoding device of the digital video system comprises:.
- picture storing means for storing the trans-mitted picture eIement words after interpolating;
- means for detecting the moving area of the - present picture with respect to the previous stored picture by means of comparison of the word difference between two words representative of two corresponding elements of the present picture and the previous stored .picture with a predetermined threshold;
- the data bit number NB allocated to each line of a.picture in said digital transmission medium being constant and the average bit number B allocated to each encoded signal word of a line being greater than or e~ual to a first predetermined integer' - said moving area detecting means producing for each line of a picture the coordinates of the two ledge picture elements defining the moving area of said present picture with respect to the corresponding line of said previous picture so as to deduce thereby the number NP of picture elements in said moving area of the line likely to be encoded ana said average bit number B, - a linear predicting means for delivering DPCM
1 1 626~ 2 predicted p.icture element worcl;Erom th~ ~ored plcture element words and presen-t picture element wordsi - firs-t and second clown-counting means controlled by said movement area detecting means and having their counts C1, C2, set to NB and NP at the start of the moving area of each present picture line :Eor down-counting the number of bits remaining -to be allocated to said line and the number of picture element words remaining likely to be encoded at the line element frequency;
- means connected to down-counting means for comparing the counts of said first and second down-count-ing means to select the DPCM words representing the picture element to be transmitted each time Cl/B ~ C2, - means receiving said DPCM words and controlled by comparing means for encoding, according to a predeter-mined quantization law, said selected DPCM words in order to multiplex said selected DPCM words in said digital transmission medium; and - means connected to said encoding means for - 20 linearly interpolating the PCM unselected picture element words.
According to an advantageous characteristic of the present invention and, in order to reduce the data quantity to be transmitted, the encoding means of the encoding device transmits on the digital transmission medium, not the amplitude of the DPCM quantization level of each selected modified element, but rather a B-bit PCM word representing the ~uantification lever number.
Preferably,two identical decoding means are included in the transmitter encoding device and the receiver decoding device respectively and restore a word represen-tative of said level so that the transmitter and receiver frame store.identical words for each pel o~f the moving area of a line after interpolatinq and low-pass filtering, if required. In ,~ .~
~ ~ 626~2 accordance with a Eirst p~efcrrecl cmhod~ment of the encodlng device,lneans are provided for calcula-ting the maxi~u~ 3~
and average D values of the DPCM encoded words of all the elements in the moving area of_a line such that the DPCM
encoding means can select a 2 B level quantization law peculiar to the moving area of the line. This enables the variation characteristics of the incoming video signal to be reduced as much as possible. A quantization law associated with a line may be reconstitu-ted in the decoding device of the receiver, since D and DMAX are included in the data preamble which is assigned to the line and which precedes the selected level words of the line. In accordance to a second preferred embodiment, which is less complex than the first preferred embodiment, the level numbers of a plurality of quantification laws are stored in the encoding means of the encoding device.
For each line, a stored quantification law is selected as function of the average number B alloca-ted to selected and transmitted level words of the line.
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention as illustrated in the accompanying drawings, in which:
- Fig. 1 is a schematic diagram showing the moving area of a picture displayed on the screen of a videotelephone;
- Fig. 2 is a block diagram of the encoding device of the transmitter according to the first embodiment and partlv to the second embodiment;
- Fig. 3 is a detailed block diagram of the movement detector of the transmitter which includes an arithmetic unit for calculating B and NP analogous to the that of the decoding device illustrated in Fig. 13, Flg. 4, which is disposed on the same sheet of I ~ 626~2 drawings as Flgure 1, i5 a clatailed block diagram o~ the bl-t distributing clrcuit whish selec-ts the changed pel to be transmitted, - Fig. 5 is a detailed block diagram of the arithmetic unit for calculating DMAX and D, - Fig. 6 is a detailed block diagram of the PCM
encoder of the -transmitter according to the firs-t embodi-mentz Fig. 7 is a detailecl block diagram of the PCM
decoder of the transmitter or receiver according to -the first embodiment;
Fig. 8 is a detailed block diagram of the PCM
coder of the transmitter according to the second embodi-ment~
- Fig. 9 is a detailed block diagram of the PCM
decoder of the transmitter or receiver according to the second embodiment;
- Fig. 10 is a detailed block diagram of a linear interpolating circuit, - Fig. 11 is a detailed block diagram of a conditional spatial filtering circuit;
- Fig. 12 is a diagram illustrating the sub-sampling in the moving area of a line; and - Fig. 13 is a block diagram of the decoding device of the receiver according to the first embodiment and partly to the second embodiment.
. .
9 ~ 62642 Reference will be made :Ln this description, for example purposes, to a standard videotelephone the functional features of which are as follows:
Definition of a picture displayed by a videotelephone:
- 313 l:ines, 288 of which are used the visible picture portion and 25 of which are allocated to the field (or half-frame) synchronizing and blanking signal;
- each line contains 284 elements, 53 of which are allocated to the line synchronizing and bIanking signal and 231 of whiGh are visible picture elements (pels);
- frequency of the field synchronizing signal equals to 50 Hz i.e. 25 frames per second with two interlacing;
- frequency of the line synchronizing signal :
7.825 kHz ;
- frequency of the elements: 7.825 x 284 = 2.2223 MHz.
After sampling of the video signal which is trans-mitted by the camera of the videotelephone, the encoding device of the transmitter receives a digital signal having a frequency of 8 x 2.2223 = 17.778 M bits/s in which each element is sampled over 256 level values between white (l volt) and black (0.3 volts) and takes up a time-slot T = 450 nsec corresponding to an 8-bit word.
After encoding the video digital signal is conveyed on a digital link which is connected to the output of the transmitted is of the TNl type in accordance with international recommendations. It has a rate equal to 30 2.048 Mbits/s and transmits a repeating frame having 32 eight-bit bytes (octets) whose time intervals TI0 and TIl6 are reserved, inter alia, for frame alignment, signaling and stuffing indication purposes. An 8-bit time interval of the link frame is allocated to a 64kbit/s digital channel . _ . . . _ _ .. .. .. . . . . . . . .. .. , .. . . . . .. . . . .... __ . .
whlch conveys the addltlonal data such as the sound. Con-sequently, 29 time intervals in a 2.048 Mbit/s digital frame are occupied by the video signal produced by the transmitter, namely a video bit-rate at the output of the transmitter equal to:
2.048 x 29/32 = 1.856 Mbit/s In accordance with the invention, the encoding device makes its possible to reduce the picture-carrying video signal rate from 17.778 Mbits/s to 1.856 Mbits/s by assigning a constant number of bits N in the outcoming encoded digital signal to each useful line amongst 288 of a frame which is equal, as per the foregoing parameters, to:
N = 1.856 x 106/(288 x 25) : 258 bits per picture line It will be assumed in what follows that, amongst - these 258 bits, the first 27 are given over to a preamble which contains words intended, in particular, for the line synchronization and certain discriminations inherent in the invention-orientated encoding. It follows from this that NB = 258 - 27 = 231 bits remain which are truly allocated to the transmission of the visible portion of a picture line. These NB bits are generally split into words of at least three bits. Each word indicates the amplitude of a particular line element selected as per DPCM encoding accor-ding to the invention, the principle of which is described hereinafter in reference to Fig. 1.
On this figure, we have schematically shown the contour of the moving picture on a videotelephone screen, such that the speaker's (S) face (shaded area) stands out against a fixed background area BA which is generally unicolour, or more exactly has a uniform colorimetric level.
Each line can be divided into an area BAl, BA2 or two areas BAl and BA2 which represent the background BA and which vary from one frame to the next only in terms of i 1 62642 camera noise, and/or a c~ntral. or lateral area S~ whlch is essentially moving and represents the moving speaker S or the suddenly uncovered background. In this way, for lines Ll, L2, L3, L4 above area S, at the speaker's face level, at the speaker's neck level and at the speaker's shoulder level when fully filmed respectively, as shown in Flg. 1, the area distribution is given by table I below:
TABLE I
Area BAl SA A2_ _ line Llfixed empty empty line L2fixed moving fixed line L3empty moving fixed line L4empty moving empty For each line, these areas are marked ofE by two picture elements Ml and M2 of coordinates X, and X2, or more precisely, the moving area SA of the speaker pictures is defined with respect to the background BA by pairs of elements Ml, M2. Since the video signal representative of the back-ground has a constant amplitude variation on each line, only the pels on picture area SA are of any interest when re-producing the picture in the videotelephone system receiver.
For example, the area Ml M2 of the line L2 is small, the area-Ml M2 of the line L3 occupies the major portion of the 25 left hand side of the screen and the area Ml M2 of the line L4 occupies the whole screen. Since the number of bits NB
allocated to a line is constant, the encoding device transmits the frame data of a line area Ml M2 by reducing the real contents of this received data to 8-bit words at 17.778 Mbits/s in accordance with certain criteria which are based, on the one hand, on the temporal redundancy of the frame or handing only those frame areas which are moving and, on the other hand, on the spatial redundancy with a view to cutting down the range of the transmitted signal by differential pulse .d, -' .
~ .1 82642 cod.ing (DPC~
The various transmitter encoding devlce circuits are illustrated in Fig. 2 and will be described below as we come to them in the processing of the 17.778 Mbit/s digital video signal leaving the camera and the associated sampler.
The encoding device essentially comprises a frame store 1 which momorizes the odd field followed by the even field of one and the same frame, a movement detector 2, a bit distributing circuit 3, a lineas predictor 4, an arithmetic unit 5 which produces digital values D~X and D
which characterize the reducing of the incoming video signal, a PCM encoder 6, a PCM decoder 7, an interpolating circuit 8 and a conditional spatial filtering circuit 9. It further comprises two shift registers (or line delay circuit) Rl and R2 which are connected in series and each having 231 x 8 stages, as well as a digital subtractor 41 and a digital adder 42, an input of each of which is connected to the out-put 40 of the predictor 4. The input I of the encoding device receives only 8-bit words P (F, L) at the binary rate of 17.778 Mbits/s which are representative of the 231 visible elements of a line L of a frame F. Filtering and separating means (not shown) are inserted up line of the input I, in order to separate the video information from the frame and line synchronizing and blanking information. These devices are well known in prior art and do not come within the scope of this invention. Likewise, the multiplexing and transmit-ting circuits connected to the outputs of the encoding device for making up the 2.048 Mbit/s outcoming digital signal shall not be described. In addition, it will be noted that the various links depicted on the drawings are simple connections of bus-bars and that the logic circuits are referred to here-below by their unction and generally comprise a number of such elementary circuits in parallel. The numerical references at the inputs and outputs of blocks in Fig. 2 (and Fig. 13) 1 ~ 626~ 2 designate terminals or inpu~ Ol ou-tput components which may come up in corresponding detailed block diagrams of other figures.
First and foremost, in order to process the area of the moving picture relating to a line L, we must detect the above- defined elements Ml and M2. This function is ful-filled by movement detector 2 shown in Fig. 3. In this detector 2, a digital subtractor 20 receives through its direct input (+) a pel word P (F, L) of a line L in the frame F to be processed which is transmitted by the input I, and through its inverse input (-) a pel word P (F-l,, L) of the line L of the preceding frame (F-l) which is transmitted from the output 10 of the frame store 1.
In accordance with the invention, detection of the movement is based on the element-to-element comparison of the edge zones at elements Ml and M2 (Fig.l) between the frame F being received at the input I and the previous one F-l stored in the frame store 1. In this respect, the frame store 1 (Fig.2) stores all the pel words P' (F, L) of a frame, i.e. 288 x 231 8-bit words. These words P' (F, L) are in fact formed after encoding, as will be seen here-after. The store 1 is, for instance, made up of 34 modules with a capacity equal to 16 kbits. It is of the random access type (RAM) and is written in and read out at a period which is substantially lower than the time slot occupied by a pel word P (F, L). It will moreover be noted that, in the drawings, we have not shown the time base of the encoding device which delivers by means of a clock, such as phase locking loop set at a line frequency of 7.825 kHz, the various monitoring signals peculiar to the monitoring component circuits 1 to 9.
Each element P (F, L) of the present frame F and the corresponding element P' (F-l, L) of the previous frame (F-l) are transmitted into two buffer registers 210 and 220 of the movement detector 2, whlch ar~ .rcspectively inter-connec-ted between the direct input (-~) of the subtractor 20 and the input I and between the i.nverse input (-) of the subtractor 20 and the output 10 of frame store 1. The out-put of the subtractor 20 provides a word representative of difference P (F,L) - P' (F-l, L) which is applled to the inputs of two arithmetic units 211 and 221. The first, 211, transmits a word indicating the absolute value of the difference /P (F, L) - P' (F-l, L)/ to one of the inputs of a digital comparator 23, the other input of which receives a threshold signal T. This threshold T is, for example, equal to the gap between two or three successive levels of the 256 equidistributed levels corresponding to the sampling of the incoming video signal. If /P (F, L) - P' (F-l, L)j> T, the output of comparator 23 isin.state 1 and is in state O otherwise. The second arithmetic unit 221 delivers a 1 if the difference /P (F, L) - P (F-l,L)/ is positive and a O otherwise. The output of comparator 23 and the arithmetic unit 221 are connected to AND gates 213 and 223 respct-ively, having for example three inputs. One of inputs 214, 224 of an AND gate 213, 223, is directy connected to the output of the comparator 23, respectively of the unit 221.
Each of the other two inputs of these gates are connected to the latter input 214, 224 via one delay line 215, 216, two delay lines 215, 216, 225, 226, respectively. These delay lines introduce a delay equal to T and ensure that the.amplitude of three consecutive elements of a line of the present frame have fluctuated with a magnitude differeNce greater than the threshold T and have the same sign with respect to the corresponding elements of the previous frame (F-l). If the sign is positive, then the output of the AND gate 223 applies a 1 to one input of an AND gate 26.
If the sign is negative,.the output of a NOR gate 24, the three inputs of which are connected in parallel to those 1 ~ 62642 of the AND ga-te 223, applles a 1 to the above lnput of the yate 26. The two inputs oE the ya-te 26 are connected to the outputs of the AND gate 213 and, via an OR gate, 25, to the outputs of AND gate 223 and NOR gate 24. In this way, as soon as the output of the AND gate 26 is state 1 at the start of the line processing operation, this indicated the detection of the element Ml. After the transmission of the other moving-picture elements of the major portion of the area SA (Fig. 1) which is modified beyond the threshold T
from one frame to the next, when-the output of the AND gate 26 reverts to state O , this indicates the detection of the element M2. The criterion implicated in movement detector 2 is thus founded on the displacement of the transition or contour between the areas BAl and BA2 on the one hand and the area SA on the other, namely on the inter-frame difference in the amplitudes of the moving elements.
This criterion also distinguishes the moving elements from camera noise by the choice of a suitable value for threshold T.
The output Pf the AND gate 26 is connected to a logic circuit 27 which delivers the coordinates Xl, X2 of the detected elements Ml and M2. The circuit 27 comprises two monostable flip-flops 271 and 272 which are connected directly and via an inverter 270 to the output of the AND
gate 26. The outputs of the flip-flops 271, 272 are con-nected to two AND gates 273 and 274. The other inputs of the AND gates 273, 274 are connected to the output of an element counter 277. This counter 277 is triggered after the end of the line synchronizing signal following the first 53 elements and is reset to zero and held after the 231st following element. The output of the counter 277 thus transmits the successive coordinates 1 to 231 of the line elements. Buffer registers 275 and 276 connected to the outputs of the AND gates 273 and 274 store the Xl and X2 i 1 62642 coordinates of the detec-ted elements Ml and M2.
It will be noted, as will be explained later on, that the detection of elements Ml and M2 by means of the movement detector 2 is performed over a line transmission period equal to 1/7.825 second. Throughout this detection, the 231 8-bit pel words P (F, L) of the line L are delayed in series in the first shift register Rl connected to the input I. Reading of the Xl and X2 coordinates from the registers 275 and 276 is controlled at the start of the following line L + 1 received at the input I. The various delays lasting one line L or two lines 2L for carrying out the various operations inherent in the encoding are indicated in the drawing by blocks representing line synchronizing signal delay circuits.
Referring now to Fig. 4, bit distributing circuit 3 delivers, upon reception of the-second next line L + 2-at the input I, the average number of bits s allocated to each pel cf line L to be transmitted and selects in accordance with distribution criteria the elements that will be really transmitted in order to adapt the 17.778 Mbits/s incoming rate to the 1.856 Mbits/s outgoing rate, i.e. to the real rate of 2.048 Mbits/s after multiplexing. The distribution criteria are as follows:
a) each pel to be transmitted is so indicated by a word having at least three bits as to obtaining a DPCM encoding giving adequate picture qualities in the receiver; the number of bits in a transmitted pel word is preferably restricted by a high limiting value equal to six for instance;
b) since the frequency pass band is reduced in the moving area SA (Fig. 1), due in particular to the blurring inherent to integration in camera, subsampling of the moving elements ~.r can be perEormed; ln o~h~r words, certain el~ments of a line in area S are neither encoded nor transmitted and will be reconsti-tuted upline of the frame store, both in the transmitter encoding device (Fig. 2) and in the receiver decodin~ dev;lce (Fig. 13) by means of interpolating and filtering circuits such as 8 and 9;
c) when the total number of bits NP ~ B of the NP pel words in the SA area is less than the number of bits NB reserved for a line, i.e.
- when the SA area or X2 - Xl is very small, then filling bits without sense and/or eventually additional data words, such as pel PCM words, can be mixed with the NP x B bits to come up to NB bits.
Bit distribution and sample selection mainly depend on the width of the area SA equal to X2 - Xl on the line L. With this in mind, the movement detector 2 shown in Fig. 3 includes an arithmetic unit 28 which calculates the number of elements NP of the SA area lying between M
and M2, including the latter, and the average number of bits B to be assigned to each element to be transmitted.
Under control of the synchronizing signal of the following line L + 1 prior to the start of line L pel word transfer from register Rl to register R2, shown in Fig. 2, the X
and X2 coordinates are read in the registers 275 and 276 via reading AND gates 28I and 282. They are transmitted, on the one hand, to inputs 510 and 520 of the arithmetic unit 5 (Fig.5) and, on the other hand, to the inverse (-) and direct (+) inputs of a digital subtractor 283, respectively.
The difference (X2 - Xl) is added to unity in an adder 284 to deliver X2 - Xl + 1 = NP to a register 285 and to the input of an divide -by- NB devider 286. The divider 286 I 1 62~2 performs the integer division: integer part (NB/NP) =
b = average number of bits. The number b delivered by the divider 286 is compared with three and six in a comparator 287. If 6 > b ~ 3, then an output 2871of the comparator 287 opens an AND gate 2880 so as to transmit the number of bits allocated to each pel after encoding, such that b =
s, from the output of the divider 286 to a register 289, via an OR gate 2881. If b < 3, then an output 2873 of the comparator 287 applies the lower limiting integer value of the average bit number B equal to 3 to the register 289 via the OR gate 2881. Finally, if b > 6, then an output 2876 of the comparator 287 applies the upper limiting integer value of the average bit number B equal to 6 to the register 289 via the OR gate 2881.
The bit distribution circuit 3 shown in Fig. 4 comprises two down-counters 31 and 32 which have their counts initially set to NB and NP respectively by reading a read-only memory (not shown) and the register 285 (Fig.3) controlled by the line synchronization signal. The count of a down-counter 30 is also initially set to xl by reading the register 275 (Fig. 3) so that, once its count reaches zero it triggers counting in down-counters 31 and 32 at the element frequency l/t, simultaneously with the series transmission of the pel words P (F, L) of the line L from register R2 to the input 600 of the encoder 6 via the sub-tractor 41 (Fig. 2). The counts in down-counters 31 and 32 are delivered on output buses 310 and 320, at the element frequency of 1/l = 2.2223MHz, to two digital multiplying circuits 33 and 34 by NP and NB, respectively. The outputs of the circuits 33 and 34 are connected to the direct (~) and inverse (-) inputs of a digital comparator 35. When the difference of the compared words in the comparator 35 is positive, its output 350 is in state 1 and controls the opening of an AND gate 36, the other input of which receives the average number oE bits B kransm:Lt-ted by the regist~r 289 (Fig. 3) at each period ~. Coun-ting input 311 of the down-counter 31 is connected to the outpwt of AND gate 36 and down-counting input 321 of the down-counter 32 receives a 1 at each period ~ corresponding to the NP elements of moving area SA of the line L.
It can be seen rom the bit distributing circuit
3 shown in Fig. 4 that the down-counter 31 counts down the number of available bits remaining to be allocated to the line L and that the down-counter 32 counts down the number of remaining bits of moviny area SA. The count C2 of the down-counter 32 is successively decremented by unity for each element lying between Ml and M2. The count Cl of the down-counter 31 is reduced by B each time output 350 of the comparator 35 is positive, i.e. when Cl/B > C2 or Cl x NP > C2 x NB and Cl x NP > B x NP.
When the above inequality is satisfied, the element is sampled, i.e. transmitted, the down-counter 31 is decremented by B and the gate 36 applies the word B
via the bus 360 to down-counting input 311 of the down-counter 31 and to an input 601 of the encoder 6, so as to encoding said element into DPCM code. On the other hand, should the above inequality not be satisfied, the element is subsampled, i.e. will be reconstituted by interpolation in the interpolating circuit 8 (Figs. 2 and 10), the AND
gate 36 remains closed and the down-counter 31 is not decremented. The down-counter 32 is always decremented by unity when passing from one element to the next.
The two following tables II and III illustrate a simple example of the bit distribution operation for a number NB of available bits per line equal to 20 bits, although in practice this number is higher.
i 1626~2 TABLl~. II
_ _ .
NB = 20 bits . NP = 6 elements b = 3 B =
_ filling line elements Ml M2 bits _ _ __ _ Cl X NP
(output of 33) 120 102 84 66 4~ 30 C2 x NB
(output of 34) 120 100 80 60 40 20 sampled . .
elements 15 (output 360) 3 3 3 3 3 3 2 _ _ - TABLE I I I
. _ NB = 20 bits NP - 11 elements to B = 3 line elements ~1 __ _ ~ M2 filling bits _ _ _ I _ (~utput of 33)220 187 187 154 154 121 88 8~ 55 55 22 . _ __ _ _ _ C2 x NB 22000 180 160 140 120 100 30 60 40 20 out- sampled _ _ _ _ _.
put elements B 3 3 _ 3 3 3 _ 3 2 360 elements subsampled and repro- 0 0 0 0 0 duced by _ tniOnrpola- __ __ L L _ ^~r - 21 -~ de~CriptiOIl wll l llOW b~ given of circuits 4 and 5 which are lntended for reducing the line resolution of the digital incoming signal~
The linear predictor 4 shown in Fig. 2 is of a known type. The 8-bit predictor pel word PP (F, L) trans-mitted by the output 40 is obtained by a linear combina-tion of already transmitted pel words for it to be indentical at the transmitted and receiver, so as to avoid the transmission of additional data. The prediction is based on the linear combination of the PCM-coded amplitude of predetermined elements which belong to the present frame F (intra-frame prediction) and/or the previous frame F-l (inter-frame or frame difference prediction). These various predictions are described, for instance, in B.G. HASKELL's article, entitled -Entropy Measurements for Nonadaptive and Adaptive, Frame-to-Frame, Linear-Predictive Coding of Videotelephone Signals . The Bell System Technical Journal, July-August 1975, pages 1155 to 1174. For an element P(F,L) of the frame F on the line L, the corresponding 20 predicted element may be, for example:
1) PP (F,L) = P' (F-l,L) or 2) PP (F,L) = (P-l)' (F,L) or 3) PP (I,L) = (P-l)' (F,L) + P' (F,L-l) - (P-l)' (F,L-l) or 4) pp (I,L) = ((P-l)' (F,L) + (P+l)' (F,L-l)) /2 P-l and P+l designate the elements coming before and after element P on a line L of a frame F. P', (P-l)' and (P+l)' relate to the values which are obtained after encoding and interpolation, then stored into the frame store 1. The predictor 4 can be of the nonadaptive type and in which case always carries out the same prediction operation for all elements. It can also be of the adaptive type where upon it operates for each frame line as per one of the preceding linear predictions in terms of certain criteria, .
such as the rela-tive movement ~f -th~ present frame F with respect to the previous Erame (F-l). In the latter case, for suitable line reproduction in the receiver, an output 43 of predictor 4 transmits a so-called prediction word PW
which indicates the prediction opera-tion selected for the frame line. This word PW is inserted in the 27-bi-t data preamble assigned to the line in the 2.048 Mbits/s digital link. As shown in Fig. 2, for each pel word P (F,L~ of a line L of a frame F transmitted by the output of the second shift register R2, the output 40 of the predictor
When the above inequality is satisfied, the element is sampled, i.e. transmitted, the down-counter 31 is decremented by B and the gate 36 applies the word B
via the bus 360 to down-counting input 311 of the down-counter 31 and to an input 601 of the encoder 6, so as to encoding said element into DPCM code. On the other hand, should the above inequality not be satisfied, the element is subsampled, i.e. will be reconstituted by interpolation in the interpolating circuit 8 (Figs. 2 and 10), the AND
gate 36 remains closed and the down-counter 31 is not decremented. The down-counter 32 is always decremented by unity when passing from one element to the next.
The two following tables II and III illustrate a simple example of the bit distribution operation for a number NB of available bits per line equal to 20 bits, although in practice this number is higher.
i 1626~2 TABLl~. II
_ _ .
NB = 20 bits . NP = 6 elements b = 3 B =
_ filling line elements Ml M2 bits _ _ __ _ Cl X NP
(output of 33) 120 102 84 66 4~ 30 C2 x NB
(output of 34) 120 100 80 60 40 20 sampled . .
elements 15 (output 360) 3 3 3 3 3 3 2 _ _ - TABLE I I I
. _ NB = 20 bits NP - 11 elements to B = 3 line elements ~1 __ _ ~ M2 filling bits _ _ _ I _ (~utput of 33)220 187 187 154 154 121 88 8~ 55 55 22 . _ __ _ _ _ C2 x NB 22000 180 160 140 120 100 30 60 40 20 out- sampled _ _ _ _ _.
put elements B 3 3 _ 3 3 3 _ 3 2 360 elements subsampled and repro- 0 0 0 0 0 duced by _ tniOnrpola- __ __ L L _ ^~r - 21 -~ de~CriptiOIl wll l llOW b~ given of circuits 4 and 5 which are lntended for reducing the line resolution of the digital incoming signal~
The linear predictor 4 shown in Fig. 2 is of a known type. The 8-bit predictor pel word PP (F, L) trans-mitted by the output 40 is obtained by a linear combina-tion of already transmitted pel words for it to be indentical at the transmitted and receiver, so as to avoid the transmission of additional data. The prediction is based on the linear combination of the PCM-coded amplitude of predetermined elements which belong to the present frame F (intra-frame prediction) and/or the previous frame F-l (inter-frame or frame difference prediction). These various predictions are described, for instance, in B.G. HASKELL's article, entitled -Entropy Measurements for Nonadaptive and Adaptive, Frame-to-Frame, Linear-Predictive Coding of Videotelephone Signals . The Bell System Technical Journal, July-August 1975, pages 1155 to 1174. For an element P(F,L) of the frame F on the line L, the corresponding 20 predicted element may be, for example:
1) PP (F,L) = P' (F-l,L) or 2) PP (F,L) = (P-l)' (F,L) or 3) PP (I,L) = (P-l)' (F,L) + P' (F,L-l) - (P-l)' (F,L-l) or 4) pp (I,L) = ((P-l)' (F,L) + (P+l)' (F,L-l)) /2 P-l and P+l designate the elements coming before and after element P on a line L of a frame F. P', (P-l)' and (P+l)' relate to the values which are obtained after encoding and interpolation, then stored into the frame store 1. The predictor 4 can be of the nonadaptive type and in which case always carries out the same prediction operation for all elements. It can also be of the adaptive type where upon it operates for each frame line as per one of the preceding linear predictions in terms of certain criteria, .
such as the rela-tive movement ~f -th~ present frame F with respect to the previous Erame (F-l). In the latter case, for suitable line reproduction in the receiver, an output 43 of predictor 4 transmits a so-called prediction word PW
which indicates the prediction opera-tion selected for the frame line. This word PW is inserted in the 27-bi-t data preamble assigned to the line in the 2.048 Mbits/s digital link. As shown in Fig. 2, for each pel word P (F,L~ of a line L of a frame F transmitted by the output of the second shift register R2, the output 40 of the predictor
4 delivers the corresponding predicted word PP(F,L) in terms of at least one of the words (P-l)'(F,L), (P-l)' (F,L-l) P'(F-l,L) and (P+l)'(F,L-l) which is delivered from the output 11 of the frame store 1. The digital subtractor 41 applies the difference word such as DP(F,L)=
P(F,L) - PP(F,L) to the input 600 oE the encoder 6.
The encoder 6 of the encoding device quantizes the digital differential signal DP(F,L) with respect to a number of quantization levels NQ which depends upon the number of bits B allocated to each sampled element of a common line L by the bit distributing circuit 3. In fact, the encoding from the encoder 6 is established on the absolute value ¦DP (F,L)¦ , where the values corresponding to DP (F,L) < O are obtained by symmetry. The quantization levels are distributed, as shown below, right across the variation range of the incoming differential signal DP(F,L) for the moving area SA of a line L.
The maximal and average values of the incoming differential signal DP (F,L) for a line L are designated by DMAX (L) and D (L) such that:
DMAX(L) = Max ¦P(F,L) - PP (F,L)¦
Ml < P < M2 1 ~ 626~2 ~= M2 D(L) = 1 ~ ¦P(F,L) - PP (F,L)¦
P=M
For the quantization level number NQ = 2B, the encoder 6 equidistributes the levels half and half over the ~-D,~D] range and r-DMAX,-D tand~ D, DMAX] ranges. Encoding such as this obviates encoder overflow, which is a phenomenon producing drag and visible pin-poin.t flaws.
-It can thus be seen from the foregoing that encoding any element selected by the bit distributing circuit 3 calls for prior knowledge, on the one hand, of Xl and X2 and, on the other hand, of DMAX and D. DMAX and D are consequently caIculated before encoding in the .encoder 6 but after calculation of coordinates Xl and X2, since this calculation depends on the latter. The time required for processing a line is at the most 1/7.825 kHz =
128 ~s and does not permit the successive calculations of Xl and X2 then D and DMAX followed by the encoding.
The various operations preceding the encoding of the line L are carried out simultaneously with the respective encoding of the preceding lines, L-2 and L-l, as indicated in the following table IV:
. .
'~'ABLE, LV
Calculation o~ Xl,X, Ca:lcula-tion oE NP ~it d.l,tr:Lbutlon in 2 ~Fig 3) and ~ in 2 (FicJ.3) :Ln 3 and encod:i.ng-. . and calcula-tlon of decoding in 6,7 D and DMAX in 5 and 8 (Figs.6,7 (Fig.5) and 8) . .
Register R1 Register R2 Line L Line L - 1 Line L - 2 Line L + 1 Line L Line L - 1 Line L + 2 ~ Line L + 1 Llne L
With reference to Fig. 5, the arithmetic unit 5 .15 firstly comprises a circuit 50 for calculating a predicted value PP' (F,L~ close to the real predicted value PP (F,L) which is transmitted by the output 40 of the predictor 4.
Indeed, in the event of an intraframe prediction taking into account, for example, the previous element (P-l)(F,L) (preceding predictions 2, 3 and 4), this element can not be provided by the frame store 1, since it is obtained af-ter encoding in the encoder 6 and decoder 7 and interpolating in the circuit 8. These operations follow the calculation of D and DMAX. If such a prediction is selected, the value - (P-l)'(F,L) is substituted to the real value (P-l)(F,L) which is transmitted from the output of the first shift . register Rl via a delay circuit 500 to an input of a pre-dicting circuit 501 included in the unit 5. Should the prediction be based on the elements P(F,L-l) and (P+l) (F,L-l) of the previous line (L-l) (preceding predictions 2 and 4), then the evaluation of these values is also based on the values received to the input I of the encoding device. Indeed, one the value P(F,L) has been transmitted by the output of the register Rl, the recorded value P'(F,L-l) . - 25 -~r . ~ .
.. ~ ~ . .
i J 6~642 to be s-tored in the frame store 1 Joes under evaluat~on in encoder and decoder 6-7 or in -the lnterpola-tlng clrcult 8, and the value (P+l)'(F,L-1) correspondlng to the value (P~
(F,L-l) after encoding or lnterpolating will not yet have been transmitted by the output of the register R2. It follows that, for such predictions, consideration is taken of the real values P(F,L-l) and (P+l)(F,L-l) transmitted from the last and first-to-last stages of the register R2 to two inputs of the predicting circuit 501 respectively.
Finally, when the prediction is founded on an elemen-t such as (P-I)(F,L-l) (intra-frame prediction 3) or an element such as P(F-l,L) (inter-frame prediction 1), then the cor-responding values (P-l)'(F,L-l) and P'(F-l,L) obtained after encoding or interpolating are already stored in the frame store 1. These values are transmitted to two other inputs of the predicting circuit 501 from the output 12 of the frame store 1 simultaneously with the transmission of P(F,L) from the output of the register Rl. To recapitulate, the predicted pel word PP'(F,L) delivered from the output of the predicting 501, which is analagous to the predictor 4, is given by the following relations in comparison with the four above prediction:
1) PP'(F,L) = P'(F-l,L) equal to PP(F,L) 2) PP'(F,L) = /P-l)(F,L) different from PP(F,L) 5 3) PP'(F,L) = (P-l)(F,L) + P(F,L-l) - (P-l)'(F,L-l) different from PP(F,L) 4) PP'(F,L) = ((P-l)(F,L) + (P + l)(F,L-l)~ ~ 2 different from PP(F,L) The different predictions are selected by the detection of the PW word which is delivered from the output 43 of the predictor 4 to the predicting circuit 501.
In the arithmetic unit 5, after the de-tection of the synchronizing signal related to the line L+l, two down-counters 51 and 52 are decremented by unity at every period I J fi26~2 ~ ln time. The counts oE th~se down-counters are lnitially set beforehand to the Xl and X2 values whlch are transmitted to their inputs 510r 520 from the registers 275 and 276 via reading AND gates 281 and 282 (Fig. 3). As long as the count in the down~counter 51 is not zero, its outpu-t 511 remains in state 'o'' and closes AND gates 502, 503, 50~, 505 and 506 via an AND gate 507. These gates 502 to 506 are intended for transmittin~ the respective values P(F,L) from ~he out-put of the register Rl, (P-l)(F,L) from the output of delay line 500, (P+l)(F,L-l) from the last-but-one stage of the register R2, P(F,L-l) from the last stage or output of the register R2 and P' (F-l'L) and (P-l)'(F,L-l) from the output 12 of the frame store 1 to the predicting circuit 501 when the outputs 511, 521 of the down-counters 51, 52 are in state 1 , via AND gate 507. The count in the down-counter 51 is then equal to zero after the transmission of pel word representative of the element Ml from the output of the register Rl and the count in the down-counter 52 is less than or equal to X2. The predicting circuit S01 therefore delivers the predicted words PP' (F,L) which correspond to all the elements lying between Ml and M2 of each line L.
The predicted value PP' (F,L) iS applied to one of the inputs of a subtractor 53, the other input of which receives the real value P(F,L) from the output of the AND
gate 502. The absolute value ¦ P(F,L)-PP'(F,L) ¦is trans-mitted by the subtractor 53 to be added in an accumulator 55 to the sum of the absolute values which are previously calculated for the elements Ml to P-l. The absolute value ¦P(F,L) - PP'(F,L)¦ iS also compared in a comparator 56 with the value of the previously-received absolute values.
When the count in the down-counter 52 is equal to zero, which corresponds to the transmission of the element as per the element M2 by the output of the register Rl, the output 521 of this down-counter opens two AND gates 550 1 ~ 62642 and 560 via an lnver-ter 522 whlch dellver the following values:
P = M2 D x NP =) ¦P (F L) PP (F L) ¦
P = Ml DMAX = Max ¦P(F,L) - PP' (F,L)¦
Ml < p < M2 The average value D is obtained by a divide-by-NP
divider 551 which is connected to the output of the AND gate - 550 and receiues NP from the register 285 of the movement detector 2 (Fig.3). This average value D is stored into a memory 57, read during the encoding of the present line L, and is transmitted to the inverse input (-) of a sub-tractor 58 which receives the value DMAX from the AND gate 560 through its direct input (+). The subtractor 58 delivers DMAX-D to a memory 59l also read during the encoding of the line L. The accumulator 55 and comparator 56 are then automatically reset to zero.
The output 61 of the encoder 6 shown in Fig. 6 transmits a B-blt binary coded word LEV(F,L) representing the quantization number out-of NQ=2B levels, each time the bit distributing circuit 3 delivers on the output 360 of the AND gate 36 (Fig.4) the word B which indicates the average number of bits to be allocated to a sample word DP(F,L) transmitted by the subtractor 41 (Fig.2). The word B is transmitted to common input 601 of a B word detecting circuit 62 and an arithmetic unit 63. The circuit 62 can be, for example, a 3-comparator which delivers a 1 at its output each time it detects a word such that B ~ 3.
In this case, it opens a writing AND gate 620 of the encoder 6 and a writing AND gate 720 of the decoder 7 (Fig.7) so as to select the DP(F,L) samples in 8-bit DPCM code which . . .
.
i J 62642 are delivered to khe digital input of the AND gate 620 from the subtractor 41. The DP(F,L) words corresponding to B=O, as indicated in the last line of table III for example, are subsampled, i.e. are not transmitted by closing AND gate 620 and correspond to P'(F,L) pel words which are deduced by interpolation in the circuit 8, as will be seen in reference to Fig. 10. The arithmetic unit 63 comprises a calculation mo~ule 630 which performs the operation NQ=2B, a divide-by-2 divider 631, a divide-by-4 divider 632, an adder 633 and subtractors 63~, 635, 636, SO as to produce the numbers NQ/2, NQ/2-1, MQ/4, NQ/4-1, 3NQ/4 and 3NQ/4-1 at its six outputs. These integer numbers serve in the calculation of LEV (F,L) in the encoder 6 and of the sample word after decoding DP~ (F,L) in the decoder 7.
AS already stated, the NQ levels are equidistributed half and half into the interval L-Dr +D~ and the double-interval [-DMAX, -D L~] D, DMAX~. The level number NQ
is therefore adapted by the encoder 6 to the available bit number NB per line in terms of the numbers of elements NP
in the SA area of the line L.
A11 the logic operations in the encoder and decoder are carried-out with 8-bit words and the output words LEV(F,L) of the encoder have B bits for each line respectively, with B which is greater than or equal to a first predetermined number equal to 3 and which is less than or equal to a second predetermined number equal to 6.
For each sampled element, these operations last less than a time T .
We have assumed for the embodiment of the encoder and decoder illustrated in Figs. 6 and 7, that the numbers of levels are in an increasing order from O to NQ-1 for the levels increasing from -DMAX to DMAX and the encoding level DP'(F,L) of a sample DP(F,L) is equal to the middle quan-tization level of the quantization range to which DP (F,L~
1 ~ B264 2 belongs. O~ course, other level distxibutlons and numberlng can be chosen, provided the decoders at the transmi-tter and receiver be respectively identical.
In keeping with the above example, the following relations give, for the three equidistribution intervals of the levels, the level number LEV(F,L) as a function oE the sample DP(F,L) in DPCM code and the value of the corresponding sample DP'(F,L) in DPCM code after quantization as a function of LEV (F,L) ; SGN designates the sign of DP(F,L), i.e. +l when DP > O and -1 when DP < O and the divisionsare whole.
NQ
a) when -D < DP ~ D then 4 < LEV < 3 NQ/4 LEV = [(DP x NQ x l)+ SGN] 1 + NQ
DP' = (LEV - (NQ/2 - 1 3) x 4 x D
NQ
b) when DP > D > O then 3 Q < LEV < NQ
LEV = ((DP - D) X Q x + SGN) 2 + 3NQ - 1 DP' = (( LEV+3NQ/4 - 1)) x 4Q x (DMAX-D)) + D
c) when DP <-D < O then ~ LEV < 4Q
LEV = ((DP + D) x NQ x 1 + SGN) 1 ~ NQ _ 1 2 _ 2 4 DP' = ((LEV - (NQ/4 - 1)) x NQ x (DMAX - D)) - D
The following tables V and VI indicate the quanti-zation numbers and the corresponding sample values, LEV and DP', which have been calculated as per the above relations ..
1 ~ 626~2 for values oE B such th~t B - 3 ~nd B = 4.
DP LEV DP' ~(D + 3DMAX)/4, DMAX~ 7 DMAX
~3D + DMAX)/4, (D + 3DMAX)/4~ 6 (DMAX ~ D)/2 L3D/4, (3D + DMAX/4L 5 D
LD/4, 3D/4 L 4 D/2 J ~D/4, D/4 r 3 O
-3D/4, -D/4~ 2 -D/2 r( 3D - Dl~AX)/4, -3D/41 1 _ ~-DMAX, (-3D - DMAX)/4~ -(DMAX+D) :
TABLE VI (B = 4, NQ = 16) DP LEV DP' _ [(D+7DMAX)/8, DMA,~J 15 D~X
~3D+5DMAX/8, (D+7DMAX)/8 L 14 lD+3DMAX)/4 ~5D+3DMAX)/8, (3D~5DMAX)/8~ 13 (D+DMAX)/2 t(7D+DMAX)/8, (5D+3DMAX)/8 r. 12 (3D+DMAX)/4 r;7D/8, (7D+DMAX)/8~ 11 D
L5D/8, 7D/8~ 10 3D/4 L3D/8, 5D/8~ 9 D/2 CD/8, 3D/8~ 8 D/4 -D/8, D/8~ 7 O
-3D/8, D/81 6 ~/4 -5D/8, -3D/8~ 5 -D/2 -7D/8, -5D~8~ 4 -3D/4 -~p/DMA~/8, - 7D/8~ 3 D
-~5D+3DMAX)/8, -(7D+DMAX)/8~ 2 -(3D+DMAX)/4 -(3D+5DMAX)/8, -(5D+3DMAX)/8~ 1 -(D+DMAX)/2 L -DMAX, -(3D+5DMAX)/8~ O -(D+3DMAX)/4 . _ . ~.
... . .
1 1 626~2 As shown ln Fig. 6, the encoder 6 comprises a main channel, the logic circuits of which are common to the LEV(F,L) calculations in the three above cases a,b,c, and are interlinked as per the order of the LEV(F,L) calculation operations. These logic circuits deal first of all with the distinction of the three cases, then a subtraction of DP(F,L), if required, and a multiplication by NQ/2, the division by D of (DMAX-D) followed by the addition of SGN
and the division by 2, and finally, if necessary, an addition of a factor such as NQ/2-1, 3NQ/4-1 or NQ/4-1. The sign SGN of DP~F,L) is obtained from the following operations on the DP(F,L) sign bit which is O when positive, and 1 when negative: negation in 621, multiplication by 2 in 622 and subtraction of unity in 623. The circuit assemblies performing the latter four operations are represented by the numbering prefixes 64, 65, 66 and 67j in Fig. 6, respectively. The arithmetic unit 63 delivers NQ/2 to the input of a multiplier 651 of the encoder, NQ/2-1 to an input of an AND gate 67a of the encoder and an input of an AND gate 75a of the-decoder, NQ/4 to the inverse input (-) of a subtractor 740 of the decoder and to an input of a divider 752 of the decoder, NQ/4-1 to the digital input of an AND gate 67c of the encoder and to the digital input of an AND gate 75c of the decoder, 3NQ/4 to the inverse input (-) of a subtractor 741 of the decoder, 3NQ/4-1 to the digital input of an AND gate 67b of the encoder and to the digital input of an AND gate 75b of the decoder. Memories 57 and 59 of the arithmetic unit 5 (Fig.5) are read at the rate of 1/T after the detection of the synchronizing signal related to the L+2 line. The memory 57 delivers, via link 570, the avera~e value D of the DP(F,L) samples to the in-verse input (-) of a subtractor 640, to an input of an adder 641 and to the digital input of an AND gate 66a of encoder 6 and to the respective digital inputs of AND gates 76a, , 77b and 77c oE decocler 7 (l'lg./). Th~ ~ND ga~e 77c receives in fact -D by means oE a unity subtrac~or 770.
The memory 59 delivers, via link 590, the difference DM~X-D
to the digital input of an AND gate 66bc of the encoder and to the digital input of an AND gate 76bcof the decoder.
The logic circuit 64 distinguishes between -the three cases a), b), c). It comprises the subtractor 640 and adder 641 which have their other inputs connec-ted to the output of the writing AND gate 620, and two zero comparators 642 and 643 which have their respective inputs receiving DP(F,L)-D from the subtractor 640 and DP(F,L)+D from the adder 641. The outputs of the AND gate 620, subtractor 640 and adder 641 are also connected to the digital inputs of AND gates 65a, 65b and 65c, respectively. When DP(F,L)-D > O
(case b), then the output of the comparator 642 is in state 1 and when DP(F,L)+D > O (cases a and b), then the output of the comparator 643 is in state 1 . These two output signals are combined by means of AND gates 64a, 64b and 64c to control the various calculation operations of LEV(F,L) as per cases a, b and c. The control AND gate 64a has its respective inputs connected to the output of the comparator 642 through an inverter 644 and directly to the output of the comparator 643, and has its output connected to the control inputs of the AND gates 65a, 66a and 67a. The control AND gate 64b has its inputs connected directly to the outputs of the comparators 642 and 643 and its output controlling the opening of the AND gates 65b and 67b and that of the AND gate 66bc via an OR gate 660. The last con-trol AND gate 64c has its respective inputs connected to the outputs of the comparators 642 and 643 via inverters 644 and 645 and controls the opening of the AND gates 65c and 67c and that of the AND gate 66bc via the OR gate 660.
The difference of DP(F,L) with the zero value or D, or the addition of DP(F,L) to D is transmitted in the cixcuit 65, via an ~R gate 650 connec-ted to the outputs of the AND gates 65a, 65b and 65c, to the other input of NQ/2 multiplier 651. The division of the word outgoing of the multiplier 651 by D or (DMAX-D) is performed in a divider 661 whose other input is connected via an OR gate 622 to the outputs o AND gates 66a and 66bc. The result of the above division i5 added to SGN in an adder 663 and is then divided by in a divider 664. The divider 664 is interconnected between the output of the adder 663 and one of the inputs of an adder 670. The outputs of AND gates 67a, 67b and 67c are connected via an OR gate 671 to the other input of the adder 670 such that this adder 670 adds the last term NQ/2-1, 3NQ/4-1 and NQ/4-1 depending on the cases a, b, and c. The output of adder 670, common to output 61 of the encoder, transmits the level number LEV(F,L) in B-bit pure binary code to input 70 of the decoder 7(Fig.7) and via a buffer store 68 to an input of the transmitter multiplexing circuit (Fig.2). The buffer store 68 makes it possible to adapt the 17.778 Mbits/s incoming digital rate to the 2.048 Mbits/s outgoing one. With this in mind, the LEV (F,L) words delivered from the output 61 are written under the control of B detecting circuit 62 and are read at 2.068 MHz frequency. The capacity of store 68 is equal t max Referring now to Fig. 7, the decoder 7 comprises a main-channel, the logic circuits of which 74, 75, 76 and 77 are common to the calculations of DP'(F,L) as per the three cases a, b and c. These logic circuits follow one after the other in the order of the basic operations in the relations given earlier on.
The circuit 74 relates to the distinction of the three cases. It comprises the subtractors 740 and 741 and two zero-comparators 742 and 743 whose inputs are connected to the outputs of the subtractors 740 and 741,respectively.
The direct :inp~l-ts (~) o~ ~he s~l~stractor 740 and 741, as well as that of a substractor 750 are connected to -the out-put of the wrlting AND gate 720, digital input 70 of which receives the LEV(F,L) word under the control of the outpu-t signal from B word detecting circuit 62 (Fig.6). When NIV > NQ/4 (case a), the output of the comparator 742 is in state 1 . When LEV > 3NQ/4 (case b), output 74b oE the comparator 743 is in state 1 . The inputs of a first AND
gate 74a which controls the calculation of DP'(F,L) according to the case a, are connected directly to the output of the comparator 742 and, via an inverter 744, to the output of the comparator 743. The output of the AND gate 74a is con-nected to the control inputs of the AND gates 75a and 76a and to that of an AND gate 77a whose digital input receives to zero-value. The calculation of DP'(F,L) according to the case b is controlled directly by output 74b of the comparator 743 which is connected to the control inputs of the AND gates 75b and 77b and, via an OR gate 760, to that of the AND gate 76bc. Finally, the calculation of DP'(F,L) as per case c, is controlled by an inverter74c, the input of which is connected to the output of the zero-comparator 742. The output of the inverter 74c is connected to the control inputs of the AND
gates 75c and 77c and, via OR gate 760, to the AND gate 76bc.
The difference of LEV (F,L) with the number NQ/2-1, 3NQ/4-1 or NQ/4-1 is obtained by the subtractor 750, the inverse input (-) of which is connected, via an OR gate 751, to the outputs of the AND gates 75a, 75b and 75c. The above difference is divided by NQ/4 in the divider 752 which is interconnected between the output of the subtractor 750 and an input of a multiplier 760. This multiplier 760 multiplies by D or (DAMX-D) which is transmitted to its other input by the outputs of the AND gates 76a and 76bc, via an OR gate 761. The result of the muItiplication is transmitted to an input of an adder 771. The other input of the adder 771 ,~i~, I Jfi2642 receives -the value O, D or -D ~-hroucJh th~ outputs of the gates 77a, 77b and 77c via an OR gate 772. The output of the adder 771 is common to that 71 of the decoder 7 and transmits the 8-bit DP'(F,L) word to the other input of adder 42, shown in Fig. 2. The adder 42 adds DP'~F,L) to the element word PP(F,L) predicted by the predictor 4 in order to transmit PC (F,L) = PP(F,L) ~ DP'(F,L), which differs little from P(F,L) for a sampled element (DP' ~ O) or is equal to PP(F,L) for a subsampled element (DP' = O), in the direction of the input 13 of the frame store 1, after interpolation and filtering (Fig.2). This sample value PC(F,L) is so obtained after decoding and is recorded in the frame store 1 so as to establish the predicted samples of the following line and/or following frame.
The description of Fig. 6 brings to light the fact that the encoder 6 adapts the bit number of the LEV(F,L) word representing the sample to the ratio B = NB/NP cal-culated in movement detector 2 (Fig.3). This number B
lies between 3 and 6. The multiplexing circuit in the trans-mitter, upon detection of the synchronizing signal of the L+2 line, multiplexes the words contained in the 27-bit pre-amble allocated to the line, which are:
- Xl(Ml) and X2(M2) delivered from the registers 275 and 276 (Fig.3), - D and DMAX-D delivered from the memories 57 and 59 (Fig.5), and - possibly the prediction word PW delivered from the output 43 of the predictor 4 (Fig.2) when the predictor is adaptive.
Then, after detection of the line (L+2) synchronizing signal corresponding to the start of line L sample encoding, the multiplexing circuit receives the sequence of LEV(F,L) words following the preamble via the output 61 of the encoder 6 which, via the buffer memory 68, are read at a bit-rate of ,, ;f . , ~ .
1 J 626~ 2 2.048 Mbits/s.
In accordance with A second embodiment, the quantization level number LEV(F,L) and the DP' (F,L) values for each distribution of pel words represented by the value of s charac.terizing the moving area SA of a line L are fixed, namely have been recorded beforehand in two blocks of read-only memories.
The encoder 6' according to this second embodiment is illustrated in Fig. 8. It comprises for instance four read-only memories 603, 604, 605 and 606. These memories comprise 8,16, 32 and 64 memory cells, respectively, which each stores a quantization level number LEV having 3, 4, 5 and 6 bits, respectively. Each cell of a memory 601' is read and addressed by a comparator 602' which compares the sample word DP (F,L) which is transmitted from the output of subtractor 41 (Fig.2) to the common digital input 600' of AND read control gates 613, 614, 615, 616, with the predetermined quantization limiting values corresponding to the LEV (F, L) level. The AND gates 613 to 616 are selectively opened by a B detecting circuit 62' which receives B from the bit distributing circuit 3 (Fig.4), via the output connection 360. The detecting circuit 62' compares B with 3, 4, 5 and 6 and, when B-is equal to one of the preceding integers, controls the opening of the corresponding AND gate 613 to 616 via bus 620'. Thus, for each sampled word in DPCM
code to be transmitted, one of cells 601' of the memory 60' transmits, via an OR gate 63', the s-bit LEV(F,L) level number word to the buffer store 68 and the transmitter multiplexing circuit and to the input 70' of the decoder 7'.
The decoder 7' shown in Fig. 9 comprises four AND
- gates 713 to 716, the opening of each of which is controlled by the output bus 620' of the B detecting circuit 62' and four read-only memories 723 to 726. The memories 723 to 726 1 ~ 62642 respectively comprise ~, 16, 32 an(1 6~ memory cells 720', each oE which con-tains the 8-bit DP'(~,L) quantization level value corresponding to the LEV(F,L) level number stored in the cells of the memory 603 to 606 of the encoder 6', respectively. Each memory 723 to 726 is read-controlled by a register 733 to 736 Such register comprises zero-comparators and makes the LEV(F,L) number transmitted by associated AND gate 713 to 716 correspond with the address of associated cell memory 720' with a view to reading the DP'(F,L) content thereof. The DP'(F,L) word corresponding to LEVIF,L) at the input 70' is transmitted, via an out-put OR gate 74', by one of the cells of memories 723 to 726 to the other input of adder 42(Fig.2).
It will be noted that, in accordance with this second embodiment, the encoding device no longer comprises the arithmetic unit 5 and that the preamble allocated to a line is shorter since it no longer includes the D and DMAX words. In other words, the number of available bits NB per line intended for the DPCM encoding of the line - 20 elements is greater than for the first embodiment wherein the encoder ~daptsthe quantization levels as a function of the average number of bits B per element word. Furthermore, the encoding device in this embodiment now comprises only only shift register Rl, the output of which is connected to the input 600' of the PCM encoder 6' via the subtractor 41.
The movement detector 2 calculates Xl and X2 during the reception of a line L in register Rl. Then, during the reception of the next line, L+l, the detector 2 calculates NP and B and the PCM encoder 6' encodes the DP(F,L) words.
In accordance with another embodiment of this invention, still with a view to increasing the average number of bits B per transmitted word, the encoding device receives only one field out of every two at its input I, for example all the even fields. The missing frame field is reconstituted ~ 1 62642 in the decoding dev:lce oE t~le roc~iver by duplicatlan or linear interpolation. In ~his case, the ;Erame stores of the encoding device (Fig.2) and the decoding device (Fig.13) are reduced to field stores, i.e. have a capacity of halE
that of 1 previously described. Moreover the transmitted number of bits N allocated to each line of the field is twice that of the first embodiment, namely in keeping with the afore-mentioned example N = 2x 258 = 516 bits.
Amongst these 516 bits, 54 are allocated to the line preamble and NB = 462 bits are intended for the encoding of the pel words to be transmitted, i.e. to the LEV level words.
For example, for B = 3 bits, 154 LEV(F,L) level words at the most are transmitted for each line. According to -this last embodiment, the encoding device operates as has just been described, except that the lines are processed at the rate of 2 x 7.825 = 15.650 kHz.
Reference will now be made to Figs. 10 and 11 showing a prefered embodiment of the interpolating circuit 8 and the conditional spatial filtering circuit 9 which are interconnected in series between the output 420 of the adder 42 which delivers the element word PC(F,L) = PP(F,L) + DP' (F,L), and the input 13 of the frame store 1, as shown in Fig. 2. The digital value PC(F,L) is substantially equal to P(F,L) transmitted to the input I of the encoding device apart from the corresponding quantization difference in encoder and decoder 6-7 (or 6'-7'), when the pel word P(F,L) has been encoded and selected under the control of bit distributing circuit 3. On the other hand, when the element P(F,L) has been subsampled, i.e. not sampled and encoded in reference, for instance, to the last line of Table III, or belongs to the background areas BAl and BA2 (Fig.l), then the output 420 of the adder 42 provides a word such that PC(F,L) =
PP(F,L). In that case, DP'(F~L) is not calculated in the decoder 7 (or 7') and it becomes neces~ry to find a value approximating to the real incominy value P(F,I.) by llneal interpolatiny and conditional filtering with respect to the transmitted and encoded pel words with a view to storiny it in the frame store 1 for the processing of the lines followiny the previously processed line L.
The linear interpolatlon is perEormed in the interpolating circuit 8. This ma]ces for the reconstitution of the subsamples elements based on the encoded PC(F,L) elements. Since the number of bits allocated -to a line is equal to NB = 231 bi-ts and since the number of bits allocated to each sampled element, i.e. to each transmitted LEV(F,L) level word, is at least equal to 3 bits, the number of encoded elements is equal at the most to NP = 231/3 = 77. If we consider, for instance, only subsamplinys of order 3 at the most, then the videotelephone picture standard should not comprises more than 3 x 77 = 231 visible frame elements.
The standard defined above is the maximum limit for such subsampliny. Naturally, other standards having a number of visible picture elements per line lower than 231 are also possible. If the standard is however defined with a number of visible elements per line higher than 231, then subsampling of an order of 4 or more must be considered. Such subsampling sometimes creates a significant blurring of picture and this i5 why the chosen embodiment is restricted to a subsampling of order 3.
Reporting to Fig. 12, we have shown a sequence of consecutive elements A, B, C, D, E and F of the moving area SA of a line L. Elements such as A, C and F are designated by a cross and are sampled and correspond to the transmission -30 of a LEV(F,L) word at the output of the encoder 6 (or 6').
Elements such as B, D and E are designated by a circle and are subsampled and cause no transmission of LEV(P,L) word, i.e. no transmission of word B through the output 360 of bit distributiny circuit 3 (Figs. 4 and 6). When NP < NB~3, ~,~
lJ~4~
all the line elements ln the S~ area are encoded, the LEV
(F,L) words comprise 3 to 6 ~it~ ancl we have at the output of the interpola-ting circuit 8 : PINT(F,I,) ~ PC(F,L). When NP > NB/3, certain elements are sampled and correspond to 3-bit LEV(F,L) words. In the latter case, when NB/3 < NP
~ 2NB/3, we have merely a order-2 subsampling corresponding to an element such as B, and the interpolation word is:
PINT (F,L) = PC (F,L) (element A) or PINT (F,L) = 12 [(PC-l)(F~L) + (PC+l)(F,L) ~ (element B) and if 2NB/3 < NP < NB, we have a subsampling of at the most order 3, corresponding to elements such as D and E, and the interpolation word is :
PINT (F,L) = PC (F,L) (element A) or PINT (F,L) = 12 [(PC-l)(F,L) + (PC+l)(F,L)~ (element B) or PINT (I,L) = 4l ~3(PC-l~(F,L) + (PC+2)(F,L)~ (element C) or PINT (I,L) = l4 ~(PC-2)(F,L) + 3 (PC+l) (F,L)~(element E) These relations thus make it clear that the inter-polated value PINT (F,L) of a subsampled element depends solely on those of the elements truly put into DPCM code - and not on the predicted values PP(F,L) transmitted by the output 40 of the predictor 4.
As illustrated in Fig. 10, the interpolating circuit 8 comprises a circuit 80 for calculating the four above relations and a circuit 87 for selecting one of these relations in terms of the subsampling type.
The input 800 of the calculating circuit 80 receives the PC(F,L) words in series at a frequency of 1/T
which are transmitted by the output 420 of the adder 42.
The input 800 is connected to four delay lines 811, 812, 813 -and 814 in series, each of which delaies the PC(F,L) word by T . Delay line 812 directly transmits the PC(F,L) word to a reading gate 82A, which is open for an element such as A.
An adder 83B has its inputs connected to the outputs of the , . .
. .
I ~ 62642 delay lines 811 and 813 ~nd h~s :Lts output connected to the input of a reading gate 82B via a divide-by-2 divider 84B~
Consequently, the output of the divider 84B provides PINT
(F,L) as per the interpolation related to the element B.
A second adder 83D has one input directly connected to the input 800 of the interpolating circuit and another input connected to the output of the delay line 833 via a multiply-by-3 multiplier 85D A divide-by-4 divider 84D is connected to the output of adder 83 D and transmits an interpalation word PINT(F,L) relating to an element such as D to an in-put of a reading AND gate 82D. Finally, a third adder 83E
has one input which is connected to the output of the delay line 811, via a multiply-by-3 multiplier 85E~ and has its other input which is connected to the output of the delay line 814. A divide-by-4 divider 84E is connected to the output of the adder 83E and delivers a PINT(F,L) word to the digital input of a reading AND gate 82E as per the inter-polation relation of an element such as E.
The selecting circuit 87 comprises on its input side a three-comparator 870 which receives, via connection 360, B words which are delivered from bit distributing cir-cuit 3 (Fig. 4). It will be recalled that for each B word equal to at least 3 there corresponds to the encoding of an element word to be transmitted by the output of the encoder 6 (or 6') and to the transmission of a DP'(F,L) word from the output of the decoder 7 (or 7') to the adder 42. If a B word is detected, the output 871 of the comparator 870 is in state 1 during time T, corresponding to a sampled element such as A,C or F (Fig.12). If an element is subsampled, no B word is transmitted by the bit distribution circuit 3 and the comparator's output is in state O during T .
Selection circuit 87 further comprises four delay lines 881 to 884 which are connected in series to the output 871 of the comparator 870. The output of the second I ~ 62842 delay l.i.ne 8$2 d:lrec-t~y contro ~1 tl~a ~Ip~ lllg ~,~ y.lte ~2A
~ n~ t-inLJ an il3LdL~pOlatiOn WOL'~ PIN'r(E~ (rr~r..~
corresponding to a sampled element such as A, i.e. eacil t:ime that a B word is received by the comparator 870. An AND gate 89B has -three inputs, one of which is connected to the out-put of the delay line 882 via an inverter 890B and the othcr two of which are directly connected to the outputs oE the delay lines 881 and 883. The output of the AND gate 89B is in state 1 for opening the AND yate 82B which provides a word PINT(F,L)=-2 ((PC-l)(F,L) + (PC+l)(F,L)) each timc two consecutive B words received by the comparator 870 are separated by 2~; this corresponds -to an order-2 subsampled element, such as B. A second AND gate 89D has four inputs, two.of which are directly connected to the outpu-t 871 of the comparator 870 and to the output of the delay line 883, and the other two of which are connected to the outputs of delay lines 881 and 882 via inverters 890D and 890D~ A third AND gate 89E has four inputs, two of which are connected directly to the outputs of delay lines 881 and 884 and the other two of which are connected to the outpu-ts of the delay lines 883 and 883 via two inverters 890E and 890E~ It can be seen that AND gates 89D and 89E are successively open during two consecutive subsamples elements of order 3. Each time that the comparator 870 has detected two consecutive words B separated by 3 T, the AND gate 89D controls the opening of AND gate 82D for transmitting an interpolation word PINT(F,L) = 1 ~3(PC-l)(F,L) + ~PC+2)(F,L)~ corresponding to an element such as D; then, after a time 1, the AND gate 89E controls the opening of.the gate 82E for transmitting an interpolation word PINT(F,L? = l4 C(PC_2)(F,L) + 3(PC+l)(F,L)~
corresponding to an element such as E. An OR gate 820 is connected to the outputs of the AND gates 82A, 82C, 82D and 82E and successively transmits an interpolation word PINT(F,L) at each time T to the input 900 of filtering . - 43 -'-.'~;~ , .
circuit 9.
Condi-tional spatial filterlng clrcuit 9 operates as a low-pass fllter so that the signal reconstituted ln the receiver be freed, after digital to analog converslon, of any spectrum everlap and step contours of the moving picture S on the background B. If the line L ls not sub-jected to a subsampling ~NP < NB/3), the filterlng circuit 9 directly delivers the word P'(F,L) = PINT(F,L) to the input 13 of frame store 1 for each of NP elements of the line L. On the other hand, if the line is subsampled, -then filtering circuit 9 transmits P'(F,L) = 1 ((PINT-l)(F,L) +
2 PINT(F,L) + (PINT + l)(F,L)) for an order -2 subsampling (NB/3 < NP ~ 2NB/3), and P'(F,L) = 2 ((PINT-l)(F,L) +
(PINT+l)(F,L)) for order -3 subsampling (2NB/3 < NP ~ NB) to the input 13 of frame store 1 for each of NP elements of the line L.
The conditional spatial filtering circuit 9 shown in Fig. 10 essentially comprises a calculating circuit 90 for carrying out the three above filtering relations and a selecting circuit 95 for selecting the filtering depending on the three relations.
The input 900 of the calculating circuit 90 receives in series at a rate of 1/T~ the PINT(F,L) inter-polation words which are transmitted from the output OR
gate 820 of the interpolating circuit 8. The input 900 is connected to two delay lines 911 and 912 in series and to one input of an adder 923. The output of the delay line 911 delivers P'(F,L) directly to the digital input of a reading AND gate 94, which is related to a line not sub-sampled, and to one of the inputs of an adder 922. The adder 923 has its other input connected to the delay line 912 and transmits P'(F,L) as per the relation for order-3 subsampling to the digital input of a reading AND gate 943, via a divide-by-2 divider 933. The adder 922 has its other ~ ~ 62642 input conn~c~ed to the output c~ the dlvlder 933 and sup-plies P'~F,L) as per the relation for order -2 subsampling to an input of a reading AND gate 942 via a divide-by-2 divider 932 Opening of the AND gates 941 to 943 is selectively controlled by the three outputs of the filtering selecting circuit 95.
On its input 950 side, the selecting circui-t 95 comprises two comparators 951 and 952 which receive, at the start of encoding of each line, the number of elements NP
of the picture area SA which is delivered by the register 285 of the movement detector 2(Fig. 3). The comparator 951 compares NP with NB/3 and sets its output to the state 1 when NP > NB13. The comparator 952 compares NP with 2NB/~ and set its output to the state 1 when NP > 2NB/3.
When NP < NB/3, the output of the comparator 951 is in state 0 and controls the opening of the AND gate 941 via an inverter 961, which corresponds to a not subsampled line L.
An AND gate 97 has one input connected directly to the input of the comparator 951 and another input connected, via an inverter 962, to the input of the comparator 952. When NB13 < NP < 2NB/3 is satisfied, the output of the AND gate 97 is in state 1 and controls the opening of the AND gate 942 related to the filtering of an order-2 subsampled line.
Lastly, then NP > 2NB/3, the output of the comparator 952 is in state 1 and directly controls the opening of the AND
gate 943 related to the filtering of an order -3 subsampled line. The output of one of reading AND gates 941~ 942 and 943 transmits in series, via an OR gate 98, the sequence of the NP suitable filtering P'(F,L) words of the processed line L to the input 13 of the frame store 1 in order to store them. The other element words related to background areas BAl and/or BA2, if present, are not modified in frame store 1, the latter being writing controlled by means (not shown) solely during the transmission of the width X2 - X
~1 1 62642 of each line's mov~ng areLI SA.
The decod~ng device at the receiver is shown in block form in Fig. 13. I-t performs the same operations of bit distribution, decoding, prediction, interpolation and filtering as those carried out in the encoding device in the transmitter.
After demultlplexing the date transmitted along the 2.048 Mbits/s digital ]ink TNi the input bus of the encoding device receives the line preamble words such as Xl, X2, DMAX-D, D and possibly PW and the LEV (F,L) data words which represent elements encoded by the distant speaker's transmitter encoding device. All the operations required for calculating the decoding parameters for the words of level LEV(F,L.) are performed during the time interval pre-ceding the video signal and peculiar to the reconstitution of the line synchronizing signal. We would recall that all the line synchronizing and blanking signals and field syn-chronizing and blanking signal reconstituting circuits, as well as the time base transmitting the monitoring signals specific to the decoding, will not be described in detail.
It will be noted that the blocks in Fig. 13 designated by the number references carrying the index rare identical to the blocks with the same reference numbers in the transmitter.
The Xl and X2 coordinate words indicating the start Ml and end M2 of SA area of the L line are applied to the inputs 281r and 282r of an arithmetic unit 28r; the Xl word is also delivered to the down- counting input of a down-counter 28r of a bit distributing circuit 3r Arithmetic unit 28r,as does the circuit 28 in the movement detector 2, calculates the average bit number B which has been allocated to each LEV(F,L) word and the element number NP of moving area SA of the line L. Its register 289r delivers B to the digital input of the AND gate 36r f a bit distributing circuit I J 626~2 3r which is analo~ous to circuit 3 in Fig. 4~ and 1-ts register 285r delivers NP to the triggering input of the down-counter 32r and to one of the inputs of the multiply-by-NP multiplier 33r of the bit distributing circuit 3r and to the input 950r of a conditional spatial filtering circuit 9r which is analogous to the circuit 9 in Fig. 11. As in the transmitters, the bit distributing circuit 3r transmits the word B at its output bus 360r each time an element is sampled, i.e. at the most NPmaX = 77 times per line. This transmission of words B takes place right from the start of the visible portion of the line to be reconstituted. Each word B is delivered, via bus 360r~ to three comparator 870r of a linear interpolating circuit 8r which is analogous to the circuit 8 in Fig. 10, and to the common input 601r of a B detecting circuit 62r and an arithmetic unit 63r which are analogous to 62 and 63 of the PCM encoder 6 shown in Fig. 6, respectively.
The output of the unit 63r delivers the coefficients as a function of NQ = 2B such as NQ/4, NQ/4-1, NQ/2-1, 3NQ/4 and 3NQ/4-1 to the appropriate inputs of a PCM decoder 7r which is analogous to the decoder 7 in Fig. 7.
In view of the fact that the LEV(F,L) words are conveyed in series on the 2.048 Mbit/s digital Link TNl, a buffer store 68r is provided for with a capacity NPmaX = NB/3.
In the store 68r, the bits of the LEV(F,L) words are written at the frequency of 2.048 Mbits/s and each LEV/(F,L) word is read during a time ~ under the control of reading signal 621 which is delivered from the B detecting circuit 62r.-The read words LEV(F,L) are applied to the input 70p of the decoder 7p and correspond solely to the sampled elements such as A,C and F shown in Fig. 12. The D and DMAX-D
words of the line preamble are supplied by the demultiplexing circuit of the receiver, are also stored in two buffer registers 57r and 59r in response to the detection of the line L preamble and are transmitted under the control of reading ,~ .
signal 621 at the appropriat~ :I.npu-ts o~ the decoder 7r~ vla bus-bars 570r and 590r. The decoder 7r calculates a quantization level DP'tF,L) each time its input 70r receives a level word LEV(F,L).
Next, as in the transmi-tter encoding device, DP'(I,L) is added in an adder 42r to the corresponding pre-dicted word PP(F,L) which is provided from the output 40r of a linear predictor 4r analogous to the prediction 4 of the encoding device. The predictor 4r may receive a pre-diction indicating word PW at its input 43r through the demultiplexing circuit, a word which was included in the line preamble. It will be noted that, as in the encoding device, the predicted words PP(FrL) are established from quantization levels which are calculated in the encoder 6 (Fig. 6) and are selected under the control of analogous bit distributing circuits 3 (Fig.4) and 3r The output 420r of the adder 42r provides the decoded words PC(F,L) =
PP(F,L) + DP'(F,L) at the input 800r of the linear inter-polating circuit 8r. Following this, after interpolation in terms of the subsampling order, the output OR gate 820 of the circuit 8r delivers PINT(F,L) to the input 900r f the conditional spatial filtering circuit 9r' the output OR
gate 98r of which supplies P'(I,L) to the input 13r f the frame store lp of the encoding device. The output llp of store lr transmits the element words P'(F,L) for the calcul-ation of the predicted word PP(F,L) at the 1/T rate as per one of the four predicted relations 1 to 4, to the input 44r of the predictor 4r The reading output 14 of the frame store lr also transmits.in series the P'(F,L) words at the frequency 1/T to the video means (screen) of the video-telephone after a digital-to-analog conversion.
It will be noted that, in the case of the second embodiment (Figs. 8 and 9) of the encoding device related to the quantization levels that are static but nevertheless .--,ji, ~ .
.
- .~
selectecl a5 a ~lnctiorl of the l~v~raC~e ~I.L: numl~cr 1~ all-.Jca~ed to an LEV(F,I,) word, the decocl.i.n~ clevice doe6 nol. comprise an arithmetic Ullit 63r and buffer reyis-ters 57r and 59r and has its PCM decoder which is analogous to that illus-trated in Fig. 9. According to the emhodiment relative to an available number of bits NB equal to 462 and to encodiny of one field out oE two, the store lr Of the decoding device is a field store which has a capacity reduced by half. On the video side, the output of this field store is connected to a missing-field duplicating or reconstituting circuit.
Although the invention has been described in reference to a particular videotelephonic standard, it will be appreciated that other embodiments using the invention are possible. It may provide encoding and decoding devices for other incoming and outcoming digital ra-~es which present ratios higher or lower than 8, and for incoming element word formats different from 8. Furthermore, the digital -transmis-sion medium can convey other secondary data signals, such as telecopier channel for instance. Generally speaking, the subsampling order can be greater than 3 and the number of bits N allocated to a frame line can be of any value, but defined however depending on the incoming and outgoing digital bit rates. The data contained in the preamble of each line are such that they suffice for allowing suitable decoding at the receiver. According to the first embodiment, they may further include Xl, X2; Xl,X2-Xl; B, NP ; or NQ, NP for example.
Moreover, the videotelephone signal may be a digital signal which is representative of monochromatic black and white pictures or a digital component signal representative of a chromatic or luminance component of a colour video signal. In the latter case, three encoding and decoding systems are provided in parallel.
P(F,L) - PP(F,L) to the input 600 oE the encoder 6.
The encoder 6 of the encoding device quantizes the digital differential signal DP(F,L) with respect to a number of quantization levels NQ which depends upon the number of bits B allocated to each sampled element of a common line L by the bit distributing circuit 3. In fact, the encoding from the encoder 6 is established on the absolute value ¦DP (F,L)¦ , where the values corresponding to DP (F,L) < O are obtained by symmetry. The quantization levels are distributed, as shown below, right across the variation range of the incoming differential signal DP(F,L) for the moving area SA of a line L.
The maximal and average values of the incoming differential signal DP (F,L) for a line L are designated by DMAX (L) and D (L) such that:
DMAX(L) = Max ¦P(F,L) - PP (F,L)¦
Ml < P < M2 1 ~ 626~2 ~= M2 D(L) = 1 ~ ¦P(F,L) - PP (F,L)¦
P=M
For the quantization level number NQ = 2B, the encoder 6 equidistributes the levels half and half over the ~-D,~D] range and r-DMAX,-D tand~ D, DMAX] ranges. Encoding such as this obviates encoder overflow, which is a phenomenon producing drag and visible pin-poin.t flaws.
-It can thus be seen from the foregoing that encoding any element selected by the bit distributing circuit 3 calls for prior knowledge, on the one hand, of Xl and X2 and, on the other hand, of DMAX and D. DMAX and D are consequently caIculated before encoding in the .encoder 6 but after calculation of coordinates Xl and X2, since this calculation depends on the latter. The time required for processing a line is at the most 1/7.825 kHz =
128 ~s and does not permit the successive calculations of Xl and X2 then D and DMAX followed by the encoding.
The various operations preceding the encoding of the line L are carried out simultaneously with the respective encoding of the preceding lines, L-2 and L-l, as indicated in the following table IV:
. .
'~'ABLE, LV
Calculation o~ Xl,X, Ca:lcula-tion oE NP ~it d.l,tr:Lbutlon in 2 ~Fig 3) and ~ in 2 (FicJ.3) :Ln 3 and encod:i.ng-. . and calcula-tlon of decoding in 6,7 D and DMAX in 5 and 8 (Figs.6,7 (Fig.5) and 8) . .
Register R1 Register R2 Line L Line L - 1 Line L - 2 Line L + 1 Line L Line L - 1 Line L + 2 ~ Line L + 1 Llne L
With reference to Fig. 5, the arithmetic unit 5 .15 firstly comprises a circuit 50 for calculating a predicted value PP' (F,L~ close to the real predicted value PP (F,L) which is transmitted by the output 40 of the predictor 4.
Indeed, in the event of an intraframe prediction taking into account, for example, the previous element (P-l)(F,L) (preceding predictions 2, 3 and 4), this element can not be provided by the frame store 1, since it is obtained af-ter encoding in the encoder 6 and decoder 7 and interpolating in the circuit 8. These operations follow the calculation of D and DMAX. If such a prediction is selected, the value - (P-l)'(F,L) is substituted to the real value (P-l)(F,L) which is transmitted from the output of the first shift . register Rl via a delay circuit 500 to an input of a pre-dicting circuit 501 included in the unit 5. Should the prediction be based on the elements P(F,L-l) and (P+l) (F,L-l) of the previous line (L-l) (preceding predictions 2 and 4), then the evaluation of these values is also based on the values received to the input I of the encoding device. Indeed, one the value P(F,L) has been transmitted by the output of the register Rl, the recorded value P'(F,L-l) . - 25 -~r . ~ .
.. ~ ~ . .
i J 6~642 to be s-tored in the frame store 1 Joes under evaluat~on in encoder and decoder 6-7 or in -the lnterpola-tlng clrcult 8, and the value (P+l)'(F,L-1) correspondlng to the value (P~
(F,L-l) after encoding or lnterpolating will not yet have been transmitted by the output of the register R2. It follows that, for such predictions, consideration is taken of the real values P(F,L-l) and (P+l)(F,L-l) transmitted from the last and first-to-last stages of the register R2 to two inputs of the predicting circuit 501 respectively.
Finally, when the prediction is founded on an elemen-t such as (P-I)(F,L-l) (intra-frame prediction 3) or an element such as P(F-l,L) (inter-frame prediction 1), then the cor-responding values (P-l)'(F,L-l) and P'(F-l,L) obtained after encoding or interpolating are already stored in the frame store 1. These values are transmitted to two other inputs of the predicting circuit 501 from the output 12 of the frame store 1 simultaneously with the transmission of P(F,L) from the output of the register Rl. To recapitulate, the predicted pel word PP'(F,L) delivered from the output of the predicting 501, which is analagous to the predictor 4, is given by the following relations in comparison with the four above prediction:
1) PP'(F,L) = P'(F-l,L) equal to PP(F,L) 2) PP'(F,L) = /P-l)(F,L) different from PP(F,L) 5 3) PP'(F,L) = (P-l)(F,L) + P(F,L-l) - (P-l)'(F,L-l) different from PP(F,L) 4) PP'(F,L) = ((P-l)(F,L) + (P + l)(F,L-l)~ ~ 2 different from PP(F,L) The different predictions are selected by the detection of the PW word which is delivered from the output 43 of the predictor 4 to the predicting circuit 501.
In the arithmetic unit 5, after the de-tection of the synchronizing signal related to the line L+l, two down-counters 51 and 52 are decremented by unity at every period I J fi26~2 ~ ln time. The counts oE th~se down-counters are lnitially set beforehand to the Xl and X2 values whlch are transmitted to their inputs 510r 520 from the registers 275 and 276 via reading AND gates 281 and 282 (Fig. 3). As long as the count in the down~counter 51 is not zero, its outpu-t 511 remains in state 'o'' and closes AND gates 502, 503, 50~, 505 and 506 via an AND gate 507. These gates 502 to 506 are intended for transmittin~ the respective values P(F,L) from ~he out-put of the register Rl, (P-l)(F,L) from the output of delay line 500, (P+l)(F,L-l) from the last-but-one stage of the register R2, P(F,L-l) from the last stage or output of the register R2 and P' (F-l'L) and (P-l)'(F,L-l) from the output 12 of the frame store 1 to the predicting circuit 501 when the outputs 511, 521 of the down-counters 51, 52 are in state 1 , via AND gate 507. The count in the down-counter 51 is then equal to zero after the transmission of pel word representative of the element Ml from the output of the register Rl and the count in the down-counter 52 is less than or equal to X2. The predicting circuit S01 therefore delivers the predicted words PP' (F,L) which correspond to all the elements lying between Ml and M2 of each line L.
The predicted value PP' (F,L) iS applied to one of the inputs of a subtractor 53, the other input of which receives the real value P(F,L) from the output of the AND
gate 502. The absolute value ¦ P(F,L)-PP'(F,L) ¦is trans-mitted by the subtractor 53 to be added in an accumulator 55 to the sum of the absolute values which are previously calculated for the elements Ml to P-l. The absolute value ¦P(F,L) - PP'(F,L)¦ iS also compared in a comparator 56 with the value of the previously-received absolute values.
When the count in the down-counter 52 is equal to zero, which corresponds to the transmission of the element as per the element M2 by the output of the register Rl, the output 521 of this down-counter opens two AND gates 550 1 ~ 62642 and 560 via an lnver-ter 522 whlch dellver the following values:
P = M2 D x NP =) ¦P (F L) PP (F L) ¦
P = Ml DMAX = Max ¦P(F,L) - PP' (F,L)¦
Ml < p < M2 The average value D is obtained by a divide-by-NP
divider 551 which is connected to the output of the AND gate - 550 and receiues NP from the register 285 of the movement detector 2 (Fig.3). This average value D is stored into a memory 57, read during the encoding of the present line L, and is transmitted to the inverse input (-) of a sub-tractor 58 which receives the value DMAX from the AND gate 560 through its direct input (+). The subtractor 58 delivers DMAX-D to a memory 59l also read during the encoding of the line L. The accumulator 55 and comparator 56 are then automatically reset to zero.
The output 61 of the encoder 6 shown in Fig. 6 transmits a B-blt binary coded word LEV(F,L) representing the quantization number out-of NQ=2B levels, each time the bit distributing circuit 3 delivers on the output 360 of the AND gate 36 (Fig.4) the word B which indicates the average number of bits to be allocated to a sample word DP(F,L) transmitted by the subtractor 41 (Fig.2). The word B is transmitted to common input 601 of a B word detecting circuit 62 and an arithmetic unit 63. The circuit 62 can be, for example, a 3-comparator which delivers a 1 at its output each time it detects a word such that B ~ 3.
In this case, it opens a writing AND gate 620 of the encoder 6 and a writing AND gate 720 of the decoder 7 (Fig.7) so as to select the DP(F,L) samples in 8-bit DPCM code which . . .
.
i J 62642 are delivered to khe digital input of the AND gate 620 from the subtractor 41. The DP(F,L) words corresponding to B=O, as indicated in the last line of table III for example, are subsampled, i.e. are not transmitted by closing AND gate 620 and correspond to P'(F,L) pel words which are deduced by interpolation in the circuit 8, as will be seen in reference to Fig. 10. The arithmetic unit 63 comprises a calculation mo~ule 630 which performs the operation NQ=2B, a divide-by-2 divider 631, a divide-by-4 divider 632, an adder 633 and subtractors 63~, 635, 636, SO as to produce the numbers NQ/2, NQ/2-1, MQ/4, NQ/4-1, 3NQ/4 and 3NQ/4-1 at its six outputs. These integer numbers serve in the calculation of LEV (F,L) in the encoder 6 and of the sample word after decoding DP~ (F,L) in the decoder 7.
AS already stated, the NQ levels are equidistributed half and half into the interval L-Dr +D~ and the double-interval [-DMAX, -D L~] D, DMAX~. The level number NQ
is therefore adapted by the encoder 6 to the available bit number NB per line in terms of the numbers of elements NP
in the SA area of the line L.
A11 the logic operations in the encoder and decoder are carried-out with 8-bit words and the output words LEV(F,L) of the encoder have B bits for each line respectively, with B which is greater than or equal to a first predetermined number equal to 3 and which is less than or equal to a second predetermined number equal to 6.
For each sampled element, these operations last less than a time T .
We have assumed for the embodiment of the encoder and decoder illustrated in Figs. 6 and 7, that the numbers of levels are in an increasing order from O to NQ-1 for the levels increasing from -DMAX to DMAX and the encoding level DP'(F,L) of a sample DP(F,L) is equal to the middle quan-tization level of the quantization range to which DP (F,L~
1 ~ B264 2 belongs. O~ course, other level distxibutlons and numberlng can be chosen, provided the decoders at the transmi-tter and receiver be respectively identical.
In keeping with the above example, the following relations give, for the three equidistribution intervals of the levels, the level number LEV(F,L) as a function oE the sample DP(F,L) in DPCM code and the value of the corresponding sample DP'(F,L) in DPCM code after quantization as a function of LEV (F,L) ; SGN designates the sign of DP(F,L), i.e. +l when DP > O and -1 when DP < O and the divisionsare whole.
NQ
a) when -D < DP ~ D then 4 < LEV < 3 NQ/4 LEV = [(DP x NQ x l)+ SGN] 1 + NQ
DP' = (LEV - (NQ/2 - 1 3) x 4 x D
NQ
b) when DP > D > O then 3 Q < LEV < NQ
LEV = ((DP - D) X Q x + SGN) 2 + 3NQ - 1 DP' = (( LEV+3NQ/4 - 1)) x 4Q x (DMAX-D)) + D
c) when DP <-D < O then ~ LEV < 4Q
LEV = ((DP + D) x NQ x 1 + SGN) 1 ~ NQ _ 1 2 _ 2 4 DP' = ((LEV - (NQ/4 - 1)) x NQ x (DMAX - D)) - D
The following tables V and VI indicate the quanti-zation numbers and the corresponding sample values, LEV and DP', which have been calculated as per the above relations ..
1 ~ 626~2 for values oE B such th~t B - 3 ~nd B = 4.
DP LEV DP' ~(D + 3DMAX)/4, DMAX~ 7 DMAX
~3D + DMAX)/4, (D + 3DMAX)/4~ 6 (DMAX ~ D)/2 L3D/4, (3D + DMAX/4L 5 D
LD/4, 3D/4 L 4 D/2 J ~D/4, D/4 r 3 O
-3D/4, -D/4~ 2 -D/2 r( 3D - Dl~AX)/4, -3D/41 1 _ ~-DMAX, (-3D - DMAX)/4~ -(DMAX+D) :
TABLE VI (B = 4, NQ = 16) DP LEV DP' _ [(D+7DMAX)/8, DMA,~J 15 D~X
~3D+5DMAX/8, (D+7DMAX)/8 L 14 lD+3DMAX)/4 ~5D+3DMAX)/8, (3D~5DMAX)/8~ 13 (D+DMAX)/2 t(7D+DMAX)/8, (5D+3DMAX)/8 r. 12 (3D+DMAX)/4 r;7D/8, (7D+DMAX)/8~ 11 D
L5D/8, 7D/8~ 10 3D/4 L3D/8, 5D/8~ 9 D/2 CD/8, 3D/8~ 8 D/4 -D/8, D/8~ 7 O
-3D/8, D/81 6 ~/4 -5D/8, -3D/8~ 5 -D/2 -7D/8, -5D~8~ 4 -3D/4 -~p/DMA~/8, - 7D/8~ 3 D
-~5D+3DMAX)/8, -(7D+DMAX)/8~ 2 -(3D+DMAX)/4 -(3D+5DMAX)/8, -(5D+3DMAX)/8~ 1 -(D+DMAX)/2 L -DMAX, -(3D+5DMAX)/8~ O -(D+3DMAX)/4 . _ . ~.
... . .
1 1 626~2 As shown ln Fig. 6, the encoder 6 comprises a main channel, the logic circuits of which are common to the LEV(F,L) calculations in the three above cases a,b,c, and are interlinked as per the order of the LEV(F,L) calculation operations. These logic circuits deal first of all with the distinction of the three cases, then a subtraction of DP(F,L), if required, and a multiplication by NQ/2, the division by D of (DMAX-D) followed by the addition of SGN
and the division by 2, and finally, if necessary, an addition of a factor such as NQ/2-1, 3NQ/4-1 or NQ/4-1. The sign SGN of DP~F,L) is obtained from the following operations on the DP(F,L) sign bit which is O when positive, and 1 when negative: negation in 621, multiplication by 2 in 622 and subtraction of unity in 623. The circuit assemblies performing the latter four operations are represented by the numbering prefixes 64, 65, 66 and 67j in Fig. 6, respectively. The arithmetic unit 63 delivers NQ/2 to the input of a multiplier 651 of the encoder, NQ/2-1 to an input of an AND gate 67a of the encoder and an input of an AND gate 75a of the-decoder, NQ/4 to the inverse input (-) of a subtractor 740 of the decoder and to an input of a divider 752 of the decoder, NQ/4-1 to the digital input of an AND gate 67c of the encoder and to the digital input of an AND gate 75c of the decoder, 3NQ/4 to the inverse input (-) of a subtractor 741 of the decoder, 3NQ/4-1 to the digital input of an AND gate 67b of the encoder and to the digital input of an AND gate 75b of the decoder. Memories 57 and 59 of the arithmetic unit 5 (Fig.5) are read at the rate of 1/T after the detection of the synchronizing signal related to the L+2 line. The memory 57 delivers, via link 570, the avera~e value D of the DP(F,L) samples to the in-verse input (-) of a subtractor 640, to an input of an adder 641 and to the digital input of an AND gate 66a of encoder 6 and to the respective digital inputs of AND gates 76a, , 77b and 77c oE decocler 7 (l'lg./). Th~ ~ND ga~e 77c receives in fact -D by means oE a unity subtrac~or 770.
The memory 59 delivers, via link 590, the difference DM~X-D
to the digital input of an AND gate 66bc of the encoder and to the digital input of an AND gate 76bcof the decoder.
The logic circuit 64 distinguishes between -the three cases a), b), c). It comprises the subtractor 640 and adder 641 which have their other inputs connec-ted to the output of the writing AND gate 620, and two zero comparators 642 and 643 which have their respective inputs receiving DP(F,L)-D from the subtractor 640 and DP(F,L)+D from the adder 641. The outputs of the AND gate 620, subtractor 640 and adder 641 are also connected to the digital inputs of AND gates 65a, 65b and 65c, respectively. When DP(F,L)-D > O
(case b), then the output of the comparator 642 is in state 1 and when DP(F,L)+D > O (cases a and b), then the output of the comparator 643 is in state 1 . These two output signals are combined by means of AND gates 64a, 64b and 64c to control the various calculation operations of LEV(F,L) as per cases a, b and c. The control AND gate 64a has its respective inputs connected to the output of the comparator 642 through an inverter 644 and directly to the output of the comparator 643, and has its output connected to the control inputs of the AND gates 65a, 66a and 67a. The control AND gate 64b has its inputs connected directly to the outputs of the comparators 642 and 643 and its output controlling the opening of the AND gates 65b and 67b and that of the AND gate 66bc via an OR gate 660. The last con-trol AND gate 64c has its respective inputs connected to the outputs of the comparators 642 and 643 via inverters 644 and 645 and controls the opening of the AND gates 65c and 67c and that of the AND gate 66bc via the OR gate 660.
The difference of DP(F,L) with the zero value or D, or the addition of DP(F,L) to D is transmitted in the cixcuit 65, via an ~R gate 650 connec-ted to the outputs of the AND gates 65a, 65b and 65c, to the other input of NQ/2 multiplier 651. The division of the word outgoing of the multiplier 651 by D or (DMAX-D) is performed in a divider 661 whose other input is connected via an OR gate 622 to the outputs o AND gates 66a and 66bc. The result of the above division i5 added to SGN in an adder 663 and is then divided by in a divider 664. The divider 664 is interconnected between the output of the adder 663 and one of the inputs of an adder 670. The outputs of AND gates 67a, 67b and 67c are connected via an OR gate 671 to the other input of the adder 670 such that this adder 670 adds the last term NQ/2-1, 3NQ/4-1 and NQ/4-1 depending on the cases a, b, and c. The output of adder 670, common to output 61 of the encoder, transmits the level number LEV(F,L) in B-bit pure binary code to input 70 of the decoder 7(Fig.7) and via a buffer store 68 to an input of the transmitter multiplexing circuit (Fig.2). The buffer store 68 makes it possible to adapt the 17.778 Mbits/s incoming digital rate to the 2.048 Mbits/s outgoing one. With this in mind, the LEV (F,L) words delivered from the output 61 are written under the control of B detecting circuit 62 and are read at 2.068 MHz frequency. The capacity of store 68 is equal t max Referring now to Fig. 7, the decoder 7 comprises a main-channel, the logic circuits of which 74, 75, 76 and 77 are common to the calculations of DP'(F,L) as per the three cases a, b and c. These logic circuits follow one after the other in the order of the basic operations in the relations given earlier on.
The circuit 74 relates to the distinction of the three cases. It comprises the subtractors 740 and 741 and two zero-comparators 742 and 743 whose inputs are connected to the outputs of the subtractors 740 and 741,respectively.
The direct :inp~l-ts (~) o~ ~he s~l~stractor 740 and 741, as well as that of a substractor 750 are connected to -the out-put of the wrlting AND gate 720, digital input 70 of which receives the LEV(F,L) word under the control of the outpu-t signal from B word detecting circuit 62 (Fig.6). When NIV > NQ/4 (case a), the output of the comparator 742 is in state 1 . When LEV > 3NQ/4 (case b), output 74b oE the comparator 743 is in state 1 . The inputs of a first AND
gate 74a which controls the calculation of DP'(F,L) according to the case a, are connected directly to the output of the comparator 742 and, via an inverter 744, to the output of the comparator 743. The output of the AND gate 74a is con-nected to the control inputs of the AND gates 75a and 76a and to that of an AND gate 77a whose digital input receives to zero-value. The calculation of DP'(F,L) according to the case b is controlled directly by output 74b of the comparator 743 which is connected to the control inputs of the AND gates 75b and 77b and, via an OR gate 760, to that of the AND gate 76bc. Finally, the calculation of DP'(F,L) as per case c, is controlled by an inverter74c, the input of which is connected to the output of the zero-comparator 742. The output of the inverter 74c is connected to the control inputs of the AND
gates 75c and 77c and, via OR gate 760, to the AND gate 76bc.
The difference of LEV (F,L) with the number NQ/2-1, 3NQ/4-1 or NQ/4-1 is obtained by the subtractor 750, the inverse input (-) of which is connected, via an OR gate 751, to the outputs of the AND gates 75a, 75b and 75c. The above difference is divided by NQ/4 in the divider 752 which is interconnected between the output of the subtractor 750 and an input of a multiplier 760. This multiplier 760 multiplies by D or (DAMX-D) which is transmitted to its other input by the outputs of the AND gates 76a and 76bc, via an OR gate 761. The result of the muItiplication is transmitted to an input of an adder 771. The other input of the adder 771 ,~i~, I Jfi2642 receives -the value O, D or -D ~-hroucJh th~ outputs of the gates 77a, 77b and 77c via an OR gate 772. The output of the adder 771 is common to that 71 of the decoder 7 and transmits the 8-bit DP'(F,L) word to the other input of adder 42, shown in Fig. 2. The adder 42 adds DP'~F,L) to the element word PP(F,L) predicted by the predictor 4 in order to transmit PC (F,L) = PP(F,L) ~ DP'(F,L), which differs little from P(F,L) for a sampled element (DP' ~ O) or is equal to PP(F,L) for a subsampled element (DP' = O), in the direction of the input 13 of the frame store 1, after interpolation and filtering (Fig.2). This sample value PC(F,L) is so obtained after decoding and is recorded in the frame store 1 so as to establish the predicted samples of the following line and/or following frame.
The description of Fig. 6 brings to light the fact that the encoder 6 adapts the bit number of the LEV(F,L) word representing the sample to the ratio B = NB/NP cal-culated in movement detector 2 (Fig.3). This number B
lies between 3 and 6. The multiplexing circuit in the trans-mitter, upon detection of the synchronizing signal of the L+2 line, multiplexes the words contained in the 27-bit pre-amble allocated to the line, which are:
- Xl(Ml) and X2(M2) delivered from the registers 275 and 276 (Fig.3), - D and DMAX-D delivered from the memories 57 and 59 (Fig.5), and - possibly the prediction word PW delivered from the output 43 of the predictor 4 (Fig.2) when the predictor is adaptive.
Then, after detection of the line (L+2) synchronizing signal corresponding to the start of line L sample encoding, the multiplexing circuit receives the sequence of LEV(F,L) words following the preamble via the output 61 of the encoder 6 which, via the buffer memory 68, are read at a bit-rate of ,, ;f . , ~ .
1 J 626~ 2 2.048 Mbits/s.
In accordance with A second embodiment, the quantization level number LEV(F,L) and the DP' (F,L) values for each distribution of pel words represented by the value of s charac.terizing the moving area SA of a line L are fixed, namely have been recorded beforehand in two blocks of read-only memories.
The encoder 6' according to this second embodiment is illustrated in Fig. 8. It comprises for instance four read-only memories 603, 604, 605 and 606. These memories comprise 8,16, 32 and 64 memory cells, respectively, which each stores a quantization level number LEV having 3, 4, 5 and 6 bits, respectively. Each cell of a memory 601' is read and addressed by a comparator 602' which compares the sample word DP (F,L) which is transmitted from the output of subtractor 41 (Fig.2) to the common digital input 600' of AND read control gates 613, 614, 615, 616, with the predetermined quantization limiting values corresponding to the LEV (F, L) level. The AND gates 613 to 616 are selectively opened by a B detecting circuit 62' which receives B from the bit distributing circuit 3 (Fig.4), via the output connection 360. The detecting circuit 62' compares B with 3, 4, 5 and 6 and, when B-is equal to one of the preceding integers, controls the opening of the corresponding AND gate 613 to 616 via bus 620'. Thus, for each sampled word in DPCM
code to be transmitted, one of cells 601' of the memory 60' transmits, via an OR gate 63', the s-bit LEV(F,L) level number word to the buffer store 68 and the transmitter multiplexing circuit and to the input 70' of the decoder 7'.
The decoder 7' shown in Fig. 9 comprises four AND
- gates 713 to 716, the opening of each of which is controlled by the output bus 620' of the B detecting circuit 62' and four read-only memories 723 to 726. The memories 723 to 726 1 ~ 62642 respectively comprise ~, 16, 32 an(1 6~ memory cells 720', each oE which con-tains the 8-bit DP'(~,L) quantization level value corresponding to the LEV(F,L) level number stored in the cells of the memory 603 to 606 of the encoder 6', respectively. Each memory 723 to 726 is read-controlled by a register 733 to 736 Such register comprises zero-comparators and makes the LEV(F,L) number transmitted by associated AND gate 713 to 716 correspond with the address of associated cell memory 720' with a view to reading the DP'(F,L) content thereof. The DP'(F,L) word corresponding to LEVIF,L) at the input 70' is transmitted, via an out-put OR gate 74', by one of the cells of memories 723 to 726 to the other input of adder 42(Fig.2).
It will be noted that, in accordance with this second embodiment, the encoding device no longer comprises the arithmetic unit 5 and that the preamble allocated to a line is shorter since it no longer includes the D and DMAX words. In other words, the number of available bits NB per line intended for the DPCM encoding of the line - 20 elements is greater than for the first embodiment wherein the encoder ~daptsthe quantization levels as a function of the average number of bits B per element word. Furthermore, the encoding device in this embodiment now comprises only only shift register Rl, the output of which is connected to the input 600' of the PCM encoder 6' via the subtractor 41.
The movement detector 2 calculates Xl and X2 during the reception of a line L in register Rl. Then, during the reception of the next line, L+l, the detector 2 calculates NP and B and the PCM encoder 6' encodes the DP(F,L) words.
In accordance with another embodiment of this invention, still with a view to increasing the average number of bits B per transmitted word, the encoding device receives only one field out of every two at its input I, for example all the even fields. The missing frame field is reconstituted ~ 1 62642 in the decoding dev:lce oE t~le roc~iver by duplicatlan or linear interpolation. In ~his case, the ;Erame stores of the encoding device (Fig.2) and the decoding device (Fig.13) are reduced to field stores, i.e. have a capacity of halE
that of 1 previously described. Moreover the transmitted number of bits N allocated to each line of the field is twice that of the first embodiment, namely in keeping with the afore-mentioned example N = 2x 258 = 516 bits.
Amongst these 516 bits, 54 are allocated to the line preamble and NB = 462 bits are intended for the encoding of the pel words to be transmitted, i.e. to the LEV level words.
For example, for B = 3 bits, 154 LEV(F,L) level words at the most are transmitted for each line. According to -this last embodiment, the encoding device operates as has just been described, except that the lines are processed at the rate of 2 x 7.825 = 15.650 kHz.
Reference will now be made to Figs. 10 and 11 showing a prefered embodiment of the interpolating circuit 8 and the conditional spatial filtering circuit 9 which are interconnected in series between the output 420 of the adder 42 which delivers the element word PC(F,L) = PP(F,L) + DP' (F,L), and the input 13 of the frame store 1, as shown in Fig. 2. The digital value PC(F,L) is substantially equal to P(F,L) transmitted to the input I of the encoding device apart from the corresponding quantization difference in encoder and decoder 6-7 (or 6'-7'), when the pel word P(F,L) has been encoded and selected under the control of bit distributing circuit 3. On the other hand, when the element P(F,L) has been subsampled, i.e. not sampled and encoded in reference, for instance, to the last line of Table III, or belongs to the background areas BAl and BA2 (Fig.l), then the output 420 of the adder 42 provides a word such that PC(F,L) =
PP(F,L). In that case, DP'(F~L) is not calculated in the decoder 7 (or 7') and it becomes neces~ry to find a value approximating to the real incominy value P(F,I.) by llneal interpolatiny and conditional filtering with respect to the transmitted and encoded pel words with a view to storiny it in the frame store 1 for the processing of the lines followiny the previously processed line L.
The linear interpolatlon is perEormed in the interpolating circuit 8. This ma]ces for the reconstitution of the subsamples elements based on the encoded PC(F,L) elements. Since the number of bits allocated -to a line is equal to NB = 231 bi-ts and since the number of bits allocated to each sampled element, i.e. to each transmitted LEV(F,L) level word, is at least equal to 3 bits, the number of encoded elements is equal at the most to NP = 231/3 = 77. If we consider, for instance, only subsamplinys of order 3 at the most, then the videotelephone picture standard should not comprises more than 3 x 77 = 231 visible frame elements.
The standard defined above is the maximum limit for such subsampliny. Naturally, other standards having a number of visible picture elements per line lower than 231 are also possible. If the standard is however defined with a number of visible elements per line higher than 231, then subsampling of an order of 4 or more must be considered. Such subsampling sometimes creates a significant blurring of picture and this i5 why the chosen embodiment is restricted to a subsampling of order 3.
Reporting to Fig. 12, we have shown a sequence of consecutive elements A, B, C, D, E and F of the moving area SA of a line L. Elements such as A, C and F are designated by a cross and are sampled and correspond to the transmission -30 of a LEV(F,L) word at the output of the encoder 6 (or 6').
Elements such as B, D and E are designated by a circle and are subsampled and cause no transmission of LEV(P,L) word, i.e. no transmission of word B through the output 360 of bit distributiny circuit 3 (Figs. 4 and 6). When NP < NB~3, ~,~
lJ~4~
all the line elements ln the S~ area are encoded, the LEV
(F,L) words comprise 3 to 6 ~it~ ancl we have at the output of the interpola-ting circuit 8 : PINT(F,I,) ~ PC(F,L). When NP > NB/3, certain elements are sampled and correspond to 3-bit LEV(F,L) words. In the latter case, when NB/3 < NP
~ 2NB/3, we have merely a order-2 subsampling corresponding to an element such as B, and the interpolation word is:
PINT (F,L) = PC (F,L) (element A) or PINT (F,L) = 12 [(PC-l)(F~L) + (PC+l)(F,L) ~ (element B) and if 2NB/3 < NP < NB, we have a subsampling of at the most order 3, corresponding to elements such as D and E, and the interpolation word is :
PINT (F,L) = PC (F,L) (element A) or PINT (F,L) = 12 [(PC-l)(F,L) + (PC+l)(F,L)~ (element B) or PINT (I,L) = 4l ~3(PC-l~(F,L) + (PC+2)(F,L)~ (element C) or PINT (I,L) = l4 ~(PC-2)(F,L) + 3 (PC+l) (F,L)~(element E) These relations thus make it clear that the inter-polated value PINT (F,L) of a subsampled element depends solely on those of the elements truly put into DPCM code - and not on the predicted values PP(F,L) transmitted by the output 40 of the predictor 4.
As illustrated in Fig. 10, the interpolating circuit 8 comprises a circuit 80 for calculating the four above relations and a circuit 87 for selecting one of these relations in terms of the subsampling type.
The input 800 of the calculating circuit 80 receives the PC(F,L) words in series at a frequency of 1/T
which are transmitted by the output 420 of the adder 42.
The input 800 is connected to four delay lines 811, 812, 813 -and 814 in series, each of which delaies the PC(F,L) word by T . Delay line 812 directly transmits the PC(F,L) word to a reading gate 82A, which is open for an element such as A.
An adder 83B has its inputs connected to the outputs of the , . .
. .
I ~ 62642 delay lines 811 and 813 ~nd h~s :Lts output connected to the input of a reading gate 82B via a divide-by-2 divider 84B~
Consequently, the output of the divider 84B provides PINT
(F,L) as per the interpolation related to the element B.
A second adder 83D has one input directly connected to the input 800 of the interpolating circuit and another input connected to the output of the delay line 833 via a multiply-by-3 multiplier 85D A divide-by-4 divider 84D is connected to the output of adder 83 D and transmits an interpalation word PINT(F,L) relating to an element such as D to an in-put of a reading AND gate 82D. Finally, a third adder 83E
has one input which is connected to the output of the delay line 811, via a multiply-by-3 multiplier 85E~ and has its other input which is connected to the output of the delay line 814. A divide-by-4 divider 84E is connected to the output of the adder 83E and delivers a PINT(F,L) word to the digital input of a reading AND gate 82E as per the inter-polation relation of an element such as E.
The selecting circuit 87 comprises on its input side a three-comparator 870 which receives, via connection 360, B words which are delivered from bit distributing cir-cuit 3 (Fig. 4). It will be recalled that for each B word equal to at least 3 there corresponds to the encoding of an element word to be transmitted by the output of the encoder 6 (or 6') and to the transmission of a DP'(F,L) word from the output of the decoder 7 (or 7') to the adder 42. If a B word is detected, the output 871 of the comparator 870 is in state 1 during time T, corresponding to a sampled element such as A,C or F (Fig.12). If an element is subsampled, no B word is transmitted by the bit distribution circuit 3 and the comparator's output is in state O during T .
Selection circuit 87 further comprises four delay lines 881 to 884 which are connected in series to the output 871 of the comparator 870. The output of the second I ~ 62842 delay l.i.ne 8$2 d:lrec-t~y contro ~1 tl~a ~Ip~ lllg ~,~ y.lte ~2A
~ n~ t-inLJ an il3LdL~pOlatiOn WOL'~ PIN'r(E~ (rr~r..~
corresponding to a sampled element such as A, i.e. eacil t:ime that a B word is received by the comparator 870. An AND gate 89B has -three inputs, one of which is connected to the out-put of the delay line 882 via an inverter 890B and the othcr two of which are directly connected to the outputs oE the delay lines 881 and 883. The output of the AND gate 89B is in state 1 for opening the AND yate 82B which provides a word PINT(F,L)=-2 ((PC-l)(F,L) + (PC+l)(F,L)) each timc two consecutive B words received by the comparator 870 are separated by 2~; this corresponds -to an order-2 subsampled element, such as B. A second AND gate 89D has four inputs, two.of which are directly connected to the outpu-t 871 of the comparator 870 and to the output of the delay line 883, and the other two of which are connected to the outputs of delay lines 881 and 882 via inverters 890D and 890D~ A third AND gate 89E has four inputs, two of which are connected directly to the outputs of delay lines 881 and 884 and the other two of which are connected to the outpu-ts of the delay lines 883 and 883 via two inverters 890E and 890E~ It can be seen that AND gates 89D and 89E are successively open during two consecutive subsamples elements of order 3. Each time that the comparator 870 has detected two consecutive words B separated by 3 T, the AND gate 89D controls the opening of AND gate 82D for transmitting an interpolation word PINT(F,L) = 1 ~3(PC-l)(F,L) + ~PC+2)(F,L)~ corresponding to an element such as D; then, after a time 1, the AND gate 89E controls the opening of.the gate 82E for transmitting an interpolation word PINT(F,L? = l4 C(PC_2)(F,L) + 3(PC+l)(F,L)~
corresponding to an element such as E. An OR gate 820 is connected to the outputs of the AND gates 82A, 82C, 82D and 82E and successively transmits an interpolation word PINT(F,L) at each time T to the input 900 of filtering . - 43 -'-.'~;~ , .
circuit 9.
Condi-tional spatial filterlng clrcuit 9 operates as a low-pass fllter so that the signal reconstituted ln the receiver be freed, after digital to analog converslon, of any spectrum everlap and step contours of the moving picture S on the background B. If the line L ls not sub-jected to a subsampling ~NP < NB/3), the filterlng circuit 9 directly delivers the word P'(F,L) = PINT(F,L) to the input 13 of frame store 1 for each of NP elements of the line L. On the other hand, if the line is subsampled, -then filtering circuit 9 transmits P'(F,L) = 1 ((PINT-l)(F,L) +
2 PINT(F,L) + (PINT + l)(F,L)) for an order -2 subsampling (NB/3 < NP ~ 2NB/3), and P'(F,L) = 2 ((PINT-l)(F,L) +
(PINT+l)(F,L)) for order -3 subsampling (2NB/3 < NP ~ NB) to the input 13 of frame store 1 for each of NP elements of the line L.
The conditional spatial filtering circuit 9 shown in Fig. 10 essentially comprises a calculating circuit 90 for carrying out the three above filtering relations and a selecting circuit 95 for selecting the filtering depending on the three relations.
The input 900 of the calculating circuit 90 receives in series at a rate of 1/T~ the PINT(F,L) inter-polation words which are transmitted from the output OR
gate 820 of the interpolating circuit 8. The input 900 is connected to two delay lines 911 and 912 in series and to one input of an adder 923. The output of the delay line 911 delivers P'(F,L) directly to the digital input of a reading AND gate 94, which is related to a line not sub-sampled, and to one of the inputs of an adder 922. The adder 923 has its other input connected to the delay line 912 and transmits P'(F,L) as per the relation for order-3 subsampling to the digital input of a reading AND gate 943, via a divide-by-2 divider 933. The adder 922 has its other ~ ~ 62642 input conn~c~ed to the output c~ the dlvlder 933 and sup-plies P'~F,L) as per the relation for order -2 subsampling to an input of a reading AND gate 942 via a divide-by-2 divider 932 Opening of the AND gates 941 to 943 is selectively controlled by the three outputs of the filtering selecting circuit 95.
On its input 950 side, the selecting circui-t 95 comprises two comparators 951 and 952 which receive, at the start of encoding of each line, the number of elements NP
of the picture area SA which is delivered by the register 285 of the movement detector 2(Fig. 3). The comparator 951 compares NP with NB/3 and sets its output to the state 1 when NP > NB13. The comparator 952 compares NP with 2NB/~ and set its output to the state 1 when NP > 2NB/3.
When NP < NB/3, the output of the comparator 951 is in state 0 and controls the opening of the AND gate 941 via an inverter 961, which corresponds to a not subsampled line L.
An AND gate 97 has one input connected directly to the input of the comparator 951 and another input connected, via an inverter 962, to the input of the comparator 952. When NB13 < NP < 2NB/3 is satisfied, the output of the AND gate 97 is in state 1 and controls the opening of the AND gate 942 related to the filtering of an order-2 subsampled line.
Lastly, then NP > 2NB/3, the output of the comparator 952 is in state 1 and directly controls the opening of the AND
gate 943 related to the filtering of an order -3 subsampled line. The output of one of reading AND gates 941~ 942 and 943 transmits in series, via an OR gate 98, the sequence of the NP suitable filtering P'(F,L) words of the processed line L to the input 13 of the frame store 1 in order to store them. The other element words related to background areas BAl and/or BA2, if present, are not modified in frame store 1, the latter being writing controlled by means (not shown) solely during the transmission of the width X2 - X
~1 1 62642 of each line's mov~ng areLI SA.
The decod~ng device at the receiver is shown in block form in Fig. 13. I-t performs the same operations of bit distribution, decoding, prediction, interpolation and filtering as those carried out in the encoding device in the transmitter.
After demultlplexing the date transmitted along the 2.048 Mbits/s digital ]ink TNi the input bus of the encoding device receives the line preamble words such as Xl, X2, DMAX-D, D and possibly PW and the LEV (F,L) data words which represent elements encoded by the distant speaker's transmitter encoding device. All the operations required for calculating the decoding parameters for the words of level LEV(F,L.) are performed during the time interval pre-ceding the video signal and peculiar to the reconstitution of the line synchronizing signal. We would recall that all the line synchronizing and blanking signals and field syn-chronizing and blanking signal reconstituting circuits, as well as the time base transmitting the monitoring signals specific to the decoding, will not be described in detail.
It will be noted that the blocks in Fig. 13 designated by the number references carrying the index rare identical to the blocks with the same reference numbers in the transmitter.
The Xl and X2 coordinate words indicating the start Ml and end M2 of SA area of the L line are applied to the inputs 281r and 282r of an arithmetic unit 28r; the Xl word is also delivered to the down- counting input of a down-counter 28r of a bit distributing circuit 3r Arithmetic unit 28r,as does the circuit 28 in the movement detector 2, calculates the average bit number B which has been allocated to each LEV(F,L) word and the element number NP of moving area SA of the line L. Its register 289r delivers B to the digital input of the AND gate 36r f a bit distributing circuit I J 626~2 3r which is analo~ous to circuit 3 in Fig. 4~ and 1-ts register 285r delivers NP to the triggering input of the down-counter 32r and to one of the inputs of the multiply-by-NP multiplier 33r of the bit distributing circuit 3r and to the input 950r of a conditional spatial filtering circuit 9r which is analogous to the circuit 9 in Fig. 11. As in the transmitters, the bit distributing circuit 3r transmits the word B at its output bus 360r each time an element is sampled, i.e. at the most NPmaX = 77 times per line. This transmission of words B takes place right from the start of the visible portion of the line to be reconstituted. Each word B is delivered, via bus 360r~ to three comparator 870r of a linear interpolating circuit 8r which is analogous to the circuit 8 in Fig. 10, and to the common input 601r of a B detecting circuit 62r and an arithmetic unit 63r which are analogous to 62 and 63 of the PCM encoder 6 shown in Fig. 6, respectively.
The output of the unit 63r delivers the coefficients as a function of NQ = 2B such as NQ/4, NQ/4-1, NQ/2-1, 3NQ/4 and 3NQ/4-1 to the appropriate inputs of a PCM decoder 7r which is analogous to the decoder 7 in Fig. 7.
In view of the fact that the LEV(F,L) words are conveyed in series on the 2.048 Mbit/s digital Link TNl, a buffer store 68r is provided for with a capacity NPmaX = NB/3.
In the store 68r, the bits of the LEV(F,L) words are written at the frequency of 2.048 Mbits/s and each LEV/(F,L) word is read during a time ~ under the control of reading signal 621 which is delivered from the B detecting circuit 62r.-The read words LEV(F,L) are applied to the input 70p of the decoder 7p and correspond solely to the sampled elements such as A,C and F shown in Fig. 12. The D and DMAX-D
words of the line preamble are supplied by the demultiplexing circuit of the receiver, are also stored in two buffer registers 57r and 59r in response to the detection of the line L preamble and are transmitted under the control of reading ,~ .
signal 621 at the appropriat~ :I.npu-ts o~ the decoder 7r~ vla bus-bars 570r and 590r. The decoder 7r calculates a quantization level DP'tF,L) each time its input 70r receives a level word LEV(F,L).
Next, as in the transmi-tter encoding device, DP'(I,L) is added in an adder 42r to the corresponding pre-dicted word PP(F,L) which is provided from the output 40r of a linear predictor 4r analogous to the prediction 4 of the encoding device. The predictor 4r may receive a pre-diction indicating word PW at its input 43r through the demultiplexing circuit, a word which was included in the line preamble. It will be noted that, as in the encoding device, the predicted words PP(FrL) are established from quantization levels which are calculated in the encoder 6 (Fig. 6) and are selected under the control of analogous bit distributing circuits 3 (Fig.4) and 3r The output 420r of the adder 42r provides the decoded words PC(F,L) =
PP(F,L) + DP'(F,L) at the input 800r of the linear inter-polating circuit 8r. Following this, after interpolation in terms of the subsampling order, the output OR gate 820 of the circuit 8r delivers PINT(F,L) to the input 900r f the conditional spatial filtering circuit 9r' the output OR
gate 98r of which supplies P'(I,L) to the input 13r f the frame store lp of the encoding device. The output llp of store lr transmits the element words P'(F,L) for the calcul-ation of the predicted word PP(F,L) at the 1/T rate as per one of the four predicted relations 1 to 4, to the input 44r of the predictor 4r The reading output 14 of the frame store lr also transmits.in series the P'(F,L) words at the frequency 1/T to the video means (screen) of the video-telephone after a digital-to-analog conversion.
It will be noted that, in the case of the second embodiment (Figs. 8 and 9) of the encoding device related to the quantization levels that are static but nevertheless .--,ji, ~ .
.
- .~
selectecl a5 a ~lnctiorl of the l~v~raC~e ~I.L: numl~cr 1~ all-.Jca~ed to an LEV(F,I,) word, the decocl.i.n~ clevice doe6 nol. comprise an arithmetic Ullit 63r and buffer reyis-ters 57r and 59r and has its PCM decoder which is analogous to that illus-trated in Fig. 9. According to the emhodiment relative to an available number of bits NB equal to 462 and to encodiny of one field out oE two, the store lr Of the decoding device is a field store which has a capacity reduced by half. On the video side, the output of this field store is connected to a missing-field duplicating or reconstituting circuit.
Although the invention has been described in reference to a particular videotelephonic standard, it will be appreciated that other embodiments using the invention are possible. It may provide encoding and decoding devices for other incoming and outcoming digital ra-~es which present ratios higher or lower than 8, and for incoming element word formats different from 8. Furthermore, the digital -transmis-sion medium can convey other secondary data signals, such as telecopier channel for instance. Generally speaking, the subsampling order can be greater than 3 and the number of bits N allocated to a frame line can be of any value, but defined however depending on the incoming and outgoing digital bit rates. The data contained in the preamble of each line are such that they suffice for allowing suitable decoding at the receiver. According to the first embodiment, they may further include Xl, X2; Xl,X2-Xl; B, NP ; or NQ, NP for example.
Moreover, the videotelephone signal may be a digital signal which is representative of monochromatic black and white pictures or a digital component signal representative of a chromatic or luminance component of a colour video signal. In the latter case, three encoding and decoding systems are provided in parallel.
Claims (14)
1. A digital video system having an encoding device in the transmitter for encoding a digital video signal at a high given rate constituted of PCM words which have a predetermined bit number and are representative of consecutive picture elements of a scanned picture, into a digital encoded signal transmitted on a low rate digital transmission medium conveying words which are representative of present picture elements, the levels of which have varied relative to those corresponding to the previous picture, said encoding device comprising:
- picture storing means for storing the transmitted picture element words after interpolating;
- means for detecting the moving area of the present picture with respect to the previous stored picture by means of comparison of the word difference between two words representative of two corresponding elements of the present picture and the previous stored picture with a predetermined threshold;
- the data bit number NB allocated to each line of a picture in said digital transmission medium being constant and the average bit number B allocated to each encoded signal word of a line being greater than or equal to a first predetermined integer;
- said moving area detecting means producing for each line of a picture the coordinates of the two ledge picture elements defining the moving area of said present picture with respect to the corresponding line of said previous picture so as to deduce thereby the number NP
of picture elements in said moving area of the line likely to be encoded and said average bit number B;
- a linear predicting means for delivering DPCM
predicted picture element word from the stored picture element words and present picture element words;
- first and second down-counting means controlled by said movement area detecting means and having their counts C1, C2 set to NB and NP at the start of the moving area of each present picture line for down-counting the number of bits remaining to be allocated to said line and the number of picture element words remaining likely to be encoded at the line element frequency;
- means connected to down-counting means for comparing the counts of said first and second down-counting means to select the DPCM words representing the picture elements to be transmitted each time C1/? ? C2;
- means receiving said DPCM words and controlled by comparing means for encoding, according to a predetermined quantization law, said selected DPCM words in order to multiplex said selected DPCM words in said digital transmis-sion medium; and - means connected to said encoding means for linearly interpolating the PCM unselected picture element words.
- picture storing means for storing the transmitted picture element words after interpolating;
- means for detecting the moving area of the present picture with respect to the previous stored picture by means of comparison of the word difference between two words representative of two corresponding elements of the present picture and the previous stored picture with a predetermined threshold;
- the data bit number NB allocated to each line of a picture in said digital transmission medium being constant and the average bit number B allocated to each encoded signal word of a line being greater than or equal to a first predetermined integer;
- said moving area detecting means producing for each line of a picture the coordinates of the two ledge picture elements defining the moving area of said present picture with respect to the corresponding line of said previous picture so as to deduce thereby the number NP
of picture elements in said moving area of the line likely to be encoded and said average bit number B;
- a linear predicting means for delivering DPCM
predicted picture element word from the stored picture element words and present picture element words;
- first and second down-counting means controlled by said movement area detecting means and having their counts C1, C2 set to NB and NP at the start of the moving area of each present picture line for down-counting the number of bits remaining to be allocated to said line and the number of picture element words remaining likely to be encoded at the line element frequency;
- means connected to down-counting means for comparing the counts of said first and second down-counting means to select the DPCM words representing the picture elements to be transmitted each time C1/? ? C2;
- means receiving said DPCM words and controlled by comparing means for encoding, according to a predetermined quantization law, said selected DPCM words in order to multiplex said selected DPCM words in said digital transmis-sion medium; and - means connected to said encoding means for linearly interpolating the PCM unselected picture element words.
2. A digital video system as claimed in claim 1, in which said moving area detecting means further comprises means triggered at the start of the visible portion of each line for counting the elements of said line and means for controlling the reading of said counting means when the absolute difference values of a predetermined number of PCM
consecutive picture element words of two corresponding lines of said present picture and said previous picture exceed said threshold and when the differences relative to the PCM consecutive picture element words have the same sign to produce said coordinates of said two ledge picture elements defining moving area of the present line.
consecutive picture element words of two corresponding lines of said present picture and said previous picture exceed said threshold and when the differences relative to the PCM consecutive picture element words have the same sign to produce said coordinates of said two ledge picture elements defining moving area of the present line.
3. A digital video system as claimed in claim 1 or 2, in which said moving area detecting means comprises comparison means for said average number of bits (?) allocated to each encoded signal word to be less than or equal to a second predetermined integer and to be more than or equal to said first predetermined integer.
4. A digital video system as claimed in claim 1, in which said encoding means comprises a PCM encoder for delivering for each selected DPCM picture element word a B -bit word which is representative of the number of the quantization law level of said selected DPCM word and which is multiplexed in said digital transmission medium, a PCM
decoder connected to said DPCM encoder for delivering for each B-bit level word a decoded word having said predetermined bit number which is representative of the amplitude of the selected DPCM word quantization level and means for adding said decoded word to the corresponding DPCM predicted word in a PCM selected picture element word applied to said interpolating means.
decoder connected to said DPCM encoder for delivering for each B-bit level word a decoded word having said predetermined bit number which is representative of the amplitude of the selected DPCM word quantization level and means for adding said decoded word to the corresponding DPCM predicted word in a PCM selected picture element word applied to said interpolating means.
5. A digital video system as claimed in claim 4, comprising means for calculating the maximum and average values DMAX, ? of words in DPCM code for all the picture elements in said moving area of a line L and in which said encoding means selects-a quantization law for each line, such that the quantization levels be equidistributed into half between -? and +? and half between -DMAX and -? and between ?
DMAX and be equal in number to 2B, and calculates the quantization level corresponding to this law for each selected DPCM picture element word of said line.
DMAX and be equal in number to 2B, and calculates the quantization level corresponding to this law for each selected DPCM picture element word of said line.
6. A digital video system as claimed in claim 5, comprising delay means for delaying each line of said high rate digital video signal by a duration of two lines and in which for each line, said moving area detecting means cal-culates said coordinates of said two ledge picture elements of said moving area of said line during the reception of said line, said maximum and average value calculating means performs said calculation during the reception of the follow-ing first line and said encoding means encodes said selected DPCM words during the reception of the following second line.
7. A digital video system as claimed in claim 5 or 6, in which said maximum and average values calculating means comprises predicting means controlled by said moving area detecting means and analogous to said linear predicting means for calculating DPCM picture element words for all the elements in said moving area of said line based on the PCM
picture element words of the corresponding elements transmit-ted by said high rate digital video signal and element picture words determined by predictions related to transmitted and possibly delayed high rate digital video signal words and to encoded and/or interpolated words stored in said picture storing means.
picture element words of the corresponding elements transmit-ted by said high rate digital video signal and element picture words determined by predictions related to transmitted and possibly delayed high rate digital video signal words and to encoded and/or interpolated words stored in said picture storing means.
8. A digital video system as claimed in claim 4, in which said DPCM encoder comprises means for storing the level numbers of a plurality of predetermined quantization laws and means for storing words representative of the level amplitudes of said quantization laws and in which said count comparing means selects a pair of storage means relating to a quantization law having 2B levels as a function of said average bit number B and for each selected DPCM element picture word so that said encoder produces a PCM level number word by means of the comparisons of the selected DPCM
element picture word with the level amplitudes of the selected quantization law and so that the DPCM decoder produces a decoded word representative of a selected quantification law level by means of comparisons of said produced PCM level number word with the level numbers of said selected quantization law.
element picture word with the level amplitudes of the selected quantization law and so that the DPCM decoder produces a decoded word representative of a selected quantification law level by means of comparisons of said produced PCM level number word with the level numbers of said selected quantization law.
9. A digital video system as claimed in claim 8, comprising delay means for delaying each line of said high rate digital video signal by a duration of one line, and in which, for each line, said moving area detecting means calculates said coordinates of said two ledge picture elements of said moving area of said line during reception of said line and said encoding means encodes said selected DPCM
words during the reception of the following line.
words during the reception of the following line.
10. A digital video system as claimed in claim 4, in which said linear interpolating means comprises means controlled by said count comparison means for distin-guishing the PCM selected encoded picture element words and the subsampling order of the PCM untransmitted and unselected subsampled picture element word relative to the moving area of each line, where the subsampling order is greater than or equal to two, and a circuit connected to the output of the adding means for linearly inter-polating each subsampled picture element word as a function of its subsampled order and the immediately neighboring selected picture element words.
11. A digital video system as claimed in claim 10, comprising low-pass digital filtering means interconnected between said linear interpolating means and the input of said picture storing means for filtering solely said PCM selected and subsampled element picture words.
12. A digital video system as claimed in claim 11, in which said filtering means selectively filters said PCM selected and subsampled words of each line by comparison of the number NP of elements in said moving area of said line with said constant bit number NB in terms of the maximum subsampling order likely to be produced by encoding said DPCM picture element words of said line.
.
.
13. A digital video system as claimed in claim 1, in which the number of bits allocated to each line in said digital transmission medium includes a predetermined number of bits which precede said data bit number NB
and which are assigned to a line preamble, said line preamble comprising a line synchronizing word, words for indicating discriminations regarding the line encoding in said DPCM encoding means and the prediction in said linear predicting means and two words representa-tive of said coordinates of said two ledge picture elements which define said moving area of said line.
and which are assigned to a line preamble, said line preamble comprising a line synchronizing word, words for indicating discriminations regarding the line encoding in said DPCM encoding means and the prediction in said linear predicting means and two words representa-tive of said coordinates of said two ledge picture elements which define said moving area of said line.
14. A digital video system as claimed in claim 1, having a decoding device in the receiver for decoding said digital encoded signal from the digital transmission medium into a digital video signal having said high given rate, said decoding device comprising:
- picture storing means for storing the received picture elements words after interpolating;
- linear predicting means analogous to that of said encoding device for delivering predicted picture element words from stored words:
- means receiving said coordinates of said two ledge picture elements defining the moving area of each line for thereby deducing said number NP of said picture elements of said line moving area and said data bit number B allocated to each encoded signal word;
- means receiving the encoded signal words for decoding said encoded words into decoded word as a function of said predetermined law;
- down-counting means and comparising means analogous to those of said encoding device for control-ling the reading of said DPCM encoded words in said decoding means at the frequency equal to said high given rate to deduce the PCM selected element picture words by addition to the corresponding predicted words;
and - means connected to said decoding means for linearly interpolating the PCM unreceived element picture words of said moving area of said line as a function of said selected and received element picture words so as to store the PCM selected and interpolated picture element words in said picture storing means.
- picture storing means for storing the received picture elements words after interpolating;
- linear predicting means analogous to that of said encoding device for delivering predicted picture element words from stored words:
- means receiving said coordinates of said two ledge picture elements defining the moving area of each line for thereby deducing said number NP of said picture elements of said line moving area and said data bit number B allocated to each encoded signal word;
- means receiving the encoded signal words for decoding said encoded words into decoded word as a function of said predetermined law;
- down-counting means and comparising means analogous to those of said encoding device for control-ling the reading of said DPCM encoded words in said decoding means at the frequency equal to said high given rate to deduce the PCM selected element picture words by addition to the corresponding predicted words;
and - means connected to said decoding means for linearly interpolating the PCM unreceived element picture words of said moving area of said line as a function of said selected and received element picture words so as to store the PCM selected and interpolated picture element words in said picture storing means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000356138A CA1162642A (en) | 1980-07-14 | 1980-07-14 | Digital video signal encoding and decoding system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000356138A CA1162642A (en) | 1980-07-14 | 1980-07-14 | Digital video signal encoding and decoding system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1162642A true CA1162642A (en) | 1984-02-21 |
Family
ID=4117418
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000356138A Expired CA1162642A (en) | 1980-07-14 | 1980-07-14 | Digital video signal encoding and decoding system |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1162642A (en) |
-
1980
- 1980-07-14 CA CA000356138A patent/CA1162642A/en not_active Expired
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