CA1162237A - Universal power module - Google Patents
Universal power moduleInfo
- Publication number
- CA1162237A CA1162237A CA000365745A CA365745A CA1162237A CA 1162237 A CA1162237 A CA 1162237A CA 000365745 A CA000365745 A CA 000365745A CA 365745 A CA365745 A CA 365745A CA 1162237 A CA1162237 A CA 1162237A
- Authority
- CA
- Canada
- Prior art keywords
- input
- signal
- output
- pwm
- pulses
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Abstract
UNIVERSAL POWER MODULE
ABSTRACT OF THE DISCLOSURE
A universal power supplying module for controlling the application of power to a plurality of loads is disclosed.
The universal power module receives a Pulse-Width Modulated (PWM) data signal which includes a plurality of PWM pulses.
Each of the PWM pulses is associated with a respective one of the loads and has a width which is indicative of whether or not power is to be applied to its associated load. The universal power module stores binary information in accord ance with the pulse width of the PWM pulses and controls the application of power to the loads as a function of the stored information.
ABSTRACT OF THE DISCLOSURE
A universal power supplying module for controlling the application of power to a plurality of loads is disclosed.
The universal power module receives a Pulse-Width Modulated (PWM) data signal which includes a plurality of PWM pulses.
Each of the PWM pulses is associated with a respective one of the loads and has a width which is indicative of whether or not power is to be applied to its associated load. The universal power module stores binary information in accord ance with the pulse width of the PWM pulses and controls the application of power to the loads as a function of the stored information.
Description
" \
2 ~ 3 7 UNIVERSAL pOWER ~ODULE
__ .
~BACKGROUND OF THE IN~ENT~ON
The present invention is directea towards a power module and, more particularly, to a power`module which can control the operation of a plurality of relaiively high current loads as a function of relatively low current signals generated by a control circuit such as a microprocessor.
A universal power module of the foregoing type is especially useful in connection with the control oE major appliances. Such appliances contain a multiplicity of loads, either resistive (e.g., a heater) or inductive (e.g.
motors and solenoids) which re~uire curren-ts well in excess of that which can presently be d~elivered by most integrated circuits. By way of example, such loads require currents up to 40 amps and voltages up to 240 volts. In contrast, the output of a typical integrated circuit will be in the 100 milliamp, 10 volt range. To solve this problem, most prior art appliances uiilize mechanical switches and relays to switch on and off respective loads. While such switching circuits are suitable where loads are manually switched on and off by a user of the appliance or automatically switched off by a timer motor, they do not lend themselves to satisfactory use in modern appliances where the appliance loads are controlled electronically by a microprocessor.
In such appliances, the mi~croprocessor is capable of generating only relatively weak signals to activate the power swilching device. The primary object of the present invention is to provide a universal power module which can switch on and o~ selected loads of the appliance (or other electronically controlled apparatus) as a ~unction of the relatively low level signals generated by the microprocessor while at the same time providing rPlatively high currents 1 3 6223'f (e.g., 40 ampsl and voltages (e.g., 2~0 volts) to the load.
It is a further major object of the present invention to perform this function in the most efficient, least expensive manner possible.
BRIEF DE5CRIP:TION OF T~E INVENTION
_ In order to achieve the foregoing and other objects of the invention, which objects will become apparent from the following descrip~ion, the universal power module of the present invention controls the application of power to N
electrical loads, N being an integer greater than 1, as a Eunction of a pulse-wid-th-modulated (PW~) data signal which includes N PWM pulses, each of which is associated with a respective one of said loads and each of which has a width which is indicative of whether power is to be applied to its associated load. To this end, the universal power module of the present invention comprises:
A~ memory means having N storage locations, each of said storage locations being associated with a respective said load, ~hereby each of the storaye locations is associated with a respective one of the PWM pulses;
B) input circuit means or storing either a firsr of second type of binary signal in each of the storage locations, the particular type of binary signal which is stored in any given storage location being determined by the widrh of the PWM signal associated therewith~ whereby the rype of binary signal srored in each of the storage locations indica~es whether power is ro be applied to the load associated with that storage locarion; and C) ourput circuit means for applying power to those ones of said loads whose associated storage location contains a binary signal which indlcates that power is to be applied there~o.
I J ~2237 BRIEF DESCRIPTION OF TE~E DRAWINGS
_ For the purpose of illustrating the invention,. there is shown in the dra~ings an embodiment which is presently preferred; it being understood~ however, that the invention is not limi.ted to th:e precise arrangements and instrumental-ities shown, Figure 1 is a circuit diagram of a power module constructed in accordance with the principles of the present invention;
Figure 2 is a circuit diagram i.llustrating a single load circuit which is controlle'd by the power module of Figure l;
Figure 3 is a timing diagram illustrating various wave forms of the circuit of Figure 1 over several cycles of an A.C. waveform being applied to the load of Figure 2; and Figure 4 is a detailed tim.ing diagram illustrating a portion of the timing diagram of Figure 3.
DETAILED DESCRIP'TION OF THE PRE_ERRED EMBODIMENT
Referring now to the drawings, wherein like numerals indicate like elements, ihere is shown in Figure 1 a circuit diagram of a universal po~er module constructed in accordance with the principles of the present invention and designated generally as 10. Power module 10 comprises an input circuit 12, a shift register 14 and an outp.ut circuit 16. Input circuit 12 receiues an input signal Vl (see Figure 3B) which i5 generated by a microcontroller such.'as a programmed micro-processor and controls the operation of both shift register 14 and output circuit 16 as a funct'ion ther:eof.
~s shown in Flgure 3B, Ihe input signal Vl includes two types of signals; reLatively short data input signals 22 and relatively long t.riac firin~ signals 24. As best shown in Figure 4A,. the data input signa~l:22 comprises a Rd-11436 plurality of pulse-width-modulaied (PWM) pulses having a relatively high frequency (10,000 cycles per second in the example shown). Each of the PWM pulses of data signal 22 indicates whether an associated one of the loads 28 (one of which i.s illust~ated in Figure 2) bein~ controlled by the power module 10 is to receive power. In the example illustrated, a relatively short pulse having a duty cycle of 50 percent represents a binary "O" while a relati~rely long pulse having a duty cycle of 90 percent represents a binary "1". Input circult 12 examines the length of each of the pulses of the data input signal 22 and causes a binary "l"
or a binary "0" to be read into shi.ft register 14 in accord-ance with the length of the indivldual pulses of the data input signal 22. In the preferred embodlment, the micro-controller generates one data input signal 22 durlng each cycle of the voltage waveforn V of the power supply which is applied to the loads 28. As such, input circuit 12 reads new digiial informatlon .into shift register 14 during each cycle of Ihe power supply. It should be understood, however, tha~ the data input slgnals may be generated by the microcontroller and read into shlft reglster 14 at a greater or lesser frequency, as deslredO
In the preferred embodlment, the output circuit 16 includes a pluraliiy of triacs 26, one of which is lllustrated in Figure 2. Each triac 26 is coupled in series with the power source V and one o~ the loads 28 beiny controlled by A~
power module 10. Output circuit 16 enables those loads 28 whose associated iriac 26 recelves a firlng pulse on its g.ate electrode 30. For peak eEficiency, it is pxeferred that power module lO enable each trlac 26 at the current zero crosslng of the load 28 with:which lt is assoc:iated.
If a purely reslstive load 28 is being controlled, it is ~ ~ ~223~
possible to fire the triac 26 at the voltage zero crossing of the power source V . In such a case, the triac firing AC
signal 24 would have a relatively small duration hovering around the zero crossing point of the voltage wave form.
In most applicacions, however, at least some loads 28 will be inductive~ Since the current zero crossings of such loads are up to 90 out of phase with their voltage zero crossings, it is preferred that the triac firing signal 24 extend over slightly more than one-quarter cyele of the input wave form V . In this manner, each triae 26 will be fired at the AC
current zero crossing of its respective load 28 irrespective of whether the load is resistive or inductive in nature.
In addition to controlli`ng the manner in which input is read into shift rec3ister 14, input circuit 12 controls the instant at which the information stored in shift register 14 is applied to the output circuit 16 as a funccion of the input signal Vl to ensure that the triacs 26 are fired at the appropriaie current zero crossings. In order to under-stand the manner in which input circuit 12 performs this function, it is helpful to first examine the operation of shift register 14 and oucput circuir 16.
In the preferred embodiment, shift register 14 is capable of three operations: converting serial information applied to ics data input into parallel information, storing the parallel information read into shift register 14 in memory seccion of the shift register, and applying the ~-c~6 stored parallel information to the outputs ~ n of the shift register 14.
Shifc register 14 includes an input section, a storage seccion and an output section. The input section includes generally N storage locacions ~seven in the embodiment illustrated) inco which binary data information is serially shifted. Particularly, each time a clock enable signal (a signal cransitioning from a binar~ 1l0ll to a binary "1"
level) i5 applied to the CLOCK input~ of shIft register 14, the binary signal appearing on its D~TA input is applied to the first storage position of the input section. Con-currently, the remaining digi:tal signals stored in the input section of shift register 14 are shifted forward by one positi.on as the new data signal is placed into the first storage position.
Once all seven binary signals have been shifted into . the input section of shift register 14, this binary information is shifted in parallel into the stora.ge section thereof. The storage section also includes generally N.storage locations (seven in the embodiment illustrated)~ Information is shified from the input section sto.rage locations. to the storage section storage loc.ations when a strobe.enable signal (a signal transitioning from a binar~ "1". to a binary "0" in . the example shown) is applied to the STROBE input of shift register 14. The i.nformaiion stored in the:storage section of shift regis.ter 14.is not affected by new data information read into the input section thereo~ unless a new strobe enable is applied to the sTRosE input of shift register 14.
As such, any change in the information.stored in the input section of shift register 14 as a result:o~ the generation of. the triac firing signals 24 will not affect the information stored in the.storage section of shift register 14.
The output section of shift register 14 includes N
outputs Q0-Qn ~seven outputs, Q0~Q6, i.n the example shown).
The digital siynals stored in the N s~t~orage locations of the storage section o~ shift register 14 are applied to the N
o.utputs of the output section of shi;ft register 14 each time an outpwt enable signal (a binary "1" in the.examp:Le shown) is 1 ~ 6~237 appliQd to the OUTPUT ENABLE input of shift register 14. A5 such, the binar~ in~ormation.stored in the storage section of shift regis.ter 14 is applied io the output section thereof whenever an output enabIe signal is applied to the OUTPUT ENABLE inpu~ of shift register 14. While any approp-riate shift register may be us.ed, one suitable shift register can be obtained ~rom several manu~acturers under the general designation 4094.
The operation of shift register 14 is coNtrolled by input circuit 12. Input ci.rcuit 12 has four sub-circuits; an isolation circuit 32, a data detection ci.rcuit 34, a strobe detection circuit 36 and an output enable detection circuit 38. Isolation circuit 32 includès Opto-Isolator 20 and inverting transistor 40 and serves to isolate. the microprocessor from the power:module 10. As noted above, the input signal Vl is applied across the diode 18 of Opio-Isolator 20 and causes transistor 41 to turn on whenever the input signal Vl is at a binary "1" level. ~hen transistor 41 turns on, it grounds the base of transisior 40 causing the voltage V1' appearing across resistor R1 to pulse. to the bi.asing vo.ltage level Vb (a binary l'l"). Conversely, when the input signal Vl is at the binary "0" level, transistor 41 turns off and the base of transistor 40 receives Vb volts via resistor R2. In this condition, transistor 40 is. turned off and the voltage Vl' drops to 0 volts DC (a binary "0"). As shown in Figures 3B and 3C, the net effect of the foregoing is to produce an isolated input signal Vl' which.is substantially identical in form to the input signal Vl.
The isolated input signal Vl' comprises two types of signals; .isolated data input signals 22' and isolated triac firing signals 23'. The input signals V1' generated by isolation circui~ 32 is applied to each of the detection 1 1 ~2~37 RD-11436 circuits 3A, 36 and 3~.
Data deiection circuit 34-includes an RC circuit comprising resistor R3 and capacitor Cl and clocks in an amplitude-modulated binary "0" or an ampli-tude-modulated binary "1" at the end of each PWM pulse of the data input signal 22. This operation may better be understood with reference to Figures 4B and 4C. As shown in Figure 4C, each time the input signal Vl' pulses to the binary "1" level, capacitor Cl charges to the binary"l" level and then discharges towards 0 volts DC when the input pulse Vl' returns to the binary "0"
level. As a result, the magnitude of the voltage acro.ss capacitor Cl at the beginning oE each PWM pulse is determined by the duty cycle of the last generated P~M pulse. This may be best understood with reference to pulses 42 and 44 of Figure 4B. At time t0, input signal Vl' pulses to the binarv "1"
level, causing capacitor Cl to charge to the binary "1" level through resistor R3. At time tl~ pulse 42 drops to the binary "0" level and capacitor Cl begins discharging through resistor R3. Since the duty cycle of pulse 42 is approximately 2Q 50 percent~ capacitor Cl is able to discharge for a substantial time period and is discharged to a binary "0" level at time t2.
At time t2, the leading edge of pulse 44 enables the CLOCK
input of shift register 14, causing shift register 14 to read a binary "0" into the first storage location of the input section of shift register 14.
Immediately thereafter, capacitor Cl begins recharging to a binary "1" level through resistor R3 and continues charging until time t3. At -time t3, pulse 44 pulses to the binary "0" leveI and capacitor Cl beings discharging through resistor R3. Since the duty cycle of pulse 44 is approximately 90 percent, capacitor Cl discharges only sligh-tly by time t4 and therefore remains at a binary "1" level. ~t time t4, a ~ 1 62~37 RD-11436 binary "1" is read into the first ~torage location of the input section of shift register 14 and the binary "0"
previously.stored in that position i.s shifted to the second storage location thereof. This process continues until time t6 when all seven binary bits of the.isolaied data input signal 22' (see Figure 4B) have been read into the input section o~ shift regi.ster 14.
After the entire data input signal 22' has been read into ihe input section of shift register 14, strobe detection circuit 36 applies a strobe enable pulse ta the ~TROBE input of shift register 14 causing each of the seven bits of infor-mation stored in the input section o~ shift register 14 to be transferred to the seven storàge locations of the storage section thereof. Strobe detection circuit 36 includes a voltage doubler circuit 45 and a switching transistor 46. ~oltage doubler 45 comprises resistor ~4, capaciiors C2 and C3, and diodes Dl and D2. This circuit is frequency responsive and pumps charge thr.ough capacitor C2 into capacitor C3 50 as to create a voltage differential between the base and emi.tter 2Q of switching transistor 44. A small amount of charge is supplied to capacitor C3 during each positive transition of the data input signal 22. The pulse width of each of the PWM
pulses o~ data input signal 22 is,.itself, insufficient to create a sufficient charge across capacitor C3 to turn transistor 46 on for a sustained time period. After the generation of several PWM pulses (six in the example shown) of the data input signal 22', the charge across capacitor C3 is finally suf~icient to turn transistor 44 on, thereby permitting some. current to flow through resistor R5. This current increases until transistox 46 is driven to saturation, at which poi.nt the voltage across resistor R5 will be at the biasing voltage level Vb. At time t5, capacitor C3 no longer I ~ ~2237 RD-11436 receives charge from capacitor C2 and begins slowly discharging. through resistor R6 and diocle D2. The charge across capacito.r C3 remains sufficiently high, however, to maintain transistor 46 in saturation until time t7, at which lime the transi.stor rapidly begirls turnlng off.
See Figure 4E. The negative going signal Vs enables the STROBE input of shift register 14, causing the seven binary bits stored in the input section o~ shift register 14 to be transferred to the storage section of shift register 14.
As best seen in Figure 3F~ this information is retained in the storage portion of shift register 14 until time t8, when a new strobe signal Vs is generated. This occurs after a new da-ta input signal 22l has been read into the input section of ~hift register 14.
As noted above, an enable signal is applied to the gate 30 of each of the triacs 26 whose associated load 28 is to be turned on. More particularly, the enabling signal is applied to the gate 30 during the triac firing period defined by triac firing signals 24 in order to ensure that . the triacs 26 will fire at their current zero crossings.
In order to ensure this result, input circuit 12 causes the digital information stored in the storage section of shift register 14 to be applied to the output section thereof (and there~ore to be applied to output circuit 16) during each triac firing period defined by. the triac firing signals 24.
The triac firing signals are detected by output enable detection circuit 38 whi.ch includes a capacitor C4, a resistor ~7 and a diode D3. Capacitor C4 is charged via resistor R7 whenever the input signal Vl' is at the binary "1" level and is discharged -th.rough diode D3 whenever the input signal Vl' is at the bi.na:ry "0" level. The value 1 1 ~223~ RD-11436 of resistor R7 is chosen to be relatively large. As a result, the charging time constant of capacitor C4 is relatively long compared to the charging time constant of capacitors C1 and C3. As such, capacitor C4 charges only slightly during each PWM pulse of the data input signals 22. See Figures 4C and 4D. Capacitor C4 is quickly discharge~
through diode D3 during the intervals between successive PWM pulses such that the voltage Vo across capacitor C4 remains at the binary "0" level throughout the period cluring which the data input signals 22 are generated.
As best shown in Figures 3B and 3C, the duration of each triac firing signal 24' is relatively long compared to the duration of each PWM pulse o~f the data input signals 22'.
As a result, each isolated triac firing signal 24' is at the binary "1" level for a sufficient period of time to permit capacitor C4 to charge through resistor R7 to the binary "1"
level. As lon~ as the voltage Vo across eapacitor C4 is at the binary "1" level, it will enable the OUTPUT ENABLE
input of shift register 14 and eause the digital information stored in the storage section of shift register 14 to be applied in parallel to outputs Q0-Q6 thereof. This infor-mation will remain on the outputs of shift register 14 as long as the output enable signal Vo remains at the binary "1"
level. As a result, the information stored in the storage seetion of shift register 14 will appear at the outputs Q0-Q6 of shift register 14 during substantially the entire duration of each triac iring signal 24.
The outputs Q0-Q6 of shift register 14 are applied to respective inputs of Darlington driver eireuit 48.
Darlington ~river cireuit 48 ineludes seven Darlington transisiors whose inputs ar~ coupled to respective ones of the outputs Q0-Q6 of shift register 14 ancl whose outputs ~ J ~23~
RD~114 3 6 a.re connected to respective ones of resistors R8-R14 . Resiscors R8-R14 are, in turn, coupled to th.e gate e.lectrode 30 of respective ones of triacs 26. Each of. the Darlington transis ors in Darlington driver circuit 43 whose associated output Q0-Q6 is.at:a binary "1" level applies a binary "1" to its associated resistor R-R14 and each of the Darlington transi.stors of Darlington driver circuit 48 whose associated output QO-Q6 is at a binary ~'0" level applies a binary "0"
to iis associated resistor R8-R14. AS such/ each of the triacs 26 whose associ.ated shi:ft register output Q0-Q6 is at the binary "1" level will be turned on at the zero current crossing point of its associated load 28 while the remaining triac~26 will be ofE. In.chis manner, the binàry information stored in the storage section oE shift register 14 controls the operation of each o~ the.loads 2 8 .
The pres:ent.invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof and, accordingly, reference should be made to the appended claims, rather than to the foregoing specification, as indi:cating the scope of the invention.
__ .
~BACKGROUND OF THE IN~ENT~ON
The present invention is directea towards a power module and, more particularly, to a power`module which can control the operation of a plurality of relaiively high current loads as a function of relatively low current signals generated by a control circuit such as a microprocessor.
A universal power module of the foregoing type is especially useful in connection with the control oE major appliances. Such appliances contain a multiplicity of loads, either resistive (e.g., a heater) or inductive (e.g.
motors and solenoids) which re~uire curren-ts well in excess of that which can presently be d~elivered by most integrated circuits. By way of example, such loads require currents up to 40 amps and voltages up to 240 volts. In contrast, the output of a typical integrated circuit will be in the 100 milliamp, 10 volt range. To solve this problem, most prior art appliances uiilize mechanical switches and relays to switch on and off respective loads. While such switching circuits are suitable where loads are manually switched on and off by a user of the appliance or automatically switched off by a timer motor, they do not lend themselves to satisfactory use in modern appliances where the appliance loads are controlled electronically by a microprocessor.
In such appliances, the mi~croprocessor is capable of generating only relatively weak signals to activate the power swilching device. The primary object of the present invention is to provide a universal power module which can switch on and o~ selected loads of the appliance (or other electronically controlled apparatus) as a ~unction of the relatively low level signals generated by the microprocessor while at the same time providing rPlatively high currents 1 3 6223'f (e.g., 40 ampsl and voltages (e.g., 2~0 volts) to the load.
It is a further major object of the present invention to perform this function in the most efficient, least expensive manner possible.
BRIEF DE5CRIP:TION OF T~E INVENTION
_ In order to achieve the foregoing and other objects of the invention, which objects will become apparent from the following descrip~ion, the universal power module of the present invention controls the application of power to N
electrical loads, N being an integer greater than 1, as a Eunction of a pulse-wid-th-modulated (PW~) data signal which includes N PWM pulses, each of which is associated with a respective one of said loads and each of which has a width which is indicative of whether power is to be applied to its associated load. To this end, the universal power module of the present invention comprises:
A~ memory means having N storage locations, each of said storage locations being associated with a respective said load, ~hereby each of the storaye locations is associated with a respective one of the PWM pulses;
B) input circuit means or storing either a firsr of second type of binary signal in each of the storage locations, the particular type of binary signal which is stored in any given storage location being determined by the widrh of the PWM signal associated therewith~ whereby the rype of binary signal srored in each of the storage locations indica~es whether power is ro be applied to the load associated with that storage locarion; and C) ourput circuit means for applying power to those ones of said loads whose associated storage location contains a binary signal which indlcates that power is to be applied there~o.
I J ~2237 BRIEF DESCRIPTION OF TE~E DRAWINGS
_ For the purpose of illustrating the invention,. there is shown in the dra~ings an embodiment which is presently preferred; it being understood~ however, that the invention is not limi.ted to th:e precise arrangements and instrumental-ities shown, Figure 1 is a circuit diagram of a power module constructed in accordance with the principles of the present invention;
Figure 2 is a circuit diagram i.llustrating a single load circuit which is controlle'd by the power module of Figure l;
Figure 3 is a timing diagram illustrating various wave forms of the circuit of Figure 1 over several cycles of an A.C. waveform being applied to the load of Figure 2; and Figure 4 is a detailed tim.ing diagram illustrating a portion of the timing diagram of Figure 3.
DETAILED DESCRIP'TION OF THE PRE_ERRED EMBODIMENT
Referring now to the drawings, wherein like numerals indicate like elements, ihere is shown in Figure 1 a circuit diagram of a universal po~er module constructed in accordance with the principles of the present invention and designated generally as 10. Power module 10 comprises an input circuit 12, a shift register 14 and an outp.ut circuit 16. Input circuit 12 receiues an input signal Vl (see Figure 3B) which i5 generated by a microcontroller such.'as a programmed micro-processor and controls the operation of both shift register 14 and output circuit 16 as a funct'ion ther:eof.
~s shown in Flgure 3B, Ihe input signal Vl includes two types of signals; reLatively short data input signals 22 and relatively long t.riac firin~ signals 24. As best shown in Figure 4A,. the data input signa~l:22 comprises a Rd-11436 plurality of pulse-width-modulaied (PWM) pulses having a relatively high frequency (10,000 cycles per second in the example shown). Each of the PWM pulses of data signal 22 indicates whether an associated one of the loads 28 (one of which i.s illust~ated in Figure 2) bein~ controlled by the power module 10 is to receive power. In the example illustrated, a relatively short pulse having a duty cycle of 50 percent represents a binary "O" while a relati~rely long pulse having a duty cycle of 90 percent represents a binary "1". Input circult 12 examines the length of each of the pulses of the data input signal 22 and causes a binary "l"
or a binary "0" to be read into shi.ft register 14 in accord-ance with the length of the indivldual pulses of the data input signal 22. In the preferred embodlment, the micro-controller generates one data input signal 22 durlng each cycle of the voltage waveforn V of the power supply which is applied to the loads 28. As such, input circuit 12 reads new digiial informatlon .into shift register 14 during each cycle of Ihe power supply. It should be understood, however, tha~ the data input slgnals may be generated by the microcontroller and read into shlft reglster 14 at a greater or lesser frequency, as deslredO
In the preferred embodlment, the output circuit 16 includes a pluraliiy of triacs 26, one of which is lllustrated in Figure 2. Each triac 26 is coupled in series with the power source V and one o~ the loads 28 beiny controlled by A~
power module 10. Output circuit 16 enables those loads 28 whose associated iriac 26 recelves a firlng pulse on its g.ate electrode 30. For peak eEficiency, it is pxeferred that power module lO enable each trlac 26 at the current zero crosslng of the load 28 with:which lt is assoc:iated.
If a purely reslstive load 28 is being controlled, it is ~ ~ ~223~
possible to fire the triac 26 at the voltage zero crossing of the power source V . In such a case, the triac firing AC
signal 24 would have a relatively small duration hovering around the zero crossing point of the voltage wave form.
In most applicacions, however, at least some loads 28 will be inductive~ Since the current zero crossings of such loads are up to 90 out of phase with their voltage zero crossings, it is preferred that the triac firing signal 24 extend over slightly more than one-quarter cyele of the input wave form V . In this manner, each triae 26 will be fired at the AC
current zero crossing of its respective load 28 irrespective of whether the load is resistive or inductive in nature.
In addition to controlli`ng the manner in which input is read into shift rec3ister 14, input circuit 12 controls the instant at which the information stored in shift register 14 is applied to the output circuit 16 as a funccion of the input signal Vl to ensure that the triacs 26 are fired at the appropriaie current zero crossings. In order to under-stand the manner in which input circuit 12 performs this function, it is helpful to first examine the operation of shift register 14 and oucput circuir 16.
In the preferred embodiment, shift register 14 is capable of three operations: converting serial information applied to ics data input into parallel information, storing the parallel information read into shift register 14 in memory seccion of the shift register, and applying the ~-c~6 stored parallel information to the outputs ~ n of the shift register 14.
Shifc register 14 includes an input section, a storage seccion and an output section. The input section includes generally N storage locacions ~seven in the embodiment illustrated) inco which binary data information is serially shifted. Particularly, each time a clock enable signal (a signal cransitioning from a binar~ 1l0ll to a binary "1"
level) i5 applied to the CLOCK input~ of shIft register 14, the binary signal appearing on its D~TA input is applied to the first storage position of the input section. Con-currently, the remaining digi:tal signals stored in the input section of shift register 14 are shifted forward by one positi.on as the new data signal is placed into the first storage position.
Once all seven binary signals have been shifted into . the input section of shift register 14, this binary information is shifted in parallel into the stora.ge section thereof. The storage section also includes generally N.storage locations (seven in the embodiment illustrated)~ Information is shified from the input section sto.rage locations. to the storage section storage loc.ations when a strobe.enable signal (a signal transitioning from a binar~ "1". to a binary "0" in . the example shown) is applied to the STROBE input of shift register 14. The i.nformaiion stored in the:storage section of shift regis.ter 14.is not affected by new data information read into the input section thereo~ unless a new strobe enable is applied to the sTRosE input of shift register 14.
As such, any change in the information.stored in the input section of shift register 14 as a result:o~ the generation of. the triac firing signals 24 will not affect the information stored in the.storage section of shift register 14.
The output section of shift register 14 includes N
outputs Q0-Qn ~seven outputs, Q0~Q6, i.n the example shown).
The digital siynals stored in the N s~t~orage locations of the storage section o~ shift register 14 are applied to the N
o.utputs of the output section of shi;ft register 14 each time an outpwt enable signal (a binary "1" in the.examp:Le shown) is 1 ~ 6~237 appliQd to the OUTPUT ENABLE input of shift register 14. A5 such, the binar~ in~ormation.stored in the storage section of shift regis.ter 14 is applied io the output section thereof whenever an output enabIe signal is applied to the OUTPUT ENABLE inpu~ of shift register 14. While any approp-riate shift register may be us.ed, one suitable shift register can be obtained ~rom several manu~acturers under the general designation 4094.
The operation of shift register 14 is coNtrolled by input circuit 12. Input ci.rcuit 12 has four sub-circuits; an isolation circuit 32, a data detection ci.rcuit 34, a strobe detection circuit 36 and an output enable detection circuit 38. Isolation circuit 32 includès Opto-Isolator 20 and inverting transistor 40 and serves to isolate. the microprocessor from the power:module 10. As noted above, the input signal Vl is applied across the diode 18 of Opio-Isolator 20 and causes transistor 41 to turn on whenever the input signal Vl is at a binary "1" level. ~hen transistor 41 turns on, it grounds the base of transisior 40 causing the voltage V1' appearing across resistor R1 to pulse. to the bi.asing vo.ltage level Vb (a binary l'l"). Conversely, when the input signal Vl is at the binary "0" level, transistor 41 turns off and the base of transistor 40 receives Vb volts via resistor R2. In this condition, transistor 40 is. turned off and the voltage Vl' drops to 0 volts DC (a binary "0"). As shown in Figures 3B and 3C, the net effect of the foregoing is to produce an isolated input signal Vl' which.is substantially identical in form to the input signal Vl.
The isolated input signal Vl' comprises two types of signals; .isolated data input signals 22' and isolated triac firing signals 23'. The input signals V1' generated by isolation circui~ 32 is applied to each of the detection 1 1 ~2~37 RD-11436 circuits 3A, 36 and 3~.
Data deiection circuit 34-includes an RC circuit comprising resistor R3 and capacitor Cl and clocks in an amplitude-modulated binary "0" or an ampli-tude-modulated binary "1" at the end of each PWM pulse of the data input signal 22. This operation may better be understood with reference to Figures 4B and 4C. As shown in Figure 4C, each time the input signal Vl' pulses to the binary "1" level, capacitor Cl charges to the binary"l" level and then discharges towards 0 volts DC when the input pulse Vl' returns to the binary "0"
level. As a result, the magnitude of the voltage acro.ss capacitor Cl at the beginning oE each PWM pulse is determined by the duty cycle of the last generated P~M pulse. This may be best understood with reference to pulses 42 and 44 of Figure 4B. At time t0, input signal Vl' pulses to the binarv "1"
level, causing capacitor Cl to charge to the binary "1" level through resistor R3. At time tl~ pulse 42 drops to the binary "0" level and capacitor Cl begins discharging through resistor R3. Since the duty cycle of pulse 42 is approximately 2Q 50 percent~ capacitor Cl is able to discharge for a substantial time period and is discharged to a binary "0" level at time t2.
At time t2, the leading edge of pulse 44 enables the CLOCK
input of shift register 14, causing shift register 14 to read a binary "0" into the first storage location of the input section of shift register 14.
Immediately thereafter, capacitor Cl begins recharging to a binary "1" level through resistor R3 and continues charging until time t3. At -time t3, pulse 44 pulses to the binary "0" leveI and capacitor Cl beings discharging through resistor R3. Since the duty cycle of pulse 44 is approximately 90 percent, capacitor Cl discharges only sligh-tly by time t4 and therefore remains at a binary "1" level. ~t time t4, a ~ 1 62~37 RD-11436 binary "1" is read into the first ~torage location of the input section of shift register 14 and the binary "0"
previously.stored in that position i.s shifted to the second storage location thereof. This process continues until time t6 when all seven binary bits of the.isolaied data input signal 22' (see Figure 4B) have been read into the input section o~ shift regi.ster 14.
After the entire data input signal 22' has been read into ihe input section of shift register 14, strobe detection circuit 36 applies a strobe enable pulse ta the ~TROBE input of shift register 14 causing each of the seven bits of infor-mation stored in the input section o~ shift register 14 to be transferred to the seven storàge locations of the storage section thereof. Strobe detection circuit 36 includes a voltage doubler circuit 45 and a switching transistor 46. ~oltage doubler 45 comprises resistor ~4, capaciiors C2 and C3, and diodes Dl and D2. This circuit is frequency responsive and pumps charge thr.ough capacitor C2 into capacitor C3 50 as to create a voltage differential between the base and emi.tter 2Q of switching transistor 44. A small amount of charge is supplied to capacitor C3 during each positive transition of the data input signal 22. The pulse width of each of the PWM
pulses o~ data input signal 22 is,.itself, insufficient to create a sufficient charge across capacitor C3 to turn transistor 46 on for a sustained time period. After the generation of several PWM pulses (six in the example shown) of the data input signal 22', the charge across capacitor C3 is finally suf~icient to turn transistor 44 on, thereby permitting some. current to flow through resistor R5. This current increases until transistox 46 is driven to saturation, at which poi.nt the voltage across resistor R5 will be at the biasing voltage level Vb. At time t5, capacitor C3 no longer I ~ ~2237 RD-11436 receives charge from capacitor C2 and begins slowly discharging. through resistor R6 and diocle D2. The charge across capacito.r C3 remains sufficiently high, however, to maintain transistor 46 in saturation until time t7, at which lime the transi.stor rapidly begirls turnlng off.
See Figure 4E. The negative going signal Vs enables the STROBE input of shift register 14, causing the seven binary bits stored in the input section o~ shift register 14 to be transferred to the storage section of shift register 14.
As best seen in Figure 3F~ this information is retained in the storage portion of shift register 14 until time t8, when a new strobe signal Vs is generated. This occurs after a new da-ta input signal 22l has been read into the input section of ~hift register 14.
As noted above, an enable signal is applied to the gate 30 of each of the triacs 26 whose associated load 28 is to be turned on. More particularly, the enabling signal is applied to the gate 30 during the triac firing period defined by triac firing signals 24 in order to ensure that . the triacs 26 will fire at their current zero crossings.
In order to ensure this result, input circuit 12 causes the digital information stored in the storage section of shift register 14 to be applied to the output section thereof (and there~ore to be applied to output circuit 16) during each triac firing period defined by. the triac firing signals 24.
The triac firing signals are detected by output enable detection circuit 38 whi.ch includes a capacitor C4, a resistor ~7 and a diode D3. Capacitor C4 is charged via resistor R7 whenever the input signal Vl' is at the binary "1" level and is discharged -th.rough diode D3 whenever the input signal Vl' is at the bi.na:ry "0" level. The value 1 1 ~223~ RD-11436 of resistor R7 is chosen to be relatively large. As a result, the charging time constant of capacitor C4 is relatively long compared to the charging time constant of capacitors C1 and C3. As such, capacitor C4 charges only slightly during each PWM pulse of the data input signals 22. See Figures 4C and 4D. Capacitor C4 is quickly discharge~
through diode D3 during the intervals between successive PWM pulses such that the voltage Vo across capacitor C4 remains at the binary "0" level throughout the period cluring which the data input signals 22 are generated.
As best shown in Figures 3B and 3C, the duration of each triac firing signal 24' is relatively long compared to the duration of each PWM pulse o~f the data input signals 22'.
As a result, each isolated triac firing signal 24' is at the binary "1" level for a sufficient period of time to permit capacitor C4 to charge through resistor R7 to the binary "1"
level. As lon~ as the voltage Vo across eapacitor C4 is at the binary "1" level, it will enable the OUTPUT ENABLE
input of shift register 14 and eause the digital information stored in the storage section of shift register 14 to be applied in parallel to outputs Q0-Q6 thereof. This infor-mation will remain on the outputs of shift register 14 as long as the output enable signal Vo remains at the binary "1"
level. As a result, the information stored in the storage seetion of shift register 14 will appear at the outputs Q0-Q6 of shift register 14 during substantially the entire duration of each triac iring signal 24.
The outputs Q0-Q6 of shift register 14 are applied to respective inputs of Darlington driver eireuit 48.
Darlington ~river cireuit 48 ineludes seven Darlington transisiors whose inputs ar~ coupled to respective ones of the outputs Q0-Q6 of shift register 14 ancl whose outputs ~ J ~23~
RD~114 3 6 a.re connected to respective ones of resistors R8-R14 . Resiscors R8-R14 are, in turn, coupled to th.e gate e.lectrode 30 of respective ones of triacs 26. Each of. the Darlington transis ors in Darlington driver circuit 43 whose associated output Q0-Q6 is.at:a binary "1" level applies a binary "1" to its associated resistor R-R14 and each of the Darlington transi.stors of Darlington driver circuit 48 whose associated output QO-Q6 is at a binary ~'0" level applies a binary "0"
to iis associated resistor R8-R14. AS such/ each of the triacs 26 whose associ.ated shi:ft register output Q0-Q6 is at the binary "1" level will be turned on at the zero current crossing point of its associated load 28 while the remaining triac~26 will be ofE. In.chis manner, the binàry information stored in the storage section oE shift register 14 controls the operation of each o~ the.loads 2 8 .
The pres:ent.invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof and, accordingly, reference should be made to the appended claims, rather than to the foregoing specification, as indi:cating the scope of the invention.
Claims (16)
1. A universal power supply for controlling the application of power to N electrical loads, N being an integer greater than 1, as a function of a PWM
data signal, said PWM data signal including N serial PWM pulses, each of said PWM pulses being associated with a respective one of said N loads and having a width which is indicative of whether power is to be applied to its associated load, said power supply comprising:
(A) memory means having N storage locations, each associated with a respective load, for accepting a binary signal as a function of the width of each of said N pulses and responsive to each of N associated clock pulses; said memory means also for storing the binary signal for each associated one of said PWM pulses in an associated one of the storage locations responsive to a strobe signal and providing each of the binary signals at one of N outputs each associated with one of said N storage locations;
(B) an input circuit having means for providing one of said clock pulses responsive to each of said PWM pulses and either a first or a second level of said binary signal to said memory means for storage in each of said storage locations, with the particular level of binary signal which is stored in any given storage location being determined by the width of the PWM signal associated therewith an indicative of whether power is to be applied to the load associated with that storage location;
said input circuit also including means for providing said strobe signal to said memory means only after all of said N PWM pulses have been received; and (C) output circuit means coupled to said memory means outputs for applying power to those ones of said N loads whose associated memory means storage location contains a binary signal of level indicating that power is to be applied to its associated load.
data signal, said PWM data signal including N serial PWM pulses, each of said PWM pulses being associated with a respective one of said N loads and having a width which is indicative of whether power is to be applied to its associated load, said power supply comprising:
(A) memory means having N storage locations, each associated with a respective load, for accepting a binary signal as a function of the width of each of said N pulses and responsive to each of N associated clock pulses; said memory means also for storing the binary signal for each associated one of said PWM pulses in an associated one of the storage locations responsive to a strobe signal and providing each of the binary signals at one of N outputs each associated with one of said N storage locations;
(B) an input circuit having means for providing one of said clock pulses responsive to each of said PWM pulses and either a first or a second level of said binary signal to said memory means for storage in each of said storage locations, with the particular level of binary signal which is stored in any given storage location being determined by the width of the PWM signal associated therewith an indicative of whether power is to be applied to the load associated with that storage location;
said input circuit also including means for providing said strobe signal to said memory means only after all of said N PWM pulses have been received; and (C) output circuit means coupled to said memory means outputs for applying power to those ones of said N loads whose associated memory means storage location contains a binary signal of level indicating that power is to be applied to its associated load.
2. A universal power supply according to Claim 1, wherein said output circuit means includes N electronic switches, each of said switches being coupled in series with a power source and a respective one of said loads whereby each switch is associated with one of said loads and wherein each of said switches includes a con-trol electrode which determines whether or not said power source is applied to its associated load.
3. A universal power module for controlling the application of A.C. power to N electrical loads, N
being an integer greater than 1, as a function of an input signal containing both PWM data signals and load firing signals on a single input line, each of said PWM data signals including N serial PWM pulses, each of said PWM pulses being associated with a respective one of said N loads and having a width which is indicative of whether power is to be applied to its associated load, said power supply comprising:
(A) memory means having N storage locations, each associated with a respective load, for accepting a binary signal as a function of the width of each of said N pulses and responsive to each of N associated
3. A universal power module for controlling the application of A.C. power to N electrical loads, N
being an integer greater than 1, as a function of an input signal containing both PWM data signals and load firing signals on a single input line, each of said PWM data signals including N serial PWM pulses, each of said PWM pulses being associated with a respective one of said N loads and having a width which is indicative of whether power is to be applied to its associated load, said power supply comprising:
(A) memory means having N storage locations, each associated with a respective load, for accepting a binary signal as a function of the width of each of said N pulses and responsive to each of N associated
Claim 3 continued:
clock pulses; said memory means also for storing the binary signal for each associated one of said PWM pulses in an associated one of said storage locations responsive to a strobe signal; said memory means also for providing each of the binary signals at one of N outputs, each associated with one of said N storage locations, responsive to an output enabling signal;
(B) first means for providing one of said clock pulses responsive to each of said PWM pulses and either a first or a second level of said binary signal to said memory means for storage in each of said storage locations with a particular level of binary signal stored in any given storage location being determined by the width of the PWM pulses, in an immediately-previously-received PWM data signal, associated therewith and indicative of whether power is to be applied to the load associated with that storage location; said first means also for providing said strobe signal to said memory means only after all of said N PWM pulses have been received; said first means also for providing said output enabling signal to said memory means only when one of said load firing signals is received on said single input line; and (C) second means coupled to said memory means outputs for applying power to those ones of said N
loads whose associated memory means storage location contains a binary signal of level indicating that power is to be applied thereto, said second means applying power to said loads which are to receive power during a time period determined by said load firing signals and the current zero crossings of the loads which are to receive power.
clock pulses; said memory means also for storing the binary signal for each associated one of said PWM pulses in an associated one of said storage locations responsive to a strobe signal; said memory means also for providing each of the binary signals at one of N outputs, each associated with one of said N storage locations, responsive to an output enabling signal;
(B) first means for providing one of said clock pulses responsive to each of said PWM pulses and either a first or a second level of said binary signal to said memory means for storage in each of said storage locations with a particular level of binary signal stored in any given storage location being determined by the width of the PWM pulses, in an immediately-previously-received PWM data signal, associated therewith and indicative of whether power is to be applied to the load associated with that storage location; said first means also for providing said strobe signal to said memory means only after all of said N PWM pulses have been received; said first means also for providing said output enabling signal to said memory means only when one of said load firing signals is received on said single input line; and (C) second means coupled to said memory means outputs for applying power to those ones of said N
loads whose associated memory means storage location contains a binary signal of level indicating that power is to be applied thereto, said second means applying power to said loads which are to receive power during a time period determined by said load firing signals and the current zero crossings of the loads which are to receive power.
4. A universal power module according to Claim 3, wherein said first means causes said binary signals located in said input section of said memory means to be transferred to said storage section responsive to said PWM data signals but not responsive to said load firing signals.
5. A universal power module according to Claim 3, wherein said second means includes N electronic switches, each of said switches being associated with a respective said load and being coupled in series with its associated load and an AC power source.
6. A universal power source according to Claim 5, wherein each of said switches includes a control electrode and wherein said second means applies enabling signals to the control electrodes of those loads whose associated storage location contains a binary signal level indicating that power is to be applied to that load.
7. A universal power module according to Claim 6, wherein said second means applies said enabling signals, to said electrodes of said switches whose associated loads are to receive power, only during intervals determined by said load firing signals.
8. A universal power supply according to Claim 1, wherein the clock pulse and binary signal providing means includes a resistance-capacitance circuit receiving each of said PWM pulses at an input thereof and providing said binary signal level at an output thereof responsive to the width of the pulse at said input, each of said clock pulses being provided to said memory means responsive to an edge of each pulse at the input of said resistance-capacitance circuit.
9. A universal power supply according to Claim 8, wherein said input circuit strobe signal providing means includes a voltage-doubler having an input receiving said serial PWM pulses and an output, at which a predetermined level is provided only after receipt of all of said N PWM pulses; and a switching device having an input connected to the output of said voltage-doubler and an output at which said strobe signal appears responsive to the output of said voltage-doubler reaching said predetermined level.
10. A universal power supply according to Claim 1, wherein said input circuit further includes means for isolating a source of said PWM pulses from both said clock pulse and binary signal providing means and said strobe signal providing means.
11. A universal power supply according to Claim 10, wherein said isolation means includes an isolation device having an input receiving the PWM
pulses from said source thereof and having an output at which appears an inverted representation of the pulses applied to said isolation device input; and an active inverter circuit having an input receiving the output signals of said isolation device and an output at which appears a signal substantially identical to the PWM pulse signal at said isolation device input.
pulses from said source thereof and having an output at which appears an inverted representation of the pulses applied to said isolation device input; and an active inverter circuit having an input receiving the output signals of said isolation device and an output at which appears a signal substantially identical to the PWM pulse signal at said isolation device input.
12. A universal power module according to Claim 3 wherein said first means includes a data detection circuit including a resistance capacitance circuit receiving each of said PWM pulses at an input thereof and providing said binary signal level at an output thereof responsive to the width of the pulse at said input, each of said clock pulses being provided to said memory means responsive to an edge of each pulse at the input of said resistance-capacitance circuit.
13. A universal power supply according to Claim 8, wherein said first means includes a strobe detection circuit including a voltage-doubler having an input receiving said serial PWM pulses and an output at which a predetermined level is provided only after receipt of all of said N PWM pulses; and a switching device having an input connected to the output of said voltage-doubler and an output at which said strobe signal appears responsive to the output of said voltage-doubler reaching said predetermined level.
14. A universal power module according to Claim 3, wherein said first means include an output enable detection circuit including a resistance-capacitance-diode circuit receiving each of said PWM pulses at an input thereof and having an output at which is provided said output enabling signal as a signal charging with a selected time constant to said first binary level, when present at said input, and substantially immediately discharging to said second binary level when said second binary level is present at said input.
15. A universal power module according to Claim 12, wherein said first means further includes means for isolating a source of said PWM pulses from at least one of said data, strobe and ouput enable detection circuits.
16. A universal power module as set forth in Claim 15, wherein said isolating means include an isolation device having an input receiving the PWM
pulses from said source thereof and having an output at which appears an inverted representation of the pulses applied to said isolation device input; and an active inverter circuit having an input receiving the output signals of said isolation device and an output at which appears a signal substantially identical to the PWM pulse signal at said isolation device input.
pulses from said source thereof and having an output at which appears an inverted representation of the pulses applied to said isolation device input; and an active inverter circuit having an input receiving the output signals of said isolation device and an output at which appears a signal substantially identical to the PWM pulse signal at said isolation device input.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000365745A CA1162237A (en) | 1980-11-28 | 1980-11-28 | Universal power module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000365745A CA1162237A (en) | 1980-11-28 | 1980-11-28 | Universal power module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1162237A true CA1162237A (en) | 1984-02-14 |
Family
ID=4118580
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000365745A Expired CA1162237A (en) | 1980-11-28 | 1980-11-28 | Universal power module |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1162237A (en) |
-
1980
- 1980-11-28 CA CA000365745A patent/CA1162237A/en not_active Expired
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4338503A (en) | Inductive heating apparatus | |
| CA1162237A (en) | Universal power module | |
| US4262213A (en) | Universal power module | |
| EP0512746A2 (en) | Solid state strobe tube control circuit with programmable flash pattern | |
| JPS59501040A (en) | proximity switch circuit | |
| US3292005A (en) | High-resolution switching circuit | |
| US3193693A (en) | Pulse generating circuit | |
| US5668712A (en) | Circuit for controlling a DCC converter in a power supply circuit for a discharge lamp of a motor vehicle headlight | |
| JPS61274814A (en) | Electric discharge machining power supply | |
| GB2133947A (en) | Electronic control circuit | |
| US3436608A (en) | Trigger circuit for inductive load | |
| US4303838A (en) | Master-slave flip-flop circuits | |
| US3621296A (en) | Power pulse circuit | |
| KR960009035Y1 (en) | Base driving control circuit of motor | |
| JPH0115173B2 (en) | ||
| SU1129715A1 (en) | Multivibrator based on thyristors | |
| SU1179475A1 (en) | Transducer for checking thyristors of high-voltage rectifier | |
| SU1583989A1 (en) | Bistable electromagnetic relay with control circuit | |
| JPH0354330U (en) | ||
| SU1422390A1 (en) | Solid-state gate | |
| SU860301A1 (en) | Pulse modulator | |
| SU788337A1 (en) | Method of control of pulse power amplifier thyristors | |
| SU603066A1 (en) | Pulsed dc converter | |
| SU813709A1 (en) | Flip-flop device | |
| JPH0229117A (en) | Reset circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |