CA1159173A - Digital data transmission system modem - Google Patents

Abstract

DIGITAL DATA TRANSMISSION SYSTEM MODEM
Abstract of the Disclosure A modem for transmission systems providing for simultaneous conventional baseband telephone signaling and digital data transmission on nonloaded telephone wires is disclosed. The modem includes a data transmitter that converts digital data to be transmitted from binary form into F1/F2 FSK form and a receiver that converts received digital data from F3/F4 FSK form into binary form. The modem is designed to be connected between a telephone transmission line and provide simultaneous conversion between binary form and FSK form.

Description

~ 159~73 DI~ITAL DATA TRANSM18SION SYSTEM MODEM
Teohnio~l l;ield This invention relates to communication systems and, more particularly, to wired communication systems adapted to carry both digital data signals and analog communication signals.
Background of the Invention At present, full duplex digital data transmission between two subscribers connected to the same central office requires the use of two nonloaded wire pairs. That is, at present, when it is necessary or desirable for two subscribers to have the capability of simultaneously transmitting digital data between each other (commonly called full duplex digital data transmission capability), two pairs of nonloaded wires running between each subscriber and the central office are required.
The two pairs of wires are jumpered at the main distribution frame of the central office so that one pair of wires can carry transmissions in one direction and the other pair of wires can carry transmissions in the other direction. At the subscriber's locations, the pairs of wires are connected to data terminals via modems (mcdulator-demodulator systems). Various data transmission techniques are utilized to transmit digital data over the two pairs of so connected wires, including relatively low Frequency Shift Keying (FSK) techniques.
One of the major disadvantages of the foregoing type of data transmission system is the need for two pairs of wires. More specifically, telephone operating companies (TELCO's) charges to subscribers are based in part on the number of pairs of wires running between the central office and each subscriber's premises. ~s a result, a data transmission system requiring two pairs of wires is substantiaUy more expensive than a comparable data system requiring only a single pair of wires.
In addition to the two wire pair requirement for f~dl duplex digital data capability, at present, usuaUy, a subscriber needs at least one additional pair of wires if conventional telephone communication is desired. That is, usually, the digital data wire pairs used to carry digital data, carry digital data orly and an ,.~

additional pair of wires is needed for voice communication, when simultaneous digital data and voice communication is desired. As a result, the subscriber's costs are further increased.
Located in various offices of many businesses are data terminals 5 connected to a common data processing cent~er. The offices may be in the same building, several adjoining buildings or scattered throughout a metropolitan area. In the past this arrangement has had a number of disadvantages when data terminals are moved or added.
Turning first to the situation where the data terminals and the data 10 processing center are located near one another, i.e., in the same building oradjoining buildings; each time a data terminal is moved or added, either new wires for connecting the data terminal to the data processing center must be run or existing wires moved. Both running new wires and moving wires ~re time consuming(and, therefore, expensive) tasks. Moreover, running new wires and moving wires are 15 often disruptive, because offices other than the ones directly associated with the new or moved data terminals are often disturbed as wires are strung or moved in ceiling, wall and other passageways.
Not only is the running of new wires and the moving of old wires disruptive of other offices, it may also delay the use of vacant offices where the 20 data terminal(s) are to be located. That is, the time required to wire or rewire vacant space to accommodate data terminals must be included in the timing of a move into the space. As with other factors affecting a move, the availability ofpersonnel, material, etc., can create time delays even if the wiring or rewiring is scheduled to coincide with other changes. Such delays can contribute to delays in 25 the occupancy of the vacant space. Consequently, there is demand for a data transmission system that aUows the data terminals of a data processing system to be readily added or moved without requiring the running of new, or the moving of existing, wires used to connect the data terminals to the data processing center.
Turning next to the situation where the data terminals are 30 separated from the data processing center by a substantial distance; such a situation may exist where a number of branch offices all associated with a central or "home"
office. Such a situation exists in many commercial environments, e.g., banking, real estate, etc. In such instances, the branch offices and the central or home office include data terminals connected to a data processing center located at one of the 35 offices, which is usuaUy the central or home office, but may be one of the branch offices or even an entirely separate office. In any event, as branch offices areopened and closed for various reasons data terminals must be moved. Further, thelocation of data terminals in the various offices is sometimes changed. This l 159~73 situation is ~omewhat different than the foregoing situQtion where the data terminals are located relatively near to the data processing center. Specifically, in the situation where the data terminals are separated from the data processing center, the terminal~ are usuaUy connected to tlhe center via telephone wires~ As a result, when data terminals are to be added or moved, the owner or lessee of thedata terminal is not reqllired to add or move wires. On the other hand a relatedproblem does e~ist in this situation. Specifically, when data terminals requiring dedicated (to the terminal) telephone wires are added or moved, the telephone company (TEI.CO) must change the telephone service. This may simply require connecting up existing unused wires, or adding new wires. In either situation, the owner or lessee of the data termin~l must pay for the additional or changed service.
The use of dedicated telephone wires has a further disadvantage. SpecificaUy, telephone wires dedicated to data terminals cannot be used for audio communications. As a result, separata data and audio communication wires are required for each office location requiring a data terminal. Since each pair of telephone wires is leased, the users costs are increased. (A somewhat similar situation exists where the data terminals are connected to telephone wires via acoupler, as required, rather than using dedicated telephone wires because of theadditional telephone capacity required when the data terminal is using the telephone wires.) Many businesses that have a data processing system wherein a plurality of data terminals are located in the vicinity of the data processing center have a private automatic branch exchange (PABX) telephone system. As with TELCO
central office (CO), the PABX routes telephone conversations from, to and between the business' telephone stations. Usually the telephone stations are widely scattered throughout the various offices of the business so as to be readily available to the business' employees. Consequently, usuaUy a telephone station is located in the vicinity of each data terminal.
In view of the foregoing discussion, it will be apparent that the present method of transmitting data between data terminals and a data processing center has a number of disadvantages. The nature of the disadvantages varies in accordance with the distance separating the data terminals from the data processing center. It will also be apparent that telephone stations are usuaUy located in the vicinity of data terminals. However, in the past the use of such telephone stations to transmit digital data has been limited due to the high costs involved in suchutilization. The invention is directed to economically utilizing this available transmission medium.
Thus, it is a general object of this invention to provide a new and imploved digit~l data transmis;ion ~ em.
It is a~ther general object of t~ invention Lo provlde a modem for a digital data tr~lnsmission sys~ern suitable for transmitting digital data over telephone ~ires without interfering witil the sirnultaneous use of the same wires to carry5 baseband telephone signals.
lt is a fur~her general object of ~his invention to provide a modem suitable for use in a translnissio~ systern for transmitting digital data from data terminals to ~ data processing center on telephone wires without impairing the use of the telephone wires to simultaneously carry baseband telephone signals.
As will be better understood frorn the following description, the present invention conternplates trans:nitting digital data in Frequency Shift Keying (FSK) form~ As will be readily understood by those familiar with FSK digital data transmission, such transmissk3n requires the production of a signal that shif tsbetween two different frequencies. In order to minimize the bandwidth used by this 15 transmission method, it is necessary that the phase of the sine waves of the transmitted signals be maintained coherent when shifting from one frequency to the other. It is a further object of this invention to provide a modem that includes an FSK transmitter that accomplishes this result. That is, it is a further object of this invention to provide a modem that includes a new and improved FSK transmitter 20 that maintains the coherence between the phases of generated sine waves when changing form one FSK frequency to another FSK frequency.
As will also be understood by those familiar with FSK data transmission, when full duplex transmission on a single pair of wires is to take place, in addition to being at different frequencies, the waveforms of the transmitted and 25 received signals must be such that they do not include harmonics at the other signal frequencies. Or, if such harmonics are included in the waveforms, the level of such harmonics must be so low as to be undetectable.
Therefore, it is a still further object of this invention to provide a modem for a full duplex FSK digital data transmission system wherein the 30 transmitted and received FSK signal pairs are at different frequencies and wherein the waveforms of the various FSK signals are very low in harmonics at or near the fundamental frequencies of the other FSK signals.
It is yet another object of this invention to provide a modem for a full duplex FSK digital àata transmission system wherein the waveforms of a pair of 35 transmitted FSK signals are low in harmonics at or near the frequencies of a higher pair of received FSK signals.
It is yet a further object of this invention to provide a modem including a new and improved FSK transmitter.

- ) -It is yet a still furti~er object o~ this invention to provide a modem including an FSK ~ransrnitter thal: produces a pair of FSK signals at different frequencieY, each of said FSl~ signals havi;lg a generaLly sinusoidal waveform that is low in harmollics ~t other prede~ermilled frequencies, and that maintains phase 5 coherence between the pair of FSK signals when shifting from one signal to the other signal.
Summary of the I!lvention __.
In accordance with this invention, a modem for use in a voice and full duplex digital data transmission on a single pair of nonloaded wires is provided. In 10 one form, the digital dE3ta transmission system is incorporated in a conventional telephone system for use by subscribers connected to a centrai office by nonloaded telephone wire pairs. That is, the digital data transmission system uses the single pairs of nonloaded telephone wires extending between the main distribution frame of a central office and two subscribers to transmit digital data between the 15 subscribeFs. 13oth subscribers remain connected to the main distribution frame of the same central office via the same pairs of wire~, which also carry conventional voice communication signals simultaneously with the data signals.
In another form, a transmission system for transmitting digital data between data terminals and a data processing center on nonloaded telephone wires20 without impairing the use of the telephone wires to simultaneously carry baseband telephone signals is providedO That iS9 the digital data transmission system provides for simultaneous conventional telephone signaling and audio communication, plus digital data transmission between data terminals and a data processing center. Thîs form is useful when the data terminals and the data processing center are located 25 relatively near one another, i.e., in the same building or in adjacent buildings. The form is also useful when the data terminals are remote from the data processing center. In either case~ the telephone wires carrying the digital data, and the baseband signals, must be nonloaded. That is, the wires carrying the digital data and the baseband signals running to either a PABX or a CO, as the case may be, must 30 form nonloaded loops, which means that no loading coils (i.e~, inductances) are connected to the wires.
The preferred form of a subscriber pair digital data communication system includes a modem located at each subscriber's premises. The modems are connected to the subscriber's data terminals and include a transmitter that produces 35 one or the other of two FSK signals (F1 or F2), depending upon the binary nature (0 or 1) of a particular data bit to be transmitted. The modems also include receivers that detect two other FSK signals (F3 and F4) and, depending upon the frequency of the recei~ed ~igrlal, produc~ ~>inary d~ta bits (0 or 1) in accordance therewith. In a(1dition, the rno~e1-ns inc1ude voice ~reque;lcy fi1ters that couple the subscriber's teiephones to the wire pnirs rllnning~ to the central office in a manner that prevents 1 SK ~;ignals f~om reaching the ~elephones. Aisc, included is a repeater located at the central o~fice that couples the two data cha~ e1s together at the main distribution l`rame. In addition to ~imply eoupling the lines together, the repeater bidirectionaUy converts transmitt~d FSl~ s;gnals (i.e., ~l and 12 signals) into receivable FSK signals (i.e., F3 and F~ signals) and forwards the converted signals to the receiving modem.
Further, the repeater includes a voice frequency filter that couples the subscriber's lines to the line switching equipment ~>f the central office so that voice communication either between the subscribers or between one of the subscribers and others can take place.
The preferred form of a station/data processing center digital data communication system includes a station modem located adjacent a telephone located near to a data terminal. The station modems are connected to the telephon and to the data terminal. Each station modem includes a data transmitter that converts digital data to be transmitted from binary form into Frequency Shift Keying (FSK) form for transmission and a receiver for converting received digital data from FSK form into binary form. More specifically, the transmitters include a frequency synthesizer that produces one or the other of two FSK signals (F1 and F2) depending upon the binary nature (0 or 1) of a particular data bit to be transmitted;
and, ihe receivers include frequency detectors that detect two other FSK signals (F3 and F4) and, depending upon the frequency of the detected signal, produce a corresponding binary data bit (0 or 1). The station modems also include voice filters that prevent the FSK data signals from reaching the associated station telephones and prevent any spurious high frequency signal generated by the telephone from reaching the nonloaded telephone wires. The digital data communication system also includes a CO or PABX subsystem located at the central office (CO~ or private automatic branch exchange (PABX), as the case may be, connected to the other endof the station telephone wires. The CO or PABX subsystem includes a receiver that converts the F1/F2 FSK signals produced by the station transmitter into binary digital data. A multiplexer/demultiplexer multiplexes the data from several stations and forwards the data to the data processing center. The multiplexer/demultiplexer also demultiplexes multiplexed binary digital data produced by the data processing center; and the PABX or CO modems include transmitters that convert the demultiplexed binary data into F3/F4 FSK signaLs and forward the F3/F4 FSK signals to the related station modem. Further, the CO or PABX subsystem includes voice frequency filters that connect the main distribution frame telephone lines to the CO

7.~

or PA~X line switchillg equipment hl a manner that prevents the FSK signals fromreachiIlg that equiplnent nnd prevenls high fre~luency noise signals generated by the CO or PAB~ from reaching the nonloaded telephone wires.
In nccordance with ~urther features of this invention, the modem transmitters include frequency synlhesizers that create the transmitted FSK signals.
The frequency synthesizers produce signnls having a general~y sinusoidal shape, but stair step in fs)rm. By approE~riately choosing the number and sizes of the steps, the signals produced by the frequency synthesizers w;ll be low in harmonics near thereceived frequencies.
In its preferred form, each frequency synthesizer includes an operational amplifier, a resistance network and a control circuit. The resistance network includes a pair of resistors of equal value connected in series between a reference voltage source and ground. The junction between the resistors is connected to one of the inputs of the operational amplifier (e.g~, the non;nverting input). Another resistor of the resistance network is connected between the output of the operational amplifier and the other input (e.g., the inverting input). One end of each of the remaining resistors of the resistance network is connected to thefeedback resistance input ~e.g., inverting) of the operational amplifier. The other ends of the remaining networks are connected to a switching system forming part of the control circuit. The switching system is also connected to the reference voltage, to ground and to the junction between the pair of voltage divider resistors such that either ground, the reference voltage or onehalf of the reference voltage can be applied to the other ends of the remaining resistors. The control circuitcontrols the switching sytem in sequence such that nine (9~ discrete voltage levels are produced at the output of the operational amplifier. More specificaIly, the control circuit controls the switching systern such that sinusoidally weighted voltage level changes occur at equal intervals at the output of the operational amplifier.
Since a sinusoid is symmetrical, eighteen (18) intervals, each at the appropriate one of the nine (9) voltage levels, form a complete sinusoid. Since eighteen intervals make up a complete sinusoid, the frequency of the intervals is equal to eighteentimes the frequency of the signal to be transmitted (i.e., F1 of F2). Moreover, simply changing the interval frequency without changing any of the other parameters provides a smooth shift between the frequencies to be transmitted (e.g., F1 and F2)~ As a result? phase coherence between the two signals during a frequency change is maintained.
In accordance with further features of this invention, the receiver portion of each subscriber's modem determines the frequency of a received FSK
signal in a conventional manner by counting clock pulses occurring between the zero 9 ~ 7 ;~

crossing E~oints of a complet~ cycle of the received signal. The results of the count are decoded and, in order to prevent erroneous operation due to extraneous signals, tested by a gunrding circuit. The guarding circuit requires that at least two cycles of a part;cular ~requency be detected before a signal is accepted as a trlle FSKdigital data s;gnal. In addition9 the decoder produces outputs when the frequency of the received signal, even though Iying outside of the band determined by a true FSK
digital data signal, is s~Ich that it can provide information regarding the operat;on of the system.
It will be appreciated from the foregoing brief description that the L0 invention provides a new and improved modem for audio and digital data carrier systems~ The digital data carrier system provides for the simultaneous transmission of digital data between two subscribers on a single pair of nonloaded telephone wires. In addition, the same wires that carry digital data can also carry simuleaneous audio and D.C. communication signals. Conse~uently, the need for a subscriber to lease a plurality of pairs of wires to carry the same amount of audio and digital data is eliminated. As a result, the vverall costs of an audio and full duplex data carrier system are reduced. In addition to providing a new and improved audio nnd data carrier system modem, the invention also provides a modem that includes a new and improved FSE~ frequency synthesizer. More specifically, the invention provides an uncomplicated frequency synthesizer adapted to produce FSKsignals relatively free of harmonics which interfere with other FSK signals. Notonly are the produced FSK signals relatively free of harmonics at other predetemrined frequencies, the frequency synthesizer of the invention provides for a smooth, phase coherent, shift from one FSK frequency to another FSK frequency.
As a result, the bandwidth occupied by the transmitted FS~ signals is relativelynarrow.
It will also be appreciated that the digital data carrier system overcomes the foregoing disadvantages of present systems for connecting data terminals to data processing centers. Specifically, rather than running or rerunning 3û wires, or adding or changing TELCO service, when a new data terrninal is to be connected to the data processing center, or the location of a present data terminal is to be changed, the digital data carrier system merely requires that the new location include a telephone location near the new data terminal. In most instances the telephone will already exist; or, provision wiU have been made to instaU a telephone. The only requirement is that the telephone be connected to the CO or PABX, as the case may be, by nGnloaded wires. The modems used by the invention aUow digital data to be transmitted and received without irnpairing the normal operation of the telephoneO That is, the telephone can be utilized to transmit and receive baseballcl telephone sign~l~s siln~ arlel~usly with the trarlsmission and reception of t~le FSK digital dElta signals all 011 l.he same pa.ir of unloadecl wires.
In ~umina~y1 in accordance wilth the present invention, there is provided R ll!lOdelll Sllitable for sir~ tnneollsly converting dig;lal daia from binary sig~l t`orrn illtO FSK signal :form ~md ~rorn FSK signal form into binary signul form, said Inodem comprising:
a transmitter, said ~rflnsmit:ter including a frequency synthesizer for convertillg digital data frolll binary sigllal for~n into FSK sigrlal form such that a binary zero ~0) causes said E~SK sign~ll to have a first frequency, F1, and a binary (1) 10 causes said FSK signal to have a second frequency, F2, said frequency synthesizer producing said F1 and F2 signals in a manner that maintains phase coherency during shifts between said Ei1 and F2 sign~ls and in a manner such thflt the ~aveforms of said Fl and F2 FSK signals are substantial:ly free of harmonics at third and fourth frequencies, F3 and F4; and, a receiver, said receiver including a frequency detector for detecting an FSK signal at said third and fourth frequencies, F3 and F4, and converting digital data from FSK signal form into binary signal form such that an FSK signal at said third frequency, F3, causes a binary zero (0) and an FSK signal at said fourth frequency, F4, causes a binary one (1).

Brief Description of the Drawin~
The foregoing objects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the foUowing detailed description when taken in conjunction with the accompanying drawings wherein:
FIGURE 1 is a partially block and partial:ly pictorial view illustrating an audio and full duplex digital data carrier system including a modem formed inaccordance with the invention;
FIGURE 2 is a block diagram illustrating a subscriber modem formed in accordance with the invention suitable for use in the audio and fuU duplex digital 30 data carrier system il.lustrated in FIGURE 1;
FIGURE 3 is a schematic diagram of a transmitter suitable for use in the modem illustrated in FIGURE 2;
FIGURE 4 is a waveform diagram illustrating the stair step form of the signals prodslced by the frequency synthesizer illustrated in FIGURE 3;
FIGURE 5 is a waveform diagram pictorially illustrating how phase coherence is maintained between two signals produced by the frequency synthesizer illustrated in FIGU:RE 3 during a frequency change;

FIGUKE fi ix A bloc1s ciiagrarn of a receiver suitable for use in the~nodem ilhls~ t~d in FIGURE 3;
Fl(lURE 7 is ~l timiilg diagra~ r,ed to describe the decoding of signals by the receiver ilhlstlated in EIGUR~ 6;
FIG~]RE 8 is a blos~k diagr~m of a repentel suitable for use in the audio nnd full d~lplex digital data carrier system illustrRted in FIGURE t;
FIGU RE 9 is a pm tially block and partinlly pictorial view illustrating a digital data transmission system including a modem ~ormed in accordance with theinvention; and, FIGURE lO is a block diagram illustrating a central office or private automatic branch exchange modem and data multiplexer/demultiplexer subsystem suitable for use in the digital data transmission system illustrated in FIGURE 9.
Description OI the Preferred Embodiments FIGUlRE 1 is a partially block and partially pictorial diagram of an 15 audio and fuU duplex digital data earrier system. Included in FIGURE 1 is a central office 11 connected by a first pair of telephone wires 13 (commorlly called tip and ring wires) to a first subscriber's premises 15, denoted subscriber A; and, by a second pair of telephone wires 17 to a second subscriber's premises 19; denoted subscriber B. The pairs of wires 13 and 1~ are nonloaded and, thus9 form nonloaded loops, 20 which means that no loading coils (i.e., inductances) are connected to the wires. In most instances this means that the subscribers' premises 15 and 19 are within three miles of the centrPI office 11.
The subscribers' end of each pair of telephone wires 13 and 17 is connected to a modem 21 formed in accordance with the invention. The modems, in 25 turn, are connected to the subscriber's telephone 23 and data terminal 25. The centr~l office end of each pair of telephone wires 13 and 17 is connected through a protector 27 to appropriate terminals on a vertical main distribution frame 29 and, thence, in a conventional manner to a horizontal main distribution frame 31. Forpurposes of identification, the terminals of the horizontal main distribution frame 31 30 connected to the central office end of the pair of telephone wires 13 running to subscriber A are denoted pair 1; and, the terminals of the horizontal main distribution frame connected to the central office end of the pair of telephone wires 17 running to subscriber B are denoted pair 2. The pair 1 and pair 2 terminals are connected to a central office repeater 33, which also forms a portion of the 35 invention.
A prei`erred embodiment of a central office repeater is illustrated in ~IGURE 8 and hereinafter described. As will be better understood from that description, the central office re2eater 33 includes pair terminals, related to subscribers A and B, that are eonnected to the line switching eguiprnent of the .3 ~ 3 c~trui of îice Vi~l the horizontal main distribution ~rame 31. In this regard, the pair of rnuin di~;t~ihution f~ame terminals relat~(l to subscriber ~ are denoted pair 3 and the pair ot` Inain dislribution fralne ~errninals related to subscriber B are denoted pair 4. Pair~; 3 and-~ are connes~ted ~lia the hori~ontal main distribution frame 31 to 5 tlIe appropriate line s~^/itching eqllipment of the ~entral office 11 related to ~ubscribers /~ and ~.
~s will be t)etter understood from the following description of FIGUE~ES 2-R, the sub;criber mo~ems ~l conlIect the subscriber's telephone 23 tothe related pair of telephone wires ~hrough an audio or voice frequency filter. In addition, lhe modems include transrnitters and receivers that transmit one pair of YSK signals and receive another pair. I~lore specifically, when a subsciiber's data terminal is transmitting data, the modem converts the data from binary form (i.e., 0 and 1 bit form) into FSK ~orm. That is, the modem transmitters produce a signal at one or the other of two frequencies, the particular frequency being dependent upon whether or not the binary data i5 a zero or a one. The FSK signals produced by the subscriber binary modems are received by the central office repeater 33, via therelated pair of telephone wires and vertical and horizontal main distribution frames 29 and 31. The central office repeater converts the signals it receives from transmitted form into reception form. More specificaUy, the subscriber modems transmit l?SK signals at one pair of frequencies (F1 and F2) and receive FSK signals at different pair of frequncies (F3 and F4~. The repeater bidirectionaUy converts the transmitted signals it receives into modem receivable frequencies. SpecificaUy, F1 signals are converted into F3 signals and F2 signals are converted into F4 signals.
The central office repeater also couples the telephone wire pairs to the horizontal main distribution frame 31 so that di~l signals can aetuate the line switching equipment of the central office in a conventional manner and voice conversationscan take place. The repeater includes voice filters that prevent FSK signals from affecting these functions, which occur in a conventional manner.
Since the transmitted and received FSK signals are at different frequencies, full duplex digital data transmission is provided by the invention assuming that the FSK signals are of a form that do not include undesirable harmonics. As will be better understood from the following discussion, the waveforms of the FSK signals and their frequencies are such that harmonic interference is avoided. In addition to full duplex digital data, the system has the capabiltiy of simultaneously carrying s~oice communication signals. Thus, the invention provides for audio and full duplex data transmission on a single pair of nonloaded wires.

[~IGUI~ . 2 is a t)lock diagrdln of a sllbicriber modem 21, formed in accordallce with the in~/elltion7 sllitable for u :e in the system illustrated in FIGURE
1 a~d inclu-les: a voice fre(lllency (Vl ) ~ilter ~11; a pair of coupling capacitors 43A
Mnd 43~j a coupling trans~orrner 45; a leceiver ~7; a transmitter 49; a data sync and colltrol ciruit 51; ~q crystal clocl~ 53; an ~nitomntic gain control (AGC) circuit 55;
and, an interface 57.
As scllematically illustruted in l lGURE 2, the subscriber end of the related tip ~T) nnd ring (R) pair of nonloacled telephone wires are connected through the voice freqllency filter 41 to the subscriber's telephone. The voice frequency filter 41 is bidirectional, i.e., vo;ce signals can pass to and from the subscriber's telephone. However, the filter prevents FSK signals from being applied to the telephone. In this regard, the FSK signals are chosen to lie above the normal voice frequency band. Specific examples of FSK signsl frequencies are set forth below.The subscriber end of the related tip and ring pair of telephone wires are also connected via the coupling capacitors 43A and 43B to one side of the coupling transformer 45. Tlle other side of the coupling transforrner 45 is connected to the input of the receiver 47 and to the output of the transmitter 49. The output of the receiver is connected to an input to the data sync and control circuit 51 and the intput of the transmitter 49 is connected to an output of lhe data synch andcontrol circuit 51. In addition, the data sync and control circuit 51 is connected to the crs~stal clock 53 so as to receive clock pulses~ Also, the automatic gain control circuit 55 has its input connected to the receiver 47 and its output connected to a control input of the transmitter 49. Finally, the data sync and control circuit S1 is connected through the interface 57 to the subscriber's data terminal.
As noted above, the FSK signals transmitted by the transmitter 49 may be denoted F1 and F2. For purposes of discussion, it is assumed that F1 is produced when the data terminal produces a binary zero and F2 is pro:luced when the data terminal produces a binary one. The FSK signals received by the receiver 47, as also noted above, are designated F3 and F4. For purposes of discussion, it is assumedthat an F3 signal denotes a binary zero in FSK form and an F4 signal denotes a binary one in FSK form. Further, in addition to being above the voice frequency band, preferably, the frequency of F3 is equal to twice the frequency of F1 and the frequency of F4 is equal to twice the frequency of F2. While various specific freq~lencies can be utilized, in one actual embodiment of the present invention, F1 had a nominal value of 36 KHz, F2 had a nominal ' ;3 -13~

value of 4n K~l~., F3 had a nominal v~lue of 72 ~Hz and F4 had a nominal value of 80 KHæ.
As illustrated in FIGURE 2, the transmitter 49 includes an Fl/F2 frequency synthesizer and an Pl/F2 filter. The frequency synthesizer receives 5 the zero/one binary data signals produced by the data terminal, via the interface 57 and the data sync and control circuit 51. In addition, the Fl/F2 Irequency synthesizer receives clock pulses prodllced by the crystal clock 53; and, an amplification control signal prodllced by the alltomaic gain control ~AGC) circuit 55. In accordance therewith, as hereinaf~er described in detnil, the îrequency 10 synthesizer produces Fl and F2 signals. The output of the Fl/F~ frequency synthesizer 59 is cor.nected through the Fl/F2 filter 61 to the coupling transformer 45. The ~l~F2 filter is a bandpass filter that passes signals in theFl/F2 frequency range alld rejects signals at other frequencies.
The receiver 47 includes an F3/F4 filter 63, an amplifier 65 and an 15 F3~F4 frequency detector 67. The input of the F3/F4 filter is connected to the receiver side of the coupling transformer 45 and only passes ~SK signals in the F3/F4 frequency range. The output of the F3J~4 filter 63 is connected through the amplifier 65 to the input of the F3/F4 frequency detector 67. The output of the frequency detector, which determines whether or not the incoming frequency 20 is an F3 signal or an F4 signal, is connected to the data sync and control circuit 51.
In as3dition to being connected to the input of the P3/F4 frequency detector 67, the output of the amplifier 65 of the receiver 47 is connected to the control input of the automatic gain control circuit 55. The output of the 25 automatic gain control circuit 55, as previously noted, is connected to the ~1/F2 frequency synthesizer 59. The AGC circuit 55 inversely controls the magnitude of the signal produced by the ~l/F2 frequency synthesizer in accordance with themagnitude of the received signal. More specifically, the magnitude of the transmitted signal, as will be better understood from the following description, is 30 controlled by the AGC circuit such that its logarithm is proportional to the negative logarithm of the magnitude of the received signal. This arrangement compensates for the attenuation differences of different length pairs of tip andring wires. More specifically, the longer the tip and ring wires connecting the modem of the receiving subscriber to the central office, the weaker will be the 35 received signal. As a consequence of the negative logarithmic AGC control a weak received signal causes a strong transmitted signal. This arrangement assures that the central office will receive modulated data signals from the subscribers at nearer the same level, regardless of any difference in the distance between the central office nnd the subscriber's premises.
FIGURE 3 is A partiA11y schematic and partially block diagram illustrating in more detail a transmitter 49 formed in accordance with the invention. More specifically, FIGURE 3 includes the Fl/~72 frequency synthesizer59 and the FVF2 filter 61. The FI/F2 frequency synthesizer 59 is illustrated as including: a freql~ency controller 77; an Fl divider i93 an F2 divider 81; a switch controller 83; ~n operational amplifier 85; seven resistors designated RlA, RlB,R2, R3, R4, R5 and ~6; flnd, a multiple switch 87. While the multiple switch &7 is illustrated as cornprising four separately actuated single pole, triple throw10 mechanical switches, designated S3, S4, S5 and S6, it is to be understood that this simplification is for descriptive purposes only. That is, rather than being formed by four single pole, triple throw mechanical switches, in an actual embodiment of tl1e invention, S3, S4, S5 and S6 would be formed by plurality of semiconductor switches.
The zero/one (0/1) binary data signals produced by the data sync and control circuit, in accordance with the binary data produced by the data terminal tas received by the interface 57), are applied to the control input of the frequency controller 77. The frequency controller 77 includes two outputs, denoted one n) and zero (0). When the frequency controller 77 receives a binary 20 one data signal, the one (1) output of the frequency controller carries an enable signal. When the frequency controller receives a binary zero data signal, the zero output of the frequency controller 77 carries an enable signal. ~urther, when one of these output carries an enable signal, the other carries a disable signal. Thus, in essence, the frequency controller 77 forms a decoder that 25 enables one or the other of two outputs, based on the nature of its input. The function of the controller is readily accomplished by applying the 0/1 input directly to one output; and, inverting the 0/1 input and applying the inverted value to the other input.
The output of the crystal clock 53, shown in FIGURE 2 as applied 30 to the Fl/F2 frequency synthesizer 59, is connected to the clock inputs of both the Fl divider and the P2 divider. The enable input of the Fl divider is connected to the one (1) output of the frequency controller 77 and the enable input of the P2 divider is connected to the zero ~0) output of the frequency controller 77. The outputs of the Fl and F2 dividers are connected to control inputs of the switch 35 controller 83. The output of the switch controller 83 is connected to control the multiple switch 87.
A variable reference voltage denoted +VR is connected through RL~ in series with RlB to ground. The resistance value of RLA is equal to the resistflnce value of RlB. Thus, the voltnge at lhe junct;on between RlA and RlB
is ~VlR/2. This junction is con11ected to the noninverting input of the operational amplifier 85.
T}le magnitude of +Y~ is controlled by the output of the AGC
5 circuit 55 through a suitable control circuit (not shown)~ Alternatively, the AGC
circuit 55 could produce ~VR directly. In arly event, the value of +V~ is derived from the negative logarithrll of the amF)littlde of the received signal, as previously described.
As noted above, S3~ S4~ S5 and S6 are illustrated as separately 10 actuated, single pole, triple throw mechanical switches, everl though preferably formed of semiconductor switches~ In any event, each switch has a 'lcommon"
terminal and three "remote" terminnls. l?or purposes of description, the remote terminals S3, S~, S5 and S6 are denoted the upper remote terminal, the middle remote terminal and the lower remote terminal. This notation corresponds to 15 how the switches are illustrate~ in FIGURE 3. The upper remote terminal of S3, S4, S5 and S6 are all connected together and to ground. The middle remote terminal of S3, S4, S5 and S6 are all connected together and to the junction between RlA and RIB. The lower remote terminals of S3, S4, S5 and S6 are all connected together and to ~VR. The common terminal of S3 is connected 20 through R3 to the inverting input of the operational amplifier 85. The common terminal of S4 is connected through R4 to the inverting terminal of the operational amplifier 85 and the common terminal of S5 is connected through R5 to the inverting terminal of the cperationai amplifier 85. Finally, the cornmon terminal of S6 is connected through R6 to the inverting terminal of the 25 operational amplifier 85. The output of operational amplifier 85 is connectedthrough R2 to its inverting input. The output of the operational amplifier 85 isalso connected to the input of the Fl/F2 filter 61.
Turning now to a description of the operation of the frequency synthesizer illustrated in FIGVRF 3; in this regard, attention is directed to 30 FIGVRES 4 and 5, as well as FIGURE 3. As illustrate~ in FIGI~ RE 3, the frequency of the clock signal received by the frequency synthesizer 59 is equal to 18 x Fl x E72. This signal may be produced directly by the crystal clock 53 or may be formed by counting down a higher frequency clock signal. In any event, the 18x Fl x F2 clock signal is divided down by either the ~1 divider or the P2 divider, 35 depending upon which divider is enabled. More specifically, as previously discussed, the frequency controller 77 has two outputs, one cormected to the enable input of the Pl divider and the other connected to the enable input of the F2 divider. One and only one of the two outputs of the freguency controller 77 5 ~ 31. '1 e3 carrie~s an enable signal. Which output is deterrnined by the nature of the signal received by the frequency controller from the data sync and control circuit 519 as previously described. Thus, one and only one of the Fl and E;2 div;ders is enabled.
If the Fl divider is enabled, it produces a cignal at a frequency equal to 18~2,because the El divider divides tlle 18 x Fl x F2 signal by Fl. If the F2 divider is enabled, it produces a signal at frequency 18]?1, because the F2 divider s~ivides the 18 x Fl x F2 signal by F2. Whichever signal is produced, that signal controls the frequency of switch position changes produced by the switch controller 83. More specifically, the sequence of position changes of S3, S4~ S5 and S6 is fixed, as10 discussed below. However, the frequency of shifting from one switch position to the next switch position is controlled. This frequency control is based on whichone of the Fl and F2 dividers is enabled.
FIGURE 4 illustrates that there are nine (9) discrete switch position configurations utilized by the preferred embodiment of the invention, 15 which change in a stair step manner. The sequence is such that a decreasing stair step is followed by an increasing stair step to make up a waveform having a generally sinusoidal shape. Thus the nine positions are repeated, first in one direction (i.e., decreasing) then in the other direction (i.e., increasing). Thus, eighteen (18) separate step intervals define a complete cycle. While the pre-20 ferred embodiment of the invention includes nine discrete switch position configurations to create nine discrete voltage levels, it will be appreciated that other numbers can be chosen, depending upon the type and number of harmonics that are acceptable. Nine was chosen for the preferred embodiment because no harmonics lower than the seventeenth (17th) harmonic occur.
As will be understood from the foregoing description of FIGURE 3, and as shown in FIGURE 4, R3, R4, R5 and R6 can be referenced to either ground, +VR/2 or +YR. More specifically, when the common terminal of a particular switch (S3, 54, S5 or S) is connected to its upper remote terminal, its related resistor (R3, R4, R5 or R6) is referenced to circuit ground. When the 30 common terminal of a particular switch is connected to its center remote terminal, its related resistor is referenced to +V~/2. Further, when the common terminal of a particular switch is connected to its lower remote terminal, its related resistor is referenced to +VR. The stair step sinusoid~l waveform is created by controlling the switches such that the resistors are referenced to the 35 appropriate value at the appropriate point in the eighteen interval sequence. ln this regard, starting at the top of the sinusoid, R3 through R6 are all referenced to ground. That is, S3 through S6 are all positioned such that their respective common terminals are connected to their upper remote terminals. As a result, ~ ~ 5 ~

the highest output voltage producible is produced at the output of the operational amplifier 85. The next step in the sequence is to rnaintain S3, S4 and S5 positioned such that their re~istors (R3, R4 and R5, respectively) are referenced to ground and position S6 such that R6 is referenced to +YR/2~ As a result, the 5 output voltage of the operational amplifier 85 drops by a predetermined incremental value. lhe next step in the sequence is to maintain R3 and R4 referenced to ground by not changing the positions of S3 and S4; and, position S5 such that R5 is referenced to +VR/2, while maintaining R6 referenced to +V~/2.
As a result, the output voltage of the operational amplifier drops by a further 10 incremental amount. Next, R3 alone is maintained referenced to ground while R4, R5 and R6 are ~11 referenced to +VR/2. As a result, the output voltage dropsby a further incremental amount. Next, R3, R4, R5 and R6 are all referenced to +VRj2 whereby a further incremental drop in the output of the operstional amplifier 85 occurs. The next step is to maintain R4, R5 and R6 referenced to 15 +VR/2 while referencing R3 to +VR. This result is created by causing S3 to connect its common terminal to its lower remote terminal while mnintaining S4, S5 and S6 positioned such that their common terminals are all connected to theirmiddle remote terminals. As a result, the output voltage drops by a further incremental amount. The next step is to cause S3 and S4 to connect their 20 common terminals to +VR while maintaining S5 and S6 positioned such that their common terminals are connected to their middle remote terminals. Again, the output voltage drops by a further increment. The next step is to cause R3, R4 and R5 to all be referenced to +VR while maintaining R6 referenced to +VR/2.
This results in a further incremental drop in the output voltage. Finally, R3, R4, 25 R5 and R6 are all referenced to +VR, whereby the output voltage of the operational amplifier drops to its minimum value. This declining stair step voltage is followed by an inclining stair step voltage during which the foregoing sequence is reversed. The end result is a declining stair step followed by an inclining stair step, the totality of which has a sinusoidal configuration if the 30 values of R3, R4, R5 and R6 are chosen so that the appropriate ratios exist therebetween. In this regard, the appropriate ratios will exist if R3 = 29.4K, R4 = 33.2K, R5 = 45.3K and R6 - 84.5K.
In summary, the amplitude of the waveform is controlled by a reference voltage (+VR) derived from the amplitude of the received signal via 35 the AGC circuit. The two divider resistors (RlA and RlB) produce a voltage ofone-half the reference voltage, which is applied to the noninverting input of the operational amplifier 85. The output of the amplifier is controlled by R2 and the summing resistors R3 through R6, which ~re switched by switches S3 through S6 so as to be referenced to one of the three p,ossible voltages consisting of +VR,~VR/2 and circuit ground. The output of the oE~erational amplifier is filtered by the Fl/F2 filter, which passes the fundamental frequencies of Fl and ~2 and feeds them to the coupling transformer 45.
The length of the step intervals of the stair step waveform are controlled by counting down a clock signal eqllal ~o the number of step intervals ~8~ times the desired frequency (E;l or F2). Producing a clock signal that is equal to the number of step intervals times both Fl and F2, and dividing the signal bythe undesired frequency, Fl or F2, results in a clock signal at a frequency equal to the desired frequenc$l times the number of intervals. The switch controller, in accordance with this clock signal causes S3 through S6 to change positions, at 18 times the desired frequency. As a result, the composite stair step waveform has a frequency equal to the desired frequency.
By wny of example only, the swi$ch controller could comprise an eighteen state ring counter clocked by the output of the enabled divider; and, adecoder ior controlling the position of the switches based on the state of the ring counter.
It is highly desirable, if not mandatory, that the signals produced by the frequency synthesizer have two important properties. First, it is desirable that changing from one frequency to the other occurs without loss of coherence of the phase oE the sine wave of the overall signal. FIGURE 5 illustrates how the frequency synthesizer of the invention achieves this important result~ Specifi-cally, for purposes of illustration only, FIGURE S illustrate~s a signal wherein F2 is equal to twice the frequency of Fl. As noted above, in an af tual embodiment of the invention, F2 would be close to, but spaced from Fl by a small amount, such as 1~ percent of Fl. However, so related signals are difficult to illustrate.
As a result, FIGURE 5 uses a 50 percent frequency difference to illustrate how phase coherence is maintained. More specifically, FIGURE 5 illustrates on the right an Pl stair step sinusoidal waveform, representing a binary zero signal, as shown on the bottom line of FIGURE 5. At this time~ the F2 divider is enabled.
At time X, the digital input shifts from zero to one. As a result, the F2 divider is disabled and the Fl divider is enabled. Since the switch controller controls the sequence of switch position changes, the switches continue in the same sequence when the divider enablement changes. That is, the divider enablement only changes the step interval changes, not the magnitude of the step interval voltages. As a result, a smooth transition from Fl to F2 occurs at point ~. At point Y, the signal shifts back from F2 to Fl, as the result oi the binary data changing from one to zero. Again, only the step interval changes, whereby a smooth transition occurs from I'2 to Fl. Hence? the invention provides a fregllellcy synthesizer wherein frequency shif~s between Fl and F2, and ~rice versa, occur without si~lificant changes in phase. As a result, the coherence ofthe phnse of the sinusoidal wave is maintP~ined through the frequency shift. It S will be appreciRted that maintaining phase coherence reduces the bandwidth occupied by the synthesized signal.
The second important requirernent of the waveform of the signal produced by the frequency synthesizer is that it ~e very low in harmonics at or near the frequency of Ule signal ~o be recei~ed. That is, Fl and F2 form FSK
10 signals to be translllitted. In order for these signals not to interfere with the FSK signals to be received (i.e., F3 and F4), Fl and F2 must be low in F3 and E4harmonics. In this regard, as noted above, F3 and F4, preferably, are equal to twice the freqency of Fl and F2, respectively. As a result, it is necessary thatthe frequency synthesizer produce signals that are substantially free of second 15 harmonics. If the signals are not substantially free of second harrnonics, the transmitted signal will interfere with the received signals and cause errors. This avoidance of interfering harmonics is of particular significance because the magnitude of the transmitted signals can be easily 40db higher than the receivedsignals. The frequency syr thesizer of the present invention produces waveforms 20 that avoid this problem. More specifically, it can be shown theoretically, and has been verified experimentally, that if the amplitude of the steps of the stair step sinusoidal waveform are chosen properly, the first nonzero harmonic component of the fundamental frequency F is at the frequency 17F. Because the first significant harmonic is the 17th harmonic of the fundamental frequency, the 25 produced waveform requires very little in the WQy of filtering to create a pure sinusoid of frequency El or F2. Thus, harmonic interference is avoided and an accurate frequency controlled signal digitally derived from ~ crystal oscillator is produced~
FIGURE 6 is a block diagram of a receiver 47 suitable for use in 30 the modem illustrated in FIGURE 2 and comprises: the F3/P4 filter 63; the amplifier 65; and, the frequency detector 67. The frequency detector 67 is illustrated QS comprising an interval timer 91; a decoder 93; a guarding circuit 95;
and, a zero crossing detector 97. As previously discussed with respect to FIGURE 2, the coupling transformer 45 is connected through the F3/F4 filter to 35 the input of the amplifier 65. As illustrated in FIGURE 6, the output of the amplifier 65 is connected to an input of the zero crossing detector 97 and to the AGC circuit. The output of the zero crossing detector is connected to a reset input of the interval timer 91 and a control (read~ input of the decoder 93.

~ urther, the clock signal produ( ed by the crystnl clock 53 is connected to theclock inpllt of the interv~l timer 91. Ihe oulputs of appropriate stages of the interval timer 91 are connected to the decc~er 93. Selected outputs of the decoder 93 are cormected to the guarding circuit 95 and the output of the 5 guarding circuit 95 is connected to the data sync and control circuit 51. In addition, the decoder 93 is connected to output terminals denoted TROUBLE
INDICATOR and INTERNAL CON I`ROL, which are r epresentative of various outputs hereinafter described.
The F3/F4 filter fi3 passes F3/F4 signals, which are amplified by 10 the amplifier 65. The zero crossing detector 97 converts the amplified signalinto a square wave9 which is applied to the reset input of the interval timer 91.
The interval timer 91 is adapted to be reset either on each low to high rise of the signal applied to its reset input or each high to low fall. Regardless of whether a rise or a fall is chosen to reset the interval timer, the timer is reset at the same 15 point in each square wave cycle. Thus, the interval timer counts clock pulses for each cycle. Just prior to being reset, the interval timer count is read by the decoder 93.
At the end of esch count, the decoder 93 categorizes the time interval counted by the interval timer into one of five categories denoted M, N,20 O, P and Q in FIGURE 7. Interval M extends from zero to some predetermined time Tl. If the decoded count falls fall in this interval (M), the frequency of the received signal ;s higher than F4. The next interval, denoted interval N, lie between Tl and a later time denoted T2. If the decoded count lies in interval N,i.e., between Tl and T2, the frequency of the received signal is F4 (or near 25 enough to F4 to be considered a valid F4 signal); and, a binary 1 is applied to the guarding circuit 95. The next interval, denoted interval O, lies between T2 and a later time denoted T3. If the incoming signal falls in interval O, the frequencyof the received signal lies between F3 and F4, but not close enough to either F3or ~4 to be recognized as either a valid F3 or F4 signal. The next interval, 30 denoted interval P, lies between T3 and a later time denoted T4~ If the decoded count indicates that the frequency of the received signal lies in interval P, the frequency of the received signal is F3 (or near enough to F3 to be considered a valid F3 signal); and, the decoder applies a binary zero to the guarding circuit 95.
Finally, if decoded count indicates that the frequency of the received signal has 35 a period greater than T4, the signal lies in interval Q, which means that the frequency of the received signal is less than the F3 frequency.
In summary, the interval timer applies a clock pulse count to the decoder. The pulse count is related to the period of the received signal. The decoder decodes 1:he pulse CO~ t and calegoriZes the time Interval into one of five categorics. The clccoder classifies counts falling in interval N as the receipt of a binary one and those fallinE~ in interval P as -the receipt of a binary zero.
Preierably, the output o~ the decoder is a DC signal whose level denotes nature ~0 or 1) o~ the decoded bit~ The decoded ones and ~eros are applied to the guarding circuit 95, which ir-sures that the one or zero is not the result of transient noi~e or an interfering siE~nal by requiring that the one or zero exist for at least two S~JCCessiVe intcrvals. That is, the nature of the received signal must remain constant for at least two sinllsoidal waveIorms before the signal is acknowledged by the guarding circ-l;t S5 as a valid zero or one; and, forwarded to the data sync and control circuit 51. lllus, if the guarding circuit is outputting a level corresponding to a zero, it will change to a one if, and only if, it receives two successive signals in category N irom the decoder 93. Alternatively, iI the guarding circuit 95 is outputting a level corresponding to a one, it will change to a zero if, and only i~, it receives two successive signals in category P from the decoder 93.
Signals in categories M, O or Q cause signals on the TROUBLE
INDICATOR or INTERNAI CONTROL outputs, as appropriate. For example, signals in category C) could create a TROUBLE INDICATOR output. A series of such outputs could be used to indicate to the subscriber that the received FSK
signal is falling between the two data bit signals. This would, or course, indicate to the subscriber that the circuitry is functioning incorrectly. Alternatively, a succession of signals in category Q could be used to indicate to the modem that it should connect its input to its output for remote test purposes. Obviously, these are only two of many examples of how the TROUBLE INDICATOR and INTERNAL CONTROL signals can be used.
Frequency detectors of the type generally illustrated in FIGURE 6 are well known to those skilled in the telephone and other communication arts.
In this regard, attention is directed to U.S. ~'atent 3,917,912 entitled "Multifrequency Dialing Signal Receiver for Push-button Type Telephone Systems" and to U.S. Patent 4,145,576 en~itled "DTMF and Rotary Dial Pulse Digit Receiver", both of which disclose in detail Irequency detectors that include time interval counters, decoders and guarding circuits, as part of other systems.
FIGURE 8 is a block diagram o~ a repeater suitable for use in the audio and fulJ duplex digital data carrier system illustrated in FIGURE I and comprises: two voice Irequency (YF~ filters 101 and 103; two sets of coupling capacitors 105A and B and 107A and B; two coupling tranIormers 109 and 111; two -~2-

2 fillers 113 llnd 115; two con~Io~lAble aTnplifier; 117 and 119; two frequ~ncy doublers 121 and 123; two automatic gain contI ol (AGC~ circuits 125 and 127; two F3/F4 filters 129 and 131; ~wo fixed flmplifiers 133 and 135; and, a loopback switch 137~ Pair 1, which is connected to the central office end of the tip and ring wire 5 pair running lo subscriber A via the horizootnl and vertical main distributionframes, as illustrRted in FIGURE I and previously described, is connected to oneside of the first voice frequency filter 101. The other side of the first voice frequency filter is connected to pnir 4. Pair 1 is also coupled via the first pair of coupling capacitors 105A and 105B to one side of the first coupling transformer 10 109. The other side of the coupling transformer 109 is connected between ground and the input of the first Fl/F2 filler 113. The output of the first Fl/F2 filter 113 is connected through the first controllable amplifier 117 to th~ input of the first frequency doubler 121. The output of the first frequency doubler 121 is connected to the input of the first automatic gain control circuit 125, whose output is 15 connected to the control input of the first controllable amplifier 11~. The output of the first frequency doubler 121 is also connected through the first F3/F4 filter 129 to the input of the first fixed amplifier 133. Similarly, pair 2 (which is connected to subscriber B) is connected to one side of the second voice filter 103 and the other side of the second voice filter 103 is connected to pair 3. Pair 2 is 20 also coupled by the second pair of coupling capacitors 107A and 107B to one side of the second coupling transformer 111. The other side of the second coupling transformer 111 is connected between ground and the input of the second Fl/F2 filter 115. The output of the second FVF2 filter 115 is connected to the input of the second controllable amplifier 119. The output of the second controllable 25 amplifier 119 is connected to the input of the second frequency doubler 123; and, the output of the second frequency doubler 123 is connected to the input of the second automatic gain control circuit 127. The output of the second automatic gain control circuit 127 is connected to the control input of the second controllable amplifier 119. The output of the second frequency doubler 123 is also 30 connected through the second F3/F4 filter 131 to the input of the second fixed amplifier 135.
The loopback switch 137 comprises two single pole, double throw switches 139 and 141 ganged together. Thus, each switch has a common terminal and two remote terminals. The cornmon terminal of the first switch 139 is 35 connected to the output of the first fixed amplifier 133. The common terrninal of the second switch 141 is connected to the output of the second fixed arnplifier 135. The remote terminals of the switches are connected together on aone-t~one basis such that when the common terminal of one switch is connected I 11 ~? ~317 -2~-to a particuIar one of its remote terminRIs, the common terminal of the other switch is connected to the other rernote terminal. Further, the common connection between one set of remote terIllinals is connected to the junction between the second coupling transformer 111 and the input of the se~ond ~71/P2 5 filter 115; and, the common connection between the other set of remote terminals is connected to the junction between the first coupling transformer 109 and the input of the first Fl/F2 filter 113.
In operation, the first and second voice frequency filters 101 and ll)3, of course, prevent the FSK data signals from being applied to the line 10 switching equipment of the central office 11. The pairs of coupling capacitors 105A, B and 107A, B couple the transmitted FSK signals (i.e., Fl and F2) to the coupling transformers, which in turn, couple these signals to the Fl/F2 filters.The filtered Fl and F2 signals are amplified by the controllable amplifiers 117 and 119 and, then~ the signal frequency is doubled by the frequency doublers 121 and15 123. After doubling, whirh converts Fl signals into F3 signals and F2 signals into F4 signals, the signals are filtered by the F3tF4 filters 129 and 131. Thereafter, the F3 and F4 signals are applied to the opposing loop via the loopbQck switch 137 and the other channel's coupling transformer and coupling capacitors. The AGC
circuits 125 and 127 feedback gain control signals around the frequency doublers20 to assure proper operation.
By way of a specific example, when digital data is being transmitted by subscriber A, the Fl and F2 FSK signals are coupled by the first pair of coupling capacitors 105A and 105B and the first coupling transformer 109to the input of the first FVF2 filter 113. The output of the first Fl/F2 filter is 25 amplified by the first controllable amplifier 117. Thereafter, the frequency of the transmitted FSK signals are doubled by the frequency doubler 121. The resultant F3 and F4 FSK signals are filtered by the first F3/F4 filter 129 and amplified by the first fixed amplifier 133. The amplified F3 and F4 FSK signals are then fed by the loopback switch to subscriber B's pair of telephone wires via 30 the second coupling transformer 111 and the second pair of coupling capacitors 107A and 107B. Similarly, Fl and F2 FSK signals transmitted by subscriber B are coupled via the second pair of coupling transformers 107A and 107B and the second coupling transformer 111 to the input of the second Fl/F2 filter 115. These signals are filtered by the second Fl/F2 filter 115, and amplified by the second35 controll~ble amplifier 119. After being amplified, the frequency of the Fl and P2 PSK signals produced by subscriber B ~re doubled by the second frequency doubler 123 and, thus, converteà into F3 and ~4 FSK signals. The F3 and F4 PSK
signaLs are filtered by the second F3/1;4 filter 131 and, then, amplified by the -2~1-second fixed ainplifier l35~ '~fter umplifiealio~ he ;e signals are applied to the pair of telephone wires running to subscriber A via lhe loopback switch, the first coup1ing transformer -LO9 and lihe first pair of coupling capacitors 105A and 105B.
~ will be readily appre~iated by those skilled in the electronics art, the first and seconcl fixed amplifiers 133 and 135 must have high output impedances.
Alternatively, if low output impedance amplifier; (such as operational amplifiers) are chosen, n suitable high impedance coupling circuit ~such as a tank circuit) rnust be connected in eircuit between the output of the amplifiers and the re]ated junction between the coupling transformers and the F1/F2 filters.
Preferably, tlle frequency doublers merely full wave rectify the signals they receive to double the frequency o~ these signals. ln addition, ;t should be noted the loopback switch can be positioned so as to "loop back" incoming signals fromboth subscribels to their respective origins. This can be done for test purposes or, if desired, to prevent transmitted FSE~ signals from being received by the other 15 subscriber's modem.
It will be appreciated from the foregoing description that a modem for an audio and full duplex digital data calrier system is provided by the invention.
Even though only a single pair of nonloaded wires are required, full duplex digital data transmission, plus simultaneous audio communication can take place. That is, 20 full duplex digital data transmission between a pair of subscribers, plus regular audio communication can take place simultaneously all on the same single pair of wiresconnecting each subscriber to the same central office.
FIGURE 9 is a partially block and partially pictorial diagram of a digital data transmission system for communicating between a plurality of telephone 25 stations and a data processing center. Included in FIGURE 9 are a plurality OI
telephone stations 211 denoted Station 1, Station 2 . . . Station N; a private automatic branch exchange (PABX) or central office (CO) of a telephone company (TELCO~ 213; and, a data processing center 215. Each station 211 includes a modem 221; a telephone 223; and, a data terminal 225. The telephorle 223 and the data 30 terminal 225 of the station~s are connected to their respsctive modems 221. The modems, in turn, are connected to the station ends of nonloaded loops 227, which run to protectors 231 forming part of the PABX or CO 213. The protectors 231, in turn, are connected through the vertical main distribution frame (MDF) 233 in a conventional manner to the horizontal MDF 235. The terminals of the horizontal 35 MDF 235 are, in turn, conneeted to a PABX or CO subsystem 237, which includesmodems and a data multiplexer/demultiplexer as llereinafter described. In addition to being connected to the PABX or CO end of the wires running to the stations 211, the PABX or CO subsystem 23~ is also connected via the horizontal main distributioIl frame ~5 to the line ~ witching equipment 239 of the PABX or CO 213.
For purp~;ex ot identi~icfltion, the terminals oî the PAE~X or CO subsystem connected lo tlle :tations are correspondincrly denoted l, 2 . . . N. The corresponding terminals of the PAE~X or CO subsys~em connected to tlle Line switching equipment are also denoted 19 2 . . . N.
In nddition to being connected to the stations 211 and the line switching equipment 2l3, the PABX or CO subsystem 237 is also connected via the hori~ontal MD~ 235 and the vertical MDE; 233 to the dala processing center 215 via a pair of ~vires. The terminals of the PA13X or CO subsystem connected to the data tO processing center 215 are denoled M in FIGURE 9~
The station modems 221 are similar to the subscriber modems illustrated in FIGURE 2 and connec~ the telephones 223 to the related pair of tip and ring telephone wires forming the nonloaded loop through an audio or voice requency filter, which prevents the transmitted and received digital data signals from being applied to the telephones and prevents spurious high frequency signals generated by the telephone from reaching the nonloaded loops. The F1 and F2 FSK signals produced by the station modems are forwarded to the PABX or CO subsystem 237 via the related nonloaded loop 227; and9 vertical and horizontal MDFs 233 and 235.
As will be better understood from the following description of FIGURE 10, the PABX or CO subsystem includes a modem dedicated to each station. The PABX or S~O modems reconvert the signals they receive from F1/F2 FSK form into binary form. The data from the PABX modems is multiplexed by a multiplexer/demultiplexer and the multiplexed binary data is transmitted to the data processing center via the horizontal and vertical MDFs and the pair of connecting wires. At the data processing center 215, the received data is demultiplexed by a multiplexer/demultiplexer 241; and, the demultiplexed data is applied to a computer 243 via an interface 245.
When the computer desires to transmit data to a particular data terminal, the binary data produced by the computer is applied through the interface 245 to the multiplexer/demultiplexer 241 of the data processing center 215, where it is multiplexed with data destined for other data terminals. The multiplexed data is transmitted to the PABX or CO subsystem 237 where it is demultiplexed and applied to the related modem of the PABX or CO subsystem. The modems convert the demultiplexed data from binary form into FSK form, but at a different pair of FSK
signal frequencies. More specifically, the FSK signals produced by the PABX or CO
modems are at frequencies F3 (binary zero) and F4 (binary one), which are separated from F1 and F2 by a suitable bandwidth. The FSK signals produced by the PABX or CO modems are transmitted to the station modems via the hori2;ontal MDF 235, the ~ 1~9~7~
-2fi-ver~ical Mr)~ 233 ~nd the related nonloaded loop 227. The station modem reconvertx the FSK signal it recieves in~o ~he related binary signals and forwards the binary sigrlals to the associated dat~ ~erminal 225.
FIGUl~E 10 is a block diagraln of a PABX or CO subsystem 237 5 sui~able for use in the digital data carrier ;ystem iUustrated in FIGURE 1 andcomprises: a plurality of P~RX or CO modc ms 28t-1, 281-2 . . . 281-N; and, a multiplexer/demultiplexer 283. Since the PABX or CO modems are identical, only the PABX or CO modern 281-l related to Station 1 is illustrated in detail in FIGURE

3.
Eacll of the PABX or CO modems 281-1, 281-2 . . . 281-N include. a voice frequency (VFl filter 291; a pair of coupling capacitors 293A and 293B; a coupling transIormer 295; a receiver 297; a transmitter 299; a data sync and control circuit 301; a crystal clock 303; and, an interfaee 305. As iUustrated in FIGURE 10, the central office end OI the tip and ring pair of nonloaded wires running to Station 15 1, are connected through the VF filter 291 to the PABX or CO line switching equipment. As with the station modems, the voice frequency filter 291 is bidirectional, i.e., voice signals can pass to and from the PABX or CO line switching equipment; however, F1, F2, F3 and F4 FSK signals are prevented from being applied to the line switching equipment. Further, high frequency noise signals generated by 20 the PABX or CO are prevented from reaching the nonloaded telephone wires by the VF filter 291.
The central office end of the nonloaded wires running to Station 1 are connected via the coupling capacitors 293A and 293B to one side of the coupling transformer 295. The other side of the coupling transformer 295 is connected to the 25 input of the receiver 297 and to the output of the transmitter 299. The output of the receiver 297 is connected to an input of the data sync and control circuits 301 and the input of the transmitter 299 is connected to an OUtpllt of the data sync and control circuit 301. In addition, the data sync and control circuit 301 is connected to the crystal clock 303 so as to receive cloclc pulses. Further, the data sync and 30 control circuit 301 is connected through the interface 305 to the multiplexer/demultiplexer 283. The multiplexer/demultiplexer 283 is connected tothe multiplexer/demultiple2cer of the data processing center 215 as illustrated in FIGURE 9 and previously described.
The receiver 297 includes: an F1/F2 filter 311; an amplifier 313; and, 35 an F1/F2 frequency detector 315. The input of the F1/F2 filter 311 is connected to the receiver side of the coupling transformer 295 and only passes FSK signals in the F1/F2 frequency range. The output of the F1/F2 filter 311 is connected through the amplifier 313 to the input of the F1/F2 frequency detector 315. The output of the -2~-F l/~ 2 fre(~ ncy detector is conneeterl to th~ dlat~ syrlc and control circuit 301.
~s ~ill he appreciated from the î~regoitlg description, the receiver 297 of the YAF3X or CO rnodems are generally similar to the receiver 47 of the statiorl modern~;, except that the input filter is adap~ed to pflSS F1/F2 signals, rather than ~3/F~ si~nals; and, the frequell~y detector is adapted to detect F1/F2 signals, rather than F3/~4 signnls. In asly event, as with the frequency detector of the receiver of the stfltion moderns, the Erequency detector 315 of the receiver 297 of the PABX or CO moderns detects the presence of T~l and ~2 signals and, in accordance therewith, produces binary ~eros and ones, which a~e applied to the data sync and control circuit 301 The transmitter 299 of the P~BX or CO modems includes an F3/F4 frequency synthesizer 317 and an F3/F4 filter 319. The frequency synthesizer receives the 0/1 binary data signals forwarded by the data sync and control circuit 301 in the manner herein described. In addition, the F3/Ei4 freqllency synthesizer receives clock pulses produced by ~he crystal clock 303. In accordance therewith, the frequency synthesi~er produces F3 and F4 signals. These signals are applied to the F3/F4 filter 319, which is a bandpass filter that passes signals in the F3/F4 range and rejects signals at other frequencies. The filtered F3/F4 signals are applied to the coupling transformer 295 and, from there, to the tip and ring pair forming the nonloaded telephone line.
The data sync and control circuit 301 ;s connected to the multiplexer/demultiplexer 283 via the interface 30l. Thus, binary digital data produced by the PABX or CO modems is available for multiplexing by the multiplexer/demultiplexer. Further, the multiplexer/demultiplexer is connected to tile data processing center. As a result multiplexed data is sent to the data processing center. In addition, data processing center multiplexed data is forwarded to the appropriate PABX or CO modem after demultiplexing by the multiplexer/demultiplexer 283.
Turning now to a more detailed description of the operation of the digital data transmission system illustrated in FIGURE 9; when the data terminal225 of a station produces data, its related station modem 221 converts the binary digital data into F1/F2 signals, as previously described. These signals are transmitted via the associated nonloaded loop 227 to the receiver of the relatedPABX or CO modem. The receiver 297, reconverts the F1/F2 digital data signals into binary digital datfl form. The binary digital data is synchronized by the data sync and control circuit in accordance with pulses received from the crystal clock 303 in a conventional manner and the synchronized data is forwarded by the interface 305 to the multiplexer/demultiplexer 283. The multiplexer/demultiplexer --~8-mul tipl~xe; the bhl~lry digitai data it rec~i~re~i frGm the various PABX or CO
rnodems and forwa~ds the mul~iplexed data to ~he data processirlg center where it is demultiplexed nnd applied to the computer via the interface 245 as previouslydescribed. When the computer produces binary digital data to be forwarded to thevarious statlons, it is multiplexed by the data processing center multiplexer/demultiplexer 241 and forwarded to the multiplexer/demultiplexer 283of the PABX or CO subsystem. The multiplexer/demultiplexer of the PABX or CO
s~lbsystem, iLlustrated in F[GURE lO, demultiplexes binary digital data receivedfrom the data processing center and applies appropriate station data to the related PABX or CO modem via the interface and data sync and control circuitO The transmitters of the PABX or CO modems, in accordance therewith, convert the binary digital data into F3/F4 FSK digital data and forward the data through theF3/F4 filter to the nonloaded loop rlmning to the related station. As previouslydescribed, the F3/F4 signals received by the receiver of the related stations are converted by the F31F4 frequency detectors into binary ~ero and one signals. Theresultant binary zero and one signals are applied via the data sync and control circuits and the interface of the stations to their respective data tarminals~ The foregoing sequence of operation can occur simultaneously with transmission of baseband telephone signals over the tip and ring pairs of telephone wires without 2û interference between the two different types of communication signals provided the F1, F2,F3 and F4 signals Ue well outside the baseband frequency range.
While a preferred embodiment of the invention has been illustrated and described, it will be appreciated that various changes can be made therein without departing from the spirit and scope of the invention. For example, while5 preferably, the frequency of F3 and F4 are twice the frequency of Fl and F2, respectively, obviously, other frequency relationships can be utili~ed if desired. In faet, the F3 and F4 signal frequencies do not even have to be integral multiples of the F1 and F2 signal frequencies. However, if the illustrated relationship is maintained, the overaU system can be made as uncomplicated as disclosed.
Further, the higher frequencies (F3 and F4) could be transmission frequencies, rather than the reception frequencies, if desired. Still further, the system can be used for digital data transmission without a simultaneous audio capability, if desired. Hence, the invention can be practiced otherwise than as specifical:ly described herein.

Claims (14)

1. The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows.
   
   l. A modem suitable for simultaneously converting digital data from binary signal form into FSK signal form and from FSK signal form into binary signal from, said modem comprising:
   a transmitter, said transmitter including a frequency synthesizer for converting digital data from binary signal form into FSK signal form such that abinary zero (0) causes said FSK signal to have a first frequency, F1, and a binary (1) causes said FSK signal to have a second frequency, F2, said frequency synthesizer producing said F1 and F2 signals in a manner that maintains phase coherency during shifts between said F1 and F2 signals in a manner such that the waveforms of said F1 and F2 FSK signals are substantially free of harmonics at third and fourth frequencies, F3 and F4; and, a receiver, said receiver including a frequency detector for detecting an FSK signal at said third and fourth frequencies, F3 and F4, and converting digital data from FSK signal form into binary signal form such that an FSK signal at said third frequency, F3, causes a binary zero (0) and an FSK signal at said fourth frequency, F4, causes a binary one (1).
2. 2. A modem as claimed in Claim 1 wherein the frequencies of F3 and F4 are integral multiples of the frequencies of F1 and F2, respectively.
3. 3. A modem as claimed in Claim 2 wherein the frequencies of F3 and F4 are twice the frequencies of F1 and F2, respectively.
4. 4. A modem as claimed in Claim 3 wherein said frequency synthesizer produces signals at said F1 and F2 frequencies having a stair step approximation of a sinusoidal waveform.
5. 5. A modem as claimed in Claim 4 wherein a single cycle of the stair step approximation of the sinusoidal waveform signals produced by said frequency synthesizer includes 18 equal step intervals.
6. 6. A modem as claimed in Claim 5 wherein said frequency synthesizer includes:
   a voltage source;
   an operational amplifier;
   
   a voltage divider connected between said voltage source and ground, said voltage divider including a tap connected to one input of said operational amplifier;
   a feedback resistor connected between the output of said operational amplifier and the other input of said operational amplifier;
   a resistance network comprising a plurality of resistors, one end of each of said plurality of resistors connected to said other input of said operational amplifier;
   switching means connected between the other ends of said plurality of resistors and ground, the tap of said voltage divider and said voltage source; and, control means for controlling said switching means such that the other end of said plurality of resistors are selectively connected to ground, the tap of said voltage divider and said voltage source.
7. 7. A modem as claimed in Claim 6 wherein said control means comprises:
   a first divider for dividing a clock signal by F1;
   a second divider for dividing a clock signal by F2;
   a clock source for producing clock pulses at a frequency equal to 18 x F1 x F2, said clock source being connected to the clock inputs of said first andsecond dividers;
   a frequency controller connected to receive binary form digital data signals and, in accordance therewith, enable one or the other of said first and second dividers; and, a switch controller connected to the outputs of said first and second dividers so as to be controlled by whichever one of said first and second dividers is enabled, said switch controller connected to said switching means to control theoperation of said switching means.
8. 8. A modem as claimed in Claim 1 including an automatic gain control circuit connected between said receiver and said transmitter of said modem such that the logarithm of the amplitude of the F1 and F2 FSK signals produced by said frequency synthesizer of said transmitter is controlled by the negative logarithm of the amplitude of the F3 and F4 FSK signals received by said receiver.
9. 9. A modem as claimed in Claim 1 wherein said frequency synthesizer produces signals at said F1 and F2 frequencies having a stair step approximation of a sinusoidal waveform.
10. 10. A modem as claimed in Claim 9 wherein a single cycle of the stair step approximation of the sinusoidal waveform signals produced by said frequency synthesizer includes 18 equal step intervals.
11. 11. A modem as claimed in Claim 10 wherein said frequency synthesizer includes:
    a voltage source;
    an operational amplifier;
    a voltage divider connected between said voltage source and ground, said voltage divider including a tap connected to one input of said operational amplifier;
    a resistance network comprising a plurality of resistors, one end of each of said plurality of resistors connected to said other input of said operational amplifier;
    switching means connected between the other ends of said plurality of resistors and ground, the tap of said voltage divider and said voltage source; and, control means for controlling said swtiching means such that the other end of said plurality of resistors are selectively connected to ground, the tap of said voltage divider and said voltage source.
12. 12. A modem as claimed in Claim 11 including an automatic gain control circuit connected between said receiver and said transmitter of said modem such that the logarithm of the amplitude of the F1 and F2 FSK signals produced by said frequency synthesizer of said transmitter is controlled by the negative logarithm of the amplitude of the F3 and F4 FSK signals received by said reciever.
13. 13. A modem as claimed in Claim 12 wherein the magnitude of the voltage produced by said voltage source is controlled by said automatic gain control circuit.
14. 14. A modem as claimed in Claim 13 wherein said control means comprises:
    a first divider for dividing a clock signal by F1;
    a second divider for dividing a clock signal by F2;
    a clock source for producing clock pulses at a frequency equal to 18 x F1 x F2, said clock source being connected to the clock inputs of said first andsecond dividers;
    a frequency controller connected to receive binary form digital data signals and, in accordance therewith, enable one or the other of said first and second dividers; and, a switch controller connected to the outputs of said first and second dividers so as to be controlled by whichever one of said first and second dividers is enabled, said switch controller connected to said switching means to control theoperation of said switching means.