CA1137581A - Low-frequency supplementary information transmitting arrangement for a digital data transmission system - Google Patents
Low-frequency supplementary information transmitting arrangement for a digital data transmission systemInfo
- Publication number
- CA1137581A CA1137581A CA000343230A CA343230A CA1137581A CA 1137581 A CA1137581 A CA 1137581A CA 000343230 A CA000343230 A CA 000343230A CA 343230 A CA343230 A CA 343230A CA 1137581 A CA1137581 A CA 1137581A
- Authority
- CA
- Canada
- Prior art keywords
- parity
- signal
- digital data
- supplementary information
- data signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/12—Arrangements providing for calling or supervisory signals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
Abstract
ABSTRACT OF THE DISCLOSURE:
A supplementary information transmitting arrangement for a digital data transmission system in which the supplementary information is a low-frequency wave modulated or not modulated.
There is provided means for modulating the ?high? level parity of the incoming digital data signal by the low-frequency wave and means for restoring the low-frequency wave from the outgoing resulting digital signal from said modulating means. The incoming digital signal can be binary or ternary coded and, if binary coded, be scrambled. The modulating of the ?high?
level parity is performed, in dependence on the period or phase of the low-frequency wave, by inserting a predetermined word or by modifying a ternary word when the incoming binary slgnal is scrambled and converted in ternary code.
A supplementary information transmitting arrangement for a digital data transmission system in which the supplementary information is a low-frequency wave modulated or not modulated.
There is provided means for modulating the ?high? level parity of the incoming digital data signal by the low-frequency wave and means for restoring the low-frequency wave from the outgoing resulting digital signal from said modulating means. The incoming digital signal can be binary or ternary coded and, if binary coded, be scrambled. The modulating of the ?high?
level parity is performed, in dependence on the period or phase of the low-frequency wave, by inserting a predetermined word or by modifying a ternary word when the incoming binary slgnal is scrambled and converted in ternary code.
Description
1137~8~
The present invention relates to digital data trans-mitting systenswhich convey digital words whose digits can have two levels (1, 0) as a binary word, or three levels (-1, 0, 1) as ternary word. In the following specification, the high level (H>~ level) indicates 1>~ levels, whether the levels are positive or negative.
In known digital data transmitting systems of this kind, it is often difficult to transmit a supplementary infor-mation without, firstly, increasing the complexity of the trans-mission and reception equipment and, secondly, without resortingto the use of a supplementary transmission support, such as an auxiliary pair of coaxial cables.
The main object of this invention is to provide a sup-plementary information transmitting arrangement for a digital data transmission system, in which the transmission of the sup-plementary information is performed without resorting to the use of an auxiliary transmission support, in cases where an existing transmission equipment is available, this existing equipment being associated with one or a number of reception equipments constituted by very simple circuits.
More particularly, the present invention proposes a supplementary information transmitting arrangement for a digital data transmission system comprising means receiving an incoming digital data signal and a digital supplementary information si-gnal having a rate much lower than that of the incoming digital data signal for inserting parity check words in the incoming data signal into a resulting digital data signal, the logic levels of digits of the parity check words being as a function of the logic level of the supplementary inforrnation signal so that the accumulated parity of the resulting digital data signal is constant between two successive parity check words, and B. 'h~'i -- 2 ~
1~37S81 means receiving the resulting digital data signal including the parity check words for detecting parity modifications in the resulting data signal to restore the supplementary information signal.
~ ccording to the invention, it is possible to transmit simultaneously with the digital signal from the transmission equipment a low-frequency wave. The low-frequency wave may then . in itself constitute the supplementary information, or alternati-vely it can be modulated by the supplementary information. For transmitting the low-frequency wave, the transmission arrange-ment according to ~137581 the invention entails a ~<H levels parity check. It is already known to use in repeaters H level parity check method for detecting the rate of operating errors. This method ls described in articles Nos. 59 and 54 of the Study Commission XVIII and IV of the International Telegraph and Telephone Consultative Committee. According to this known method, the H level parity between predetermined instants must be even in the absence of error, i.e. the number of H levels (high levels) between these predetermined instants is even.
According to this invention, the H level parity is not constant, but alternates. Accordingly, a supplementary information transmitting arrangement for a digital data transmission system in which the supplementary information is a low-frequency wave modulated or not modulated, comprises means for modulating the high level parity of the incoming digital signal by said low-frequency wave and means for restor ing said low-frequency wave from the outgoing resulting digital signal from said modulating means. According to circumstances in each instance, modulation of the H level parity can be
The present invention relates to digital data trans-mitting systenswhich convey digital words whose digits can have two levels (1, 0) as a binary word, or three levels (-1, 0, 1) as ternary word. In the following specification, the high level (H>~ level) indicates 1>~ levels, whether the levels are positive or negative.
In known digital data transmitting systems of this kind, it is often difficult to transmit a supplementary infor-mation without, firstly, increasing the complexity of the trans-mission and reception equipment and, secondly, without resortingto the use of a supplementary transmission support, such as an auxiliary pair of coaxial cables.
The main object of this invention is to provide a sup-plementary information transmitting arrangement for a digital data transmission system, in which the transmission of the sup-plementary information is performed without resorting to the use of an auxiliary transmission support, in cases where an existing transmission equipment is available, this existing equipment being associated with one or a number of reception equipments constituted by very simple circuits.
More particularly, the present invention proposes a supplementary information transmitting arrangement for a digital data transmission system comprising means receiving an incoming digital data signal and a digital supplementary information si-gnal having a rate much lower than that of the incoming digital data signal for inserting parity check words in the incoming data signal into a resulting digital data signal, the logic levels of digits of the parity check words being as a function of the logic level of the supplementary inforrnation signal so that the accumulated parity of the resulting digital data signal is constant between two successive parity check words, and B. 'h~'i -- 2 ~
1~37S81 means receiving the resulting digital data signal including the parity check words for detecting parity modifications in the resulting data signal to restore the supplementary information signal.
~ ccording to the invention, it is possible to transmit simultaneously with the digital signal from the transmission equipment a low-frequency wave. The low-frequency wave may then . in itself constitute the supplementary information, or alternati-vely it can be modulated by the supplementary information. For transmitting the low-frequency wave, the transmission arrange-ment according to ~137581 the invention entails a ~<H levels parity check. It is already known to use in repeaters H level parity check method for detecting the rate of operating errors. This method ls described in articles Nos. 59 and 54 of the Study Commission XVIII and IV of the International Telegraph and Telephone Consultative Committee. According to this known method, the H level parity between predetermined instants must be even in the absence of error, i.e. the number of H levels (high levels) between these predetermined instants is even.
According to this invention, the H level parity is not constant, but alternates. Accordingly, a supplementary information transmitting arrangement for a digital data transmission system in which the supplementary information is a low-frequency wave modulated or not modulated, comprises means for modulating the high level parity of the incoming digital signal by said low-frequency wave and means for restor ing said low-frequency wave from the outgoing resulting digital signal from said modulating means. According to circumstances in each instance, modulation of the H level parity can be
2~ achieved according to different methods within the spirit of the present invention.
When the digital data signal is a binary signal, a first method for modulating the H~> level parity consists in slightly increasing the frequency of the digital signal to be transmitted from the transmission equipment, thereby enabling a supplementary binary word to be inserted in step with the desired modulation. The supplementary binary word is formed from one or more binary digits which are selected in such a way as to determine the parity of the ~<H levels.
This first modulation method is Still applicable in the case of a ternary digital signal; a sum of the H
levels can be made, whether they are positive or negative.
When the digital data signal is a binary signal, a first method for modulating the H~> level parity consists in slightly increasing the frequency of the digital signal to be transmitted from the transmission equipment, thereby enabling a supplementary binary word to be inserted in step with the desired modulation. The supplementary binary word is formed from one or more binary digits which are selected in such a way as to determine the parity of the ~<H levels.
This first modulation method is Still applicable in the case of a ternary digital signal; a sum of the H
levels can be made, whether they are positive or negative.
- 3 --` . 113'~581 It is useless to insert supplementary digits in the case of a ternary digital to be transmitted which is random or randcmized by some suitable means, such a scrambler. In this case, a second method for modulatlng the H~ level parity according to the invention consists in coding the digital data signal by means of a code having a certain redundancy;
thus, at least two words having~m ternary digits corresponds to oné word having n binary digits; at least one of these ternary words changes the H level parity of the digital data signal, and at least one other of these ternary words does not change the H level parity.
However, according to the invention, the H level parity state have not to determine the choice of the m-ternary digit word for all configurations of words having n binary digits. In accordance with a preferred embodiment which is realized on the basis of an nBmT coding, such as the known three-level MS 43 code, account is only taken of the H~
level parity for coding of the configuration or the 4-bit word 1100.
The MS 43 code presents three different alphabets Al, A2 and A3 which correspond to each configuration of four binary digits, as set out in the table I below.
TABLE I
First Second Third Blnaryalphabet Al alphabet A2 alphabet A3 O O O O + - O + - O + - O
O O O 1 + + O O O - O O -O 0 1 0 + O + O - O O - O
O 0 1 1 O + + _ _ + _ _ +
0 1 0 0 + + - + _ _ + _ _ 0 1 0 1 0 - + 0 - + 0 - +
O 1 1 0 - O + - O+ - O+
0 1 1 1 + _ + + - + _ _ _ -...
1 o o o + + + +
1 o o 1 + o - + o - + o -1010 0+- 0+- 0+-1 o 1 1 + + + + o 1 ,1 o o + o o + o o - o o 1 1 o 1 o + o o + o - o -l 1 1 0 O O + O O ~ _ _ o .. 1111 -+o -+o -+o In the usual way, the choice of the alphabets Al, A2 and A3 is determined by the algebraic sum of the levels 1 and -1 specified at the end of each ternary word. This sum, known as the synchronized sum, is arbitrarily limited -to the values -2, -1, 0 and 1; to this end, the alphabet A
is used for each ternary word when the synchronized sum at the end of the preceding ternary word equals -2, the alphabet A2 is used when this same sum equal -1 or 0, and the alphabet A3 is used when the synchronized sum e~uals +1. This is in accordance with conventional usage of the three-level MS 43 code.
By way of example, adaptation of the MS 43 code for the purposes of the invention entails retaining the whole of the table I and the above-stated rules, with the exception of the thirteenth line of the table I which corresponds to the binary word 1100. This line is replaced by the iwo lines set out ln the table II below:
TABIE II
Binary A2 A3 ~- O O + O O - O O , ',X~
The f irst of these two lines of the table II is used if the existing H level parity is to be maintained, and the second line is used if the existing H level parity is to be changed. Further, choice of the alphabets Al, A2 and A3 is always,made as a function of thP synchronized sum.
The supplementary information transmitting arrangement for implementing the first H'level parity modulation method ~according to the invention comprises timing means for producing a timing signal having a rate slightly more than the digit rate of the incoming digital data signal, means for detecting the high~> level parity of said incoming digital data signal and means controlled by said timing means and said detecting , means for inserting supplementary digits thereby obtaining an outgoing resulting digital signal in which said supplementary digits fix said <~high level parity at a predetermined value.
The supplementary digit inserting means comprises a buffer ~-memory receiving said incoming data signal, counting means connected to said timing means for controlling write-in in said buffer memory at said rate of said incoming data signal and controlling read-out in said buffer memory at said outgoing resulting signal, and AND-gate having a first input receiving said low-frequency wave and a second input connected to said high~ level parity detecting means, an OR-gate having a first lnput connected to the output of said A~D-gate and a second input connected to the output of said buffer memory and pulse shaping means controlled by said timing means and connected to the output of said OR-gate for delivering said outgoing resulting signal.
The supplementary information transmitting arrangement for implementlng the second ~1~ level parity modulation method according to the invention comprises means for scrambling the incoming binary data signal, means for selectively converting 1137S~
each word of m binary digits of the scxambled binary signal into a word of n ternary digits of an outgoing digital signal, each n-ternary digit word modifying or not modifying the ~<high level parity of said outgoing digi~al signal, means connected to the output of said converting means for detecting said H level parity of said outgoing digital signal, and means receiving said low-frequency wave and connected to the output of said detecting means for comparing said high level parity of said outgoing digital signal and a predetermined parity fixed to the phase of said low-frequency wave so as to control the selection of said n-ternary digit word in said converting means. The converting means is an nBmT transcoder type usin~ a binary-to-ternary code having several ternary alphabets. The choice of the used ternary word for one or several binary words is determined by the comparison result of the comparing means as a function of the high level parity of the outgoing digital signal and the phase condition of the low-frequency wave to be transmitted simultaneously with the incoming digital data signal.
ZO At the reception end, the device by means of which the low-frequency wave and consequently the supplementary information are restored, is composed of a bistable flip-flop receiving said outgoing resulting digital signal and a band pass filter connected to said flip-flop and having its band pass centred on a frequency which is the same as or a multiple of the frequency of said low-frequency wave.
However, when transmission of the digital signal is impaired through the presence of errors, a better reception of the supplementary information transmitted is obtained by interconnecting between the bistable flip-flop and the band pass filter a low pass filter and a half-wave or full-wave 1137~8~
rectifying means.
BRIEF DESCRIPTION OF THE DRAWING
The present invention will now be described in detail with reference to the accompanying drawings in which:
- Fig. 1 ls a schematic block-dlayram of the transmission device for implementing ~he first H level parity modulation method by means of which it is possible, according to the invention, to transmit supplementary information;
- Fig. 2 is a block-diagram of the supplementary information bit inserting circuit of the transmission device in Fig. l;
- Fig. 3 is a schematic block-diagram of the transmission device for implementing the second H level parity modulation method by means of which is it possible, according to the invention, to transmit supplementary information;
- Fig. 4 is a schematic block-diagram of a reception device for restoring the supplementary information; --- Fig. 5 is schematic block-diagram of another reception device for restoring the supplementary information, this reception device being mainly used when transmission of the digital signal is impaired through the presence of errors;
and - Flg. 6 shows diagrams of pulse trains illustrating the operation of the time base forming part of the transmission device embodying the invention.
DESCRIPTION OF T~E PREFFERRED EMBODIMENTS
Referring to Fig. 1, the digital data signal to be transmitted, or high-frequency signal, including a succession of binary or ternary digits, is fed to the input terminal 1 of the transmission device 2 by means of which it is possible, according to the invention, to transmit supplementary information.
This low-frequency supplementary information is fed to the input terminal 3 of this same device. The input terminal 1 is 1~37SB~
connected to the input terminal 4 of a time base 5, to the input terminal 6 of a supplementary bit inserting circuit 7, and to the input terminal 8 of a ~)~ level parity detecting circuit 9. This circuit 9 is, for example, a bistahle flip-flop, whose statc alters ln response to each rlslng flank oE
the digital data signal to be transmitted. When the incoming di~ital data sig~al includes ternary digits, the flip-flop 9 is preceded by a rectifier 10, which is indicated in dashed line in Fig. 1~ The output terminal 11 of the parity detecting circuit 9 is connected to a first control termiIIal~
12 of the supplementary bit inserting circuit 7. An output terminal 13 of the time base S produces the repetition frequency of the incoming digital signal to be transmitted, as shown in line a of Fig. 6, and is connected to a second control terminal 14 of the circuit 7. A second output terminal 15 of the time base 5 produces a signal at the repetition frequency at which the outgoing signal including the digital data signal and the supplementary information will be transmitted, as shown in line b of Fig. 6, and is connected to a third control terminal 16 of the clrcuit 7. An output terminal 17 of the time base 5 generates a low-frequency carrier wave as ~hown in line c of Fig. 6. The output terminal 17 is connected to the input terminal 18 of a modulating circuit 19, whose a second input terminal 20 is connected to the second input terminal 3 of the transmission device 2 embodying the invention. The output terminal 21 of the modulating circuit 19 delivers to a fourth control terminal 22 of the circuit 7 the low-frequency wave which is modulated by the supplementary information to be transmitted. Another output terminal 23 of the time base 5 is connected to a fifth control terminal 24 of the inserting circuit 7. This output terminal 23 delivers a timing signal which has the same frequency as that shown in line b of Fig. 6, _ g _ 1137S~31 although it has gaps such as are shown in line _ of Fig. 6.
In other words, the rate of the timing signal at line d of Fig. 6 during a period of the low-frequency wave iS slightly more than the rate of the timing si~nal at line a.
The ou-tput termlnal 25 of the circuit 7 ls connected to the output terminal 26 of the transmission device 2 and transmits the outgoing resulting digital signal having a rate slightly more than the rate of the incoming digital data signal at the input 1.
Fig. 2 illustrates in greater detail the supplementary bit inserting circuit 7, with its input terminal 6, its output terminal 25, and its control terminals 12, 14, 16, 22 and 24.
The input terminal 6 is connected to a buffer store 30, which is written subject to the control of a writing counter 31 which is connected to the input terminal 14, and read subject to the control of a reading counter 32 which is connected to the input terminal 24. The control terminals 22 and 12 are connected to the input terminals of an AND-gate 33, whose output terminal 34 i5 connected to the first input terminal 35 of an OR-gate 36. The second input terminal 37 of the OR-gate 36 is connected to the output terminal 38 of the buffer store 30. The output terminal 39 of the OR-gate 36 is connected to the input terminal 40 of a pulse-shaping circuit 41, which is controlled by the timing signal applied to the control terminal 16 and whose output terminal is the output terminal 25 of the supplementary bit inserting circuit.
By way of example, a supplementary 3-bit word is inserted for every 200 binary digits. This supplementary word has one or the other of the two following configurations :
001 and 110. The first configuration is used when the H
level parity state is to be change, and the second configuration is used when the existing H level parity state is to be ~i37581 maintained unaltered.
Fig. 3 schematically illu.strates a second embodiment of the transmission device for modulating the aH level of an incoming binary digital data signal. This device 50 comprises two lnput terminals 51 and 52 and an output terminal 53. The incoming binary data signal to be transmitted is received at the input terminal 51 which is the input terminal of a scrambling circuit 54. The output terminal 55 of the scrambling circuit S4 delivers the randomized serial binary signal to the input terminal 56 of a transcoder 57. The transcoder 57 converts each word of m binary digits into a word of n ternary digits.
~he output terminal 58 of the transcoder 57 is connectea to the output terminal 53 of the transmission device 50 and to the input terminal 59 of a H level parity detecting circuit 60. The output terminal 61 of the circuit 60 is connected to the first input terminal 62 of a comparing circuit 63, for comparing the existing parity of the outgoing digital signal and the desired parity which is fixed by the phase of the low-frequency carrier wave which is or is not modulated. The carrier wave appears at the input terminal 52 of the device 50, which is the second input terminal of the comparing circuit 63.
The output terminal 64 of this comparing circuit 63 is connected to the control terminal 65 of the transcoder 57 and selectively controls the transcoder 57 so that a choice of m-ternary digit words whlch modify or do not modify the H level parity of the outgoing signal, corresponds to at least one n-binary digit word of the scrambled signal. This choice is made in dependence upon the parity of the outgoing signal and the parity fixed by the low-frequency wave phase. The modification of the binary-to-ternary code used in the transcoder 57 and the selection of the three alphabets Al, A2 and A3 when the MS 43 code is used are made as already stated in reference with the ,~
113758~
Tables I and II.
Fig. 4 clearly brings out the simplicity of the reception device 70, which is required for receiving the low-frequency wave and, consequently, the supplementary information transmitted according to the invention. The input terminal 71 of the reception device 70 receives the outgoing resulting digital signal from the output of the transmission device, via the digital transmission line. The input terminal 71 is the input terminal of a bistable fli-flop 72, whose output terminal 73 is connected to the input terminal 74 of a band pass filter 75 restorin~ the low-frequency wave. The output terminal 76 of the band pass filter 75 is the output terminal of the reception device 70. The band pass of the filter 75 is centred on a frequency which is equal to the frequency or a multiple of the frequency of the low-frequency wave trans-mitting the supplementary information.
Fig. 5 illustrates a variant of the device for receiving the supplementary information. The use of this variant is more particularly recommended when the line trans-mission of the digital signal is impaired through the presenceof errors. The reception device 80 comprises also a bistable flip-flop 72 whose input terminal 71 receives the outgoing resulting digital signal from the transmission device output and is the input terminal of the reception device 80. The input terminal 82 of a low pass filter 81 is connected to the output terminal 73 of the bistable flip-flop 72. The input terminal 84 of a half-wave or full-wave rectifier 83 is connected to the output terminal 85 of the low pass filter 81.
A band pass filter 86 has its input terminal 87 which is connected to the output terminal 88 of the rectifier 83.
The output terminal 89 of the band pass filter 86 is the output terminal of the reception device 80 and restores the low-~'! 12 -frequency wave transmitting the supplementary information.
Conveniently, the cutoff f~equency of the low pass f ilter 81 is sli~htly above the frequency of the low-frequency wave, and the central frequency of the band pass of the band pass ~ilter 8G ls equal to double oE the frequency of the low-frequency wave.
The transmission and reception devices embodying the invention can be used with advantage whenever it is desired to transmit, simultaneously and on the same support, a digital data signal and a supplementary information low-frequency wave.
Transmission of the resulting digital wave may then in itself constitute an information; for example, the measurement of its voltage level at any point in the transmission line provides information as to the quality of transmission of the digital data signal. In conjunction with this or not, the low-frequency wave can be modulated to transmit particular information between two main stations or between a main station and a series of intermediate repeaters.
. - 13 -
thus, at least two words having~m ternary digits corresponds to oné word having n binary digits; at least one of these ternary words changes the H level parity of the digital data signal, and at least one other of these ternary words does not change the H level parity.
However, according to the invention, the H level parity state have not to determine the choice of the m-ternary digit word for all configurations of words having n binary digits. In accordance with a preferred embodiment which is realized on the basis of an nBmT coding, such as the known three-level MS 43 code, account is only taken of the H~
level parity for coding of the configuration or the 4-bit word 1100.
The MS 43 code presents three different alphabets Al, A2 and A3 which correspond to each configuration of four binary digits, as set out in the table I below.
TABLE I
First Second Third Blnaryalphabet Al alphabet A2 alphabet A3 O O O O + - O + - O + - O
O O O 1 + + O O O - O O -O 0 1 0 + O + O - O O - O
O 0 1 1 O + + _ _ + _ _ +
0 1 0 0 + + - + _ _ + _ _ 0 1 0 1 0 - + 0 - + 0 - +
O 1 1 0 - O + - O+ - O+
0 1 1 1 + _ + + - + _ _ _ -...
1 o o o + + + +
1 o o 1 + o - + o - + o -1010 0+- 0+- 0+-1 o 1 1 + + + + o 1 ,1 o o + o o + o o - o o 1 1 o 1 o + o o + o - o -l 1 1 0 O O + O O ~ _ _ o .. 1111 -+o -+o -+o In the usual way, the choice of the alphabets Al, A2 and A3 is determined by the algebraic sum of the levels 1 and -1 specified at the end of each ternary word. This sum, known as the synchronized sum, is arbitrarily limited -to the values -2, -1, 0 and 1; to this end, the alphabet A
is used for each ternary word when the synchronized sum at the end of the preceding ternary word equals -2, the alphabet A2 is used when this same sum equal -1 or 0, and the alphabet A3 is used when the synchronized sum e~uals +1. This is in accordance with conventional usage of the three-level MS 43 code.
By way of example, adaptation of the MS 43 code for the purposes of the invention entails retaining the whole of the table I and the above-stated rules, with the exception of the thirteenth line of the table I which corresponds to the binary word 1100. This line is replaced by the iwo lines set out ln the table II below:
TABIE II
Binary A2 A3 ~- O O + O O - O O , ',X~
The f irst of these two lines of the table II is used if the existing H level parity is to be maintained, and the second line is used if the existing H level parity is to be changed. Further, choice of the alphabets Al, A2 and A3 is always,made as a function of thP synchronized sum.
The supplementary information transmitting arrangement for implementing the first H'level parity modulation method ~according to the invention comprises timing means for producing a timing signal having a rate slightly more than the digit rate of the incoming digital data signal, means for detecting the high~> level parity of said incoming digital data signal and means controlled by said timing means and said detecting , means for inserting supplementary digits thereby obtaining an outgoing resulting digital signal in which said supplementary digits fix said <~high level parity at a predetermined value.
The supplementary digit inserting means comprises a buffer ~-memory receiving said incoming data signal, counting means connected to said timing means for controlling write-in in said buffer memory at said rate of said incoming data signal and controlling read-out in said buffer memory at said outgoing resulting signal, and AND-gate having a first input receiving said low-frequency wave and a second input connected to said high~ level parity detecting means, an OR-gate having a first lnput connected to the output of said A~D-gate and a second input connected to the output of said buffer memory and pulse shaping means controlled by said timing means and connected to the output of said OR-gate for delivering said outgoing resulting signal.
The supplementary information transmitting arrangement for implementlng the second ~1~ level parity modulation method according to the invention comprises means for scrambling the incoming binary data signal, means for selectively converting 1137S~
each word of m binary digits of the scxambled binary signal into a word of n ternary digits of an outgoing digital signal, each n-ternary digit word modifying or not modifying the ~<high level parity of said outgoing digi~al signal, means connected to the output of said converting means for detecting said H level parity of said outgoing digital signal, and means receiving said low-frequency wave and connected to the output of said detecting means for comparing said high level parity of said outgoing digital signal and a predetermined parity fixed to the phase of said low-frequency wave so as to control the selection of said n-ternary digit word in said converting means. The converting means is an nBmT transcoder type usin~ a binary-to-ternary code having several ternary alphabets. The choice of the used ternary word for one or several binary words is determined by the comparison result of the comparing means as a function of the high level parity of the outgoing digital signal and the phase condition of the low-frequency wave to be transmitted simultaneously with the incoming digital data signal.
ZO At the reception end, the device by means of which the low-frequency wave and consequently the supplementary information are restored, is composed of a bistable flip-flop receiving said outgoing resulting digital signal and a band pass filter connected to said flip-flop and having its band pass centred on a frequency which is the same as or a multiple of the frequency of said low-frequency wave.
However, when transmission of the digital signal is impaired through the presence of errors, a better reception of the supplementary information transmitted is obtained by interconnecting between the bistable flip-flop and the band pass filter a low pass filter and a half-wave or full-wave 1137~8~
rectifying means.
BRIEF DESCRIPTION OF THE DRAWING
The present invention will now be described in detail with reference to the accompanying drawings in which:
- Fig. 1 ls a schematic block-dlayram of the transmission device for implementing ~he first H level parity modulation method by means of which it is possible, according to the invention, to transmit supplementary information;
- Fig. 2 is a block-diagram of the supplementary information bit inserting circuit of the transmission device in Fig. l;
- Fig. 3 is a schematic block-diagram of the transmission device for implementing the second H level parity modulation method by means of which is it possible, according to the invention, to transmit supplementary information;
- Fig. 4 is a schematic block-diagram of a reception device for restoring the supplementary information; --- Fig. 5 is schematic block-diagram of another reception device for restoring the supplementary information, this reception device being mainly used when transmission of the digital signal is impaired through the presence of errors;
and - Flg. 6 shows diagrams of pulse trains illustrating the operation of the time base forming part of the transmission device embodying the invention.
DESCRIPTION OF T~E PREFFERRED EMBODIMENTS
Referring to Fig. 1, the digital data signal to be transmitted, or high-frequency signal, including a succession of binary or ternary digits, is fed to the input terminal 1 of the transmission device 2 by means of which it is possible, according to the invention, to transmit supplementary information.
This low-frequency supplementary information is fed to the input terminal 3 of this same device. The input terminal 1 is 1~37SB~
connected to the input terminal 4 of a time base 5, to the input terminal 6 of a supplementary bit inserting circuit 7, and to the input terminal 8 of a ~)~ level parity detecting circuit 9. This circuit 9 is, for example, a bistahle flip-flop, whose statc alters ln response to each rlslng flank oE
the digital data signal to be transmitted. When the incoming di~ital data sig~al includes ternary digits, the flip-flop 9 is preceded by a rectifier 10, which is indicated in dashed line in Fig. 1~ The output terminal 11 of the parity detecting circuit 9 is connected to a first control termiIIal~
12 of the supplementary bit inserting circuit 7. An output terminal 13 of the time base S produces the repetition frequency of the incoming digital signal to be transmitted, as shown in line a of Fig. 6, and is connected to a second control terminal 14 of the circuit 7. A second output terminal 15 of the time base 5 produces a signal at the repetition frequency at which the outgoing signal including the digital data signal and the supplementary information will be transmitted, as shown in line b of Fig. 6, and is connected to a third control terminal 16 of the clrcuit 7. An output terminal 17 of the time base 5 generates a low-frequency carrier wave as ~hown in line c of Fig. 6. The output terminal 17 is connected to the input terminal 18 of a modulating circuit 19, whose a second input terminal 20 is connected to the second input terminal 3 of the transmission device 2 embodying the invention. The output terminal 21 of the modulating circuit 19 delivers to a fourth control terminal 22 of the circuit 7 the low-frequency wave which is modulated by the supplementary information to be transmitted. Another output terminal 23 of the time base 5 is connected to a fifth control terminal 24 of the inserting circuit 7. This output terminal 23 delivers a timing signal which has the same frequency as that shown in line b of Fig. 6, _ g _ 1137S~31 although it has gaps such as are shown in line _ of Fig. 6.
In other words, the rate of the timing signal at line d of Fig. 6 during a period of the low-frequency wave iS slightly more than the rate of the timing si~nal at line a.
The ou-tput termlnal 25 of the circuit 7 ls connected to the output terminal 26 of the transmission device 2 and transmits the outgoing resulting digital signal having a rate slightly more than the rate of the incoming digital data signal at the input 1.
Fig. 2 illustrates in greater detail the supplementary bit inserting circuit 7, with its input terminal 6, its output terminal 25, and its control terminals 12, 14, 16, 22 and 24.
The input terminal 6 is connected to a buffer store 30, which is written subject to the control of a writing counter 31 which is connected to the input terminal 14, and read subject to the control of a reading counter 32 which is connected to the input terminal 24. The control terminals 22 and 12 are connected to the input terminals of an AND-gate 33, whose output terminal 34 i5 connected to the first input terminal 35 of an OR-gate 36. The second input terminal 37 of the OR-gate 36 is connected to the output terminal 38 of the buffer store 30. The output terminal 39 of the OR-gate 36 is connected to the input terminal 40 of a pulse-shaping circuit 41, which is controlled by the timing signal applied to the control terminal 16 and whose output terminal is the output terminal 25 of the supplementary bit inserting circuit.
By way of example, a supplementary 3-bit word is inserted for every 200 binary digits. This supplementary word has one or the other of the two following configurations :
001 and 110. The first configuration is used when the H
level parity state is to be change, and the second configuration is used when the existing H level parity state is to be ~i37581 maintained unaltered.
Fig. 3 schematically illu.strates a second embodiment of the transmission device for modulating the aH level of an incoming binary digital data signal. This device 50 comprises two lnput terminals 51 and 52 and an output terminal 53. The incoming binary data signal to be transmitted is received at the input terminal 51 which is the input terminal of a scrambling circuit 54. The output terminal 55 of the scrambling circuit S4 delivers the randomized serial binary signal to the input terminal 56 of a transcoder 57. The transcoder 57 converts each word of m binary digits into a word of n ternary digits.
~he output terminal 58 of the transcoder 57 is connectea to the output terminal 53 of the transmission device 50 and to the input terminal 59 of a H level parity detecting circuit 60. The output terminal 61 of the circuit 60 is connected to the first input terminal 62 of a comparing circuit 63, for comparing the existing parity of the outgoing digital signal and the desired parity which is fixed by the phase of the low-frequency carrier wave which is or is not modulated. The carrier wave appears at the input terminal 52 of the device 50, which is the second input terminal of the comparing circuit 63.
The output terminal 64 of this comparing circuit 63 is connected to the control terminal 65 of the transcoder 57 and selectively controls the transcoder 57 so that a choice of m-ternary digit words whlch modify or do not modify the H level parity of the outgoing signal, corresponds to at least one n-binary digit word of the scrambled signal. This choice is made in dependence upon the parity of the outgoing signal and the parity fixed by the low-frequency wave phase. The modification of the binary-to-ternary code used in the transcoder 57 and the selection of the three alphabets Al, A2 and A3 when the MS 43 code is used are made as already stated in reference with the ,~
113758~
Tables I and II.
Fig. 4 clearly brings out the simplicity of the reception device 70, which is required for receiving the low-frequency wave and, consequently, the supplementary information transmitted according to the invention. The input terminal 71 of the reception device 70 receives the outgoing resulting digital signal from the output of the transmission device, via the digital transmission line. The input terminal 71 is the input terminal of a bistable fli-flop 72, whose output terminal 73 is connected to the input terminal 74 of a band pass filter 75 restorin~ the low-frequency wave. The output terminal 76 of the band pass filter 75 is the output terminal of the reception device 70. The band pass of the filter 75 is centred on a frequency which is equal to the frequency or a multiple of the frequency of the low-frequency wave trans-mitting the supplementary information.
Fig. 5 illustrates a variant of the device for receiving the supplementary information. The use of this variant is more particularly recommended when the line trans-mission of the digital signal is impaired through the presenceof errors. The reception device 80 comprises also a bistable flip-flop 72 whose input terminal 71 receives the outgoing resulting digital signal from the transmission device output and is the input terminal of the reception device 80. The input terminal 82 of a low pass filter 81 is connected to the output terminal 73 of the bistable flip-flop 72. The input terminal 84 of a half-wave or full-wave rectifier 83 is connected to the output terminal 85 of the low pass filter 81.
A band pass filter 86 has its input terminal 87 which is connected to the output terminal 88 of the rectifier 83.
The output terminal 89 of the band pass filter 86 is the output terminal of the reception device 80 and restores the low-~'! 12 -frequency wave transmitting the supplementary information.
Conveniently, the cutoff f~equency of the low pass f ilter 81 is sli~htly above the frequency of the low-frequency wave, and the central frequency of the band pass of the band pass ~ilter 8G ls equal to double oE the frequency of the low-frequency wave.
The transmission and reception devices embodying the invention can be used with advantage whenever it is desired to transmit, simultaneously and on the same support, a digital data signal and a supplementary information low-frequency wave.
Transmission of the resulting digital wave may then in itself constitute an information; for example, the measurement of its voltage level at any point in the transmission line provides information as to the quality of transmission of the digital data signal. In conjunction with this or not, the low-frequency wave can be modulated to transmit particular information between two main stations or between a main station and a series of intermediate repeaters.
. - 13 -
Claims (9)
1. A supplementary information transmitting arrange-ment for a digital data transmission system comprising:
- means receiving an incoming digital data signal and a digital supplementary information signal having a rate much lower than that of said incoming digital data signal for inserting parity check words in said incoming data signal into a resulting digital data signal, the logic levels of digits of said parity check words being as a function of the logic level of said supplementary information signal so that the accumulated parity of said resulting digital data signal is constant between two successive parity check words, and - means receiving the resulting digital data signal including said parity check words for detecting parity modifica-tions in said resulting data signal to restore said supplementary information signal.
- means receiving an incoming digital data signal and a digital supplementary information signal having a rate much lower than that of said incoming digital data signal for inserting parity check words in said incoming data signal into a resulting digital data signal, the logic levels of digits of said parity check words being as a function of the logic level of said supplementary information signal so that the accumulated parity of said resulting digital data signal is constant between two successive parity check words, and - means receiving the resulting digital data signal including said parity check words for detecting parity modifica-tions in said resulting data signal to restore said supplementary information signal.
2. A supplementary information transmitting arrange-ment according to claim 1, wherein said parity modification de-tecting means comprises means for detecting the parity of said resulting digital data signal and a band pass filter connected to said parity detecting means and having its band pass centred on a frequency which is the same as or a multiple of the fre-quency of a low-frequency wave representative of said supple-mentary information signal.
3. A supplementary information transm.itting arrangement according to claim 1, wherein said parity modification detecting means comprises means for detecting the parity of said resulting digital data signal, a low pass filter connected to the output of said parity detecting means, rectifying means connected to the output of said low pass filter and a band pass filter con-nected to the output of said rectifying means.
4. A supplementary information transmitting arrange-ment according to claim 2 or 3, wherein said parity detecting means comprises a clocked bistable means, said resulting digital data signal being applied to the clock input of said bistable means.
5. A supplementary information transmitting arrange-ment according to claim 3, wherein the band pass of said band pass filter is centred on a frequency which is twice the frequen-cy of a low-frequency wave representative of said supplementary information signal.
6. A supplementary information transmitting arrangement for a digital data transmission system in which the supplementary information is a low-frequency wave modulated or not modulated, said arrangement comprising timing means for producing a timing signal having a rate slightly more than the digit rate of the incoming digital data signal, means for detecting the ?high?
level parity of said incoming digital data signal and means con-trolled by said timing means and said detecting means for insert-ing supplementary digits thereby obtaining an outgoing resulting digital signal in which said supplementary digits fix the ?high?
level parity at a predetermined value, in dependence of said low-frequency wave.
level parity of said incoming digital data signal and means con-trolled by said timing means and said detecting means for insert-ing supplementary digits thereby obtaining an outgoing resulting digital signal in which said supplementary digits fix the ?high?
level parity at a predetermined value, in dependence of said low-frequency wave.
7. A supplementary information transmitting arrangement according to claim 6, wherein said supplementary digit inserting means comprises a buffer memory receiving said incoming data signal, counting means connected to said timing means for control-ling writing in said buffer memory at said rate of said incoming data signal and controlling read-out in said buffer memory at said outgoing resulting signal, an AND-gate having a first input receiving said low-frequency wave and a second input connected to said ?high? level parity detecting means, an OR-gate having a first input connected to the output of said AND-gate and a second input connected to the output of said buffer memory and pulse-shaping means controlled by said timing means and connected to the output of said OR-gate for delivering said outgoing resulting signal.
8. A supplementary information, transmittlng arrange-ment for a digital data transmission system wherein the supple-mentary information is a low-frequency wave modulated or not mo-dulated, and the incoming digital data signal is binary coded, said arrangement comprising means for scrambling the incoming binary data signal, means for selectively converting each word of m binary digits of the scrambled binary signal into a word of n ternary digits of an out-going digital signal, each n-ternary digit word modifying or not modifying the ?high? level parity of said outgoing digital signal, means connected to the output of said converting means for detecting said ?H? level parity of said outgoing digital signal, and means receiving said low-frequency wave and connected to the output of said detecting means for comparing said ?high? level parity of said outgoing digital signal and a predetermined parity fixed to the phase of said low-frequency wave so as to control the selection of said n-ternary digit word in said converting means.
9. A supplementary information transmitting arrange-ment according to claim 8, wherein the binary-to-ternary code used in said converting means is the three-level MS 43 code having three alphabets A1, A2 and A3 which are modified only for the 4-bit word 1100 in accordance with the following table where the first line of the three-ternary digit words of said table is used when said ?high? level parity of said outgoing resulting signal is to be maintained unaltered and the second line of the three-ternary digit words of said table is used when said ?high? level parity of said outgoing resulting signal is to be modified and in which the choice of said three alpha-bets for each ternary word in said converting means is made as a function of the value of the synchronized sum of the preceding ternary word.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR7900383A FR2446570A1 (en) | 1979-01-09 | 1979-01-09 | METHOD AND DEVICE ALLOWING THE SIMULTANEOUS TRANSMISSION OF A DIGITAL SIGNAL AND A LOW FREQUENCY WAVE |
| FRPV79-00383 | 1979-01-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1137581A true CA1137581A (en) | 1982-12-14 |
Family
ID=9220547
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000343230A Expired CA1137581A (en) | 1979-01-09 | 1980-01-08 | Low-frequency supplementary information transmitting arrangement for a digital data transmission system |
Country Status (7)
| Country | Link |
|---|---|
| BE (1) | BE881066A (en) |
| CA (1) | CA1137581A (en) |
| CH (1) | CH640678A5 (en) |
| DE (1) | DE3000941C2 (en) |
| FR (1) | FR2446570A1 (en) |
| GB (1) | GB2039447B (en) |
| IT (1) | IT1154951B (en) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IT1128766B (en) * | 1980-04-04 | 1986-06-04 | Cselt Centro Studi Lab Telecom | PROCEDURE AND DEVICE FOR THE SYNCHRONIZATION OF THE PLOT OF AN ADDITIONAL INFORMATION SIGNAL TRANSMITTED TO THE LEVEL DIVISION |
| US4393493A (en) * | 1980-11-10 | 1983-07-12 | International Telephone And Telegraph Corporation | Automatic protection apparatus for span lines employed in high speed digital systems |
| DE3042612A1 (en) * | 1980-11-12 | 1982-06-16 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | TRANSMISSION PROCEDURE FOR DIGITAL SIGNALS |
| GB2146875A (en) * | 1983-09-09 | 1985-04-24 | Racal Res Ltd | Communications systems |
| DE3401729A1 (en) * | 1984-01-19 | 1985-08-01 | ANT Nachrichtentechnik GmbH, 7150 Backnang | Digital data transmission system |
| DE3431423A1 (en) * | 1984-08-27 | 1986-03-06 | Telefonbau Und Normalzeit Gmbh, 6000 Frankfurt | METHOD FOR TRANSMITTING DIGITAL INFORMATION TO CONNECTION LINES OF TELECOMMUNICATIONS, IN PARTICULAR TELECOMMUNICATION SYSTEMS |
| GB8511804D0 (en) * | 1985-05-09 | 1985-06-19 | British Broadcasting Corp | Digital data transmission |
| DE3530546A1 (en) * | 1985-08-27 | 1987-03-19 | Ant Nachrichtentech | Transmission method for a fast and a slow data stream |
| DE3806411C2 (en) * | 1988-02-29 | 1996-05-30 | Thomson Brandt Gmbh | Method of transmitting a sound signal and an additional signal |
| DE3808829A1 (en) * | 1988-03-14 | 1989-09-28 | Deutsche Telephonwerk Kabel | Method for data transmission on lines of an integrated services digital communications network |
| GB2243056B (en) * | 1990-04-11 | 1994-03-30 | Stc Plc | Repeater supervision |
| US5390185A (en) * | 1992-10-09 | 1995-02-14 | U.S. Philips Corporation | Transmission system for a combination of a main signal and an auxiliary signal |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1250908A (en) * | 1968-12-13 | 1971-10-27 | ||
| US3671959A (en) * | 1969-01-24 | 1972-06-20 | Kokusai Denshin Denwa Co Ltd | Binary to ternary converter |
| DE2512303B1 (en) * | 1975-03-20 | 1976-07-08 | Siemens Ag | CIRCUIT ARRANGEMENT FOR THE RECEIVING SIDE STEP LENGTH DURING THE CHARACTER-FRAME-BONDED TIME-MULTIPLEX TRANSFER OF DATA |
| GB1512700A (en) * | 1975-10-23 | 1978-06-01 | Standard Telephones Cables Ltd | Data transmission |
| GB1539389A (en) * | 1975-12-30 | 1979-01-31 | Standard Telephones Cables Ltd | Data transmission |
| GB1536337A (en) * | 1976-06-02 | 1978-12-20 | Standard Telephones Cables Ltd | Error detection in digital systems |
| CH621445A5 (en) * | 1976-09-09 | 1981-01-30 | Gretag Ag | |
| FR2367383A1 (en) * | 1976-10-08 | 1978-05-05 | Int Standard Electric Corp | Error detection circuit for numeric transmission systems - operates using polarity control and is applicable to PCM systems using shift registers |
-
1979
- 1979-01-09 FR FR7900383A patent/FR2446570A1/en active Granted
- 1979-08-09 GB GB7927730A patent/GB2039447B/en not_active Expired
-
1980
- 1980-01-04 CH CH3280A patent/CH640678A5/en not_active IP Right Cessation
- 1980-01-08 CA CA000343230A patent/CA1137581A/en not_active Expired
- 1980-01-09 DE DE3000941A patent/DE3000941C2/en not_active Expired
- 1980-01-09 IT IT84103/80A patent/IT1154951B/en active
- 1980-01-09 BE BE0/198905A patent/BE881066A/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| DE3000941C2 (en) | 1985-09-26 |
| FR2446570A1 (en) | 1980-08-08 |
| IT8084103A0 (en) | 1980-01-09 |
| IT1154951B (en) | 1987-01-21 |
| GB2039447A (en) | 1980-08-06 |
| FR2446570B1 (en) | 1981-09-18 |
| GB2039447B (en) | 1983-07-27 |
| BE881066A (en) | 1980-05-02 |
| CH640678A5 (en) | 1984-01-13 |
| DE3000941A1 (en) | 1980-07-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4387460A (en) | Supplementary information transmitting arrangement for a digital data transmission system | |
| US4584690A (en) | Alternate Mark Invert (AMI) transceiver with switchable detection and digital precompensation | |
| US4415984A (en) | Synchronous clock regenerator for binary serial data signals | |
| CA1137581A (en) | Low-frequency supplementary information transmitting arrangement for a digital data transmission system | |
| US5200979A (en) | High speed telecommunication system using a novel line code | |
| US5239496A (en) | Digital parallel correlator | |
| US4979185A (en) | High speed serial data link | |
| Croisier | Introduction to pseudoternary transmission codes | |
| GB1561369A (en) | Binary data receiver | |
| US4868874A (en) | Echo canceller | |
| GB2110509A (en) | Apparatus for and methods of processing digital data | |
| US4639681A (en) | Waveform reshaping circuit | |
| US4255742A (en) | Data communication code | |
| US3418631A (en) | Error detection in paired selected ternary code trains | |
| US4276649A (en) | Receiver for digital signals in line code | |
| KR930010611B1 (en) | Waveform shaping apparatus | |
| US4123625A (en) | Digital regenerator having improving noise immunity | |
| US3261920A (en) | Asynchronous pulse multiplexing | |
| US5862177A (en) | Method for testing communications channels | |
| US3935403A (en) | Device for developing a neutralization signal for an echo suppressor | |
| US4794604A (en) | Optimal error correction method for zero byte time slot interchange (ZBTSI) clear channel data transmission | |
| CA1154539A (en) | Code converter for polarity-insensitive transmission systems | |
| CA2038472C (en) | System for suppressing spread of error generated in differential coding | |
| GB2174577A (en) | Digital communication system | |
| US4785466A (en) | Encoder/decoder circuit for B8ZS and B6ZS applications |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |