CA1120586A - Recording system - Google Patents
Recording systemInfo
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- CA1120586A CA1120586A CA000303461A CA303461A CA1120586A CA 1120586 A CA1120586 A CA 1120586A CA 000303461 A CA000303461 A CA 000303461A CA 303461 A CA303461 A CA 303461A CA 1120586 A CA1120586 A CA 1120586A
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- recording
- digital
- signals
- electrical signals
- analog
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Abstract
ABSTRACT OF THE DISCLOSURE
A recording system including a recording apparatus, a time delay device wherein analog signals are converted into digital signals and wherein said digital signals are delayed for an interval of time to provide delayed digital signals which are recorded by said recording apparatus or which are converted into delayed analog signals that are then recorded by said recording apparatus, and means responsive to said analog signal or means responsive to said digital signal for causing the recording apparatus to be placed in a recording mode of operation prior to the end of said interval of time.
A recording system including a recording apparatus, a time delay device wherein analog signals are converted into digital signals and wherein said digital signals are delayed for an interval of time to provide delayed digital signals which are recorded by said recording apparatus or which are converted into delayed analog signals that are then recorded by said recording apparatus, and means responsive to said analog signal or means responsive to said digital signal for causing the recording apparatus to be placed in a recording mode of operation prior to the end of said interval of time.
Description
5~
"RECOXDING SYSTEM"
BACKGROUND OF THE INVENTION
1~ This invention relates to recording systems and ,' more particularly to a recording system for recording ,I transduced electrical signals on a recording medium with a recording apparatus having a mode of operation responsive to the transduced electrical .signals. Even more specifically, this invention i3 directed to .systems for recordin~
I dictation. With respect to StJCIl a recordillg system, it is 10 , known in the art to use a detection and control apparatus for initiating ancl ~erminating the recording mode of operation of a recording apparatus în response to the presence or absence of sound generated electrical signals so that the recording apparatus is itl the recording mode o~
, operation on:ly where there is dictation to be recorded.
~he detection and control apparatus starts the .,.,.,.~. ~k recordiny mode of operation of -the recording apparatus in response to sound generated electrical signals and terminates the recording mode of operation of the recording apparatus in response to the absence of sound generated electrical signals for a predetermined length of time. A
detection and control apparatus is particularly useful in a recording system in which the source of the sound to be recorded is an individual who wishes to record dictation and who is remote from the recording apparatus wih no means for controlling the recording mode of operation of the recording apparatus other than the sound of his voice and resulting sound generated electrical signals.
A difficulty which has been encountered in the use of a detection and control apparatus in a recording system is that the recording apparatus is not instantaneously placed in a recording mode of operation upon the initial detection of sound generated electrical signals b~ the detection and control apparatus. Therefore, the recording apparatus is not operating in the recording mode oE
operation when sound, such as the voice of a dictator, initially reaches the recording apparatus to be recorded as sound generated electrical signals. Thus, some of the sound, such as dictation, to be recorded is lost.
In order to solve this problem some prior art recording systems have used a supplementary recording device as a stage in the transmission of the sound generated electrical signals to the recording apparatus. This supplementary recording device records the initial sound and all subsequent sound as sound generated eletrical signals and plays the sound generated signals back after a time i i 2 ~ 7 1 1 ,' "
llzasa6 delay to the recording apparatus Eor recording by the recording apparatus. The length of this time delay is determined by the length of time needed for the recording apparatus to be placed in the recording mode of operation by the detection and control apparatus after detection of the initial sound generated electrical signals by the detection and control apparatus. Once placed in the recording mode of operation by the detection and control apparatus, the recording apparatus receives the records the delayed initial sound generated electrical signals and all subsequent signals from the supplementary recording device until sound generated electrical signals have ceased for a predetermined length of time to cause the detection and control apparatus to terminate the recording mode of operation of the recording apparatus.
A recording system having a continuous loop recording device as a supplementary recording device is an example of a prior art recording syste1n which uses a supplementary recording device. The continuous loop recording device has a recording head and a playback head positioned along a continuous loop of a recording medium, such as tape. The distance between the heads is such that the period of time required for the transit of the tape from the recording head to the playback head provides the time delay required for a detection and control apparatus to place the recording apparatus in the recording mode of operation.
The disadvantages of this and other prior art recording systems using supplementary recording devices are in the inherent risk of a mechanica] failure or of tape ~, 1l i8~i breakaqe in the supplementary recording clevice. Moreover, the duplication o~ recording required the duplication oE
jl costly components in teh supplementary recording device and j in the recording apparatus and additional space to ¦~ accommodate both the supplementary recording device and the Il recording apparatus. Furthermore, gradual degradation of ¦¦ the signal in the process of recording, playing back, and re-recording sound generated electrical signals introduces a substantial amount of distortion into the final desired I recording of sound by a recording apparatus and thereby diminishes the quality of the recording.
In an effort to solve some of the problems I encountered with prior art recording systems using supplementary recording devices, the prior art has also used an analog shift register in a recording system for delaying sound generated electrical signals in their transmission to a recording apparatus. While this recording system avoids some of the problems of cost and size encountered with prior art recording systems using supplementary recording devices, as well as the problems of tape breakage or mechanical failure, this prior art recording system still causes a gradual degradation of the sound generated electrical signals to be recorded by a recording apparatus and thereby diminishes the quality of the recording.
~¦ This diminu~tio~i in the quality of the recording ¦lis unavoidable because the sound generated electrical ~signals are analoq sigrlals and because distortion of an analog signal usually occurs when an analog signal is Illamplified and processed through an analog shift register to ~provide a time delay. Moreover, the infinite variety of 'I
.~ . . I . .
distinct analog wave forms in an analog signal generated by ~¦ sound such as h~man speech precludes any reconstruction of the analog signal after it has been passed through the shift 1~ register.
Il Therefore, the quality of the recording is 1~ irretrievably lost after distortion in an analog shift il register. The invention disclosed herein solves this problem of distortion by gradual signal degradation and I other problems encountered in prior art recording systems 10¦ having a detection and control apparatus to control the recording mode of operation of a recording apparatus so that i the recording apparatus is in the recording mode of ¦ operation when there is sound to be recor~ed.
SUMMARY OF THE INVENTION
¦ The invention disclosed herein is a recording ¦ system which has a time delay device that delays the transmission of sound to be recorded by a recordin~
apparatus until the recording apparatus has been placed in a l recording mode oE oper~tion by a detection and control 20~ apparatus in response to the presence of sound to be recorded. However, it has neither the inherent I disadvantages of recording systems which use supplementary l recording devices nor the distortion caused by gradual ¦~signal degradation as in prior art recording systems in ~which the sound generated signal is recorded, played back, I and re-recorded or amplified and processed through an analog hift register to obtain a time delay.
This improvement in recording systems is provided by a recording system having a time delay device which -~ !
converts sound generated electrical signals Erom analog signals into digital signals for processing through a ~¦ digital signal delay device to a recording apparatus that has been placed in a recording mode of operation by a 11, detection and control apparatus prior to the end of the time jll delay provided by the time delay device. Depending upon the ¦l embodiment of the invention, the detection and control apparatus is responsive to the presence or absence of sound I generated electrical signals as in prior art recording 10 I systems or is responsive to the presence or absence of I digital siqnals generated in the Eresen~ system. The latter ¦ improvement provides a more reliable detector of human ¦ speech and control of the recording mode of operation of the ~ recording apparatus than has been achieved in prior art 1~ recording devices.
Moreover, depending upon the embodiment of the invention, the invention provides for the recording by a recording apparatus of the transduced electrical signals on I a recording medium either as analog signals which are 20 ¦ substantially identical to the sound generated electrical signals or as digital signals that can be subsequently ~¦ converted into analog signals which are substantially i identical to the sound generated electrical siqnals.
However, regardless of the embodiment of the invention, the Il invention provides a recording system in which there is i substantially less distortion of sound generated electrical signals to be recorded by a recording apparatus than in prior art recording systems. This is because digital ~l signals are easily restored and reconstructed since each bit 301l of digital information possesses either one of two values.
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Thus, circui.t elements in the time (3ela~ device are ab:Le to accurate.ly amplify or reproduce the diqital si.f~na],s and to aceurately reconvert them into the analocl sic~nals which the digital signals had accurately approximated for recordin~ by the recording apparatus.
Thus in this parent application the invention comprehends a recording system which has a recordiny means for recording input electxical signals on a recording mediurn as transduced el.ectrical signals when the recordiny means is in a rscording mode o operation. The system also has a means for introducing the input electrical signals and for processing the input electrical siynals to provide the transduced electr.ical signals for recording on the recording medium by the recording means. The system fur-ther comprises a first means responsive to the input electr,ical signals for providing di.gital signals and a clicJital detec-ti.on and control means for controllir1g the .recorclin~ means. The detectlorl and corl~:rol. mean,s are comp:r:i.sed oE a digital.
magnitude comparison means which iS responsive to the digital signals, and detects digital sigIIals of a magnitucle corresp-onding to the magnitude of electrical input signals desired to be recorded. A discrete output is provided in response to each of the digital sicJnals which have a magnitude correspond ing to the ~agnitude o~ electrical input signals desired to be recorcled. A first counting means which i5 responsive to a predetermined number~ of the discrete outputs, provicles a control output. ~lso provicled is a second counting means, responsive to the absence of the discrete outputs for a predetermined interval of time~ for terrninatlncJ the con-txol.
output. ~ control means, responsive to the control output of the fir~t countincJ mea~ J causz~ the recordin~ means tc, be in the recording mocle of operati.on.
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u,t^ther, the pr~s~nt inven-tion tea~hes thal: t,he f:LI,s~t:
means may provide for delayed diy.ital ~ignals and rnay cornprise an analog to diyital conversion means for converting the lnpu~
electrical signals to digital siqnalsO A digital signal delay means, responsive to the digital signals, provides the delayed digital s.ignals after a predetermlned interval OL time.
A second means, :responsive to th~ clelayed digital signals may also be provided for the analog electrical signals to be recorded on a recording ~nedi~n by the recording means.
DESC~IPTIOM OF THE DRA IN~S
These and other features and advantages of the present invention will be more clearly understood upon consideration of the following specification and accompanying drawings i.n whlch:
Fig. 1 is a block diagram o an embodiment of the invention in which the recordirlg apparatus records transduced analog ~lectri.cal signals on a recordiny snedium ancl in whi.ch thi3 det,:ecti.on and control apparat.~:ls is re.spon.s.ive to the csf.lllrld generate~d electrical siynals prior.
to such siqnals entering the time delay clevice;
F.ig. 2 is a b].ock diagram of an embodiment of the invention in which the recording apparatus records transduced digital electrical signals on a recorcling rnedium and in which t,he detection and control apparatus is responsive to dlgital sic.3nals from the time delay device;
Fig. 3 is a block diagram o:E an embodiment of the invention in which the recording apparatus records transduced analo~ electrical signals on a recordinq medium and in which the cletection ancl contro~. apparatus is responsive to digital signals from the time delay devlce;
Fig. 4 is a ischematic diagram of the analoq to digital converter in those em~odiments of the invention shown in Figs. 1, 2 and 3, 7a i86 Fig. 5A is a graphic representation of the sound ¦ generated electrical signals as the~ enter the analog to ~¦ digital converter of Fig. 4;
¦ Fig. 5B is a graphic representation of the stepped analog signal provided within the analog to digital i! converter oE Fig. 4 in response to the sound generated Il electrical signal of Fig. 5A;
Fig. 5C is a graphic representation of the ~ 1 operation of the successive approximation register in the 10 ¦¦¦ analog to digital converter of Fig. 4 and shows the digital approximation of a voltage level corresponding to the stepped analog signal that is shown between the points A and ¦ B on the time a~is of Fig. 5B and that corresponds to the ¦¦ sound generated electrical signal shown between points A and ¦~ B on the time axis of Fig. 5A; and Fig. 6 is a block diagram of the digital detection ¦~ and control apparatus in that embodiment of the invention ~I shown in Figs. 2 and 3.
~ DETAIL~D DESCRIPTION OF FIE EMBODIMENTS
20 ¦1 In the following description o several ~¦ embodiments of the invention, the invention is embodied in a ~I recording system for recording sound such as the dictation of a dictator including a recording apparatus 11 which is placed and maintained in a recording mode of operation by a jl detection and control apparatus while there is sound to be ~¦ recorded. However, it will be understood that the invention ~may be embodied in other forms and in particular, it will be understood that the invention is not limited only to those jrecording systems described herein.
~f ,. I' i 1, , ~ osa6 ~¦ Rather, the invention may be embodied in reco-rding systems which record any form of electrical signal whether initially generated by a sound or not. Moreover, it may be embodied in a recording system which does not include a detection and control apparatus and in which the time delay device disclosed herein serves only to improve the quality l of the sound to be recorded by a recording apparatus 11.
¦~ This will be better understood from a ~ consideration of Fig. 1 which is a block diagram of a 10 1 recording system that embodies the invention disclosed herein~ The recording system includes arecording apparatus 11 which may be any conventional recording apparatus for ¦~ recording sound as transduced sound generated analog or ¦¦ digital electrical signals on a recording medium such as a tape or disc, an audio converter 2 which may be any conventional transducer such as a microphone for converting the sound into sound generated electrical signals which are ¦¦ analog signals, a variable ampliier 3? a low pass ~ilter 4, ! an analog to digital converter 6 for converting analog ¦ signals to cligital signa:Ls, a digital signal delay device 7, ¦ a digita]. to analog converter 8 for converting digital ~¦ signals to analog signals, a low pass filter 9, and a detection and control apparatus 10.
As will be set forth more ully below, the purpose of the digital signal delay device 7 is to provide a means for delaying or storing a digital signal for a desired period of time after it has been generated by the analog to ll digital converter 6 and before transmitting it to the ¦I recording apparatus 11. Thus, any digital hardware device 30 il or programmed c~igital device which will per~orm this , i .",~ 1' 058ti function by delaying or storing the digital signal for a desired period o time is a digital signal delay means within the definition of the present invention. While the ~¦ digital signal delay device 7 described in the present l~ embodiment of the invention is a shift register, it is ,¦ further disclosed that an alternative embodiment of this invention may include a random access memory. In that embodiment, the random access memory receives the successive Il digital signals from the analog to digital converter 6 and ~¦ stores the digital signals for a desired period of time ¦¦ after which the digital signals are successively retrieved ¦ from the random access memory in the sequence stored and ¦~ transmitted to the recording apparatus 11.
¦ It will also be understood that the recording li apparatus 11 may be conventional recording apparatus for i recording transduced analog or digital electrical siqnals on a recording medium such as a tape or disc. ~nasmuch as the I present invention provides for converting sound generated ~ analog electrical si~nals into dic~ital signal approximations of the sound generated analog electrical signals, the ¦ signals are placed in condition for recording by a recorder adapted for recording sound on a recording medium as transduced digital electrical signals. The present invention also provides for reconverting the digital signal approximations of the sound generated analog electrical signals into analog electrical signals after said digital signals have been delayed by the digital signal delay device 7. The reconverted analog electrical signals are than in lll condition for recording by a recorder adapted for recording sound on a recording medium as transduced analog electrical '', 10 1, Z~S8~
signals. The recording apparatus adapted Eor recording sound on a recording medium as transduced digital electrical signals may be distinct from a recording apparatus adapted Il for recording sound on a recording medium as transduced ¦l analog electrical signals; however, the recording apparatus may also be adapted for recording sound on a recording ~! medium both as transduced analog or electrical digital signals. Therefore, in the recording system of the present l invention, the recording apparatus 11 is not limited only to ¦ recording apparatus adapted solely for recording sound on a recording medium as either transduced digital electrical signals or as transduced analog electrical signals, but is referred to as the recording apparatus 11 without further ~¦ limitation.
In the embodiment of the invention shown in Fig.
1, the sound to be recorded is the voice of a person who wishes to record dictation and it will be understood that the sound generated electrical ~ignals from the audio converter 2 are in the audio requency range. In the embodiments of the invention shown in Fig. 1, as well as in the embodiments of the invention shown in Figs. 2 and 3, the variable amplifier 3, the low pass filter 4, the analog to 1 low pass filter 4, the analog to digital converter 6, and ¦~ the digital delay device 7 provide a time delay device D for I¦ causing the sound generated electrical signals from the i! audio converter 2 to reach the recording apparatus 11 a predetermined length of time after the detection and control apparatus 10 or 30 has placed the recording apparatus 11 in ll a recording mode of operation. In the particular embodiment 1 of the invention shown in Fig. 1, the detection and control 1)5~6 1~ apparatus 10 is respon~ive to the sounc1 generated electrical ¦I signals from audio converter 2, and as a result, the detection and control apparatus 10 may be a conventional voice operated relay which operates the recording apparatus in conventional manner to cause the recording apparatus 11 to be placed in a recording mode of operation in response to ~I the initial sound generated electrical signals from the I audio converter 2 and to continue in a recording mode of l operation until there have been no sound generated ¦ electrical signals from the audio converter 2 for a ¦l~ predetermined length of time.
However, it will be understood that in all of the ~¦ embodiments of the invention shown in Figs. 1, 2 and 3, the ¦ sound generated electrical signals are transmitted to the variable amplifier 3 of the time delay device D which is 1~ selectively varied in convention manner to adjust the ¦l amplitude of the sound generated electrical signals from the audio converter 2 to compensate for any loss of amplitude becau~se of the length of the line 1 between the audio converter 2 an~the time delay device.
Those skilled in the art will understand that the ¦ ti~e delay device D need not include the variable amplifer 3 if the line 1 is relatively short so that line loss is minimal or if the sound generated electrical si~nals would ¦ otherwise be of sufficient amplitude for processin~ through the time delay device D as described herein when they reach ,I the low pass filter 4.
'll Whether the time delay device D includes a ¦I variable amplifier or not, the low pass filter 4 operates in I conventional manner to pass only those frequencies of the , i ., ~
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~¦ sound generated electrical ~iqnal~ which can be accornmodated j by the subsequent analog to digital converter 6 without il distortion from undersampling. Moreover, in recording ¦I systms such as those in Figs. 1, 2 and 3 in which the sound j to be recorded is the voice of a dicta-tor the low pass ¦¦ filter 4 can be selected not to pass frequencies over 3khz so as to eliminate background noise.
From Fig. 4, it will be seen that the analog to ¦ digital converter 6 includes a switching means 41, such as a complementary metal oxide semiconductor analog switch, for selectively passing electrical currents, which when momentarily operated will cause the capacitance 42 to charge ¦ to a voltage corresponding to the amplitude of the sound Il generated electrical signals fromt he low pass filter 4 at ¦ the time that the switching means 41 is momentarily ¦ operated. During the periodic intervals of time in which ¦ the switching means 41 is not operating to introduce the ¦ sound generated electrical signals from the low pa~s Eilter 4, the charge o the capacitance 42 is maintained at a 1 constant level of voltage.
Thus, it will be understood the switching means 41 ¦ and the capacitance 42 serve as a sampling means for providing successive samples of the sound qenerated ¦¦ electrical signals such as the sample S-1 represented between points A and R in F`ig. 5A. It will also be ~ understood that the operation of the switching means 41 is jl is regulated in conventional manner by the successive ¦ approximation register 46 which causes the switching means 41 to charge the capacitance 42 with a new sample of the 30 1¦ sound generated electrical signals each time the successive '1, 13 ;~r jl CV5i~6 approximation register 46 ends an approximation cycle as described below.
It will be understood that when the capacitance 42 is successfully charged to voltages corresponding to successive amplitudes of the sound electrical signals, the sound generated electrical signals are changed from continuous wave analog signals as shown in Fig~ 5A to stepped analog signas as shown in Fig. 5B. For example, the continuous wave analog signal of the sample S-1 between points A and B in Fig. SA becomes in the capacitance 42 the stepped analog signal S-2 between points A and B in Fig.
5B.
The stepped analog representation shown in Fig. 5B
is then converted into a series of digital signals in which each digital signal represents a binary number approximating the voltage of a corresponding step in the stepped analog representation of the sound generated electrical signal. A
successive approximation register 46 performs this function.
The binary approximatlon is achieved by serially comparing each oE the stepped analog voltaqes, such as the signal S~2 at the capacitance 42, with successive analog conversions of digital signals generated by the successive approximation register 46 as successive binary approximations of the analog voltage. The conversion of each of these digital signals into analog voltaqes is accomplished by using a digital to analog converter 47 to convert the digital signals, each of which represents a binary ap~roximation of the stepped analog voltage, to their correspondinq analog voltages, such as the voltage S-3' in Fig. 5C. The analog conversion of a binary approximation is then introduce~ into '1 ll 14 ~2~
the comparator 44 and compared with the stepped analog signal to be approximated.
It will be understood that, depending upon the output from the comparator 44 after the comparison of the stepped analog signal S-2 and the analog voltage S-3' corresponding to the first binary approximation of the analog voltage S-2, the successive approximation which is converted to its corresponding analoq voltage S-3'' by the ~ digital to analog converter 47 and then similarly compared I with the stepped analog signal S-2. This process is 1 continued for a predetermined number of approximations N
¦~ until the stepped analog signal S-2 at the capacitance 42 has been accurately approximated as by the analog voltage ¦¦ S-3N in Fig. 5C. I
¦I Tihose skilled in the art will understand that upon ¦ completion of the successive approximations necessary to accurately approximate the stepped analog voltage S-2, the successive approximation register 46 will have generated a digital siqnal, consisting of a sequence of electrical bits, electricall~ representLng a binary number. Moreover, they ¦ will also understand that the digital signal corresponding to the analog voltage S-3N in Fig. 5C represents a binary number which accurately corresponds to the stepped analog l voltage S-2 of Fig. 5B which in turn corresponds to the sound generated electrical signal S-1 of Fig. 5A.
¦ It will also be understood that upon completion of 'll the predetermined number of approximations by the successive approximation register 46, the successive approximation Il register 47 provides an end of cycle (EOC) output. The EOC
¦ output causes the sequence of electrical bits representing 1~l i, 2VS~;
the binary number S-3N to be transferred from the successive ¦1 approximation re~ister 47 into the digital signal delay device 7. It also causes the switch 41 to close and charge I the capacitor 42 to another stepped analog voltage such as that between points B and C in Fi~. 5B.
Thus, the successive operation of analog to ¦ digital converter 6 as described above results in the sound ¦ generated electrical signals from the low pass filter 4 ~ being changed from continuous wave analog signals as shown in Fig. SA to a series of digital signals, each consisting of a sequence of electrical bits representinq a binary li number. Thos skilled in the art will understand that the accuracy with which these digital signals represent the sound generated electrical signals from the low pass filter 4 depends upon the rate at which the sound generated electrical signals are sampled by the sampling means provided by the switching means 41 and the capacitance 42.
IIn the presently described embodiment, this samplin~ rate is in turn determined by the rate at which the uccessive approximation register 46 completes its predetermined number of approximations and provides an EOC output to the switching means 41~ This rate of approximation completion ; is controlled by the frequency of a clock oscillator 45 and by the predetermined number of approximations N made by the ¦ successive approximation register 46.
¦ Thus, in the analog to digital converter 6 as shown in Fig. 4, the clock oscillator 45 has a 100 khz I ¦¦ frequency and the predetermined number of approximations N
~ made by the successive approximation register 46 in response to the clock oscillator is nine followed by an EOC
', `
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~i j output to the switching means A1 and the simultaneous transfer to the shift reyister 7 of the digital signal corresponding to the ninth approximation. As a result, the sampling rate at which the switching means 41 is operated to sample the sound generated electrical signals from the low ~ pass filter 4 is 10 khz. The sampling rate must be chosen ¦¦ to be at least twice as great as the highest frequency ¦¦ analog electrical signal to be approximated.
I! From this sampling rate, it will be readily lO ¦ understood by those skilled in the art that Figs. 5A, 5B and 5C are merely illustrative since this rate causes the time l between the points A and B on the time lines in these ! figures to be only 1/10000th of a second and the frequencies of sound generated electrical signals admitted through the low pass filter 4 is 3 khz or less. The period of the signals is therefore at least three times the period of each sample. Fig. 5A is merely illustrative of the technique and the sampling rate is exaggerated. Moreover, it will be readily understood that at this rate and at other rates which will be apparent to those skilled in the art, the digital signals from the succes5ive approximation register 46 will accurately represent the sound generated electrical signals for the low pass filter 4u ¦ In those embodiments of the invention disclosed herein, the digital signals received from the analog to ~ digital converter 6 by the digital delay device 7 must be ¦jretained within the digital delay device 7 for a sufficient j~period of time to allow a detection and control apparatus 10 llor 30 to cause the recording apparatus 11 to be placed in 30 1¦ the recording mode of operation. Accordingly, if the digital dela~ device 7 includes a p:Lurality of digital shift registers, the number of digital shift registers must be sufficient to simultaneously transmit the complete sequence of electrical bits needed to electrically represent each binary number as each new digital signal is received from ¦ the analog to digital converter 6~ Moreover, since the digital delay device 7, in this case a plurality of di~ital shift registers, operates in response to the EOC output from I the analog converter 6, each digital shift register must be l0 ¦ of sufficient capacity so that, in spite of its successive operation in response to the EOC to keep up with the analog to digital converter 6, the digital delay device 7 will retain the initial digital signal for a sufficient period of time to allow a detection and control apparatus 10 or 30 to cause the signal recordinq apparatus 11 to be placed in a recording mode of operation before the initial digital signal passes from the time delay device D.
For example, with further rePerence to the alternative embodiment in which the digital delay device 7 is a shift register and in which each digital signal Erom the analog to digital converter 6 at the end o each approximation cycle is a digital signal consisting of a sequence of eight bits which represents a binary number, the number of digital shift registers must be sufficient to ¦!receive simultaneously all eight bits from the analog to digital converter 6. Moreover, if each of these eight bits ¦is transmitted at the rate of 10 khz described above, ¦through a shift register which is sufficîently long to '~contain 1024 distinct digital signals, the plurality of 30 1¦ shift registers will serve as a digital signal delay device - li Ii 18 Il and provide a time dela~ of 10.2 milliseconds. Tho~e skilled in the art will understnad that this delay and other ¦ time delays which can be readily obtained by varying the rate of shift and the length of the shift register are I adequate periods in which to place a recording apparatus 11 in its recording mode of operation.
Similarly, in those alternative embodiments in I which the digital signal delay device 7 includes a plurality ¦l of random access memories, the number and capacity of the random access memories must be sufficient to simultaneously store the desired number of digital signals, each consisting, for example, of eight bits, for the desired period of time. Since the input and output of the random ¦ access memories are similarly controlled by the EOC output of the successive approximation register 46, the collective storage capacity of the random access memories must be lar~e ¦lenough that a digital signal made up of eight bits which has ~¦been stored in the random acess memories may contLnue to be ¦stored within the random access memories for the desired 20 ~period of time delay without having to be removed in the sequence in which it was stored in order to make room ~or later arriving digital signals which are being introduced into the random access memory at the rate dictated by this ~frequency of approximation of the successive approximation ~register 46. For example, if the successive approximation ¦Iregister 46 approximates the analog signals at a rate of 10 khz and each digital approximation consists of eight bits, llthe collective storage capacity of the random access ;¦memories needed in order to provide a delay of 102.4 30 1! milliseconds will be 8192 bits. This collective storage l l l Il 19 ,, . ~ j Z~958~
capacity ma~, for example, be provied by eight random access memories each having a storage capacity of 1024 bits or by four random access memories each having a storage capacity of 2048 bits. In the case where at least two bits of the same digital signal are to be stored in the same random access memory, the bits of input must be multiplexed for simultaneous input and output.
In that embodiment of the invention shown in Fig.
1, digital signals from the time delay device D are l0 1 transmitted into a digital to analog converter 8 for converting the digital signals from the time delay device D
into anaIog signals corresponding to the analog signals originally approximated by the analog to digital converter 6. The digital to analog converter 8 may be any one of the number of well known and commercially available digital to analog converters. However, a digital to analog converter ~
which is well adapted to the embodiment of the invention shown in Fig~ 1 is a diyital to analog converter that l generates a stepped signal based upon the successive binary numbers it receives as digital signals from the time de1ay device D.
These stepped electrical signals are transmitted through a low pass filter 9 which filters the hiqher harmonics in the stepped analog signals for accurately approximating the sound generated electrical signals, such as that of Fig. 5A, that were initially introduced into the ¦ time delay device D. These analog signals may then be lil transmitted from the low pass filter 9 to the recording !1 apparatus 11 and recorded.
1 The embodiment of the invention shown in ~ig. 2 , I
~ 1 20 ! ¦ .
)5~6 ', , includes the audio converter 2, a recording apparatus 11, and the time delay device D. However, it differs from the embodiment oE the invention shown in Fig. 1 in that it does not include th digital to analog converter 8 and the low pass filter 9. Thus, in the embodiment of the invention shown in Fig. 2, the sound generated electrical signals from the audio converter 2 are recorded by the recording apparatus 11 as digital signals.
The embodiment of Fig. 2 also differs from the ~ ~lO embodiment of Fig. 1 in that the detection and control I apparatus 30 for causing the recording apparatus 11 to be ; placed in a recording mode of operation is responslve to the digital signal from the analog to digital converter 6 rather than to the sound generated signals from the audio converter i 2. In this respect the embodiment of the invention shown in Fig. 2 is similar to the embodiment shown in Fig. 3 which is identical to the embodiment shown in Fig. 1 and described above except that it also includes a detection and control apparatus 30 for placing recording apparatus 11 in a recording mode of operation in response to the dlgital ~ignal Erom the analog to digital converter 7.
From Fig. 6, it will be seen that the digital detection and control apparatus 30 includes at least two digital magnitude comparators 61 and 61' for detecting the presence of digital signals above and below a preselected digital value. The digital magnitude comparators 61 and 61' ¦¦ are connected by an "or" gate 62 which will provide an "up"
,I to an up-down counter 63 output signal in response to a ~¦ signal to a signal from either digital magnitude comparator 1 61 or 61'. The arrangement of the comparators 61 and 61' in ¦ 21 z~
the embodiment illustrated in Fig. 6 makes the dicJital detection ancl control apparatus 30 responsive to digital signals which ave values greater or less than a range of ~¦ digital values between an upper limit VB set into the Il digital magnitude comparator 61'. This will be more clearly understood from a consideration of Fig. 5A in which the voltage S1 is the D.C. amplitude of the sound generated electrical signals shown in Fig. 5A and in which the l voltages VB and VB' are voltages which have been arbitrarily selected as voltages which will generally be exceeded by the amplitude of sound generated electrical signals caused by human speech desired to be recorded, but not by the amplitude of sound generated electrical signals caused by background noise. It should be further understood at this point that the analog to digital converter 6 will provide digital signals corresponding to all analog signals converted by the audio converter Z and passed through the low pass filter 4 reyardless of amplitude, even if between B2 and B3l or greater than B2 or less than B3'.
It will be understood by those skilled in the art that digital magnitude comparators are digital logic devices which provide a particular output depending upon the result of the comparison of a preselected digital value selected for comparison with a separate digital input wi~h that ~¦ separate digital input. The digital input provided for ¦ comparison is the digital output from the analog to digital ¦ I converter 6 as set forth above. In the embodiment of the analog to digital converter 6 which has been described, the ll digital signal output from the analog to digital converter 6 ¦ consists of a sequence of eight bits. However, the ,, I
1~ 22 1.i I
comparison voltages V~ an~ VB' may be determined by reference to the four most signi~icant bit~ of the binary numbers representing VB and VB'. For example, the digital value of the threshold voltage of sound to be recorded might be determined to ke 00111011. Any digital signal above 00110000 might be sufficiently near this threshold voltage that the detection and control apparatus could be responsive to all such signals without sacrificing any operational advantages. Therefore, the digital magnitude comparator 61 may be set to compare only the four most significant bits of each digital slgnal from the analog to digital converter 6 with the binary sequence 00110000. This preselected binary sequence is set into the digital magnitude comparator 61 inthe conventional manner to function as the higher limit setting VB. Similarly, another binary sequence is set into the digital magnitude comparator 61' in the conventional manner to function as the lower limit setting VB'.
Since~ as indicated above, the digital magnitude comparator 61 provides a dlscrete "up" signal to the up-down counter 63 through the "or" ~ate 62 indicating when the digital signal ~rom the analog to digital converter 6 is greater than the upper limit settinq and the digital magnitude comparator 61' provides an "up" signal to the up-down counter 63 through the "or" gate 62 indicating when the digital signal from the analog to digital converter 6 is less than the lower limit setting, it will be understood that the digital magnitude comparators 61 and 61' serve to provide "up" signals to the up-down counter 63 only when the digital signal OUtpllt from the analog to digital converter 6 indicates the presence of sound generated electrical signals i11 .
'' 23 from the audio converter 2 as defined by amplitudes above VB
and below VB' in Fig. 5A.
It is only by permitting "up" signals to be provided to the up-down counter 63 in response to electrical signals having a magnitude above VB or below VB that the comparators 61 and 61l detect the presence of sound generated electrical signals provided by human speech or dictation desired to be recorded. Further, it will be understood that the comparators 61 and 61' will not provide "up" signals to the up-down counter 63 in response to noise from the audio converter 2 and the low pass filter 4 as defined by signals having amplitudes between VB and VB' in Fig. 5A. In addition, it will be understood that the sensitivit~l of the detection and control apparatus 3U in terms of its ability to respond to sound generated electrical signals which are to be recorded, while not responding to noise, may be selectively adjusted by simply changin~ the higher limit setting, the lower limit setting, or both settings.
As shown in Fiq. 6, the up-down counter 63 which receives "up" signals fromthe magnitude comparators 61 and 61' also has an input 65 from the EOC output of the successive approximation register 46 in the analog to digital converter 6. The EOC output of the successive approximation register 46 provides a clock input 65 to the up-down counter 63 and controls the up-down counter 63 to cause it to operate only at the end of each approximation cycle of the analog to digital converter 6~ Thus/ the up-down counter 63 only operates in response to those "up"
signals from the comparators 61 and 61' which are caused by - ; llZ05d6 the digital signals from the analog to digital converter 6 which represent the final approximation of the sound l~ generated electrical signals. It will be further understood j! that the up-down counter 63 will not be responsive to digital signals of large magnitude which may be generated by the successive approximation register 46 during the process of digitally approximating the sound generated electrical signals.
l~ It will be understood by those skilled in the art l0¦~ that an up-down counter may count in a binary system and ¦¦ that the binary number indicated by the up-down counter is changed in response to the presence or absence of "up"
signals at the input to the counter. It will be further ! understood that the up-down counter may have separate load and reset inputs which cause the up-down counter to indicate a preselected number or æero, respectively, in response to an input at load or reset. It will also be understood that an up-down counter which counts in a binary systeJn has separate outputs provided by -the presence o~ a "one" at particular places in the sequence of bits which makes up the binary number. For example, an output may be provided by the presence of a "one" at the seventh place in the binary number 01000000 which corresponds to the number 64 in a decimal number system.
~¦ Referring now to the embodiment of the detection and control apparatus 30 shown in Fig. 6, -the up-down counter 63 is a binary up-down counter which is responsive to the output of the "or" gate 62 each time the EOC input Il causes the up-down counter 63 to count. The presence of an 30 l "up" signal from the "or" gate 62 at the input of the !l 5~6 i~ , ¦l up-down counter 63 causes the up-down counter 63 to count up thereby causing the number indicated to increase by one.
The absence of an "up" signal from the "or" gate 62 at the ¦ input of the up-down counter 63 causes the up-down counter 63 to count down thereby causing the number indicated to decrease by one~
I The control output 73 is selected from among the different outputs o-f the up-down counter 63 to cause output only after there have been continuous input signals for a desired period of time to assure that the "up" is caused by continuous dictation. Thus, in the embodiment of the detection and control apparatus 30 shown in Fig. 6, the output is chosen to correspond to the eighth place in the binary counter so that a control output will be caused by l the presence of a "one" in the eighth place of the counter i indicating that it has counted to binary 10000000 (or 128 in the decimal system), the control output initiation number.
As set orth above, the re~uency of the clock oscillator 45 provides an EOC output from the successive approximation register 46 at a frequency of 10 khz. Therefore, continuous ~ignaLs will be required for a period of 12.8 milliseconds in order for the up-down counter to cause a control output 73. Moreover, such a control output 73 will continue as long as a "one" remains at the eighth binary position of the ~¦ up-down counter 63.
¦ The embodiment of the detection and control ¦ apparatus 30 shown in Fig. 6 also includes a feedback circuit 64 from a preselected output of the up-down counter Il 63 to an "and" gate 70. For reasons that will become apparent, the output of the up-down counter 63 which will he 1' Il 26 Ii .
... Il .
Z~58~;
~ , chosen for the feedback circuit is the output that is provided by the presence of a "one" at the eighth binary position of the up-down counter 63. However, it will be understood that an output of the up-down counter 63 other f than that caused by the presence of a "one" at the eighth binary position could have been chosen~ l In addition to the input from the feedback circuit I :
I 64, the "and" gate 70 also has inputs from the EOC output of I the successive approximation register 46 and from the "or"
gate 62. Thus, the simultaneous presence of a "one" at the eighth binary position of the up-down counter 63 (also causing a control output 73), an EOC signal, and an output from the ~or~ gate 62, indicating the continuation of dictation, causes an output to be provided from the "and" I
: gate 70 to the load input 74 of the up-down counter 63.
Conversely, the absence of dictati.on reflected by the absence of an output ~rom the "or" gate 62 precludes a load output from the "and" gate 70. Thls permits the up-down counter 63 to count down b~ preventing the up-down counter 63 from loading the preselected member.
As described above, the effect of a load input 74 ¦1 at the up-down counter 63 is to cause the up-down counter 63 f lf~ to advance to a preselected number. The selection of this ¦I number can be made in such a manner as to cause the up-down ¦
counter 63 to be advanced a suficient number of binary numbers so that, despite the continued absence of signals ¦ from the "or" gate 62 and the concurrent counting down of the up-down counter, a "one" will remain at the output of ¦ the up-down counter 63 chosen as the control output 73, in 30 I the case of the present embodiment the eighth binary f 27 i position, Eor a predetermined period oE time. Cn the ca~e ¦l of the present embodiment, the preselected binary number chosen to be loaded is 11111111 (the equivalent of decimal 255). Since a "one" is present in this preselected number at the binary position chosen as the control output 73, the control output 73 will continue until there is no longer a "one" in the eighth binary position, even though the absence of dictation signals has caused the up-down counter 63 to I count down below 11111111. Thus~ the person dictating may lO ¦ pause for a period of time, established by the number of ~ cycles by which the preselected number (255) exceeds the ¦¦ lowest number at which a control output 73 is provided (128) and the period o~ time between each EOC signal (0.1 milliseconds), without causing the recording apparatus 11 to be taken out of the recording mode of operation. This period of time permitted for a pause will be 12.8 milliseconds in the present embodiment. It will be further understood by those skilled in the art that since the load input 74 respon~ive to continued dictation signals ~rom the "or" gate 6~ does not permit the up-down counter 63 to count c~ove the preselected number, the period of time permitted for a pause will be constant regardless of the length of time for which the speaker has been dictating continuously prior to the pause.
As set forth above, the up-down counter 63 also has a reset input 75 which will cause the up-down counter 63 ¦ to indicate zero or 00000000 in a binary number system ¦I whenever an input signal is received at the reset input. In i~ the embodiment of the detection and control apparatus 30 I shown in Fig. 6, the reset input 75 is electrically .1 .
Il 28 ~ o~d6 connected to an "and" ~ate 83. Thus, the up-down counter 63 will be reset to zero whenever an output from the "anc~" gate 83 is provided.
The inputs to the "and" gate 83 are provided by:
the EOC output from the successive approximation register 46; the output of a first inverter 84 responsive to the absence of dicta~ion signals from the "or" gate 62; and the output of a second inverter 85 responsive to the absence of a signal from a preselected output oE the up-down counter 63. In the presently disclosed embodiment, the output of the up-down counter 63 chosen to provide an input to the second inverter 85 is the output corresponding to the eighth binary position of the counter, the control output termination number. However, it will be understood that the preselected output may have been chosen from another output of the up-down counter 63.
The "and" gate 83 will, therefore, only reset the up-down counter 63 to zero at the end of an approximation cycle (EOC), when the absence oE an output signal Erom the "c)r" gate 62 indicates the absence of dictation and when there is also no control output 73 from the up-down counter 63. Thus, in the present embodiment, the up-down counter 63 will reset to zero once the up-down counter 63 counts down from the second preselected load number (255~ to below the first preselected number (128), which is therefore both the control output initiation and termination number, without a resumption of dictation. It will be further understood that once the up-down counter 63 has counted below the preselected control output termination number (128) and has been reset to zero, the zero wil 1 be maintained in the `, .
1ll 29 ., ~
,zu5a~ :
¦ up-down counter 63 until the output from the "or" gate 62 indicates the reSUmptiQn of dictation and the up-down counter 63 begins to count up. Thus, the continued absence of dictation will not cause the up-down counter to "count"
down below zero and "roll-over" to produce a control output ~¦ 73, but the up down counter 63 will retain the zero until li actual dictation as indicated by the output at the l'or" gate ¦ 62 resumes.
I It will now be understood by those skilled in the lO ¦ art that the digital detection and control apparatus 30 shown in Fig. 5 will provide a control output 73 to the recording apparatus 11 to place the recording apparatus 11 in the recording mode of operation upon the detection of dictation. It will be further understood that the absence I of a control output 73 caused by the absence of dictation ¦I for a predeter~ined period of time will cause the recording apparatus 11 to be taken out of the recording mode o ¦ operation. In addition, it will be understood that the I digital detection and control apparatus 30 is selectively 20 ¦ adjustable 90 as to provide a control output only upon the detection of desired sound signals of desired magnitude such as speech or dictation and not background noise. The digital detection and control apparatus 30 is also selectively adjustable so as to provide a control output ¦ only in the presence of continuous sound qenerated signals I of selected duration thereby eliminating a control output in Il, response to short loud noises which are not dictation. It will also be understood that the digital detection and control apparatus 30 is selectively adjustable so that 301 pauses or breaks in dictation of a selected short period ., ~ 30 fa~ ~
will not cause the recording apparatus 11 to be taken out of the recording mode oE operation.
The oregoing description sets forth illustrakive embodiments of the invention in a signal recording system comprising a signal recording apparatus and a signal time : delay system. It is to be understood that the signal time delay system may be used in any signal recording system, regardless of whether the signal is generated by an audio signal or not. It is further understood that the foregoing embodiments are merely illustrative embodiments oE the invention and that the scope of the invention is limited 5 le ~ by the appe~ded claims.
:;
... . .
,
"RECOXDING SYSTEM"
BACKGROUND OF THE INVENTION
1~ This invention relates to recording systems and ,' more particularly to a recording system for recording ,I transduced electrical signals on a recording medium with a recording apparatus having a mode of operation responsive to the transduced electrical .signals. Even more specifically, this invention i3 directed to .systems for recordin~
I dictation. With respect to StJCIl a recordillg system, it is 10 , known in the art to use a detection and control apparatus for initiating ancl ~erminating the recording mode of operation of a recording apparatus în response to the presence or absence of sound generated electrical signals so that the recording apparatus is itl the recording mode o~
, operation on:ly where there is dictation to be recorded.
~he detection and control apparatus starts the .,.,.,.~. ~k recordiny mode of operation of -the recording apparatus in response to sound generated electrical signals and terminates the recording mode of operation of the recording apparatus in response to the absence of sound generated electrical signals for a predetermined length of time. A
detection and control apparatus is particularly useful in a recording system in which the source of the sound to be recorded is an individual who wishes to record dictation and who is remote from the recording apparatus wih no means for controlling the recording mode of operation of the recording apparatus other than the sound of his voice and resulting sound generated electrical signals.
A difficulty which has been encountered in the use of a detection and control apparatus in a recording system is that the recording apparatus is not instantaneously placed in a recording mode of operation upon the initial detection of sound generated electrical signals b~ the detection and control apparatus. Therefore, the recording apparatus is not operating in the recording mode oE
operation when sound, such as the voice of a dictator, initially reaches the recording apparatus to be recorded as sound generated electrical signals. Thus, some of the sound, such as dictation, to be recorded is lost.
In order to solve this problem some prior art recording systems have used a supplementary recording device as a stage in the transmission of the sound generated electrical signals to the recording apparatus. This supplementary recording device records the initial sound and all subsequent sound as sound generated eletrical signals and plays the sound generated signals back after a time i i 2 ~ 7 1 1 ,' "
llzasa6 delay to the recording apparatus Eor recording by the recording apparatus. The length of this time delay is determined by the length of time needed for the recording apparatus to be placed in the recording mode of operation by the detection and control apparatus after detection of the initial sound generated electrical signals by the detection and control apparatus. Once placed in the recording mode of operation by the detection and control apparatus, the recording apparatus receives the records the delayed initial sound generated electrical signals and all subsequent signals from the supplementary recording device until sound generated electrical signals have ceased for a predetermined length of time to cause the detection and control apparatus to terminate the recording mode of operation of the recording apparatus.
A recording system having a continuous loop recording device as a supplementary recording device is an example of a prior art recording syste1n which uses a supplementary recording device. The continuous loop recording device has a recording head and a playback head positioned along a continuous loop of a recording medium, such as tape. The distance between the heads is such that the period of time required for the transit of the tape from the recording head to the playback head provides the time delay required for a detection and control apparatus to place the recording apparatus in the recording mode of operation.
The disadvantages of this and other prior art recording systems using supplementary recording devices are in the inherent risk of a mechanica] failure or of tape ~, 1l i8~i breakaqe in the supplementary recording clevice. Moreover, the duplication o~ recording required the duplication oE
jl costly components in teh supplementary recording device and j in the recording apparatus and additional space to ¦~ accommodate both the supplementary recording device and the Il recording apparatus. Furthermore, gradual degradation of ¦¦ the signal in the process of recording, playing back, and re-recording sound generated electrical signals introduces a substantial amount of distortion into the final desired I recording of sound by a recording apparatus and thereby diminishes the quality of the recording.
In an effort to solve some of the problems I encountered with prior art recording systems using supplementary recording devices, the prior art has also used an analog shift register in a recording system for delaying sound generated electrical signals in their transmission to a recording apparatus. While this recording system avoids some of the problems of cost and size encountered with prior art recording systems using supplementary recording devices, as well as the problems of tape breakage or mechanical failure, this prior art recording system still causes a gradual degradation of the sound generated electrical signals to be recorded by a recording apparatus and thereby diminishes the quality of the recording.
~¦ This diminu~tio~i in the quality of the recording ¦lis unavoidable because the sound generated electrical ~signals are analoq sigrlals and because distortion of an analog signal usually occurs when an analog signal is Illamplified and processed through an analog shift register to ~provide a time delay. Moreover, the infinite variety of 'I
.~ . . I . .
distinct analog wave forms in an analog signal generated by ~¦ sound such as h~man speech precludes any reconstruction of the analog signal after it has been passed through the shift 1~ register.
Il Therefore, the quality of the recording is 1~ irretrievably lost after distortion in an analog shift il register. The invention disclosed herein solves this problem of distortion by gradual signal degradation and I other problems encountered in prior art recording systems 10¦ having a detection and control apparatus to control the recording mode of operation of a recording apparatus so that i the recording apparatus is in the recording mode of ¦ operation when there is sound to be recor~ed.
SUMMARY OF THE INVENTION
¦ The invention disclosed herein is a recording ¦ system which has a time delay device that delays the transmission of sound to be recorded by a recordin~
apparatus until the recording apparatus has been placed in a l recording mode oE oper~tion by a detection and control 20~ apparatus in response to the presence of sound to be recorded. However, it has neither the inherent I disadvantages of recording systems which use supplementary l recording devices nor the distortion caused by gradual ¦~signal degradation as in prior art recording systems in ~which the sound generated signal is recorded, played back, I and re-recorded or amplified and processed through an analog hift register to obtain a time delay.
This improvement in recording systems is provided by a recording system having a time delay device which -~ !
converts sound generated electrical signals Erom analog signals into digital signals for processing through a ~¦ digital signal delay device to a recording apparatus that has been placed in a recording mode of operation by a 11, detection and control apparatus prior to the end of the time jll delay provided by the time delay device. Depending upon the ¦l embodiment of the invention, the detection and control apparatus is responsive to the presence or absence of sound I generated electrical signals as in prior art recording 10 I systems or is responsive to the presence or absence of I digital siqnals generated in the Eresen~ system. The latter ¦ improvement provides a more reliable detector of human ¦ speech and control of the recording mode of operation of the ~ recording apparatus than has been achieved in prior art 1~ recording devices.
Moreover, depending upon the embodiment of the invention, the invention provides for the recording by a recording apparatus of the transduced electrical signals on I a recording medium either as analog signals which are 20 ¦ substantially identical to the sound generated electrical signals or as digital signals that can be subsequently ~¦ converted into analog signals which are substantially i identical to the sound generated electrical siqnals.
However, regardless of the embodiment of the invention, the Il invention provides a recording system in which there is i substantially less distortion of sound generated electrical signals to be recorded by a recording apparatus than in prior art recording systems. This is because digital ~l signals are easily restored and reconstructed since each bit 301l of digital information possesses either one of two values.
' i .
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Thus, circui.t elements in the time (3ela~ device are ab:Le to accurate.ly amplify or reproduce the diqital si.f~na],s and to aceurately reconvert them into the analocl sic~nals which the digital signals had accurately approximated for recordin~ by the recording apparatus.
Thus in this parent application the invention comprehends a recording system which has a recordiny means for recording input electxical signals on a recording mediurn as transduced el.ectrical signals when the recordiny means is in a rscording mode o operation. The system also has a means for introducing the input electrical signals and for processing the input electrical siynals to provide the transduced electr.ical signals for recording on the recording medium by the recording means. The system fur-ther comprises a first means responsive to the input electr,ical signals for providing di.gital signals and a clicJital detec-ti.on and control means for controllir1g the .recorclin~ means. The detectlorl and corl~:rol. mean,s are comp:r:i.sed oE a digital.
magnitude comparison means which iS responsive to the digital signals, and detects digital sigIIals of a magnitucle corresp-onding to the magnitude of electrical input signals desired to be recorded. A discrete output is provided in response to each of the digital sicJnals which have a magnitude correspond ing to the ~agnitude o~ electrical input signals desired to be recorcled. A first counting means which i5 responsive to a predetermined number~ of the discrete outputs, provicles a control output. ~lso provicled is a second counting means, responsive to the absence of the discrete outputs for a predetermined interval of time~ for terrninatlncJ the con-txol.
output. ~ control means, responsive to the control output of the fir~t countincJ mea~ J causz~ the recordin~ means tc, be in the recording mocle of operati.on.
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u,t^ther, the pr~s~nt inven-tion tea~hes thal: t,he f:LI,s~t:
means may provide for delayed diy.ital ~ignals and rnay cornprise an analog to diyital conversion means for converting the lnpu~
electrical signals to digital siqnalsO A digital signal delay means, responsive to the digital signals, provides the delayed digital s.ignals after a predetermlned interval OL time.
A second means, :responsive to th~ clelayed digital signals may also be provided for the analog electrical signals to be recorded on a recording ~nedi~n by the recording means.
DESC~IPTIOM OF THE DRA IN~S
These and other features and advantages of the present invention will be more clearly understood upon consideration of the following specification and accompanying drawings i.n whlch:
Fig. 1 is a block diagram o an embodiment of the invention in which the recordirlg apparatus records transduced analog ~lectri.cal signals on a recordiny snedium ancl in whi.ch thi3 det,:ecti.on and control apparat.~:ls is re.spon.s.ive to the csf.lllrld generate~d electrical siynals prior.
to such siqnals entering the time delay clevice;
F.ig. 2 is a b].ock diagram of an embodiment of the invention in which the recording apparatus records transduced digital electrical signals on a recorcling rnedium and in which t,he detection and control apparatus is responsive to dlgital sic.3nals from the time delay device;
Fig. 3 is a block diagram o:E an embodiment of the invention in which the recording apparatus records transduced analo~ electrical signals on a recordinq medium and in which the cletection ancl contro~. apparatus is responsive to digital signals from the time delay devlce;
Fig. 4 is a ischematic diagram of the analoq to digital converter in those em~odiments of the invention shown in Figs. 1, 2 and 3, 7a i86 Fig. 5A is a graphic representation of the sound ¦ generated electrical signals as the~ enter the analog to ~¦ digital converter of Fig. 4;
¦ Fig. 5B is a graphic representation of the stepped analog signal provided within the analog to digital i! converter oE Fig. 4 in response to the sound generated Il electrical signal of Fig. 5A;
Fig. 5C is a graphic representation of the ~ 1 operation of the successive approximation register in the 10 ¦¦¦ analog to digital converter of Fig. 4 and shows the digital approximation of a voltage level corresponding to the stepped analog signal that is shown between the points A and ¦ B on the time a~is of Fig. 5B and that corresponds to the ¦¦ sound generated electrical signal shown between points A and ¦~ B on the time axis of Fig. 5A; and Fig. 6 is a block diagram of the digital detection ¦~ and control apparatus in that embodiment of the invention ~I shown in Figs. 2 and 3.
~ DETAIL~D DESCRIPTION OF FIE EMBODIMENTS
20 ¦1 In the following description o several ~¦ embodiments of the invention, the invention is embodied in a ~I recording system for recording sound such as the dictation of a dictator including a recording apparatus 11 which is placed and maintained in a recording mode of operation by a jl detection and control apparatus while there is sound to be ~¦ recorded. However, it will be understood that the invention ~may be embodied in other forms and in particular, it will be understood that the invention is not limited only to those jrecording systems described herein.
~f ,. I' i 1, , ~ osa6 ~¦ Rather, the invention may be embodied in reco-rding systems which record any form of electrical signal whether initially generated by a sound or not. Moreover, it may be embodied in a recording system which does not include a detection and control apparatus and in which the time delay device disclosed herein serves only to improve the quality l of the sound to be recorded by a recording apparatus 11.
¦~ This will be better understood from a ~ consideration of Fig. 1 which is a block diagram of a 10 1 recording system that embodies the invention disclosed herein~ The recording system includes arecording apparatus 11 which may be any conventional recording apparatus for ¦~ recording sound as transduced sound generated analog or ¦¦ digital electrical signals on a recording medium such as a tape or disc, an audio converter 2 which may be any conventional transducer such as a microphone for converting the sound into sound generated electrical signals which are ¦¦ analog signals, a variable ampliier 3? a low pass ~ilter 4, ! an analog to digital converter 6 for converting analog ¦ signals to cligital signa:Ls, a digital signal delay device 7, ¦ a digita]. to analog converter 8 for converting digital ~¦ signals to analog signals, a low pass filter 9, and a detection and control apparatus 10.
As will be set forth more ully below, the purpose of the digital signal delay device 7 is to provide a means for delaying or storing a digital signal for a desired period of time after it has been generated by the analog to ll digital converter 6 and before transmitting it to the ¦I recording apparatus 11. Thus, any digital hardware device 30 il or programmed c~igital device which will per~orm this , i .",~ 1' 058ti function by delaying or storing the digital signal for a desired period o time is a digital signal delay means within the definition of the present invention. While the ~¦ digital signal delay device 7 described in the present l~ embodiment of the invention is a shift register, it is ,¦ further disclosed that an alternative embodiment of this invention may include a random access memory. In that embodiment, the random access memory receives the successive Il digital signals from the analog to digital converter 6 and ~¦ stores the digital signals for a desired period of time ¦¦ after which the digital signals are successively retrieved ¦ from the random access memory in the sequence stored and ¦~ transmitted to the recording apparatus 11.
¦ It will also be understood that the recording li apparatus 11 may be conventional recording apparatus for i recording transduced analog or digital electrical siqnals on a recording medium such as a tape or disc. ~nasmuch as the I present invention provides for converting sound generated ~ analog electrical si~nals into dic~ital signal approximations of the sound generated analog electrical signals, the ¦ signals are placed in condition for recording by a recorder adapted for recording sound on a recording medium as transduced digital electrical signals. The present invention also provides for reconverting the digital signal approximations of the sound generated analog electrical signals into analog electrical signals after said digital signals have been delayed by the digital signal delay device 7. The reconverted analog electrical signals are than in lll condition for recording by a recorder adapted for recording sound on a recording medium as transduced analog electrical '', 10 1, Z~S8~
signals. The recording apparatus adapted Eor recording sound on a recording medium as transduced digital electrical signals may be distinct from a recording apparatus adapted Il for recording sound on a recording medium as transduced ¦l analog electrical signals; however, the recording apparatus may also be adapted for recording sound on a recording ~! medium both as transduced analog or electrical digital signals. Therefore, in the recording system of the present l invention, the recording apparatus 11 is not limited only to ¦ recording apparatus adapted solely for recording sound on a recording medium as either transduced digital electrical signals or as transduced analog electrical signals, but is referred to as the recording apparatus 11 without further ~¦ limitation.
In the embodiment of the invention shown in Fig.
1, the sound to be recorded is the voice of a person who wishes to record dictation and it will be understood that the sound generated electrical ~ignals from the audio converter 2 are in the audio requency range. In the embodiments of the invention shown in Fig. 1, as well as in the embodiments of the invention shown in Figs. 2 and 3, the variable amplifier 3, the low pass filter 4, the analog to 1 low pass filter 4, the analog to digital converter 6, and ¦~ the digital delay device 7 provide a time delay device D for I¦ causing the sound generated electrical signals from the i! audio converter 2 to reach the recording apparatus 11 a predetermined length of time after the detection and control apparatus 10 or 30 has placed the recording apparatus 11 in ll a recording mode of operation. In the particular embodiment 1 of the invention shown in Fig. 1, the detection and control 1)5~6 1~ apparatus 10 is respon~ive to the sounc1 generated electrical ¦I signals from audio converter 2, and as a result, the detection and control apparatus 10 may be a conventional voice operated relay which operates the recording apparatus in conventional manner to cause the recording apparatus 11 to be placed in a recording mode of operation in response to ~I the initial sound generated electrical signals from the I audio converter 2 and to continue in a recording mode of l operation until there have been no sound generated ¦ electrical signals from the audio converter 2 for a ¦l~ predetermined length of time.
However, it will be understood that in all of the ~¦ embodiments of the invention shown in Figs. 1, 2 and 3, the ¦ sound generated electrical signals are transmitted to the variable amplifier 3 of the time delay device D which is 1~ selectively varied in convention manner to adjust the ¦l amplitude of the sound generated electrical signals from the audio converter 2 to compensate for any loss of amplitude becau~se of the length of the line 1 between the audio converter 2 an~the time delay device.
Those skilled in the art will understand that the ¦ ti~e delay device D need not include the variable amplifer 3 if the line 1 is relatively short so that line loss is minimal or if the sound generated electrical si~nals would ¦ otherwise be of sufficient amplitude for processin~ through the time delay device D as described herein when they reach ,I the low pass filter 4.
'll Whether the time delay device D includes a ¦I variable amplifier or not, the low pass filter 4 operates in I conventional manner to pass only those frequencies of the , i ., ~
~Z~ G
~¦ sound generated electrical ~iqnal~ which can be accornmodated j by the subsequent analog to digital converter 6 without il distortion from undersampling. Moreover, in recording ¦I systms such as those in Figs. 1, 2 and 3 in which the sound j to be recorded is the voice of a dicta-tor the low pass ¦¦ filter 4 can be selected not to pass frequencies over 3khz so as to eliminate background noise.
From Fig. 4, it will be seen that the analog to ¦ digital converter 6 includes a switching means 41, such as a complementary metal oxide semiconductor analog switch, for selectively passing electrical currents, which when momentarily operated will cause the capacitance 42 to charge ¦ to a voltage corresponding to the amplitude of the sound Il generated electrical signals fromt he low pass filter 4 at ¦ the time that the switching means 41 is momentarily ¦ operated. During the periodic intervals of time in which ¦ the switching means 41 is not operating to introduce the ¦ sound generated electrical signals from the low pa~s Eilter 4, the charge o the capacitance 42 is maintained at a 1 constant level of voltage.
Thus, it will be understood the switching means 41 ¦ and the capacitance 42 serve as a sampling means for providing successive samples of the sound qenerated ¦¦ electrical signals such as the sample S-1 represented between points A and R in F`ig. 5A. It will also be ~ understood that the operation of the switching means 41 is jl is regulated in conventional manner by the successive ¦ approximation register 46 which causes the switching means 41 to charge the capacitance 42 with a new sample of the 30 1¦ sound generated electrical signals each time the successive '1, 13 ;~r jl CV5i~6 approximation register 46 ends an approximation cycle as described below.
It will be understood that when the capacitance 42 is successfully charged to voltages corresponding to successive amplitudes of the sound electrical signals, the sound generated electrical signals are changed from continuous wave analog signals as shown in Fig~ 5A to stepped analog signas as shown in Fig. 5B. For example, the continuous wave analog signal of the sample S-1 between points A and B in Fig. SA becomes in the capacitance 42 the stepped analog signal S-2 between points A and B in Fig.
5B.
The stepped analog representation shown in Fig. 5B
is then converted into a series of digital signals in which each digital signal represents a binary number approximating the voltage of a corresponding step in the stepped analog representation of the sound generated electrical signal. A
successive approximation register 46 performs this function.
The binary approximatlon is achieved by serially comparing each oE the stepped analog voltaqes, such as the signal S~2 at the capacitance 42, with successive analog conversions of digital signals generated by the successive approximation register 46 as successive binary approximations of the analog voltage. The conversion of each of these digital signals into analog voltaqes is accomplished by using a digital to analog converter 47 to convert the digital signals, each of which represents a binary ap~roximation of the stepped analog voltage, to their correspondinq analog voltages, such as the voltage S-3' in Fig. 5C. The analog conversion of a binary approximation is then introduce~ into '1 ll 14 ~2~
the comparator 44 and compared with the stepped analog signal to be approximated.
It will be understood that, depending upon the output from the comparator 44 after the comparison of the stepped analog signal S-2 and the analog voltage S-3' corresponding to the first binary approximation of the analog voltage S-2, the successive approximation which is converted to its corresponding analoq voltage S-3'' by the ~ digital to analog converter 47 and then similarly compared I with the stepped analog signal S-2. This process is 1 continued for a predetermined number of approximations N
¦~ until the stepped analog signal S-2 at the capacitance 42 has been accurately approximated as by the analog voltage ¦¦ S-3N in Fig. 5C. I
¦I Tihose skilled in the art will understand that upon ¦ completion of the successive approximations necessary to accurately approximate the stepped analog voltage S-2, the successive approximation register 46 will have generated a digital siqnal, consisting of a sequence of electrical bits, electricall~ representLng a binary number. Moreover, they ¦ will also understand that the digital signal corresponding to the analog voltage S-3N in Fig. 5C represents a binary number which accurately corresponds to the stepped analog l voltage S-2 of Fig. 5B which in turn corresponds to the sound generated electrical signal S-1 of Fig. 5A.
¦ It will also be understood that upon completion of 'll the predetermined number of approximations by the successive approximation register 46, the successive approximation Il register 47 provides an end of cycle (EOC) output. The EOC
¦ output causes the sequence of electrical bits representing 1~l i, 2VS~;
the binary number S-3N to be transferred from the successive ¦1 approximation re~ister 47 into the digital signal delay device 7. It also causes the switch 41 to close and charge I the capacitor 42 to another stepped analog voltage such as that between points B and C in Fi~. 5B.
Thus, the successive operation of analog to ¦ digital converter 6 as described above results in the sound ¦ generated electrical signals from the low pass filter 4 ~ being changed from continuous wave analog signals as shown in Fig. SA to a series of digital signals, each consisting of a sequence of electrical bits representinq a binary li number. Thos skilled in the art will understand that the accuracy with which these digital signals represent the sound generated electrical signals from the low pass filter 4 depends upon the rate at which the sound generated electrical signals are sampled by the sampling means provided by the switching means 41 and the capacitance 42.
IIn the presently described embodiment, this samplin~ rate is in turn determined by the rate at which the uccessive approximation register 46 completes its predetermined number of approximations and provides an EOC output to the switching means 41~ This rate of approximation completion ; is controlled by the frequency of a clock oscillator 45 and by the predetermined number of approximations N made by the ¦ successive approximation register 46.
¦ Thus, in the analog to digital converter 6 as shown in Fig. 4, the clock oscillator 45 has a 100 khz I ¦¦ frequency and the predetermined number of approximations N
~ made by the successive approximation register 46 in response to the clock oscillator is nine followed by an EOC
', `
~Z~5~
~i j output to the switching means A1 and the simultaneous transfer to the shift reyister 7 of the digital signal corresponding to the ninth approximation. As a result, the sampling rate at which the switching means 41 is operated to sample the sound generated electrical signals from the low ~ pass filter 4 is 10 khz. The sampling rate must be chosen ¦¦ to be at least twice as great as the highest frequency ¦¦ analog electrical signal to be approximated.
I! From this sampling rate, it will be readily lO ¦ understood by those skilled in the art that Figs. 5A, 5B and 5C are merely illustrative since this rate causes the time l between the points A and B on the time lines in these ! figures to be only 1/10000th of a second and the frequencies of sound generated electrical signals admitted through the low pass filter 4 is 3 khz or less. The period of the signals is therefore at least three times the period of each sample. Fig. 5A is merely illustrative of the technique and the sampling rate is exaggerated. Moreover, it will be readily understood that at this rate and at other rates which will be apparent to those skilled in the art, the digital signals from the succes5ive approximation register 46 will accurately represent the sound generated electrical signals for the low pass filter 4u ¦ In those embodiments of the invention disclosed herein, the digital signals received from the analog to ~ digital converter 6 by the digital delay device 7 must be ¦jretained within the digital delay device 7 for a sufficient j~period of time to allow a detection and control apparatus 10 llor 30 to cause the recording apparatus 11 to be placed in 30 1¦ the recording mode of operation. Accordingly, if the digital dela~ device 7 includes a p:Lurality of digital shift registers, the number of digital shift registers must be sufficient to simultaneously transmit the complete sequence of electrical bits needed to electrically represent each binary number as each new digital signal is received from ¦ the analog to digital converter 6~ Moreover, since the digital delay device 7, in this case a plurality of di~ital shift registers, operates in response to the EOC output from I the analog converter 6, each digital shift register must be l0 ¦ of sufficient capacity so that, in spite of its successive operation in response to the EOC to keep up with the analog to digital converter 6, the digital delay device 7 will retain the initial digital signal for a sufficient period of time to allow a detection and control apparatus 10 or 30 to cause the signal recordinq apparatus 11 to be placed in a recording mode of operation before the initial digital signal passes from the time delay device D.
For example, with further rePerence to the alternative embodiment in which the digital delay device 7 is a shift register and in which each digital signal Erom the analog to digital converter 6 at the end o each approximation cycle is a digital signal consisting of a sequence of eight bits which represents a binary number, the number of digital shift registers must be sufficient to ¦!receive simultaneously all eight bits from the analog to digital converter 6. Moreover, if each of these eight bits ¦is transmitted at the rate of 10 khz described above, ¦through a shift register which is sufficîently long to '~contain 1024 distinct digital signals, the plurality of 30 1¦ shift registers will serve as a digital signal delay device - li Ii 18 Il and provide a time dela~ of 10.2 milliseconds. Tho~e skilled in the art will understnad that this delay and other ¦ time delays which can be readily obtained by varying the rate of shift and the length of the shift register are I adequate periods in which to place a recording apparatus 11 in its recording mode of operation.
Similarly, in those alternative embodiments in I which the digital signal delay device 7 includes a plurality ¦l of random access memories, the number and capacity of the random access memories must be sufficient to simultaneously store the desired number of digital signals, each consisting, for example, of eight bits, for the desired period of time. Since the input and output of the random ¦ access memories are similarly controlled by the EOC output of the successive approximation register 46, the collective storage capacity of the random access memories must be lar~e ¦lenough that a digital signal made up of eight bits which has ~¦been stored in the random acess memories may contLnue to be ¦stored within the random access memories for the desired 20 ~period of time delay without having to be removed in the sequence in which it was stored in order to make room ~or later arriving digital signals which are being introduced into the random access memory at the rate dictated by this ~frequency of approximation of the successive approximation ~register 46. For example, if the successive approximation ¦Iregister 46 approximates the analog signals at a rate of 10 khz and each digital approximation consists of eight bits, llthe collective storage capacity of the random access ;¦memories needed in order to provide a delay of 102.4 30 1! milliseconds will be 8192 bits. This collective storage l l l Il 19 ,, . ~ j Z~958~
capacity ma~, for example, be provied by eight random access memories each having a storage capacity of 1024 bits or by four random access memories each having a storage capacity of 2048 bits. In the case where at least two bits of the same digital signal are to be stored in the same random access memory, the bits of input must be multiplexed for simultaneous input and output.
In that embodiment of the invention shown in Fig.
1, digital signals from the time delay device D are l0 1 transmitted into a digital to analog converter 8 for converting the digital signals from the time delay device D
into anaIog signals corresponding to the analog signals originally approximated by the analog to digital converter 6. The digital to analog converter 8 may be any one of the number of well known and commercially available digital to analog converters. However, a digital to analog converter ~
which is well adapted to the embodiment of the invention shown in Fig~ 1 is a diyital to analog converter that l generates a stepped signal based upon the successive binary numbers it receives as digital signals from the time de1ay device D.
These stepped electrical signals are transmitted through a low pass filter 9 which filters the hiqher harmonics in the stepped analog signals for accurately approximating the sound generated electrical signals, such as that of Fig. 5A, that were initially introduced into the ¦ time delay device D. These analog signals may then be lil transmitted from the low pass filter 9 to the recording !1 apparatus 11 and recorded.
1 The embodiment of the invention shown in ~ig. 2 , I
~ 1 20 ! ¦ .
)5~6 ', , includes the audio converter 2, a recording apparatus 11, and the time delay device D. However, it differs from the embodiment oE the invention shown in Fig. 1 in that it does not include th digital to analog converter 8 and the low pass filter 9. Thus, in the embodiment of the invention shown in Fig. 2, the sound generated electrical signals from the audio converter 2 are recorded by the recording apparatus 11 as digital signals.
The embodiment of Fig. 2 also differs from the ~ ~lO embodiment of Fig. 1 in that the detection and control I apparatus 30 for causing the recording apparatus 11 to be ; placed in a recording mode of operation is responslve to the digital signal from the analog to digital converter 6 rather than to the sound generated signals from the audio converter i 2. In this respect the embodiment of the invention shown in Fig. 2 is similar to the embodiment shown in Fig. 3 which is identical to the embodiment shown in Fig. 1 and described above except that it also includes a detection and control apparatus 30 for placing recording apparatus 11 in a recording mode of operation in response to the dlgital ~ignal Erom the analog to digital converter 7.
From Fig. 6, it will be seen that the digital detection and control apparatus 30 includes at least two digital magnitude comparators 61 and 61' for detecting the presence of digital signals above and below a preselected digital value. The digital magnitude comparators 61 and 61' ¦¦ are connected by an "or" gate 62 which will provide an "up"
,I to an up-down counter 63 output signal in response to a ~¦ signal to a signal from either digital magnitude comparator 1 61 or 61'. The arrangement of the comparators 61 and 61' in ¦ 21 z~
the embodiment illustrated in Fig. 6 makes the dicJital detection ancl control apparatus 30 responsive to digital signals which ave values greater or less than a range of ~¦ digital values between an upper limit VB set into the Il digital magnitude comparator 61'. This will be more clearly understood from a consideration of Fig. 5A in which the voltage S1 is the D.C. amplitude of the sound generated electrical signals shown in Fig. 5A and in which the l voltages VB and VB' are voltages which have been arbitrarily selected as voltages which will generally be exceeded by the amplitude of sound generated electrical signals caused by human speech desired to be recorded, but not by the amplitude of sound generated electrical signals caused by background noise. It should be further understood at this point that the analog to digital converter 6 will provide digital signals corresponding to all analog signals converted by the audio converter Z and passed through the low pass filter 4 reyardless of amplitude, even if between B2 and B3l or greater than B2 or less than B3'.
It will be understood by those skilled in the art that digital magnitude comparators are digital logic devices which provide a particular output depending upon the result of the comparison of a preselected digital value selected for comparison with a separate digital input wi~h that ~¦ separate digital input. The digital input provided for ¦ comparison is the digital output from the analog to digital ¦ I converter 6 as set forth above. In the embodiment of the analog to digital converter 6 which has been described, the ll digital signal output from the analog to digital converter 6 ¦ consists of a sequence of eight bits. However, the ,, I
1~ 22 1.i I
comparison voltages V~ an~ VB' may be determined by reference to the four most signi~icant bit~ of the binary numbers representing VB and VB'. For example, the digital value of the threshold voltage of sound to be recorded might be determined to ke 00111011. Any digital signal above 00110000 might be sufficiently near this threshold voltage that the detection and control apparatus could be responsive to all such signals without sacrificing any operational advantages. Therefore, the digital magnitude comparator 61 may be set to compare only the four most significant bits of each digital slgnal from the analog to digital converter 6 with the binary sequence 00110000. This preselected binary sequence is set into the digital magnitude comparator 61 inthe conventional manner to function as the higher limit setting VB. Similarly, another binary sequence is set into the digital magnitude comparator 61' in the conventional manner to function as the lower limit setting VB'.
Since~ as indicated above, the digital magnitude comparator 61 provides a dlscrete "up" signal to the up-down counter 63 through the "or" ~ate 62 indicating when the digital signal ~rom the analog to digital converter 6 is greater than the upper limit settinq and the digital magnitude comparator 61' provides an "up" signal to the up-down counter 63 through the "or" gate 62 indicating when the digital signal from the analog to digital converter 6 is less than the lower limit setting, it will be understood that the digital magnitude comparators 61 and 61' serve to provide "up" signals to the up-down counter 63 only when the digital signal OUtpllt from the analog to digital converter 6 indicates the presence of sound generated electrical signals i11 .
'' 23 from the audio converter 2 as defined by amplitudes above VB
and below VB' in Fig. 5A.
It is only by permitting "up" signals to be provided to the up-down counter 63 in response to electrical signals having a magnitude above VB or below VB that the comparators 61 and 61l detect the presence of sound generated electrical signals provided by human speech or dictation desired to be recorded. Further, it will be understood that the comparators 61 and 61' will not provide "up" signals to the up-down counter 63 in response to noise from the audio converter 2 and the low pass filter 4 as defined by signals having amplitudes between VB and VB' in Fig. 5A. In addition, it will be understood that the sensitivit~l of the detection and control apparatus 3U in terms of its ability to respond to sound generated electrical signals which are to be recorded, while not responding to noise, may be selectively adjusted by simply changin~ the higher limit setting, the lower limit setting, or both settings.
As shown in Fiq. 6, the up-down counter 63 which receives "up" signals fromthe magnitude comparators 61 and 61' also has an input 65 from the EOC output of the successive approximation register 46 in the analog to digital converter 6. The EOC output of the successive approximation register 46 provides a clock input 65 to the up-down counter 63 and controls the up-down counter 63 to cause it to operate only at the end of each approximation cycle of the analog to digital converter 6~ Thus/ the up-down counter 63 only operates in response to those "up"
signals from the comparators 61 and 61' which are caused by - ; llZ05d6 the digital signals from the analog to digital converter 6 which represent the final approximation of the sound l~ generated electrical signals. It will be further understood j! that the up-down counter 63 will not be responsive to digital signals of large magnitude which may be generated by the successive approximation register 46 during the process of digitally approximating the sound generated electrical signals.
l~ It will be understood by those skilled in the art l0¦~ that an up-down counter may count in a binary system and ¦¦ that the binary number indicated by the up-down counter is changed in response to the presence or absence of "up"
signals at the input to the counter. It will be further ! understood that the up-down counter may have separate load and reset inputs which cause the up-down counter to indicate a preselected number or æero, respectively, in response to an input at load or reset. It will also be understood that an up-down counter which counts in a binary systeJn has separate outputs provided by -the presence o~ a "one" at particular places in the sequence of bits which makes up the binary number. For example, an output may be provided by the presence of a "one" at the seventh place in the binary number 01000000 which corresponds to the number 64 in a decimal number system.
~¦ Referring now to the embodiment of the detection and control apparatus 30 shown in Fig. 6, -the up-down counter 63 is a binary up-down counter which is responsive to the output of the "or" gate 62 each time the EOC input Il causes the up-down counter 63 to count. The presence of an 30 l "up" signal from the "or" gate 62 at the input of the !l 5~6 i~ , ¦l up-down counter 63 causes the up-down counter 63 to count up thereby causing the number indicated to increase by one.
The absence of an "up" signal from the "or" gate 62 at the ¦ input of the up-down counter 63 causes the up-down counter 63 to count down thereby causing the number indicated to decrease by one~
I The control output 73 is selected from among the different outputs o-f the up-down counter 63 to cause output only after there have been continuous input signals for a desired period of time to assure that the "up" is caused by continuous dictation. Thus, in the embodiment of the detection and control apparatus 30 shown in Fig. 6, the output is chosen to correspond to the eighth place in the binary counter so that a control output will be caused by l the presence of a "one" in the eighth place of the counter i indicating that it has counted to binary 10000000 (or 128 in the decimal system), the control output initiation number.
As set orth above, the re~uency of the clock oscillator 45 provides an EOC output from the successive approximation register 46 at a frequency of 10 khz. Therefore, continuous ~ignaLs will be required for a period of 12.8 milliseconds in order for the up-down counter to cause a control output 73. Moreover, such a control output 73 will continue as long as a "one" remains at the eighth binary position of the ~¦ up-down counter 63.
¦ The embodiment of the detection and control ¦ apparatus 30 shown in Fig. 6 also includes a feedback circuit 64 from a preselected output of the up-down counter Il 63 to an "and" gate 70. For reasons that will become apparent, the output of the up-down counter 63 which will he 1' Il 26 Ii .
... Il .
Z~58~;
~ , chosen for the feedback circuit is the output that is provided by the presence of a "one" at the eighth binary position of the up-down counter 63. However, it will be understood that an output of the up-down counter 63 other f than that caused by the presence of a "one" at the eighth binary position could have been chosen~ l In addition to the input from the feedback circuit I :
I 64, the "and" gate 70 also has inputs from the EOC output of I the successive approximation register 46 and from the "or"
gate 62. Thus, the simultaneous presence of a "one" at the eighth binary position of the up-down counter 63 (also causing a control output 73), an EOC signal, and an output from the ~or~ gate 62, indicating the continuation of dictation, causes an output to be provided from the "and" I
: gate 70 to the load input 74 of the up-down counter 63.
Conversely, the absence of dictati.on reflected by the absence of an output ~rom the "or" gate 62 precludes a load output from the "and" gate 70. Thls permits the up-down counter 63 to count down b~ preventing the up-down counter 63 from loading the preselected member.
As described above, the effect of a load input 74 ¦1 at the up-down counter 63 is to cause the up-down counter 63 f lf~ to advance to a preselected number. The selection of this ¦I number can be made in such a manner as to cause the up-down ¦
counter 63 to be advanced a suficient number of binary numbers so that, despite the continued absence of signals ¦ from the "or" gate 62 and the concurrent counting down of the up-down counter, a "one" will remain at the output of ¦ the up-down counter 63 chosen as the control output 73, in 30 I the case of the present embodiment the eighth binary f 27 i position, Eor a predetermined period oE time. Cn the ca~e ¦l of the present embodiment, the preselected binary number chosen to be loaded is 11111111 (the equivalent of decimal 255). Since a "one" is present in this preselected number at the binary position chosen as the control output 73, the control output 73 will continue until there is no longer a "one" in the eighth binary position, even though the absence of dictation signals has caused the up-down counter 63 to I count down below 11111111. Thus~ the person dictating may lO ¦ pause for a period of time, established by the number of ~ cycles by which the preselected number (255) exceeds the ¦¦ lowest number at which a control output 73 is provided (128) and the period o~ time between each EOC signal (0.1 milliseconds), without causing the recording apparatus 11 to be taken out of the recording mode of operation. This period of time permitted for a pause will be 12.8 milliseconds in the present embodiment. It will be further understood by those skilled in the art that since the load input 74 respon~ive to continued dictation signals ~rom the "or" gate 6~ does not permit the up-down counter 63 to count c~ove the preselected number, the period of time permitted for a pause will be constant regardless of the length of time for which the speaker has been dictating continuously prior to the pause.
As set forth above, the up-down counter 63 also has a reset input 75 which will cause the up-down counter 63 ¦ to indicate zero or 00000000 in a binary number system ¦I whenever an input signal is received at the reset input. In i~ the embodiment of the detection and control apparatus 30 I shown in Fig. 6, the reset input 75 is electrically .1 .
Il 28 ~ o~d6 connected to an "and" ~ate 83. Thus, the up-down counter 63 will be reset to zero whenever an output from the "anc~" gate 83 is provided.
The inputs to the "and" gate 83 are provided by:
the EOC output from the successive approximation register 46; the output of a first inverter 84 responsive to the absence of dicta~ion signals from the "or" gate 62; and the output of a second inverter 85 responsive to the absence of a signal from a preselected output oE the up-down counter 63. In the presently disclosed embodiment, the output of the up-down counter 63 chosen to provide an input to the second inverter 85 is the output corresponding to the eighth binary position of the counter, the control output termination number. However, it will be understood that the preselected output may have been chosen from another output of the up-down counter 63.
The "and" gate 83 will, therefore, only reset the up-down counter 63 to zero at the end of an approximation cycle (EOC), when the absence oE an output signal Erom the "c)r" gate 62 indicates the absence of dictation and when there is also no control output 73 from the up-down counter 63. Thus, in the present embodiment, the up-down counter 63 will reset to zero once the up-down counter 63 counts down from the second preselected load number (255~ to below the first preselected number (128), which is therefore both the control output initiation and termination number, without a resumption of dictation. It will be further understood that once the up-down counter 63 has counted below the preselected control output termination number (128) and has been reset to zero, the zero wil 1 be maintained in the `, .
1ll 29 ., ~
,zu5a~ :
¦ up-down counter 63 until the output from the "or" gate 62 indicates the reSUmptiQn of dictation and the up-down counter 63 begins to count up. Thus, the continued absence of dictation will not cause the up-down counter to "count"
down below zero and "roll-over" to produce a control output ~¦ 73, but the up down counter 63 will retain the zero until li actual dictation as indicated by the output at the l'or" gate ¦ 62 resumes.
I It will now be understood by those skilled in the lO ¦ art that the digital detection and control apparatus 30 shown in Fig. 5 will provide a control output 73 to the recording apparatus 11 to place the recording apparatus 11 in the recording mode of operation upon the detection of dictation. It will be further understood that the absence I of a control output 73 caused by the absence of dictation ¦I for a predeter~ined period of time will cause the recording apparatus 11 to be taken out of the recording mode o ¦ operation. In addition, it will be understood that the I digital detection and control apparatus 30 is selectively 20 ¦ adjustable 90 as to provide a control output only upon the detection of desired sound signals of desired magnitude such as speech or dictation and not background noise. The digital detection and control apparatus 30 is also selectively adjustable so as to provide a control output ¦ only in the presence of continuous sound qenerated signals I of selected duration thereby eliminating a control output in Il, response to short loud noises which are not dictation. It will also be understood that the digital detection and control apparatus 30 is selectively adjustable so that 301 pauses or breaks in dictation of a selected short period ., ~ 30 fa~ ~
will not cause the recording apparatus 11 to be taken out of the recording mode oE operation.
The oregoing description sets forth illustrakive embodiments of the invention in a signal recording system comprising a signal recording apparatus and a signal time : delay system. It is to be understood that the signal time delay system may be used in any signal recording system, regardless of whether the signal is generated by an audio signal or not. It is further understood that the foregoing embodiments are merely illustrative embodiments oE the invention and that the scope of the invention is limited 5 le ~ by the appe~ded claims.
:;
... . .
,
Claims (14)
1. A recording system having a recording means for re-cording analog electrical signals on a recording medium when said recording means is in a recording mode of operation, and a means for introducing input electrical signals into said system and for processing said input electrical signals to provide said analog electrical signals for recording on said recording medium by said recording means, wherein the improvement comprises:
a first means responsive to said input electrical signals for providing delayed digital signals, said first means comprising an analog to digital conversion means for converting said input electrical signals to digital signals, and a digital signal delay means, responsive to said digital signals, for providing said delayed digital signals after a predetermined interval of time;
a second means responsive to said delayed digital signals for providing said analog electrical signals for re-cording on a recording medium by said recording means; and digital detection and control means for controlling said recording means comprising a digital magnitude comparison means for providing a discrete output in response to each of said digital signals having a magnitude greater than a predetermined magnitude, a first counting means, responsive to a predetermined number of said discrete outputs, for providing a control output, a second counting means, responsive to the absence of said discrete outputs for a predetermined interval of time, for terminating said control output, and a control means, responsive to said control output of said first counting means, for causing said recording means to be in said recording mode of operation.
a first means responsive to said input electrical signals for providing delayed digital signals, said first means comprising an analog to digital conversion means for converting said input electrical signals to digital signals, and a digital signal delay means, responsive to said digital signals, for providing said delayed digital signals after a predetermined interval of time;
a second means responsive to said delayed digital signals for providing said analog electrical signals for re-cording on a recording medium by said recording means; and digital detection and control means for controlling said recording means comprising a digital magnitude comparison means for providing a discrete output in response to each of said digital signals having a magnitude greater than a predetermined magnitude, a first counting means, responsive to a predetermined number of said discrete outputs, for providing a control output, a second counting means, responsive to the absence of said discrete outputs for a predetermined interval of time, for terminating said control output, and a control means, responsive to said control output of said first counting means, for causing said recording means to be in said recording mode of operation.
2. A recording system as recited in Claim 1 wherein said digital magnitude comparison means comprises at least one digital magnitude comparator.
3. A recording system as recited in Claim 1 wherein said first counting means comprises an up/down counter.
4. The recording system of Claim 1 wherein said pre-determined number of said discrete outputs is selectively variable.
5. The recording system of Claim 1 wherein said predetermined interval of time is selectively variable.
6. The recording system of Claim 1 further including:
reset means for setting said first counting means to a zero count in response to the concurrent absence of a dis-crete output from said digital magnitude comparison means and said control output.
reset means for setting said first counting means to a zero count in response to the concurrent absence of a dis-crete output from said digital magnitude comparison means and said control output.
7. A recording system having a recording means for recording input electrical signals on a recording medium as transduced electrical signals when said recording means is in a recording mode of operation, and a means for introducing said input electrical signals into said system and for processing said input electrical signals to provide said transduced electrical signals for recording on said recording medium by said recording means, wherein the improvement comprises:
a first means responsive to said input electrical signals for providing digital signals; and a digital detection and control means for controlling said recording means, comprising a digital magnitude comparison means responsive to said digital signals, for detecting digital signals of a magnitude corresponding to the magnitude of electrical input signals desired to be recorded and for providing a discrete output in response to each of said digital signals having a magnitude corresponding to the magnitude of electrical input signals desired to be recorded, a first counting means, responsive to a predetermined number of said discrete outputs, for providing a control out-put, a second counting means, responsive to the absence of said discrete outputs for a predetermined interval of time, for terminating said control output, and a control means, responsive to said control output of said first counting means, for causing said recording means to be in said recording mode of operation.
a first means responsive to said input electrical signals for providing digital signals; and a digital detection and control means for controlling said recording means, comprising a digital magnitude comparison means responsive to said digital signals, for detecting digital signals of a magnitude corresponding to the magnitude of electrical input signals desired to be recorded and for providing a discrete output in response to each of said digital signals having a magnitude corresponding to the magnitude of electrical input signals desired to be recorded, a first counting means, responsive to a predetermined number of said discrete outputs, for providing a control out-put, a second counting means, responsive to the absence of said discrete outputs for a predetermined interval of time, for terminating said control output, and a control means, responsive to said control output of said first counting means, for causing said recording means to be in said recording mode of operation.
8. A recording system as recited in Claim 7 wherein said digital magnitude comparison means comprises at least one digital magnitude comparator.
9. A recording system as recited in Claim 7 wherein said second counting means comprises an up/down counter.
10. The recording system of Claim 7 wherein said predetermined number of said discrete outputs is selectively variable.
11. The recording system of Claim 7 wherein said predetermined interval of time is selectively variable.
12. The recording system of Claim 7 further including:
reset means for setting said first counting means to a zero count in response to the concurrent absence of a discrete output from said digital magnitude comparison means and said control output.
reset means for setting said first counting means to a zero count in response to the concurrent absence of a discrete output from said digital magnitude comparison means and said control output.
13. A recording system as recited in Claim 7 wherein said first counting means comprises an up/clown counter.
14. A recording system as recited in Claim 13 wherein said second counting means comprises the up/down counter of said first counting means.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000303461A CA1120586A (en) | 1978-05-16 | 1978-05-16 | Recording system |
| CA000384516A CA1143470A (en) | 1978-05-16 | 1981-08-24 | Digital control apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000303461A CA1120586A (en) | 1978-05-16 | 1978-05-16 | Recording system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1120586A true CA1120586A (en) | 1982-03-23 |
Family
ID=4111482
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000303461A Expired CA1120586A (en) | 1978-05-16 | 1978-05-16 | Recording system |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1120586A (en) |
-
1978
- 1978-05-16 CA CA000303461A patent/CA1120586A/en not_active Expired
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |