CA1117599A - Time of day demand metering system and method - Google Patents

Abstract

TIME-OF-DAY DEMAND METERING SYSTEM AND METHOD
ABSTRACT OF THE DISCLOSURE

A time of day demand metering system is disclosed for registering the amount of electrical energy consumed during the one demand interval of maximum electrical energy consumption out of a plurality of demand intervals. Means is provided to engage the register of a time-of-day meter only during those demand intervals when the amount of electrical energy being consumed is in excess of the one previous demand interval of maximum electrical energy consumption.

Description

L-~MI~ ;0 TIME-OF-DAY DEMAND MF,TERING SYSTEM ~ND M:ETHC)I:~
~ , _~ ,i,,'"
sac~ground oE the Invention ~);
,,~,, This invention relates generally to demand metering !~
systems and more particularly to electronically controlled time of day demand metering systems for registering the amount of electrical energy consumed during speci~ied demand time ~ ~' intervals of the day. i"
Utility companies have generally sold electrical t~
energy on the basis of a fixed rate schedule regardless of whether high or low demand has been made upon the electrical ~,'!;~
generation system. This type of rate scheduling has not 7.
provided the consumer with the incentive to voluntarily ~;
reduce his power consumption, particularly during those periods of high peak demand. As a result, in order to prevent j~;
overloading the power distribution system, utility companies have had to add additional power generating capacity which can ;15 be brought on line during peak power periods. The addition of ~';this power generating capacity has placed an economic burden I `~x on the utility companies as well as the consumer, as the cost of the power generating equipment must he passed on to the ~ consumer. This is an undesirable economic burden, particularly 1 when it is realized that the additional power generati~g equip- ~.
¦ ment is brought on line only during those periods of high peak ¦ demand. Thus, the additional equipment is only ~sed part time, ¦ resulting in inefficiencies since a much larger power generat- ;
¦ ing plant and distribution system than is economically ~ I
¦ desirable is required in order to meet those periods of ;
peak demand. I~i In the past few years, with the escalating costs of r'~;
generating electrical energy, utility companies and the manu-- :~
¦ facturers of electrical energy metering systems have attempted ¦ to develop equipment and devices which will provide for more ~ ~ .
¦ efficient use of electrical generation and power distribution ~1 ~;
I 1 . ' ' ~`' ~ ~
, _ 7~"3.~

facilitles during both on and off peak load periods. Many of these devices have resulted in the development of multipLe rate metering of electrical power consumption which adopts the philosophy that the consumer whose consumption of electrical energy is principally during on-peak demand periods should ~e billed at a higher rate than the consumer whose consumption is primarily during periods of low, off-peak or mid-peak periods.
This multiple rate price structuring appears to be justified when it is realized that the low demand usage customer who is billed at the same rate as the high demand usage customer, in effect subsidizes the high demand user. Differential pricing would, therefore, from a customer standpoint, appear to be more equitable. From the standpoint o the utility companies, a multiple rate pricing structure will encourage consumers of electrical power to shift their consumption of power from on-peak intervals to off-peak intervals, thus increasing the overall power distribution SYstem efficiency and reducing the capital expendi-tures norma}ly required to supply extra power generating equipment daring on-peak periods.
So far as it is known, the prior art systems have employed, for the most part, conventional kilowatt-hour meters having two sets of register dials to provide a dual rate price structured billing system. One such prior art attempt to individually register different amounts of power consumed during different intervals of the day is disclosed in U.S. Patent 2j139,821 issuea December 13, 1938 to Greenwood et al. In that paten~ a simplified two-stage mechanical watt meter mechanism having an associated clock timer is disclosed. Cams on the clock timer are ased to trip a mechanism which, at selected times during the day, permit the selective driving of one or the other of two sets of meter register dials so that the amount of electrical energy consumed during the various an and off ,~

~ 9 ~ 50 peak periods of the day can be reyistered on the appropriate dials.
Developments subsequent to Greenwooa et al (U.S.
Patent 2,246,185, issued June 17, 1941) and Cameron (U.S.
Patent 2,132,256, issued October 4, 193~) utilized dual rate metering systems incorporating a clock which determined which set of various meters were to be activated during the various on and off peak periods. Other dual rate kilowatt-hour metering systems which exemplify representative prior art structures are disclosed in the following patents: Ogurpowski U.S.
Patent 2,415,653, issued February 11, 1947; Feldman et al U.S. Patent 3,683,343, issued August 8, 1972; and Kahn U.S.
Patent 2,915,704, issued December 1, 1959.
Another prior art multiple rate structure system is disclosed in U.S. Patent 4,050,020 issued September 20, 1977 to Germer et al and assigned to the assignee of the present invention. This patent is directed toward an electronic time-of-day metering system which is preprogrammed to selectively activate two sets of register dials at predetermined times of the day to register the amount of power consumption during designated peak intervals (e.g. high-peak and mid-peak). The present invention is ideally suited for operation with the invention with the invention of the U.S. Patent No. 4,050,020 dated September 20, 1977 - Germer. Further U.S. patent No. 4,093,997 dated June 6, 1978 entitled "Portable Programmer ~or ~ Time-of-Day Metering Register System" and assigned to - the assignee of the present invention ~iscIosed a programmer for programming the meter of U.S. Patent No.
4,050,020 dated September 20, 1977 - Germer. To further encourage consumers to utilize less power during on-peak intervals, utility companies have suggested a ..

~ 3~3 ~ 50 1 ~
,' I ''~:
¦l three rate billing s~ructure. In -that type of structure, the ~! consumer is billed at the norma:L rate for his total power consumption, plus an additional ~mount at a higher rate for 1 1 1l the amount of power he uses during on-peak intervals. This : -5 11 is just like the previously described two rate structure. ;
¦~ However, in the three rate pricing structure, the consumer ¦ is bil1ed still an additi.onal amount for the amount of power ¦¦ he consumes in the one demand interval of maximum power con- .
¦¦ sumption. For example, in a 30 day month, there may be thirty l0 l programmed on-peak periods (l per day), with each period last- --l ing six hours. However, durlny each of these periods there ¦ ~
f may be extremely high peak intervals when the demand for more ~ -1 energy places an overload burden on the power distribution ¦¦ system causing the utility company to bring additional power 1 j"
¦ generating equipment on line, thus increasing the cost of ¦ power generation. It is during these extremely high peak ~
1 intervals that the consumer will pay an additional amount, if :
¦¦ his demand for power exceeds a predetermined amount as estab- ;
l lished by the utility company. However, the consumer will pay only for that amount of energy consumed in the one demand .
interval, out of all of the demand intervals, of maximum ¦ energy consumption. .
There has been proposed, various types of three rate I ¦ billing structured systems. One such system contemplates the 25 ¦~ use of three conventional kilowatt-hour meters interconnected ~
through various mechanical clock and switch mechanisms. One ~:
of the meters continuously registers the total amount of con-sumed energy, while a second meter is engaged via the clock and switch mechanism to register the amount of energy consumed ¦ during predetermined on-peak periods. A third meter is engaged, ¦l via the clock and switch mechanism, to register the amount of 1 i ¦¦ energy consumed during predetermined demand intervals during 1I the on-peak periods. The utility company, taking the various ; ;

_i''"~.

7S~3~3 2l-lq~-so meter readings, can then bill the customer according to his usage of energy using the three rate structure. W~ile the three meter time-of-day demand gystem proposed may functionally perform, it has not received ~ide acceptance by the utility S companies due to the excess costs of three meters plus addition-al installation expenses.
Therefore, a need exists for a fully integrated single time-of-day demand metering system utilizing one meter which provides the ~ull capability of implementing an easily installed and readily changeable three rate billing structure to the changing rate structures o~ the utility companies.
It is therefore an object of the present invention .
to provide an improved method and apparatus for measuring and ¦ displaying electrical power consumption on different meter displays to allow a three rate billing structure to be ¦ implemented.
¦ It is another object to provide a time-of-day demand metering.system h~ g. enhanced operating.
capabilities.
A further object of the invention is to provide a system for measuring the consumption of power from an electri-cal generation and distribution system during peak periods, during predetermined demand intervals occuring in those periods and registering the amount of energy consumed during the one period of maximum demand.
Another object is to provide a system including a programmable time-of-day .demand meter having the capability of implementing a plurality of rate structured billing routines for selectively measuring and displaying the consumption of electrical energ~ from a power distxibution system during on-peak periods and during demand intervals of various selected periods in order to encourage consumers of electrical power to shift consumption oi power from on-peak to off-peak periods.

7i~9~ 21-ME-50 A still further object is to provide a method and apparatus in a time of day demand metering system for measuring the total consumption of electrical eneryy, the amount of energy consumed during prescribed peak power period~ and the amount of energy consumed during the one demand interval o~ maximum energy consumption out of all o~ the peak power periods.
It is another object to provide a programmable meter in a time of day demand metering system including a method and apparatus for measuring the amount of energy consumed during predetermined peak power periods of the day and further measur-ing the amount of energy consumed during the one demand interval, out of a plurality of predetermined demand intervals, of maximum power demand.

Summary of the Invention The present invention accomplishes the foregoing objects by providing an energy distribution system including a method and apparatus for measuring peak and demand electrical power at predetermined times o~ the day and recording the amount of energy consumed on respective peak and demand mechanical recording devices. Further, a mechanical kilowatt-hour (KWH) meter having a conventional set of decade gear driven dials, registers, on a continuous basis, the total KWH's consumed by the system.
The consumption of peak and demand power is recorded on respective decade gear driven rate dials. The peak dials are capable of being engaged and disenyaged at preselected peak power periods. The peak power periods may vary from day to day and hour to hour and, accordingly, a programmable logic control circuit is provided for selectively driving the peak rate dials and for also enabling the demand rate dials to be enabled during preselected intervals when power is in excess demand by the user (customer) of the system.
The programmable logic control aircuit utilizes as its . ~_~_ 9'~ 1 i¦ 21-ME-50 time base the 60 llz frequency derived from the energy distri-bution system being metered. A clock circuit is provided for yenerating time in the form of a control signal at specified increments (e.g. every 15 minutes) on a w~ekly basis. rL'he S logic control circuit includes a memory which is preprogrammed to contain the times at which the peak rate dials are to be engaged and the times during which the demand rate dials may be actuated or engaged.
One function command or control signal is generated 0 by the logic control circuit for engaging or disengaging the decade gear driven peak rate dials. ~nother function command or control signal is generated by the logic control circuit.
This latter control signal is provided to a demand logic cir-¦ cuit at predetermined demand intervals to either enable or dis-¦ able that circuit to engage or disengage the demand dials.
¦ A comparison is made between the magnitude of a new value ¦ proportional to the amount of energy being consumed and the magnitude of a previously stored value proportional to the one previous demand interval of maximum energy co~sumption.
When the new value is at least equal to the previous value, the demand decade driven dials are engaged to register the amount of energy consumed in excess of the maximum previously registered for the remainder or duration of the present demand interval. The present demand interval is terminated by the control signal effecting a disengagement of the demand rate dials via the demand logic circuit.

Brief Description of the Drawing Other objects, features and advantages of the present invention, will become more fully apparent from the following detailed description of the preferred embodiment, the appended claims and the accompanying drawing in which:
Fig. 1 is a high level schematic block diagram of the time of da~ demand metering system of the present invention , ,,_ ~

~ig. ~ ls a frollt view of a preferred form of mechanical three rate register incorporatiny the present invention, Fig. 3 is a schemati.c block diagram o~ the dernand logic circuit of Fig. 1 and illustrates i~s interconnection to the programmable control circuit, Fig. 4 is a leyendary drawing showing the inter-relationships between Figs. 4A and 4B when positioned as : illustrated, Fig. 4A i5 a detailed schematic logic diagram of the Demand Enable ON/OFF peak Detector Logic and the Sequencing Logic of Fig. 3, Fig. 4B is a detailed schematic logic diagram of the Demand Interval Counter/Logic, the Pulse Initiator Logic, the Time Interval Counter/Logic and the Meter Reglster Solenoid and Clutch Drive of Fig. 3, Fiys. 5, 6, 7A, 7B, 8A, 9A, 9B, 10A, 10B, llA and -llB are timing diagrams having descriptive titles useful in understanding the operation of the present invention, Figs. 7 - 11 are legendary drawings showing the interrelationshlps between their respectively associated`
drawings 7A - llB when positioned as illustrated.

Descri tion of the Preferred Embodiment P - .
Referring first tp Fig. 2, it should be understood ~ ~x~ e~ ~
that in the pre~erred two sets of decade gear driven register dials designated A (the on peak register) and ~; Demand (for registering demand interval power consumption) are included in the mechanical portion of the KWH meter of the present invention. As illustrated in Fig. 2I these two sets of dials are positioned above and below a conventional set of five dials which continuously reyister total K~H consumption ~ ` in the same manner as a conventional five-dial pointer register :
.~

E1ther set oE dials, A or Oemarld, can be engagetl to indicate consump~ion of power, or disengaged 50 that no con-sumption of power is registered, as determined by the program-mable control circuit and the Dernand loglc circuit of Fig. 1.
When disengaged, the A and Dernand dials remain fixed at their last reading until again engaged.
The purpose of having the A and Demand dials select-ively engageable is to provide utilities with a three-level rate billing structure, ie., total power usage on the Total register, ON-peak usage on the A register, and power u~age on the Demand Register during preselected demand time intervals when the amount of power being consumed is in excess of the one previous demand interval of maximum power consumption.
Reference is now made to Fig. 1 which illustrates a Programmable Control Circuit 11. The detailed structure and operational:d$s~cx~ip~ion o~ that circuit is disclosed in the afore-mentioned 4,050,020 Patent, and reference is made specifically thereto for those details. However, si~ce the present invention ma~es use of certain signals generated by the Control Circuit 11, ¦ a brief description of that circuit is provided for clarification purposes and completeness of disclosure of the present invention.
l Still referring to Fig. 1, the Control Circuit 11 ¦ senerates control signals at specified times for selectively - ¦ engaging the Peak or A Register rate drive gears 13 and for ¦ enabling a Demand Logic Circuit 15 to provide a demand reyister ~ ¦ engagement signal to the Demand Register rate drive year train I ¦ 17. The Total Register 19 receives no control signals and is ¦ driven in a conventional manner as is common in the standard ¦ KWH meter.
~ 30 ¦ The Control Circuit 11 is energized from a 60 Hz power ;~ ¦ line via a power supply 21. A Battery Charger 23 receives ¦ current from the Power Supply 21 to charge a Rechargeable ¦ Battery 25. The Battery 25 is utilized to provide current to : ' I
I . '9 r.~; . . .

2 ~ - 5 0 the contro:L Circult 11, both directly and -throu~Jh a DC-DC
Converter 27, to keep the timing ~unction of the co~trol circuit operable should a power outage occur. Xn addition to pxoviding power to the Control Circuit 11, the 60 Hz input to the power supply 21 is utilized as a time base or that circuit. The 60 Hz from the power supply is also provided to the Demand Logic Circuit for purposes to be described. A
Quartz Crystal Oscillator 29 is also provided, and serves as an alternate time base input to the control circuit during power outages. Reference is made to the aforementioned U.S.
Patent 4,050,020 for a detailed description of these latter elements.
The Programmable Control Circuit 11 also includes a timer in the form of a 7-day clock which performs the timing functions for enabling the Demand Logic Circuit 15 and for engaging and disengaging the drive gears of the Pea]c Register dials 13. The output of the 7-day clock is resolved into 15-minute intervals, with each output capable of controlling one or more timed functions at any one of the 15-minute intervals.
As an example, signals from the 7-day clock can control dis-engagement of the Peak Register 13, enablement of the Demand ~L~ Logic Circuit ~ and, if desired, switch on or off a Load Control Circuit 31 to control a customer's switch not shown.
The Control Circuit 11 can be programmed to enable or inhibit the operation o any one or all of the Demand Logic Circuit, the Load Control Circuit or the Peak Register at any time of the day on a 7-day basis. The timer also drives a single digit Time Display 33 which sequentlally displays the day, hours and minutes (see Fig. 2).
The Control Circuit 11 is elec-tronically programmed by means of a Portable Programmer Tester 35 which is disclosed in the aforementiOned United States Patent Number -4,093,997 dated June 6, 1978. The Portable Programmer " ' Tester 35 is connected -to the ~ontrol Circuit 11 by "
an electrical connector 37 (Fiy. 2) whioh is accessed throuyh a sealable opening in the meter enclosure (not shown). The ,~, Programmer Tester contains its own battery operated power ' '~
supply, an oscillator controlled,7-clay clock and appropriate ',ij circuitry for testing, reprogramming and sekting the tirne of i.,, , day demand metering system of the present invention. ,'r Still referring to Fig.,l, ~he Demand Logic Circuit ~,i,i;
15 receives input signals from a pulse initiator circuit 39 ,, and a manually operable Monkhly Reset Switch 41. The Pulse Ini~iator 39 continuously provides pulses to the Demand Logic Circuit proportional to the amount of electrical energy being ~"
consumed by the system. How ~hese pulses are utilized by the Demand Logic Circuit will subsequently be described. The Monthly Reset Switch 41 is accessed through the meter front cover (see Fig. 2) and provides a resat signal to the Demand Logic Circuit 15 when actuated by a utility company emplo,yee 'r~
such as a meter reader. The Reset Switch is normally utilized ,, to initialize the Demand Logic Circuit each month after ~e meter dials have been read.
' Reference is now made to Fig. 3 which is a schematic block diagram of the Demand Logic Circuit 15 o the present invention. The Programmable Control Circuit 11 is re-illus~a- ~' ~ ed in Fig. 3 to more clearly show its relationship with the , various circuits of the Demand Logic Circuit. , As previously described, the Control Circuit 11 17 receives the 60 Hz signal from khe power supply 21 (Fig. 1) ' and utilizes this signal as a time base to generate an output function or control signal designated Pl on a conductor 43. ' 'rhrough the program and timing or clock circuits, the Control Circuit is capable of supplying the Pl signal at specific , times to be either in or out of phase with the 60 Hz signal.
In the aforementioned U.S. Patent ~ 4,050,020, the Pl signal~is . .
_ 11 _ _ ,, ............... -- -------- - _ '~! ` , " ,,;;, . . . . .

~ 3 1~ M~
,. ,~
applied to a maynetically operated clutch asser~ly (see E'ig, 5 of 4,050,020) via a transistor,73 and triac 69 to enyaye and ;~
disengage one set of alternate rate reyister dials in accord- -, ance with the phase relationship o~ the P1 and 60 Hz signals.
In the presen~ invention, the ~emand Logic Circuit has been inserted directly into the Pl signal line 43 feeding the drive transistor 73. This connection is illustrated in ~
. Fig. 1, showing the conductor 43 connect~d to the ~emand ,.
. Logic Circuit. An output conductor 45 provides the drive signal to tran~istor 73 to effect the engagement and dis-engagement of the register dials. In the present invention! 'i that drive signal is shown as a DEM (~emand) signal in Fig. 3 feeding a block 47 designated as Meter Register Solenoid and Clutch Drive. The block 47 contains the transistor 73, triac 69, the solenoid and clutch drive and the Demand Register ;, dials 17. In the present invention, while the Demand Register l' 17 is the same as the alternate register in the U.S.Patent r' 4,050,020 it serves an ~,~ntirely diferent purpose than in the ~i 4,050,020 Patent by accumulatively displaying demand power consumption under control of the Demand Logic Circuit 15.
Referring back to Fig. 3, the Demand Logic Circuit 15 is comprised basically of, (1) a Time Interval Counter/Logic 49, ~2) a Demand Enable On/Off Peak Detector ~ogic 51, (3) a Se~- ` ~'l uencing Logic 53, (4) a Demand Interval Counter/Logic 55~ (5) ~¦
the Solenoid and Clutch Drive 47, (6) and the aforementioned ~ , Pulse Initiator Loyic 39 and Manual Reset (MR.SW.) 41.
The Control Circuit 11 generates the Pl control signal at predetermined intervals (eg. 15 minute intervalsj.
The P1 signal is received by each of the logic circuits 49, 51 and 53. It will be noted that the 60 Hz signal is also applied to logic circuits 51 and 53 along with the Pl signal, with those signals being either in or out of phase with respect to each other. `
~ ' , ~, ~ "' ;_ 12 _ .. , .. , ~ i ~ S~ ME-50 Considering firs-t the Demand ~nable On/Off Peak Detector I.ogic 51 (hereinafter xeferred to as Detec~or Logic t Circuit), that circuit responds to the phase relationships ~,}
between the Pl and 60 Hz signals to selectively generate three signals, (1) a DEN (Demand Enable) signal, (2~ an OFPK
(Off-Peak) signal, and (3) a DON (Demand On) signal. 'rhe DEN
signal is provided as a ~lnary 1 state signal to the Time ` Interval Counter/Logic 49 when the P1 and 60 Hz signals are in phase. When these latter two signals are out of phase, as ;0 detected by the Detector Logic Circuit 51, the DEN signal remains at a binary 0 state. Also when the DEN signal goes to a binary 0, the OFPK signal achieves a binary 1 state and remains in that state so long as the DEN signal is a binary 0.
The OFPK signal also becomes a binary 1 in response to an EOI
(End of Interval) signal applied to the Detector Logic 51 from the Interval Counter/Logic 49. The Detector Logic Circuit provides a binary 1 DON signal to the Sequencing Logic 53 in response to the binary 1 states of the DEN signal and an A=B
signal from the Demand Interval Counter/Logic 55.
The purpose of the Time Interval Counter/Logic 49 (hereinafter referred to as Time Counter Logic) is to coun~
the Pl signals and generate the EOI signal after a prescribed ;
number of counts to terminate a demand time interval. The EOI
signal causes the OFPK and DON signals to both achie~e a binary 0 state.
Reference is now made to the Pulse Initiator hogic r 39 and to the Demand Interval Counter/Logic 55 (hereinafter referred to as the Demand Counter Logic). The Demand Counter Logic consists basically of two counters ~or counting PS
pulses generated by the pulse initiator logic 39 and a compar- r ator for comparing the contents of those two counters. The MR.SW.41, when actuated, applies a +V binary 1 reset signal to both counters when the system is initialized causing the A=B signal to go to a binary 1. This action will cause the , l ~5~ ~ ~l~MI;'~50 DON si ~ 1 to ~ to a bin~ 1, if the D~7siynal is at a hin~y 1 at the sa~e tlme as ~e A=B b~y 1 signal is generated. So lony as the OFPK ~!
and DON signals are b~y 0's, koth coun ~ s can count the PS pul~es. ~, One of the coun~ers is enabled to count by the DON slgnal and ~.
always contains an accumulative count propoxtional ~o the !' amount of electrical energy consumed duriny the one previous ',.
demand interval of maximum energy consumption. The other ~
counter, which is reset by the OFPK signal at the end of each ~, demand lnterval, is enabled to count during each demand interval and always con~ains a count proportional to the ' t amount of electrlcal energy being consumed in the present ;~
demand interval. When the contents of the counters are egual, ' ~
the A=B signal goes to a binary 1. This causes the first' , counter to now begin counting in unison with the other counter q while simultaneously enabling the Se~uencing Logic 53 to generate at least one output pulse DEM in response to the P1 - i~
and 60 Hz signals. ' ' The Se~uencing Logic 53 is capable of generating ~;
the DEM signal as a binary 1 shifted slightly in time to be ;~
either in or out phase with the 60 Hz signal. If the DEM signal is in phase with the 60 Hz slgnal applied to the clutch and solenoid coil 59 (See Fig. 4B of the present invention and Fig. 5 of the 4j050,020 Patent) the Demand Register 17 is ~ i engaged. On the other hand, if the DEM signal is out of phase 25 ' with the 60 Hz signal, the Demand Register is disengaged.-' ~ ~
For a more detailed description of the operation o t' the invention reference is now made to Figs. 4, 4A`and ~B. The following description will be more readily understood if the schematic diagrams are positioned with their interconnecting ,~
lines lined up as shown by Flg. 4. ~
For purposes of the ensuing description it should r be as'sumed'that the time of'day demand meter o the present invention is plugged into its operating socket at a consumer residence and that it has been programmed for operation as ' . ........................................................................ ., ~- 1~ ' ' '........................ ,' !, ~. _ `
, .5~ 21-M~ 50 I, described in the aforernentivned U.S. Pat # 4,0g3,g97 .
da ted June 6, 19 7 8 . jdi, ''"
To understand the operation o~ the Demand Logic r q;
Circuit 15 of Fiys. 4A and 4B, it i5 irst considered advan-~ .
tageous to recognize that that cixcuit operates during two ~ r periods of power usage defined as, (1) on-peak period, and -(2~ off-peak period. In the preferred embodiment, the Demand ',r~'.i, Register is engaged only during on-peak periods, and dis- ~
engaged during off-peak periods. ~hile the invention, for 1';' simplicity purposes, will be described in this manner, it is ~,r''~
to be understood that these are not imperative limitations of ~
the system. This is due to the fact that the Control Circuit ~.
11 can be programmed to generate the Pl control signal at any time during either a desired on or off-peak period. As such, , the Demand Logic Circuit 15 can be enabled during either on or off-peak periods to effect engagement of the clutch con~
trolling the Demand Register dials 17. The only requirement to enable the Demand Logic Circuit to Qngage the Demand Register is for the Pl and 60 Hz signals be of the proper~
phase relationship. - - ~ ~ -In the normal course of operationj a utility meter reader will read the register dials 13, 17 and 19 (Fig. l) on a monthly basis. After the dials have been read, the meter reader will reset the Demand Logic Circuit 15 so that the ~ the meter can begin to register the amount of demand power ~ L;~;
that will be consumed in the next monthly perlod. The Demand Logic Circuit can be reset during either an off-peak period, an o~-peak periDd wh~le,a new maximum demand is being set or accumulated on Register 17, or during an on-peak period when ~;
a new maximum is not being accumulated on the~Register. ~ - ~

. Reference is now made to Figs. 4A and 5. ~ig. 5 is ; ~;
` a timing diagram showing the major signals or controlling the ~
operation of the Demand Logic 15 when the MR.SW.41 is depressed ~r , 15' ' ', ~
~ ~ ~r~r~

599 21-l~E-50 ~ ~
or activated during an o~f-peak po~er period. During ~n off- ~'~J~I' peak power period, a demand enable ~lip flop DEN F/F is in ,~
the reset state generating binary 0 and l output signals DEN AND D~N respectively. T~1e phase relationships hetween the Pl and 60 Hz signals fox controlliny the state of the f~
DEN F/F are not shown in Fig. 5, however, those signals will~ ,,l,~f!~,,s~
be described in connection with Flgs. 7A, 7B and gA - llB.
The binary l DEN signal is applied to an OR-gate 57 ~r~
which is now generating a binary 1 OFPK signal. This latter ~ J"~
signal is applied via a conductor 59 to an OR-gate 61 in the ~emand Counter Logic 55 of Fig. 4B. As shown by Fig. 5, the ~`5;j.,,~,,4 OFPK signal enables OR-gate 61 to apply a binary l MRl reset~
signal to the R ~erminal of a first or Present Interval ~ '"~
Counter 63, thus keeping that counter reset.
When the meter reader activates the MR.SW.41 an MR ''`
signal is applied to an R terminal of a second or MAX. Count ~ L;~
per Interval Counter 65, thus resetting that counter. As :;~
soon as Counter 65 is reset, the contents of both Counters 63 ,',~
and 65 are detected as being equal by a Comparator 67 receiving .
the counter outputs at its two sets of input terminals AO-AN ~"
and BO-BN. AS shown by Fig. 5, the comparator now provides ~ 'Y!~.' a binary l A=B signal on Conductor 69 to an AND-gate 71 of~ ;
Fig. 4A. The binary l A=B signal is now preparing AND-gate 71 to be enabled when the DEN signal goes to a binary 1 during an~
on-peak period.
; It should also be noted at this time, that the r binary l OFPX signal on Conductor 59 is keeping a demand on .1 flip-flop DON F/F in the reset state and also keeping an 1' Interval Counter 73 reset viatwo NAND~gates 75 and 77. Re- t, setting the Interval Counter 73 e~fectuates the generation of à binary 0 End of Interval Signal EOI on a Conductor 79. The EOI Signal is applied as a second input to OR-gate 57, and its purpose will subsequently be described. Also at this time the DON Signal on conductors 81 and 83 lS a binary 0, since the ~J~

16 _ _ _ . ,~;,'.

~ 21-~E~0 DON F/F is reset. The DON Signal is presently preventing s,/, Counter 65 from counting the PS pulses by the application ~.
of a binary 0 Signal at its enable (E) input terminal. For ;,~7 the present, let it also be accepted that the binary 0 DON i Signal is inhibitiny any operation of the Sequencing ~ogic 53, thus preventing engagement o the Demand Register via the Solenoid and Clutch Drive 47. r~ ,7L;~.
The operation of the Demand Logic Circuit 15 when the MR.SW.41 is activated during an on-peak period while the !
Demand Register 17 is belng set to a new accumulated value ;i~
will now be explained in connection with Fig. 6. First it should be recognized that the contents o~ Counters 63 and- ,~
65 are always equal and counting ~he PS pulses in unison while the Demand Register 17 is engaged recording demand power consumption. The manner in which Counters 63 and 6S - ~
achieve equality will subsequently be aescribed. However, ~ rSr,'';';~, it is significant to note at this time that the A=B signal ~
(Fig. 5) is a binary l along with the binary l DEN signal ^t:, from the now set DEN F/F. And-gate 71 is thus enabled to apply a binary l set ONPK signal to the DON F/F. As shown in Fig. 6, the DON Signal is in a binary l state.
Now, as shown in Fig. 6, when the MR.SW.41 is ~
activated the MRl and MR signals each go to a binary 1 state-~; ~ ;
to reset their respective counters 65 and 63. It should be ;~ ~.7 noted that, since both counters are reset simultaneously, ~ t~
their contents remain egual and thus the A=B signal remains ~ ~s at a binary 1. Resetting the counters of course initiallzes / ~
the Demand Logic Circuit to allow accumulation of the amount ~ r of power consumed during the prescribed demand intervals of the next monthly period.

To further understand the operation of the Demand Logic Circuit 15 of the present invention,reference is now ~ -made to the Pulse Initiator Logic 39 of Fig. 4B. The ~
, . ,.~

~ 17 ,`~

'111'~5~ 2L ML ~ "
purpose of the Pulse Initiator Logic is -to continuously .~ S
provide sync pulses PS cluring meter operation. ~he repe-tition rate or frequency of these pulses is directly ~/;J~"~;r proportional to the amount o e po~er being consumed by khe ,~
system. The Pulse Initiator 39 is comprised of a pair of light emittiny diodes 85 and ~7 connected in series between a voltage potential ~V and ground via a load resistor 89. ~.f-,.1i,.
During meter operation, diodes 85 and 87 continuously illum- : ~, . . inate light which impinges on a rotating disc 91 mounted in " ~s the time of day demand meter of the present invention. Disc ~ ?
91 has been fabricated to contain an aperture 93 through which t~
the light from the respective diodes 85 and 87 can pass as the ~~?j~.~
. disc aperture(s) rotates past those diodes~ ~
. A pair of photo transistors PTl and PT2 are juxta- l ~.
i positionally alligned with the disc aperture so that the ,~
light from the diodes 85 and 87 impinges on the base of their .
respectively associated transi~tors as the rotating disc 1~7ii i~
comes into alignment with the respective diodes and transistors .~....
Photo transistors PTl and PT2 are of the NPN type having their ~P.~' O emitters connected in common to ground so that each transistor ,'~
will conduct to generate a logic 0 signal at its collector.as i.
light strikes the base. Each transistor output is applied to .ir~.`
a Pulse Sync flip-flop 95 via an associated one of inv.er.~iers 97 and 99. ;
5 . ¦ Flip-flop 95 is triggered to alter~ately set and f,t,J',~
reset by the binary 1 slgnals from the two inverters as their ¦ respectively associated transistors are caused to conduct by ,~
¦ the light through the meter disc aperture. ~he output of the .~~;.;
Pulse Sync F/F 95 is an alternating sync Pulse PS having an .
~0 ¦ indeterminate repetition frequency which i5 proportional to rt~;~''' the unt of power beilg consumed by the system. ~he PS ~!t~
.' I`i.,.
. . ~
, ~ _~'i'~'''.
,;

2l-Mr,-50 ~, ,,~;
I t,'''"'"''"'',''' Pulses are continuously applied to a C or clock input terminal ,',s,.,;;~
of each of the Counters 63 and 65. , i, ~
. The Demand Counter Logic 55 can best be understood ,~,i,"~."~, by analyzing the input control signals applièd ~o the reset ~ f (R) and enable (E) input terminals of the counters of that , ,~,;,,~,,,6,,;!, circuit. Reference is first made to the Present Interval : s',.",., Counter 63. That counter has its E terminal connected to a -binary 1 ~V enable potential so that Counter 6i is automatic- ~r~s~
ally enabled to count the PS Pulses when the MR1 signal at, ,~,:;,~, its R terminal is a binary 0. ~s previously ~escribed, Counter 63 is reset whenever either the OFPK signal is a :~," -;., binary 1 or the MR.SW.41 is activated. ThUS, it can be seen that Counter 63 can be reset by the meter,reader on a monthly -basis. Further, Counter 63 is always reset and prevented ~
from counting by the MRl binary 1 signal as long as the OFPK ,~ ,s signal is present at the input of OR-gate 61. It is signifL- , ''''''~'i cant to realize that the counter~63 always starts to count . ~ u~
from zero at the beginning of each demand interval. Thus, :: ' ;
its count always represents the amount of power'being consumed~
during the present demand interval. Thls is clear from obaer- , ~.
vation of OR-gate 57 of Fig. 4A which~is enabled during Off-~ ;
peak periods .(DEN F/F reset) and at the end of each demand , interval by the E:OI signal to cause Counter 63 to reset to '~ . !,.,~.
zero. ~ ~
Reference is no~ made to the Maximum Count per~ , ~ s Interval Coun'ter 65. That counter is reset only when the meter ,, ~,~:', ~reader activates the MR.SW~41~ Thus, it can be seen that it .
will normally be reset only on a monthly basis (ie., after ., each reading of the meter register dials).' Counter 6~, except ' ~,..;', when in the reset state, contains an accumula~ed,count value . , ~,,,i,., propo~rt.ional.to the amount:of power consumed during the one ~. :
demand interval o~' maximum electric,al energ~ consumption. .

, " :; . . ' ~

..... ~ ,, 19 , .. , ~' _ __, _ ., .,;

~ 3~ 2i-M~ O ~ , Il ~,''':';;
Counter 65 is enable~ to count by the DOi.~ binary 1 siynal. By ~s observing the A-B signal ~rorn comparator 67 and AND-yate 71, it can be seen that the A=B signal enables AND-gate 71 to set , the DON F/F during an on~peak ~eriod (D~N F/F set), ~;
The DON F/~ is first set to enable Counter 65 to r'~j count the PS Pulses at system reset tlme by the activation of the MR.SW.41. As previously described, the MR SW.41 sq~ 'reset~ both counters 63 and 65 causing the A=B signal to go ., J
to a binary 1. ~t the time of reset, if the DEN F/F is set : -0 (ON-pea~) AND-gate 71 is enabled to set the DON F/F. At this time, since the OFPK signal is a binary 0, both of the Counters 63 and 65 will begin counking the PS Pulses in '~
unison, thus keeping the AYB signal at a binary 1. Counters ~ s 63 and 65 will continue to count the PS Pulses until the ~;
Contxol Circuit 11 generates a Pl signal. This latter Pl ,~).
signal will either reset the DEN F/F to enable OR-gate 57 '.;(system goes to o~f-peak) or have no affect at all on the ~"~DEN F/F. The Pl signal also causes an Interval Pulse F/F l0l ~,,.;,.~.
to set. When flip flop 101 sets, a 15 minute signal 15 MP is 0 applied to counter 73 causing it to generate the EOI (end of interval) signal which also enables OR-gate 57.
When OR-gate 57 is enabled by either the DEN or EOI . ;~
signals, Counter 63 and the DON F/F are both reset. With "~
Counter 63 now reset, it is conditioned to begin aounting from æero at the start of the next demand interval. 5ince the i DON F/F is now reset, the DON signal is a binary 0 disabling Counter 65 from counting the PS Pulses. It should be noted at this time that the A=~ signal is now a binary 0 to prevent !~
the DON F/F from again setting until the contents of counters ~'~
0 63 and 65 are equal. - ~s At the termination of the irst demand interval : ` ;~;
following system reset, Counter 65 contains a count proportion-al to the amount of power used during the first demand .?~i~
__ __ 20 _ _ _ j ~

c~ ~ 2l~~ S0 ' inter~al. As will subse~ ently ~e described, the Dernand Register 17 also accumulates a readiny proportional to the amount of power consumed during the time that Coun~ers 63 and 65 were counting. ,~
Let it now be assumed at a subsequeint tirne the Control Circuit 11 generates a Pl signdl which sets the DEN F/F indicating an on-peak period and the start of a second demand interval. With the DEN F/F now set, OR-gate 57 r1'.''' ~
is disabled to cause the OFPK signal to go to a binary 0. The ;r"', MRl signal from OR-gate 61 now goes to a binary 0 and the !i~,'j, - Present Interval Counter 63 begins to count the PS Pulses.
The A-B output of the Comparator 67 will remain at a binary 0 t'~i.t,t.~
so long as the contents of Counter 63 are less than the ~ ~;u;' previously accumulated count in Counter 65. ` ,.
Now let it be assumed that the demand for power in !
the present interval exceeds the maximum power consumed in ;':~
the previous maximum demand interval as manifested by the contents of Counter 65. When this maximum is achieved, the~ jt contents of Counters 63 and 65 become egual, thus causing the 0 A=B signal to go to a binary 1. Since the DEN FjF is assumed ~ ' to be set, AND-gate 71 is now enabled to set the DON F/F. The ~t-.
DON signal now goes to a binary 1 to enable Counter 65 to begin counting in unison with Counter 63. Also at this time, in a manner to be described, the Demand Register 17 is engaged S to accumulate the additional amount o~ power belng consumed during the present demand interval.
Counters 63 and 65 will continue to count and the Demand Register will remain engaged until the DON F/F is resat as ~reviously described. ; ' 0 With the preceding background, reference is now m~de to Figs. 8A and 8B in conjunction with Figs. 4A and 4B. Figs.
8A and 8B illustrate the operational timing of the Demand Logic Circuit lS to engage the clutch of the Demand Register 17 ; , . 'I
_ ~
.~, 21 -Ml~50 , when the system is operatiny on-peak, when a new demand is not ~,~
being set (ie~ Demand Register 17 is disengayed) when the ~R~SW~ ~I f 41 is activated. r~",~
Since the system is assumed to be operating on-péak. i' the DEN F/F is set. As sho~n in Fiy. 8~ activation of the ~
MR.SW.41 causes the MR and MRl signals to go to a binary 1 S, resetting both of the Counters 63 and 65. With Counters 63 ~ s and 65 reset, and equal, the A=B signal goes to a binary 1 i~
enablinq AND-gate 71 and setting the DON F/F as shown by the r,~
0 DON signal going to a binary 1. The DON signal now enables ~
Counter 65 so that both counters can begin counting the PS ~'.,!.;
Pulses as soon as the MR.SW. is opened or de-activated. -Reference is now made to Fig. 4A to a sequence flip flop (SEQ F/E) receiving a +V binary 1 enable lnput at its D
or set input terminal and providing as an output an SEQ signal i~
at its Q output terminal. As can be seen in Fig. 8A, the DON I il,'',' signal, applied to the C terminal of the SEQ F/F, now going to ~ b a binary 1 causes the SEQ F/F to set driving the SEQ signal to x a binary 0. The SEQ signal is applied as one input to an OR- 1.
gate 103, with the other input being the Pl Control signal. ~ .
Since the Pl signal is always a binary 0, except when signalling the Control Circuit 11 to switch from on-peak to off-peak~or visa versa, OR-gate 103 is now disabled. This disablement is ~
i~llustrated in Fig. 8A by a reset counter signal R-CTR going jl ' to a binary 0 state.
The R-CTR signal is applied to a reset ~R) control terminal of a Sequence Counter 105 of the Sequencing Logic 53 Counter 105 operates to remain in the reset state so long as ~ - ~
the R-CTR signal is a binary 1 (ie. it cannot count). However, l~' as soon as the R-CTR signal goes to a binary 0, counter 105 is - t~""
enabIed to count the 60 Hz Pulses from the power supply 21 (Fig. 1) applied to its C or clock input terminal. As can be . ' ~ i~' '. . .

2 2 ¦ .;1 . ~

Gl-M~ U
. '~ '^Ji~ 19 ':',' ~ tl,,~ t,, J , ,~ ~f"~
en ln ~iy. 8A, the Sequ-~nce Count~r 105 operates as a ~s,;~,~
conventional five bit binary counter which is triggered on the rising edye of' the 60 Hz pulses to'sequentially generate ,~"~i, output signals Q2 - Q5, with Ql being shown but not used, ' , Still referring to Fig. 4A, an Exclusive OR-gate 107 ,$,;,~r~l, receives the 60 Hz and DON signals to generate a 1rst strobe . , ,, output signal STl at a time as shown in Fig. SA. As is well " i,~
known in the art, an exclusive OR-gate generates a binary 0 ,, '~
output when its inputs are equal and generates a binary 1 ~,,,,,,~
output only when its inputs are opposite. As such, as can be - "',....
seen in Fig. 8A, the STl signal is a 60 Hz square wave which ~,!,,S, is 180 degrees out o phase with the 60 Hz pulses. ' ~,,,,,.,,,;
The STl signal is applied simultaneously to an inverter input of each of two delay one shot multivibrators , ~ -i'~;' ST2 OS 109 and ST3 OS 111. Each of these delay circuits is . .
triggered on the falling edge of the STl signal to generate . ~g,~..~,.'.
respective second and third output stro.be signals ST2 and ST3.,' Since the ST2 signal is taken from the 1 output terminal,of. , '~.' r ST2 OS and the ST3 signal is taken from the 0 ou~put terminal~: i~i3 '~
of ST3 OS, these signals are 180 degrees out of phase with ' , ',~
respect to each other. This phase relationship is.dep}cted '~ ~' in Pig. 8B, where it should be noted that the Pulse width of ,~ ~
the ST3 signal is approximately one-haIf,the pulse width of ~,!t.,.~
the ST2 signal. . , ~ ~J~''"'~
Refe.rring now back to the output of the Sequence.
Counter 105, two of that counter's output signals, Q3 and Q4,~
are applied to an AND-gate'113, which is enabled when those ` :?~
two signals each achieve a binary 1 state. The output of' ,:~ "~','i,...
AND-gate 113 is applied to a NAND-gate 115 in con~unction ~';.
with the ST2 signal from ST2 os to generate a ~ourth strobe ~ r~
signal ST4. In the operation of a N~ND-gate, its output,goes ;.;

to a binary,l only when its inputs are opposite or both bin6ry~
0's and ~rovides a binary 0 output when its inputs are all binary l's. The operation o~ NAN~-yate 115 is depicted in ." ,~
,, . ', , 23 . = ~ - .

3~ 21-ME-50 ,,, I '~ q~ q, ''''~
Fig. 8B, which shows the ST~ signal being a series o~ negative !,1 going pulses having the same pulse width as the ST2 signal and which occur each time the ST2 signal and the output o AND-gate 113 are both binary l's. , ' - A Demand flip flop, DEM F/F recéi~es the ST4 signal"- , ~' at its reset (R) terminal and the ST3 signal at its set (S) input terminal. As can be seen in Fig. 8B, the DEM F/F is ~,;,,~
triggered to set and reset on the rising edge of the ST3 and '''J'''"'`;
ST4 pulses respectively to generate a positlve going Demand , ,!;i''~)"' output pulse DEM having a pulse width approximately half the , ,(," , pulse width of the ST4 pulse.
The DEM pulse is applied to a Clutch Solenoid Drive rlL,:r,, (Triac) 117 of the Meter Register Solenoid and Clutch Drive~47 ~L~,','sJ'~
(See Fig. 3). The Solenoid Drive Circuit 117 is comprised f, the aforementioned transistor 73 and triac 69 of U'.S,Patent

4,050,020 (Fig. 5), and as such is depicted here as a'block , 'representative of that circuit. ,, ' , ; '~
The output of the Solenoid Drive 117 is a Clutch ~
Drive signal similar in characteristics to the DEM slgnal and~ j`~3 is utilized to drive the Clutch and Solenoid Coil 59 of Patent', ~
4,050,020. The 60 Hz pulses are also applied to the Solenoid , ,tt" l~;,;,i, ` Coil 59. " , ~'~ ~`' ','~',;;i As previously described, and as disclosed in ths ; ' àforementioned 4,050,020 patent, when the Clutch Drive or DEM
signal is in phase with the system 60 Hz signal ~rom power ,,'' '" ,~ ;,t~
supply 21, the clutch is engaged to drive the Demand Register , dials 17 and thus record the amount of power beiny consumed , , "~,~
during the present demand interval. As can be seen,in Figs. -~ 8A and 8B, the DE~and60 Hz signals are in phase to thus j~
I engage-the cIutch of the Demand Register 17. It should be , note~, in Fig. BB, while the DEM signal is shown as a series ' of four pulses, only one pulse need be generated to engage,the;

, ,: ,' .`,`~.!,!~
: 24 `

, ~ 7~5~3 ~ So clutch. In the preferred embodiment, however, it is preferred ~,"";
to pulse the clutch four times just to insure that the clutch ' ~;
engages. `i,~
Reference is now made back to the Q5 output of the Sequence Counter 105 of Fiy. 4A and to the ~5 signal of Fig. 8A~
As shown in those figures, when the Q5 stage of Counter 105 ;
is set a 4inary l~a Q5pulse is applied to a reset (R) terminal ' of the SEQ F/F causing the SEQ signal to now go to a binary 1.
The SEQ signal now enables OR-gate 103 allowing the R-CTR ;'i;~
signal to reset counter 105. Counter 105 will remain reset ~,,?
until the SEQ F/F is again set. It should also be noted in ij' b') the reset operation just described, that the INTVL Pulse F/F 101 ;, ;~
of Fig. 4B is rèset by the Q2 pulse applied to the R input r,,",,,;,, terminal of that flip flop. Flip ~lop 101 is rese~ in preparati n to generate the 15 MP signal for the Interval Counter u~on .. , receipt of the next Pl signal during either,(l) an end of ~
demand interval while on-peak. ~2~ when the system is directed r,~t,-to Off-~eak by the Pl sianal, or (3) when the system is directed ~ ,s to on-peak after monthly reset. The Q2 signal is also applied ;
to NAND-aate 75. however. it has no further effect on the ~ ~i"~
system at this time. ~ ~'~
Reference lS now made to Fias. 7A and 7B which illustrate the timing of the Demand Loaic Circuit of Figs~ 4A~ !;~ ;~
and 4B when the system is directed to on-peak to start a demand interval after monthly reset caused by activation of the ; ~ t~
MR.SW.41.
As shown in Fia. 7A. the Pl signal is a series of four ~ulses each occuring in phase with the 60 Hz pulses from ;~
power supply 21. As previously explained, when the system is ; oPerating off-peak, the DEN F/F of Fig. 4A is reset. Fiq. 7A I ~.. !
shows how the DEN F/F is set bY the Pl and 60 Hz signals to command the Lo~ic Circuit 15 to qo on-Peak for reqistering I~z~
, , ~ c~
. ~ - . . I~.,,~;i ~ ";,~

~ 7,5~3~ 21-~f~ ~) on Demand Re~ister 17. The Pl si~nal is a~PIied to an Lnverter 119 and inverted to a Pl sianal at the clock (Ck inPut of the DEN F/F. The 60 Hz signal is applied simultaneously to the ';~ ,'i set/reset D input of khe ~N F/~. The DEN F/F is triggered !~
on the positive edge of its C inPut, and this is illui~trated )',~ r b~ Fiq. 7A showinq that flip flo~ settinq on the trailinq edqe of the Pl siqnal when it qoes neqative to applY a bi.naxY 1 Pl signal to the DEN F/F causiny it to set in response to the 1'.,' binary 1 60 Hz pulse now present at the D input.
The Pl signal is also applied to ~he set (S) input , ';'r~
terminal of the INTVl. PULSE F/F'~01, causing that flip flop ) to set generating the lS MP signal at the time shown in i~ ~, Fig. 7A. The 15 MP signal has no affect on the Interval ~,~
Counter 73 at this time, because it can be triggered only .~.i on the rising edge of the 15 MP pulse, which, in thls instance, occurs prior to the DEN'signal going to a binary 1. As such,` ,1,~15, the output of NAND-gate 77 goes to a binary 0 after the 15 MP
signal and Counter 73 is unaffected by the 15 M~ !sig~al. ~ ,.,~.,~'!, Referring back to Fig. 4A, the Pl signal is further -~
applied to a set tS) input terminal of the SEQ F/F via an OR-gate 125 causing that flip flop to set making the SEQ ' signal go to a binary 0 as shown in Fig. 7A. The'SEQ signal is applied to one input of OR-gate 103, thus removing the' - p ,~
constant R-CTR binary 1 reset signal from the Sequence Counter j?!'',`' 105. The OR-gate 103 is now enabled to allow the Pl signal' ,~
to control the reset operation of Counter 105. Just how Pl ?~
affects the operation of the Sequence Counter will subsequently ~,~
be described. For the moment, however, reference is now'made to the AND-gate 71 of Fig. 4A.
AND-gate 71 receives the two input signals DEN and' A=B. The A=B signal is now a binary 1 as shown in Fig. 7A. ~ ~
It will be recalled that the signal A=B always goes to a " l~''X-'.

binary 1 when Counters 63 and 65 ~Fig. 4B) are reset by the , ~ ' ~ ;,~'"~

' 26 ' I I; ' ~r~ 21-ME-50 MR1 and MR signals at sys~ern reset time. Now, as shown in ,s Fig. 7A, when the DEN F/F is set, AND-gate 71 is enabled to ,~
apply a binary 1 ONPK signal to the S input o the DON F/F
The DON F/F is thus set to yenerate the binary 1 ~ON sign~1 at the time shown in Fig~ 7A. As previously described, the DON signal now enables Counter 6S to begin counting the PS
pulses in conjunction with Counter 63. The DON signal is also applied to the S input terminal of the SEQ F/F, however, in this instance it has no affect on that flip flop as it was -) previously set by thePLsignal. The xeset signal was removed from Counter 63 when the OFPK signal went to a binary 0 with ~,7;j~
the setting of the DEN F/F. ;
Reference is now made back to the R-CTR output ~ rtS~-signal of OR-gate 103 of Fig. 4A and to that signal as shown ~""~
S in Fig. 7A. Attention is now called to the Ql signal of Counter 105 as shown in Fig. 7A. As shown in that figure, ~the. .
Ql stage of Counter 105 is set on the rising or leading edge ~ ~ .!~
of the 60 Hz signal applied to the C input of that Counter and then immediately reset by the rising edge of the R-CTR ~
0 signal resulting from the Pl signal passing through OR-gate 103.
As shown in Fig. 7A, the Ql stage of Counter 105 is s t and ~
reset three times in response to the three R-CTR signals (Pl ; - ~ ;
passing through OR~gate 103).
After the last R-CTR pulse (also last P1 pulse) has ~J~
been generated, OR-gate 103 is disabled to now allow Counter .~"~
-105 to count the 60 Hz pulses generating the Ql-Q5 output ~ L~
signals as shown in Figs. 7A and 7B. ~
The STl-ST4 signals are generated as shown in Fiy..7B
in the manner previously described in connection wLth Figs. 8A ;"
and 8B. Also, the DEM signal i5 generated in Fiy. 7B to engage `~
the Demand Register 17 in the same manner as described for i`~", Figs. 8A and 8B. i~

Let it now be assumed that the s~stem is operatiny during a demand interval (on-peak) and that the Proyrammable 27 ~ !; ~ "~
t,~

59~ ME-SO ~ ~;

Control Circuit 11 of ~ig. 1 generates a Pl signal to terminate S
or end that interval while retaininy the siystern on-peak. The i;~'')'~;,''A' timing for this t~rmination is shown by E'iys. 9A and gB. ,, As shown in Fig. 9A, the Pl si~r,al occurs in-phase '~s'Ç, with the 60 Hz signal and since the DEN F/F is already set , ~
(on-peak), the state of that flip flop is not changed. However, );' ~';
note at this time that the Pl signal se~s the INTVL Pulse F/F
101 of ~ig. 4B to generate the 15 MP pulse which triggers the ;
Interval Counter 73 to generate the end of interval (EOI~ J; ;~
pulse on conductor 79. Counter 73 is enabled to coun~ in this particular instance because of the binary 1 DEN signal ~ ' at NAND-gate 77 disabling that gate to apply a binary 0 non-reset slgnal to Counter 73. ~ F~ s At this point it is considered informative to more thoroughly describe the purpose of the Interval Counter 73. ~ ;!s''3 In the present invention, it is desirable to program the Time Interval Counter/Logic 49 to generate an EOI signal every fifteen minutes. However, this is not a limitation of this ~ ~
circuit. It can also be programmea to generate the EOI signal ; ~r!
at other intervals (eg. every 30, 60, 120, etc. minute intervals) There are instances where the utility may want their demand ~ `~
interval to be of a longer duration than fifteen minutes. In which case, it is desirable to generate the EOI signal at some other interval than every flfteen minutes. ~"~;
By observation of the jumper pin connector oukputs of Counter 73, it can be seen that if the jumper 123 is ~ ~i;i connected to the 15 minute output, one EOI signal will be ;~
generated for each 15 MP pulse, thus causing lS minute ~ ;;,j`
Demand intervals. If a 60 minute Demand interval is desired, ~ ~ -~
jumper 123 is moved to the 60 minute (Q3) output and the Counter 73 will have to count four lS MP pulses in order to " ` ' ~' , , ~ ', 2&? , , .
_. t~

~l Zl~t~-50 '~

generate one EOI output signal. Thus, for one P1 siynal every ~ "'f fifteen minutes, it would take one hour for the Countex 73 to generate the EOI signal to terminate the present demand interval l;;;,~
It is well known in the art that the conventlonal way of expressing the rate of energy consumption is in kilowatts.
However, in ~he present invention, the Demand Register 17 is `!'-ii''i made to register the rate of energy consumption in kilowatt- ;";~
hour$/in~erval. That register reading, however, can easll~ be ~ i"
converted to kilowatts by the utility company for their use in billing the customer. This manner of conversion will be ~'f explained in the following text. ' ~ -In the present invention, if certain rules are adhered to, the demand interval length can be changed by chang-ing the jumper 123 to the various outputs of Counter 73 and ~-; F
the Demand Register 17 will properly display kilowatt hours/
interval. This i9 explained as follows. ' If it is assumed that the jumper 123 is connected ~ ~ ~
to Counter 73 or a 60 minute (1 hour) demand interval, the ~ t~s ;
Demand Register 17 will provide an actual reading of kilowatt hours/interval. 'Because it is a one hour interval, this ~
reading is also equal to kilowatts. However, a~ssume that the ' jumper 123 is connected for a 30 minute interval. The Demand Register will read the actual kilowatt-~'ours/interval'as ju'st d~
scribe~, however', sincelthe interval'isj,or ;1~ hour~:~nd~to co~ ~ ?
that reading to kilowatts to represent demand, it is necessary ~ to divide tha~t reading by 1/2 hour. This is what the utility t~
company does when figuring out the customer's bill.
Utilizing the same rule, it can be seen that when ~ ,~

the jumper 123 is connected to the 15 minute interval output '~
of Counter 73, the actual Demand Register reading should be .~ s~
divided by 1/4 hour. In a similar manner, if a 2 hour demand ',~
interval is selected by connecting the jumper 123 to the 120 i ;j1 minute interval output of Counter 73, the Demand Register ,~"l~

it''~
_ ':":'.''.'1.''''~
.
~ t~

~ '.S~.~ 'i;
reading should be divided by 2 hours to get the kilowatt ~s ~r,' demand reading for a 2 hour interval. If the 240 minute ',~
demand interval is selected, the actual Demand Register read- !
ing should be divided by 4 hours. , It i5 possible to have the Demand ~eg~ster to read in kilowatts for any demand interval if the register gear ratio is changed each time the jumper 123 is placed on a ~, ~
differ~nt output of Counter 73. Discountiny any stepped up 5),,~ "
gear ratio in the Demand Register to increase its resolution, ,~
the manner in which these various gear ratios can be calculated for the several lengths of demand intervals is explained in the following example. ~!: ', It is understandable that - if in a maximum demand j;"~;
interval of 15 minutes, x kilowatt~hours is consumed, the ,., maximum average kilowatt demand is, x kilowatt-hours divided ~i by 1/4 hour = 4 x kilowatts. Thus, a 4:1 step up gear ratio is required in the Demand Register 17 when a 15 minute ; ~
demand interval is selected. i 'i, The various other gear ratios can be figured out in the above manner for selecting the 30, 60, 120 and 240 minute demand intervals on Counter 73.
From the preceding, it can now be seen that the ~ tr~
Interval Counter 73 and its various jumper outputs provide an economical and advantageous way of readily changing the demand interval length in a demand meter register without having to make special mechanical gear ratio changes in the ~ .
register to accommodate the several lengths of demand intervals. k ~`
It is a~so significant to note that the jumper 123 can be eliminated from the outputs of Counter 73. This in .~
essence, removPs the counter circuitry from the demand logic ~;

circuit, in which case the ~OI signal will not be generated ~ 7 . . . '~

` 30 ` . t:','.''' ~' , . ~

ll ~
p-~9 21- M E 50 and the demand interval lenyth will then be e~ual to total ,~ 5 on-peak time. In this case, the kilowatt-hours/interval 5,"'Z~5 registered on the Demand Reyister will be correct, because the interval length i5 the to~al of the on-peak time. '' Now referring back to the EOI signal of Figs. 9A, 4A i,~
and 4B, it will be noted that that signal now enables OR-gate ,~
57 to qenerate a binary 1 OFPK signal resetting the DON F/F at ~I'~'.,f,, the time shown in Fig. 9A. The OFPK si~nal has no affect on i~lY
the oPeration of NAND-qate 75 at this time, and thus no affect 0 on the operation of Counter 73. However, the OFPK siqnal now enables OR-qate 61 to apply a binary 1 MRl reset siqnal to the -~
Present Interval Counter 63. The MRl siqnal now resets counter !;.,.,,~
63, having the effect of causinq the A=B siqnal to qo to a ; i'!~
binary 0 at the time shown in Fig. 9A. This is due to the ~1", ~5 fact that the contents of Counters 63 and 65 are no longer .;;
equal. ~ "~
With reference now to AND-gate 71 of Fig. 4A, it can 3~
be seen that that gate is disabled by the A=B binary 0 signal ~ ~ ~J~, at the same time~the EOI signal resets the DON F/F via OR-gate , 57. It should also be noted that the ~inary 0 DON signal on Conductor 83 now disables Counter 65 from counting the PS ~.^`l, pulses until again enabled at the next demand interval. jf; i,'! ' ~ The Ql-Q5 and s~rl-sT4 signals are generated in the same manner as previously described, with the exception that ~5 the STl signal is now out of phase with the 60 Hz signal. Thls is due to the fact that the DON signal at the input to the Exclusive OR-gate 107 is a binary 0, thus reversing the ~i~
polarity of operation of that gate. It is this out of phase relationship of the STl and 60 Hz signals which allows the ~i"~
clutch sol noid of Demand Register 17 to be disengaged as .it,ll:
shown in Fig. 9B. By comparing the DEM signal with the 60 Hz signal of Figs. 9A and 9B applied to the Solenoid '~oil 59 of t;, Fig. 4~ it can be seen that those two signals are out of phase to dise~gage the clukch.

, ~ i~

~3 ~ ~J ,r~ 21-M~-5~
,:,,;
It should also be noted -that the ~2 binary 1 output ~`
signal from Counter 105 in conjunction with the binary 1 O~PK s~l, signal (EOI is a binary 1) enables N~ND-gate 75 to apply a binary 0 signal to NAND~ga~e 77, which in turn applies a s~
binary 1 reset signal to Counter 73, thus terrninating the EOI S,!'' signal. The Q2 signal also rese~s the INTVL.PULSE F/F 101 at ,~
the same time, terminating the 15 MP signal as shown in Fig. 9A. "1~
To understand the operation of the Demand Logic Cir- i s cuit 15 of the present invention when the system is commanded ~"' to go to off-peak by the Pl signal f~om Control Circuit 11, reference is now made to the of~-peak timing diagram of Figs. -;
10A and 10B. As can be seen ln Fig. 10A~ the Pl and 60 Hz ,~
signals are now out of phase, causing the DEN F/F to reset on the trailing edge of the Pl Pulse. The DEN signal thus goes negative disabling AND-gate 71 and the DEN signal goes to a binary 1 resetting the DON F/F via OR-gate 57.
The SEQ F/F is set via OR-gate 125 as previously !,ll, described to enable Counter 105 to count the 60 Hz pulses and ~;, Counter 63 is reset by the OFPK signal via OR~gate 61. Add- ~ ,~
itionally, Counter 65 is disabled from counting the PS Pulses .
by the binary 0 DON signal. As shown in Figs 10A and 10B, -;
the Se~uence Counter will generate the Ql-Q5, STl-ST4 and DEM
signals to disengage the Demand Register Clutch in the same manner as described for Figs. 9A and 9B. '~
Let it now be assumed that the system is operating~
during a demand interval (normally ON-peak with the DEN F/F - ;.
set) and that the one previous demand interval of maximum power consumption is exceeded in this demand interval. Figs. llA and ti llB show the timing of the Demand Logic Circuit of Figs. 4A and 4B for energizing or engaging the Demand Register Clutch when ;;~
this maximum is exceeded. ;
As shown in Fig. llA the DEN signal is a binary 1, thus allowiny AND-gate 71 to be enabled when the ~=B signal ,~
. ~j:

_ ~

achieves a binary 1. In lig~ llA orll~ that one P~ Pulse going from binary 0 to binary 1 is shown that trlgyers Counter 63 to equal the count in Counter 65. With Counters 63 and 65 now equal, the A-B signal goes to a hinary 1, enabliny AND~gate 71 and thus setting the DON F/~. rrhis timing is shown in Fiy. llA l where the DON signal now achieves a binary 1 state to enable f"
Counter 65 to begin counting the PS pulses in unison with .'-., Counter 63. The DON signal also sets the SEQ F/F to enable ,., Counter 105 to count the 60 ~z pulses and further condition ~s the Exclusive OR-gate 107 to generate the STl-ST4 s1gnals at ~."
the proper time so that the DEM signal is generated in phase with the 60 Hz signal to engage the Solenoid Coil 59 of Fig. 4B
to drive the Demand Register 17.
The Demand Register will now continue to accumulate the excess amount of power being consumed in the present demand interval until the Demand Logic Circuit is commanded "
to either go off-peak or end the present demand interval. At L~
the end of the present or last demand interval, the Demand .;
Register 17 will contain a reading of the amount of electrical energy consùmed during the one demand interval, out of all demand intervals, of maximum electrical energy consumption. ~.-Further, at the termination~of the present or last demand in-terval, the Max. Count per Interval Counter 65 will contain a ,~
count or value proportional to that amount of energy manifested i~"~
by the Demand Register dials. ~ ~l;
While the Demand Logic Circuit 15 of the present '~ :
invention has been disclosed in a purely digital embodiment, it is to be understood that at least portions of that circuit could be implemented in an analog embodiment. For example, the `:
Pulse Initiator 29 could be constructed of an electronic or magnetic sensor which generates an integrated variable analog output signal or value proportional in amplitude to the amount ~
of energy being consumed by the system. ~.
The Counters 63 and 6S and Comparator 67 can be s-.`,~.l ~ 33 ,7~ ~3~
re~lacecl by their arlalo~J ,~c~uiv~lents. ~mplifiers 63 and 65 for example, may each comprise controllable long term s~oraye accumulator ~ype integrating ampliiers which are controlled similar to Counters 63 anc1 65 to increa~e their outputs only ~,~
when the analog input to each is greater than the value ', f presently stored in each amplifier. When the values of e~ch ~
of the analog amplifiers achieve equality, the analog comparator ~. , would generate a signal similar to the A=B signal to effect ,~ .
enablcment of the Clutch and Solenoid Coil 59 of Fig. 4B. ~s 0 1'he invention also includes means for inhibiting operation of the Demand Logic Circuit 15 in the event of a ,)1-power failure. Referring to Fig. 4A there is shown a con- ,i~At.,~.
ventional RC Integrator Delay network 127 receiving the ST3 OS. ~`'i'~',' As can be seen from the timing diagrams and Fig. 4A, the ST3 ''-signal is continuously generated so long as the 60 Hz signal ,:~5 is present at the input to gate 107. So long as the ST3 signal is continuously applied to the Integrator 127 its output, to a conventional squaring amplifi~r 129, remains at a constant ,-negative or binary 0 potential. However, in the event of a 0 power failure which lasts for example for five or more seconds, thè Integrator generates an output pulse to amplifier 129 simila~
.
to that shown on Conductor 131. The input Pulse to amplifier 129 is applied as a binary 1 squared off pulse to a reset R !/:
terminal of the DEN F/F and also as a set pulse to the S input ,-terminal of the SEQ F/E via OR-gate 125.
, , :::',;:
Resetting the DEN F/F takes the system out of the .
demand interval mode to reset the DON F/F via OR-gate 57, while setting the SEQ F/F disables OR-gate 103 so that upon restor-ation of power, which in turn effects the generation of the DEM
0 signal to disengage the clutch in the manner as previously desoribed. It should be recalled as previously described and as disclosed in the aforementioned patent 4,050,020, the time of day demand meter of the present invention includes a back up battery power supply and auxiliary ~requency generator which 3~ , ", ........................... ... ~

~ ` ~3. ~ 21~~-50 ;.',~

. automatically comes on line to operate the meter circuit~ in ;,~
the event of a power failure. i.. ',~j.i While the present invention has been disclosed in ..
connection with a pre.ferred embodiment thereof, it should be ; understood that there may be other embodiments which fall ~:
within the spirit and scope ~f the invention as defined by = ended ~1 'ms.

f . ' , ~ `''''~i' . ~ . ~!~ ,'.' ~:
._ __~, ~

Claims (13)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A time-of-day demand metering system for regis-tering the amount of electrical energy consumed during demand intervals comprising:
(a) selectively engageable means for registering the mount of electrical energy being consumed during said demand intervals;
(b) means for periodically generating electrical pulses having a repetition frequency proportional to the amount of electrical energy being consumed by said time-of-day demand metering system;
(c) means for generating a control signal at prescribed in-tervals;
(d) means responsive, in a first instance, to said control signal for generating an end of interval signal and res-ponsive, in a second instance, to said control signal and to a comparison signal for generating a demand inter-val on signal;
(e) means for controlling, during each demand interval, when the registering of the amount of electrical energy being consumed may take place, said means for controlling including, (i) comparator means for generating said comparison signal, (ii) first and second counter means, each receiving said electrical pulses and each having output ter-minals connected to said comparator means for pro-viding count signals thereto, said first counter means being set to a predetermined count in res-ponse to said end of interval signal and being enabled to count said electrical pulses during each demand interval in the absence of said end of in-terval signal, said second counter means, in res-ponse to said demand interval on signal, being enabled to count said electrical pulses during each demand interval when the contents of said first and second counter means are at least equal as detected by said comparator means generating said comparison signal, whereby the contents of said second counter means manifests a magnitude proportional to the amount of electrical energy consumed in a first demand interval plus that excess amount of electri-cal energy consumed in each subsequent demand in-terval in which the amount of electrical energy consumed is greater than the amount consumed in the one previous demand interval of maximum elec-trical energy consumption; and (f) means responsive to said demand interval on signal to selectively engage and disengage said means for regis-tering, whereby said means for registering registers the amount of electrical energy consumed during that one de-mand interval of maximum electrical consumption as con-trolled by said comparison signal applied to the means for generating said demand interval of signal during said second instance.

2. The time-of-day demand metering system is recited in claim 1, wherein said means for generating said electrical pulses comprises a photo-electric pulse generator for genera-ting said electrical pulses.

3. The time-of-day demand metering system as recited in claim l wherein said means responsive to said control signal comprises a demand enable flip flop responsive to said control signal for generating a demand enable signal defining the be-ginning of a demand interval, a demand flip flop for generating said demand interval on signal, means for setting said demand flip flop to generate said demand interval on signal in res-ponse to said comparison signal and the presence of said demand enable signal to effect the engagement of said means for regis-tering, means for applying said end of interval signal to said demand flip flop to effect the resetting thereof, and means responsive to a prescribed number of said control signals for generating said end of interval signal to thereby reset said demand flip flop to cause said demand interval on signal to effect disengagement of said means for registering.

4. The time-of-day demand metering system as recited in claim 3 wherein said system further includes a power source for generating an alternating current signal, with said control signal selectively occurring at a specified point in time to es-tablish a prescribed phase relationship with said alternating current signal to define an on-peak power period of said system and the beginning of a demand interval, said demand enable flip flop receiving said alternating current signal in conjunction with said control signal to set said demand enable flip flop to generate said demand enable signal when said alternating current and control signals are of said prescribed phase rela-tionship, said demand enable flip flop being reset to define an off-peak power period to effect disengagement of said means for registering when said alternating current and control sig-nals are of a second prescribed phase relationship.

5. A time-of-day demand metering system for registering the amount of electrical energy consumed during demand inter-vals comprising:
(a) selectively engageable means for registering the amount of electrical energy being consumed during said demand intervals;

(b) means for periodically generating electrical pulses having a repetition frequency proportional to the amount of electrical energy being consumed by said time-of-day demand metering system;
(c) means for generating a control signal at prescribed in-tervals;
(d) means responsive, in a first instance, to said control signal for generating an end of interval signal and res-ponsive, in a second instance, to said control signal and to a comparison signal for generating a demand interval on signal;
(e) means for controlling, during each demand interval, when the registering of the amount of electrical energy being consumed is to take place, said means for controlling including, (i) comparator means for generating said comparison signal, (ii) first and second counter means, each receiving said electrical pulses and each having output ter-minals connected to said comparator means for pro-viding count signals thereto, said first counter means being set to a predetermined count in res-ponse to said end of interval signal and being en-abled to count said electrical pulses during each demand interval in the absence of said end of in-terval signal, said second counter means, in res-ponse to said demand interval on signal, being en-abled to count said electrical pulses during each demand interval when the contents of said first and second counter means are at least equal as detected by said comparator means generating said comparison signal, whereby the contents of said second counter means manifests a magnitude proportional to the amount of electrical energy consumed in that one demand interval of maximum electrical energy con-sumption; and (f) means responsive to said demand interval on signal to selectively engage and disengage said means for register-ing, whereby said means for registering registers the amount of electrical energy consumed during that one de-mand interval of maximum electrical energy consumption as controlled by said comparison signal applied to the means for generating said demand interval on signal during said second instance.

6. A time-of-day demand metering system for registering the amount of electrical energy consumed during demand inter-vals comprising:
(a) selectively engageable means for registering the amount of electrical energy being consumed during said demand in-tervals;
(b) means for generating an energy consumption signal repre-sentative of the amount of electrical energy being con-sumed by said time-of-day demand metering system;
(c) means for generating a control signal at prescribed in-tervals;
(d) means responsive, in a first instance, to said control signal for generating an end of interval signal and res-ponsive, in a second instance, to said control signal and to a comparison signal for generating a demand interval on signal.
(e) means for controlling, during each demand interval, when the registering of the amount of electrical energy being consumed is to take place, said means for controlling including, (i) comparator means for generating said comparison signal, (ii) first and second means, each receiving said energy consumption signal for accumulatively monitoring the amount of consumed electrical energy and each being connected to said comparator means to pro-vide corresponding values to said comparator means proportional to the amount of consumed electrical energy, said first means being set to a prescribed value in response to said end of interval signal and being enabled to monitor said energy consumption signal to respondingly change its value in the ab-sence of said end of interval signal, said second means, in response to said demand interval on sig-nal, being enabled to monitor said energy consump-tion signal during each demand interval when the magnitudes of the values of said first and second means are at least equal as detected by said com-parator means generating said comparison signal, whereby the value of said second means manifests a magnitude proportional to the amount of electrical energy consumed in that one demand interval of maximum electrical energy consumption; and (f) means responsive to said demand interval on signal to selectively engage and disengage said means for regis-tering whereby said means for registering registers the amount of electrical energy consumed during that one demand interval of maximum electrical energy consumption as controlled by said comparison signal applied to the means for generating said demand interval on signal dur-ing said second instance.

7. A time-of-day demand metering system for register-ing the amount of electrical energy consumed during preselected demand intervals comprising:
(a) selectively engageable means for registering the amount of electrical energy being consumed during said demand intervals;
(b) means for periodically generating electrical pulses having a repetition frequency proportional to the amount of electrical energy being consumed by said time-of-day demand metering system;
(c) means for generating a control signal at prescribed in-tervals defining on and off peak power periods;
(d) on/off peak detector means responsive, in a first instance, to said control signal defining an off-peak power period for generating an off-peak signal and responsive, in a second instance, to said control signal defining an on-peak power period and to a comparison signal for genera-ting a demand interval on signal, said on/off peak detec-tor means further responsive, in a third instance, to an end of interval signal defining the end of a demand inter-val to effect the generation of said off-peak signal;
(e) interval counter means responsive, in said third instance, to said control signal during an on-peak power period for providing said end of interval signal to said on/off peak detector means to effect the generation of said off-peak signal;
(f) demand interval means for controlling, during each demand interval, when the registering of the amount of electrical energy being consumed is to take place, said demand inter-val means including, (i) comparator means for generating said comparison signal, (ii) first and second counter means, each receiving said electrical pulses and each having output ter-minals connected to said comparator means for pro-viding count signals thereto, said first counter means receiving said off-peak signal and responding thereto to remain in a reset state during the pre-sence of said off-peak signal and being enabled to count said electrical pulses in the absence of said off-peak signal, said second counter means, in res-ponse to said demand interval on signal, being en-abled to count said electrical pulses during each demand interval when the contents of said first and second counter means are at least equal as detected by said comparator means generating said comparison signal, whereby the contents of said second counter means manifests a magnitude proportional to the amount of electrical energy consumed in that one demand interval of maximum electrical consumption, and (g) means responsive to said demand interval on signal to selectively engage said means for registering in accor-dance with said end of interval signal applied to said on/off peak detector means, whereby said means for regis-tering registers the amount of electrical energy consumed during that one demand interval of maximum electrical energy consumption.

8. In a power system of the alternating current type, a time-of-day demand meter for registering the amount of elec-trical energy consumed by the system during preselected demand intervals comprising:

(a) selectively engageable means for registering the amount of electrical energy being consumed during said demand intervals;

(b) means for generating electrical pulses having a repeti-tion frequency proportional to the amount of electrical energy being consumed by said power system;
(c) means for generating a control signal at prescribed in-tervals which is either in or out of phase with the sys-tem alternating current during said prescribed intervals;
(d) interval counter means responsive to said control signal for generating an end of interval signal defining the end of a demand interval after counting a prescribed number of said control signals;
(e) an on/off peak detector including, (i) first detector means capable of achieving first and second states, said first detector means res-ponsive to said control signal and the system al-ternating current to achieve said first and second states in accordance with the in and out of phase relationships respectively between said control signal and the system alternating current said first detector means generating a demand enable signal representative of on and off-peak power period when in said first and second states res-pectively, (ii) second detector means capable of achieving first and second states for generating a demand interval signal in accordance with the states thereof, said second detector means including means for setting said second detector means to said first state dur-ing an on-peak power period in response to said demand enable signal and a comparison signal, and generating an off-peak signal to set said second detector means to said second state during an off-peak power period in response to said demand en-able signal, or during an on-peak power period in response to said end of interval signal;
(f) demand interval means for controlling, during each demand interval, when the registering of the amount of electrical energy being consumed is to take place, said demand interval means including, (i) comparator means for generating said comparison signal, (ii) first and second counter means, each receiving said electrical pulses and each having output terminals connected to said comparator means for providing count signals thereto, said first counter means being held in a reset state by said off-peak signal and enabled to count said electri-cal pulses in the absence of said off-peak signal, said second counter means, in response to said demand interval signal, being enabled to count said electrical pulses during each demand interval of an on-peak power period when the contents of said first and second counter means are at least equal as detected by said comparator means genera-ting said comparison signal, whereby the contents of said second counter means manifests a magnitude proportional to the amount of electrical energy consumed in that one demand interval of maximum electrical energy consumption; and (g) means responsive to said demand interval signal for se-lectively engaging and disengaging said means for regis-tering in accordance with said end of interval signal applied to said second detector means whereby said means for registering registers the amount of electrical energy consumed during that one demand interval of maximum elec-trical energy consumption.

9. In a time-of-day demand metering system, a method of registering the amount of electrical energy consumed during demand intervals comprising the steps of:

(a) continuously generating a series of pulses having a re-petition frequency proportional to the amount of electri-cal energy being consumed by said time-of-day demand metering system;
(b) providing first and second counters capable of counting said pulses;
(c) continuously comparing the contents of said first and second counters;
(d) presetting said first counter to be prescribed count be-fore a first demand interval;
(e) initiating a demand: interval of a specified length of time during which the consumption of electrical energy may be registered;
(f) applying said pulses to said first counter in all demand intervals while selectively applying said pulses to said second counter during the periods of those demand inter-vals in which the amount of electrical energy being con-sumed is in excess of the one previous demand interval of maximum electrical energy consumption when the contents of said counters are at least equal;
(g) registering the amount of electrical energy being consumed during the period in each of those demand intervals when there is at least equality in the contents of said first and second counters;
(h) terminating the present demand interval while presetting said first counter to said prescribed count to inhibit the registering of electrical energy and any further coun-ting of said pulses by said counters whereby the amount of electrical energy registered represents the amount of electrical energy consumed in the one previous demand interval of maximum electrical energy consumption; and (i) repeating steps (e) through (h) for a second demand interval.

10. A time-of-day demand metering system for register-ing the amount of electrical energy consumed during demand intervals comprising:
(a) selectively engageable means for registering the amount of electrical energy being consumed during said demand intervals;
(b) means for generating electrical pulses having a repeti-tion frequency proportional to the amount of electrical energy being consumed by said time-of-day demand meter-ing system;
(c) means for generating a control signal at prescribed intervals;
(d) means responsive, in a first instance, to said control signal for generating an end of interval signal and res-ponsive, in a second instance, to said control signal and to a comparison signal for generating a demand interval on signal;
(e) means for controlling, during each demand interval, when the registering of the amount of electrical energy being consumed is to take place, said means for controlling in-cluding;
(i) comparator means for generating said comparison signal, (ii) first and second counter means, each receiving said electrical pulses and each having output terminals connected to said comparator means for providing count signals thereto, said first counter means being reset to zero in response to said end of interval signal and being enabled to count said electrical pulses during each demand interval in the absence of said end of interval signal, said second counter means, in response to said demand interval on signal, being enabled to count said electrical pulses during each demand interval when the contents of said first and second counter means are at least equal as detec-ted by said comparator means generating said com-parison signal, whereby the contents of said sec-ond counter means manifests a magnitude propor-tional to the amount of electrical energy consumed in a first demand interval plus that excess amount of electrical energy consumed in each subsequent demand interval in which the amount of electrical energy consumed is greater than the amount con-sumed in the one previous demand interval of maxi-mum electrical energy consumption;
(f) means responsive to said demand interval on signal to selectively engage and disengage said means for regis-tering, whereby, said means for registering registers the amount of electrical energy consumed during that one demand interval of maximum electrical energy consumption;
and (g) reset switch means actuable to reset said first and second counter means to initialize said time-of-day demand metering system.

11. A three rate structured time-of-day demand meter-ing system for registering the total amount of electrical energy consumed and the amount of electrical energy consumed during on-peak power periods and preselected demand intervals, comprising:
(a) a total register for continuously registering the amount of electrical energy being consumed by the system;
(b) an on-peak register engageable to register the amount of electrical energy consumed during said on-peak power periods;
(c) a demand register engageable to register the amount of electrical energy being consumed during said demand in-tervals;
(d) a programmable control circuit for generating a control signal at prescribed intervals to engage and disengage said on-peak register during on and off peak power per-iods respectively, and during demand intervals in which the amount of electrical energy consumed is to be mea-sured;
(e) means for generating electrical pulses having a repeti-tion frequency proportional to the amount of electrical energy being consumed by the system;
(f) on-off peak detector means responsive, in a first in-stance, to said control signal defining an off-peak power period for generating an off-peak signal and res-ponsive, in a second instance, to said control signal defining an on-peak power period and to a comparison signal for generating a demand interval on signal;
(g) interval counter means responsive, in a third instance, to said control signal during an on-peak power period for generating an end of interval signal defining the end of a demand interval, said end of interval signal being provided to said on-off peak detector means to effect the generation of said off-peak signal;
(h) demand interval means for controlling, during each de-mand interval, when the registering of the amount of electrical energy being consumed is to take place, said demand interval means including, (i) comparator means for generating said comparison signal, (ii) first and second counter means, each receiving said electrical pulses and each having output terminals connected to said comparator means for providing count signals thereto, said first counter means receiving said off-peak signal and responding thereto to remain in a reset state during the pre-sence of said off-peak signal and being enabled to count said electrical pulses in the absence of said off-peak signal, said second counter means, in response to said demand interval on signal, being enabled to count said electrical pulses dur-ing each demand interval when the contents of said first and second counter means are at least equal as detected by said comparator means generating said comparison signal, whereby the content of said second counter means manifests a magnitude proportional to the amount of electrical energy consumed in the one demand interval of maximum electrical energy consumption; and (i) means responsive to said demand interval on signal to selectively engage and disengage said demand register in accordance with said end of interval signal applied to said on/off peak detector means, whereby said demand register registers the amount of electrical energy con-sumed during that one demand interval of maximum elec-trical energy of consumption.

12. The three rate structured time-of-day demand meter-ing system as recited in claim 11, further including reset switch means actuable to reset said first and second counter means to initialize said system.

13. In a time-of-day demand metering system, a method of registering the amount of electrical energy consumed during demand intervals comprising the steps of:
(a) continuously generating an eletrical signal representa-tive of the amount of electrical energy being consumed by said time-of-day demand metering system;
(b) providing from first and second means, first and second values respectively capable of being changed by said electrical signal applied to said first and second means during said demand intervals, said first value having a magnitude proportional to the amount of electrical energy being consumed during each demand interval, and said second value, at the termination of each demand interval, having a magnitude proportional to the amount of electrical energy consumed during the one previous demand interval of maximum electrical energy consump-tion;
(c) continuously comparing the magnitudes of said first and second values;
(d) presetting said first value to a prescribed magnitude before a first demand interval;
(e) initiating a demand interval of a specified length of time during which the consumption of electrical energy may be registered;
(f) during each demand interval, applying said electrical signal to said first means to change the magnitude of said first value, while selectively applying said elec-trical signal to said second means to update the magni-tude of said second value during the period of those demand intervals in which the amount of electrical energy being consumed is in excess of the one previous demand interval of maximum electrical energy consump-tion when the magnitudes of said first and second values are at least equal;
(g) registering the amount of electrical energy being con-sumed during the period in each of those demand inter-vals when there is at least equality in the magnitudes of said first and second values;
(h) terminating the present demand interval while presetting said first value to said prescribed magnitude to inhibit the registering of electrical energy and any further changing of said first and second values by said elec-trical signal, whereby the amount of electrical energy registered represents the amount of electrical energy consumed in the one previous demand interval of maximum electrical energy consumption; and (i) repeating steps (e) through (h) for a second demand interval.