CA1106978A - Simple flexible indexing method for ros storage microcomputers - Google Patents

Abstract

ABSTRACT
An improved method of modifying fixed instructions in a read only memory in a data processing system is described. The instructions stored in the read only memory are made modifiable by data stored in a random access memory. In operation, an instruction is retrieved from the read only memory and data is retrieved from the random access memory in accordance with a previously retrieved instruction. When the last retrieved instruction is to be modified an indexing gate enables the data from the random access memory to be combined with the last retrieved instruction in an adder or like logic device.
The output of the adder or like logic device is the modified instruc-tion. This simple arrangement enables a read only memory instruction set to be modified without limit.

Description

7~3 1 Field of the Invention The present invention relates to data processing systems. More particularly, the invention relates to an instruction modifying method and apparatus. The method and apparatus of the present invention is capable of modifying any portion of an instruction in the data pro-cessing system prior to its execution.
Prior Art In modern computers, especially mini and micro-computers, instruc-tion storage is usually provided by read only storage devices. This 10 results in a loss of flexibility compared to a stored program computer in which the instructions may be modified in sequence and in operation code.
In the past, complex indexing methods and apparatus including ad-ditional index registers have been enlisted in an effort to alleviate these shortcomings. Usually such methods and circuitry have applied only to a portion of the total instruction set and/or have a limited number of index registers with attendant loading and modifying com-plexities and/or cannot modify the operation portion of the instruction itself.
U.S. Patent 3,503,046 which outlines an instruction modification circuit suffers from obvious shortcomings in that the primary means for indexing is the arithmetic registers. This is unduly restrictive and requires additional machine cycles to load the register. Dummy machine cycles are wasted to modify the command and additional cycles are required for setting/resetting a flip-flop to modify the instructions desired. Only instruction address modification is provided by the aforesaid patent.
Objects of the Present Invention The principal objects of the present invention are to provide 30 improved method and apparatus for the modification of instructions ,~

CA9-77-004 ~ P7 ~3 l without requiring additional registers or complex circuitry while still being capable of modifying substantially any or all instructions.
Statement of the Invention As is well known in the art, modern computers, particularly mini and micro-computers, provide instruction storage by read only storage devices while data storage is accomplished by the use of volatile or modifiable memories such as a random access stores (RAS).
According to the present invention, instructions stored in a read only store (ROS) are modifiable by data received from a random access lO store in the computer. An instruction is retrieved from the read only store and data is retrieved from the random access store, and, if an indexing gate is active, the instruction and the data are combined in an adder. The output of the adder constitutes the modified instruction.
With this simple arrangement the read only store instruction set can be modified manyfold, limited only by the capacity of the random access store. Thus, with the addition of a small amount of structure, immense versatility is achieved.
In accordance with the present invention, method and apparatus is provided for modifying instructions in a data processing system having 20 at least two memories.
A first of these memories, typically a read only store, is ad-dressed to selectively access a stored instruction. The addressed and accessed instruction obtained from the first memory is then directed to instruction modifier means which may include an adder. Data is ad-dressed in another memory, typically a random access store, in accor-dance with an instruction received from the first memory during a pre-vious processing cycle, possibly the immediately preceding processing cycle. The addressed data is directed to instruction modification gating means which may be selectively energized to thereby selectively 30 furnish the addressed data to the instruction modifier means. The CAg-77-004 ~ 7~

1 data received by the instruction modifier means and the accessed in-struction received by it are combined by means of the instruction modifier means to prpvide a modified instruction to the data processing system typically to be put to use by the system in much the same fashion as unmodified instructions.
As may be readily inferred by experts in the art a greatly expanded instruction set has been achieved.
In order that the present invention may be readily carried into effect, it will now be described with reference to the accompanying drawings, wherein;
FIG. 1 is a block diagram of a data processing system of the prior art to which the instruction modification method of the present inven-tion may be applied.
FIG. 2 is a block diagram of a data processing system employing the method and apparatus of the present invention.
FIG. 3 is a simplified circuit diagram of an embodiment of the present invention as used in a data processing system.
To ease understanding of the present invention so that it may be readily carried into effect typical current practice in the processing 20 of instructions and data will be discussed followed by a description of the present invention all with reference to the abovementioned drawings.
The data processing system of the prior art, as depicted in Fig. 1, comprises two memories, an instruction store 1 (I-store) for the storage of instructions, and a data store 2 (D-store) for the storage of data.
An instruction comprises an operational portion or operand and an address portion or address label as is well known in the art although variants have been developed with additional portions for specialized uses. It will be realized by those skilled in the art that the method and apparatus of the present invention are readily adaptable to those 30 variants as well.

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1 Each memory has associated with it its own address register operat-ing by branching or incrementing in known fashion for selectively ad-dressing and accessing its contents. The instruction store 1 is ad-dressed by an instru~tion address register 3 (IAR) connected to it, the Data store 2 is addressed by its data address register 4 (DAR). Thus, particular instructions and data can be selectively accessed from their respective memories.
Interconnection of the registers by branch line 5 permits branching of instructions within a program while line 6 provides output instruc-10 tions to initiate data accessing from data store 2 and other instructionsequencing.
The output of instruction store 1, an instruction, is fed to operation register 7 which, when triggered by a clock pulse from the processing system in a known manner, supplies the instruction to an input 10 of an arithmetic logic unit 8 for operation upon the data received at input 11 of the arithmetic logic unit 8 (ALU) from the data store 2 connected to it and information supplied by the accumulator 9 connected to ALU input 12 and ALU output 13.
The accumulator output 14 and ALU input 12 are connected to input/
20 output devices in a known manner.
Generally, in digital data processing systems similar to those illustrated in Figs. 1, 2 and 3, instructions which are stored in the system must be fetched (accessed) from an instruction storage memory, such as the instruction store 1 in the illustration, and applied to the data stored and fetched from a data storage memory, such as the data store 2 of the system.
In modern computers, more particularly mini and micro-computers, the instruction storage memory is made from read only storage (ROS) devices commonly known as read only memories (ROM). Typically, the read 30 only memories may be obtained with built-in instructions predetermined in manufacture or as Programmable read only memories (PROM) which are programmed with a series of instructions before insertion in a data processing system.

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1 Once in place in a system, it is not usually economically feasible to change the programming of the PROM or to replace it as the down time would be unacceptable.
In systems like that of Fig. 1, the data memory is modifiable.
Typically, a random access memory or a serial memory which allows inser-tion, modification or deletion of memory stored data by the system either internally or by external inputs as is well known is provided.
As is well known in the art in system data processing, two main phases of operation are carried out cyclically, usually serially, in parallel or both. These operations consist of instruction accessing or fetching and instruction application or the execution of instructions on the data to obtain the desired result.
It will be most logical to examine the operation of a data pro-cessing system by considering its operation midstream.
First, we will consider instruction accessing, and second, in-struction execution. While a next sequential instruction is being selectively accessed from the instruction store 1 read only memory in accordance with the corresponding address label stored in the IAR 3, the execution cycle of the system is selectively fetching or accessing data from D-store 2 according to the corresponding addresses in the DAR 4 and combining it with data fed back from the output 14 of the accumulator 9 by means of the ALU 8 in a known manner.
Once the cycle of these operations has been completed, the output 13 of ALU ~ is a product of the function specified ln the operation register 7, the data output of data D-store 2 and the output 14 of accumulator 9. The output 13 is then set in the accumulator 9 in a known manner by the processing system.
Subsequently the IAR 3 is incremented to address the next sequen-tial instruction or is set directly via branching line 5 in a known manner if a branching instruction is to occur. DAR 4 is set to address the next data word according to the address label of the instruction fetched from the I-store 1.

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1 In applying the method and apparatus of the present invention to the abovementioned system of the prior art, instruction modifier means, gating means and special instructions hereinafter called modification instructions are provided as described in more detail below.
Similarly performing structures in each of the following described diagrams will be labelled similarly to those of Fig. 1.
As depicted in Fig. 2, the improved data processing system of the present invention comprises at least two addressable memories (al-though the use of additional memories for increased versatility is also contemplated) one of which is I-store 1', and another, D-store 2'.
The information contents of each is selectively accessible by their respective index registers, namely IAR 3' and DAR 4', respectively.
In this example, the instruction modifier means comprises instruc-tion modifier adder (IMA) 15 (although modifier means other than adders, for instance, AND/OR or Exclusive OR devices, etc could be used de-pending on the results desired) fed by (a) the I-store 1' at its input 16 for accepting instructions therefrom and (b) by IMA gate 17 at its input 18.
IMA gate 17 derives its data input from D-store 2'.
Operation register 7' (connected to IMA 15), ALU 8' and accumulator 9' have the same role as their counterparts in Fig. 1. Branch line 5' connecting IAR 3' and DAR 4' provides branching capability as before.
Line 19 connects IMA 15 output 20 to DAR 4' for selective accessing of data from associated D-store 2'.
As stated above, the application of the method of the invention to data processing requires the provision of a special instruction called a modification instruction which is stored in the instruction store 1' along with other conventional instructions.
In the processing systems of most concern, the instruction store 1' is unmodifiable so that its contents, the instructions, are not alter-CA9-77-004 ~L~6~37~

1 able within the instruction store 1'. The modification instruction when fetched from the instruction store 1' by means of its IAR 3'~ acts like any other conventio~al instruction obtained from the store in the in-struction or execution phase of operations. The operand and address portion of the instruction code are fetched or accessed from the in-struction store 1' at more or less the same time as data is being fetched from the data store 2' according to the address (i.e. the address of the instruction received previously along line 19) in the data address register 4'.
Provided no previous modification instruction has called for the modification of the presently considered modification instruction this instruction is passed unmodified through IMA 15 (IMA gate 17 not having been activated by a pulse via trigger line 21 and hence remaining in a blocking state).
On the activation of operation register 7' by a clock pulse on trigger line 22 in a known manner the modification instruction is pro-vided to ALU input 10' setting ALU 8' to the desired function. Data supplied from D-store 2' at ALU input 11' and previously processed data from accumulator 9' at ALU input 12' are then combined arithmetically by ALU 8' in accordance with the setting operand received at input 10' in a known manner.
At the end of the phase the accumulator 9' is set to ALU output 13' to thereby feed output devices (not shown).
At the end of this phase of operation, the IAR 3' is incremented, typically by a clock pulse, and the address portion or label of the aforementioned modification instruction enters and sets DAR 4'.
During the next phase of the operation the next sequential instruc-tion is accessed or fetched from instruction store 1' according to the address in IAR 3' in a known manner and at substantially the same time CA9-77-004 ~L~Lq~6~7~3 `~ 1 as data is fetched from D-store 2' via its address obtained from the address label of the previous instruction in DAR 4' which, in this example was a modification instruction.
According to the method of the invention, the data from D-store 2' is gated by IMA gate 17 only if a modification instruction ls being executed to achieve modification and not if the instruction executed (i.e. a previous one) is a normal non-modification instruction from instruction store 1'.
The execution of the previous modification instruction causes the subsequent activation of IMA gate 17 to feed data from the data store

2' to the input 18 of IMA 15 which combines the instructions received at input 16 and the data received at input 18 in an arithmetic manner, such as by adding, to output a modified instruction address to the DAR 4' and a modified instruction operation code or operand to the operation re-gister 7'.
Thus the improvement of the invention results in the modification instruction modifying any following instruction, the modified instruc-tion can be applied in the arithmetic logic unit 8' and elsewhere in the system in a known manner.
It will be realized by those skilled in the art that, when the output of operation register 7' decodes a modification instruction operand, known means provides a substantially instantaneous trigger signal to IMA gate 17 via trigger 21 so that only the next following instruction can be modified. However, if known decoding and storage devices are employed any following instruction may be modified.
Fig. 3 is a simplified circuit diagram of an embodiment of the present invention used in a typical data processing system such as that shown in Fig. 2 illustrating suitable components capable of carrying out the method of the invention.

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1 It will be understood by those familiar with the art that the specific embodiment to be described is applicable to microcomputers using 8 bit words, and 8 bit instructions (4 bits thereof being reserved for the address portion and the other 4 bits for the operand).
With suitable modification, which will be immediately apparent, the present invention can be used with other data word and instruction sizes.
Of course, any increase in size would expand the processing capability and increase the complexity of the system.
Typically mini and micro-computers are assembled from integrated circuit building blocks which are readily available commercially.
Preferably, off the shelf items, such as registers and gates are used where possible but other items, such as read only memories (ROM's), may be ordered to satisfy individual preferences. With this in mind, this invention, as described in relation to Fig. 2, will be presented with illustrations of suitable components.
As illustrated in Fig. 3, two addressable memories are provided (although additional memories may be useful in some instances). The instruction store 1", which is capable of storing 8 bit instructions, is derived from two masked programmed integrated circuits labelled la and lb, respectively. Each of the two integrated circuits are available as standard Part Nos. 74187 from Texas Instruments Incorporated and are available with preselected programming. As each circuit is capable of storing only 4 bit units of information two circuits are required. Unit la is used for storage of the address portion of instructions and unit lb for storage of the corresponding operands.
The ROM's are programmed with two types of instructions; regular instructions and modifier or modification instructions. The latter type have operands with selected coding having certain common characteristics capable of being decoded to provide a trigger signal for instruction modifier gating means to allow subsequent instruction modifications.

CA9-77-004 i~ 6~

The other memory, data store 2" is also formed in two parts. Each part consists of an integrated circuit forming a 16 by 4 bits RAM. The RAM is available as standard Part No. 7489 from Texas Instruments Incorporated. The RAM is labelled as 2a and 2b. Concurrent operation of each RAM permits operation with 8 bit data words.
Instruction store 1" is addressed by associated IAR 3" via in-struction access cables A and A' to permit selective access to stored instructions. The accessed stored instructions are outputted onto output cables B and B', respectively. The outputs on cables B and B' provide address and corresponding operand portions of instructions to IMA 15.
Similarly, the D-store 2" is addressed by its associated DAR 4" via data register or output cable D to selectively access stored data. Data output cables E and E' feed ALU 8".
In this example, IAR 3" comprises two cooperatively connected registers 3a and 3b. The registers 3a and 3b may be activated by in-crementing or by branch loading via branch cable c (comprised of lines Cl, C2, C3, and C4). Input lines Kl and K2 are used for load low and load high, respectively in a known manner. Registers 3a and 3b may be integrated circuits which are commercially available as Part Numbers 74163 from Texas Instruments Incorporated.
DAR 4" is a 4 bit, pulse operated latching register deriving its input from the IMA address output to cable C.
Operation register 7" derives its input from IMA operand output cable C' and, when loaded, outputs to the ALU along ALU operand input cable D'. Registers DAR 4" and 7" may be of the type commercially available as Part No. 7495 from Texas Instruments Incorporated.
Modification adder 15 comprises two adders labelled 15a, and 15b and provides the modification means in this example. Each of adders 15a or CA9-77-004 ~ ?6~7~3 1 15b can provide a 4 bit sum for the modification operations. Each ad-der 15a or 15b may be of the type commercially available as Part No. 7483 from Texas Instruments Incorporated.
Other devices can be used for the modification means, such as AND/OR circuits, Exclusive OR circuits or many other function circuits depending on the type of modification of instruction desired and it is understood that the invention is not limited to adder type modifiers alone.
Input information to the modification adder 15' is obtained via in-struction output cables B and B'. Cable B is connected to modification adder component 15a, and cable B' to adder component 15b to deliver the corresponding address and operand portions of the instruction. Gate output lines J and J' from modification adder gate components 17a and 17b, respectively of modification adder gate 17' deliver modification inputs to adder components 15a and 15b, respectively. Gate Components 17a, 17b, in this example, are integrated circuit gates which are com-mercially available as Part No. 74157 from Texas Instruments Incorporated.
Inputs E, and E' for gates 17a and 17b, respectively, are derived from the identically labelled data output cables E and E' from D-store 2".

Outputs J and J' appear only when trigger input K3 is activated by the corresponding output of decoder 23 fed by operand input cable D'.
Decoder 23 may comprise a PROM integrated circuit decoder of type 82S123 available commercially from Signetics Corporation with suitable bit patterns stored. Decoder 23 provides loading inputs Kl and K2 to load the instruction address register 3" high and low, respectively, and to activate the IMA gate 17' when appropriate signals or information are present on cable D'. In the case of the present invention, this is when the operand portion of a modification instruction is present on the cable D'. Other outputs Kn, etc., may be used at other points in the pro-cessing system, for example, to output the accumulator 9" or permit inputs to the ALU 8".
The components of arithmetic logic unit 8" comprising paired type integrated circuits, available as Part No. 74181 from Texas Instruments Incorporated and labelled 8a and 8b. Units 8a and 8b derive input via data output cables E and E' and input/out cables F and F' respectively.
Operand input cable D' sets the function desired to compare the information fed by the aforesaid cables.
ALU output cables G and G' feed components 9a and 9b of the ac-10 cumulator 9". Accumulator 9" outputs to input/output devices when loadline 24 is activated in a known manner by the system.
Accumulator 9" comprises a pair of 4 bit registers and has an output line disconnect feature for disconnecting from the ALU without affecting the accumulator contents. Each register of accumulator 9" may be an integrated circuit of the type available commercially as Part No. 74295 from Texas Instruments Incorporated.
Although the operation of the method and apparatus of the present invention should now be apparent the operation of the embodiment of the invention illustrated in Fig. 3 in accordance with the method of the 20 invention will now be described.
As stated above, two types of instructions are stored in the instruc-tion store 1", normal instructions and modification instructions. The latter type when detected by line decoder 23 or like device, procure the modification of the next following instruction.
Consider the system in mid operation, an instruction is to be fetched from instruction store 1". To obtain the instruction, the instruction address register may be operated by pulling increment line to cause sequential loading or by loading the contents of modification - l3 7~3 1 adder output cable C by pulsing selectively high load line K2 or low load line Kl in a known manner. This will enable selection of a block of instructions or a separate instruction within a block of instruc-tions.
Each activation of the IAR 3" selectively addresses an instruction in the I store via access cables A and A'. The selected instruction then appears on output cables B and B' and impresses the instruction on the inputs of modification adder input components 15a and 15b", re-spectively.
If the immediately preceding instruction was not a modification in-struction, decoder 23 will not provide a trigger input K3 to gate 17' (17a and 17b) and, consequently, gate output lines J and J' will be inactive. Hence, whatever instruction appeared on lines B and, B' will appear unmodified on modification adder output lines C and C' and the instruction will be implemented normally by the system.
If, on the other hand, the previous instruction was a modification instruction, gate 17' will be active to thereby provide information on cables E and E' from the data store 2" to lines J and J'. The modifica-tion adder will combine these arithmetically to obtain a modified instruction (the instruction accessed from I-store 1" as modified by data accessed by the previous modification instruction address).
Either the operand, address label or both parts of an instruction may be modified in this manner.
It is contemplated by the invention that all or any part of the data, eg. 2 of 8 bits may be applied for modification purposes to any part of either operand address or both parts of an instruction.
It will also be realized that, when and if the instruction to be modified is a null instruction, data accessed from D-store 2" will be inserted as the modified instruction, in effect permitting storage of instructions in the Data store 2", if desired.

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1 At the end of an instruction access cycle, a timing pulse is im-pressed on load line 25 of the DAR 4" and operation register 7" and causes the loading of output cables D and D' respectively while IAR 1"
is usually incremented once again to access new instructions.
The address portion of the modified instruction with which we are presently concerned enters data store 2" via cable D while the cor-responding modified operand appearing on cable D' sets a function in ALU
8".
ALU 8" combines data impressed on it via cables E and E' and input/
output cables F and F'.
At the next cycle, accumulator 9" (9a, 9b) is set to the output of ALU 8". This output appears on input/output lines F and F' and supplies peripheral devices such as printers, teletype units or magnetic tape units for instance.
In this manner an instruction may be modified, the data address register may be loaded with a modified instruction address, and the operation register may be loaded with a modified operand.
It should be apparent that the decoder 23 may be readily designed or selected to permit modification of any subsequent instruction rather than just the immediately subsequent one as disclosed above. Various apparent modifications to the method and the apparatus of the invention are apparent and could be made without departing from its spirit or scope.

Claims (7)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A method of modifying instructions in a data processing system having at least a read only memory and a random access modifiable data storage memory, comprising;
addressing said read only memory to selectively access a stored instruction, directing said addressed and accessed instruction to instruction modifier means in said data processing system;
addressing data in said random access memory in accordance with an instruction received from said read only memory during a previous process-ing cycle;
directing said addressed data to instruction modification gating means;
selectively energizing said gating means to thereby selectively furnish said addressed data to said instruction modifier means and;
combining said data received by said instruction modifier means with said accessed instruction received by said instruction modifier means to provide a modified instruction to said data processing system.

2. A method according to claim 1 wherein said instruction modifier means includes a modification adder and said instruction modification gating means comprises modification adder gating means selectively energizable when a modification instruction address label has been received by said modification adder gating means during the immedia-tely preceeding processing cycle to furnish said addressed data to said modification adder; and operating on said data and said addressed and accessed instruc-tion by said modification adder to provide modified instruction to said data processing system, said instruction modification including the selectively modifying of the operand portion and address label of said addressed and accessed instruction.

3. A method of modifying the effect of instructions in a digital computer data processing system having at least a read only memory and a random access memory, comprising:
addressing said read-only memory, by means of an instruction address register to access an instruction in the instruction store of said read-only memory;
where an instruction includes at least an address portion of an operand portion directing said addressed and accessed instruction to a modification adder;
addressing data in said random access memory of said data process-ing system, said data being addressed by means of a data address register in accordance with the address label of a modification instruction accessed from said read-only memory and received by said data address register during the immediately preceeding processing cycle;
providing said addressed data to modification adder gating means;
selectively energizing said modification adder gating means when the address label of a modification instruction has been accessed from said read-only memory received during the immediately preceeding data processing cycle, to furnish said addressed data to said modification adder; and arithmetically operating on said data and said accessed instruc-tion by said modification adder to provide a modified instruction to said digital computer data processing system;
said instruction modification including selectively modifying the operand portion and address label of said addressed and accessed instruction.

4. A method according to claim 3 wherein said instruction modifica-tion includes modifying selectively any portion of the addressed and accessed instruction.

5. In a cyclically operable data processing system having at least two memories, the combination of a first addressable read-only memory for the storage and selective accessing of instructions;
a second addressable random access (modifiable) memory for the storage and selective accessing of data;
instruction modifier means for accepting an instruction accessed from said first memory and data accessed from said second memory and for combining said data with said instruction to provide a modified in-struction for said data processing system, and;
instruction modifier gating means selectively energizable for the furnishing of addressed data to said instruction modifier means in accordance with an instruction received from said instruction modifier means during a previous cycle.

6. Apparatus according to claim 5 wherein said instruction modifier means includes a modification adder gating means selectively energiz-able after receiving the address label of a modification instruction during the immediately preceeding processing cycle for the selective furnishing of accessed data to said modification adder.

7. In a digital computer data processing system having at least two memories, the combination of a read-only memory for the storage of instructions, and instruc-tion address register means for addressing said read-only memory to selectively access instructions; wherein each instruction includes at least an address portion and an operand portion;
a random access memory for the storage of data, and data address register means for addressing said random access memory to selectively access data;
modification adder means for accepting an instruction accessed from said read-only memory and data accessed from said random access memory and for arithmetically operating on said data and said instruction for the provision to said digital computer data processing system of an instruction selectively modified as to any portion thereof, and;
modification adder gating means selectively energizable in receiving the address label of a modification instruction accessed from said read-only memory during the immediately preceeding data process-ing cycle for the selective furnishing of accessed data to said adder.