CA1102458A - Video synthesizer for a digital video display system employing a plurality of grayscale levels displayed in discrete steps of luminance - Google Patents
Video synthesizer for a digital video display system employing a plurality of grayscale levels displayed in discrete steps of luminanceInfo
- Publication number
- CA1102458A CA1102458A CA310,784A CA310784A CA1102458A CA 1102458 A CA1102458 A CA 1102458A CA 310784 A CA310784 A CA 310784A CA 1102458 A CA1102458 A CA 1102458A
- Authority
- CA
- Canada
- Prior art keywords
- character
- different
- video
- displayed
- luminance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/22—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of characters or indicia using display control signals derived from coded signals representing the characters or indicia, e.g. with a character-code memory
- G09G5/24—Generation of individual character patterns
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/42—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of patterns using a display memory without fixed position correspondence between the display memory contents and the display position on the screen
Abstract
ABSTRACT OF THE DISCLOSURE
A digital video display system wherein the various characters to be displayed are displayed in the form of images of the complete character rather than the standard dot-matrix pattern of the prior art. A character genera-tor in the display system stores signals representing the various characters to be displayed which are retrieved from storage in response to a character code. The signals are in the form of a binary code having a sufficient number of bits to represent a different number of levels of gray-scale or luminance values for the various picture elements making up the character image. The binary codes thus retrieved from storage are supplied to a video synthesizer that generates the video signal to display the character images which may be displayed in a number of different modes including white-on-black, black-on-white, black-on-gray, and white-on-gray as well as different combinations of such modes to represent a cursor. The video synthesizer can generate output voltage levels in discrete stops for the different luminances to be employed. The voltage out-put signals differ from level to level in accordance with the 2.2 root of luminance.
A digital video display system wherein the various characters to be displayed are displayed in the form of images of the complete character rather than the standard dot-matrix pattern of the prior art. A character genera-tor in the display system stores signals representing the various characters to be displayed which are retrieved from storage in response to a character code. The signals are in the form of a binary code having a sufficient number of bits to represent a different number of levels of gray-scale or luminance values for the various picture elements making up the character image. The binary codes thus retrieved from storage are supplied to a video synthesizer that generates the video signal to display the character images which may be displayed in a number of different modes including white-on-black, black-on-white, black-on-gray, and white-on-gray as well as different combinations of such modes to represent a cursor. The video synthesizer can generate output voltage levels in discrete stops for the different luminances to be employed. The voltage out-put signals differ from level to level in accordance with the 2.2 root of luminance.
Description
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BACKGROUND OF THE INVENTION
Field of the Invention - This invention relates to a digital Yideo display s~stem and more particularly to such a display system having a ~ideo synthesizer providing a plurality of - gray-scale le~els for a more natural display of charac-ters.
Descri~tion o t_e Prior Art There are commercially avallable today many examp-les of so called "video character displays" or "video terminals"~ These systems form representations of . j .
characters on the ~ace o~ a cathode ray tube where each ., .
character i5 ormed as a matrix of discrete points. Such a method o~ representation of characters predates elect-ronics and may he found in embroider~, mosaics, and other disciplines employing a grid pattern. Such characters displayed on a cathode ray tube are of inferior readabil-ity unless the do~ matrix allowed for each character is much larger than 5 x 7 or 7 x 9 which are the most commonly used matrices. har~er matrices require the electron beam to transverse many more points on each complete display frame, and thus require higher speed logic and cathode ray tube deflection circuits.
Although such systems may be called "video termin als'~, they are without exception incompatible with broadcast vid o standards and use a standard television set or monitor in such a crude ~ashion that half of its spatial and all of its gray-scale resolution is lost in onming an image.
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BACKGROUND OF THE INVENTION
Field of the Invention - This invention relates to a digital Yideo display s~stem and more particularly to such a display system having a ~ideo synthesizer providing a plurality of - gray-scale le~els for a more natural display of charac-ters.
Descri~tion o t_e Prior Art There are commercially avallable today many examp-les of so called "video character displays" or "video terminals"~ These systems form representations of . j .
characters on the ~ace o~ a cathode ray tube where each ., .
character i5 ormed as a matrix of discrete points. Such a method o~ representation of characters predates elect-ronics and may he found in embroider~, mosaics, and other disciplines employing a grid pattern. Such characters displayed on a cathode ray tube are of inferior readabil-ity unless the do~ matrix allowed for each character is much larger than 5 x 7 or 7 x 9 which are the most commonly used matrices. har~er matrices require the electron beam to transverse many more points on each complete display frame, and thus require higher speed logic and cathode ray tube deflection circuits.
Although such systems may be called "video termin als'~, they are without exception incompatible with broadcast vid o standards and use a standard television set or monitor in such a crude ~ashion that half of its spatial and all of its gray-scale resolution is lost in onming an image.
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The most impo~tant reason why designers have a~oided the standard ~roadcast type o video raster i5 that`it is interlaced. B~ producing the complete frame with two interlaced ~ield~, broadcast ~ideo achieves twice the vertica]. resoLution than can be achieved at I that scan rate without interlace. However, dot-matrix charac~ers appear to "~licker" when interlaced fields are used, particularl~ if the great majority o dots o~er any local region happen to fall within on~ or the other ~.ield. Flicker is a problem when interlace is employed not only for dot-matrix charactels but also when there are ~ery high contrast images. Thus, even uhen a standard ~ideo mOnitor is employed as the display de~ice for a ~ideo terminal, it is used without inter-lace and is limited in its ~ertical resolution. Be-. ~ , cause this resoIution is inadequate to display a large number of good quality dot-matrix characters, some , systems must employ ~ideo rasters which are incompatible with ~tandard ~ideo monitors. It is desirable to employ standard video monitors because o their economy due to mass production.
Such dot-matrix raster scan video displays are disclosed for example in U.S. Patent No. 3,345,458 (October 3t 1967 ~ D.A Cole et al~ ~owe~er, the concept o~ dot-matrix character generation for video display goes bac~ to 1948 as evidence by the U.S. Patent 2,972,016 t~ebruary 14, 1961 - Gerald Dirks).
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It is, then, an object of the present invention to provide in at least olle embodiment a digital video display system which provides more natural display of charact~rs and other information.
It is ano~ler object o~ the present invention to provide in at least one e ~ociiment a digital video disL~lay syst:m having interlaced scan for higher resolution but whicl display is "flickerl' free.
It is still another object of ~he present invention to provide in at least one embodiment a video digital display sys~em that can employ standard commercial video monit~rs.
Accordingly, the present invention provides a vid~o synt~lesi2er for a digital video display system, said video syn~lesizer comprising: a summing network to provide in sequence a plurality of different voltage levels which levels ~ are selected from three or more such levels to designate ; different luminance values to be displayed, said su.~ning network having a pluralit~ of different input leads, said summlng network including a plurality of resistances coupled between said respective input leads and a common connection, said resistances having dif~erent resistance values to provide to said co.~non connection different - ~ voltage levels which increase proportionately to a root of the luminance to be displayed; a storage device having a plurality o~ output leads coupled to respective ones of said summing network input leads, said storage device stoxing different monadic operation codes to activate di~ferenl . . .
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combinations of said input leads, and means coupled to said - storage device to transmit a binary code to said stora~e device which blnary code desi~nates a monadic operation code to select the particular luminance to be displayed.
: An embodiment of the pr~QsQnt invention will no~ be described, by way of example, \lith reference to the accompa-nying drawings in which:-Figure 1 is a representation of a ~o~-matri~ character as em~loyed in the prior art;
Figure 2 is a representation of a character imaye as emplo~ed in the present embodi.ment;
- - . .'~igures 3A and 3B are representaticns of the transfor-mation of luminance values as employed in the present ~ . embodJ' ment;
-` E~igure 4 is a diagram of a system employiny the present .`~. embodiment;
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Figure S is a diagram of the video synthesizer of the ~ present embodiment;
.. ~ Figure 6 is a diagram o the display mode transform logic of the present embodiment;
Figure 7 is an example of character data mapping as employed ln the present embodiment;
Figure ~ is a diagram of the digital-to-~ideo convertor of the present embodiment;
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-: Figure 9 is a diagram o~ the character generator of the present em~odiment;
Figure 10 is a diagxam o a front storage element asemployed in the present embodimen~;
Figure 11 is a diagram of the control element logic of the present embodiment;
Figure 12 is a representation of ~he "character wheel" of the present embocliment; and ~ igure 13 is a schematic diagram of the timing system of the present embodiment.
GENERAL DESCRIPTION O~ THE SYSTEM
~ or video repr sentation o~ an imaye, a signal must - ~ be provided which producës on a video monitor an approx-imation of that image which is close enough to what is perceived by the human eye. A video camera will convert - the image to à signal for the display of natural scenes For synthetic images, suc~ as character or graphic dis-- ~ plays, a synthetic video signal is produced electroni cally according to information stored within or delivered to the electronic system.
The usual analog video art requires that two discrete approximations be made to present an approxima-tion to a natural scene. The scene is composed of a ; sequence of discrete frames and each frame is composed first of a sequence of discrete scan lines. As the scan lines are traversed in sequence, the time-varying video signal is a representation of the luminance of the corresponding point in the scan. The justification for the discrete frames is the unconscious reconstruction of motion by the human observer and the justification for ~iscrete scan lines is the limited resolution of the human eye. ~
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For the displa~ o~ di~itally s~nthesized video images such as charactex and graphic displays, two additional discrete approximations are made. Each scan line is composed of a saquence of discrete picture elements (pixels). Each pix81 has a luminance value which in the present invention is approximated by one of a number o discrete values according to a sequence of binary digits~ The justification for the discrete - approximation of the pixeI is the limited resolution of the eye and equates through the sampling theorem to the bandwidth limit in an analog video signal. The justification for the discrete approximation o~ the .. ..
luminance ~alue is the limited ability of the eye to discriminate luminance when a sufficient number of levels of approximation are emplo~ed.
According to these additional approximations, an image may be represented as an array of values, either - discrete or continuous. If these values are extracted ~rom di~ital storage and produced in the order and rate corresponding to the adopted scanning order and rate, these values may be converted to an analog video signal conforming to some adopted standard and the image may be displayed using a standard ~ideo monitor.
In prior art video terminals, the chararter codes to be represented on the display screen are stored in a memory in the order in which they are to be displayed, each code representing a particular character. The code is fetched from the memory in synchronism with the raster scan and causes a character generator to generate the appropriate dot signals during that raster scan as described in the above referenced Cole patent. An ex~mple of the dot matrix type character formed in such J - 7 _ 1, X
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; a system is illustrated in Figure 1. If a standard video monitor is employed,as the displa~ unit, then the video terminal must contain the appropriate charactex store in a video synthesizer outside of the display unit.
As distinct from the dot matrix type o~ character of the prior art, the present invention is adapted to employ the full resolution and gray-scale of the standard video monitor. The synthetic images rapresenting the characters to be displayed are stored outside of the standard video monitor and activate a video synthesi~er ~ to provide the appropriate signals to create an entire - picture of the character durin~ its display. An artistic rendition of a character as displayed by the present invention is illustrated in Fi~ure 2 for comparison with the dot matrix type character o~ Pigure 1.
Before generally describing the system of the , ~ ; present embodiment, the descrip~ion will be provided of the nature of the chaxacter images and how they are form-ed. As was explained above, the present invention utiliz-es the full resolution and gray-scale of a standard video monitor. Thus, the character image display employs all of the picture elements in the particular character space.
In the present invention, eight levels o~ gray-scale are employed correspondlng to eight different levels o~
luminance which eight states can be accomodated by a three-bit number in binary code. In addition, the eight different levels are directly proportional to the luminance to be displayed rather than to the signal oltage, which is nominall~ the 2.2 root of the lumin-i 30 ance. Eight discrete levels were experimently detexmin-¦ ed to be the least power-of-two number of levels suffi-cient to represent characters ~ithout any apparant ,;
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~2~5l3 jag~edness. More or less le~els might be employed de-pending on the ~ualit~ desired, character scale r display device, or other variables.
- Figures 3A and 3B illustrate the manner in which the eight levels of luminance are employed in the present invention to represent a given character, in this case 'IA". The process by which the table of numbers is deriv-ed from the character ima~e can,be mechanized in many ways by optical and electro-optical systems. The simplest method conceptually is to diyitize to eight levels the signal output of a video camera scanning the desired character at the de~ired scale. Unlike the dbt~
matrix character, which is "composed" ag a table of binary values; the fully-foxmed character is a stored image of a s~m~ol composed without re~erence to the underlying grid ~- of picture elemPnts. A fully-formed character font may either be designed or any existing printing or typewriter font may be employed. The individual characters are each captured and processed to form representations such as that ` 20 of Figure 3B.
Optimum results can ~e achieved only with great difficulty by digitizing the output of a video camera, because no camera has an ideal physical aperture. I~ the spot size of the camera i5 too small compared to the scan line spacing, the video image will contain higher spatial frequencies than sam~ling considerations allow. Convers-ely, if the spot ~ize of the camera is too large, the e~fecti~e aperture is non-isotropic depending on scanning direction, and the video image will be at too low a resolution~
In the present embodiment, the procedure employed is one in which the image of a character is captured ~, _ g _ z~
at approximatel~ ten times the resolution at which it~
` will appear on the video display, and this high resolution image is pro~essed digitally in orde~",,to simulate the e~ec~ o~ an ideal scanning aperture. Because the aper-ture itself is a spatial ~ilter, the process of computing ' ~he luminance values to represent the character image limits the spatial frequencies approximately to those limits required by the sampling, theorem. The proper luminance value for each picture alement is computed by weighing luminance contributions ~rom an area centered on - the picture element. The weig~ y function is exactly like a physical aperture. The weighted sum of the lumin-ance contributions from the area centered on'the picture element whose value is to be determined is rounded to ~ - ei~ht ~or some chosen number of) levels.
,' ~here are many choices of a weighing ~unction, or '~ aperture, that will produce satisfactory results. A
function that is unity within the picture element area, -I d by d, and ~ero el~ewhere, is the simplest weighing ~unction from the computational standpoint. Somewhat better results can be achieved by using a triangular 'weighingfunction with a base of 2d, which is equivalent to convolving the picture element aperture with itself.
; ~Other possibilities will occur to those skillad in the ar~ . The dlsplayed image shown in Figure 3B subtends 7 scan lines with eight gray levels, and the stored image was derived ~rom a computation based on the picture element aperture~
Tha images produced on a video monitor by the ~ 30 s~nthetic video signal derived ~rom such stored character - ima~es are technically indistinguishable ~rom those that would be produced by an ideal video camera pointed at a ~ 1 0 ~. X
page of text. ~cco~dingly, the video medium is used as it was intended to ~e used, and "flickerl' due to excess-i~e c~ntrast edges ~ith the interlaced display is absent.
The CRT spot o~ the video monitor employed is a physical aperture who~e size and shape determine a spatial filter exactly like the abstract apertures used to compute luminances~ In practice, the spot is not exactly uniform at all point~ in the raster, bu~ ~he spot size can be -` adjusted generally to minimize the scan line texture, and this adjustment produces a suitablè aperture ~or construct-in~ the im~ge from sampled data ~icture elements. It is ~n economically important property of the fully-formed symbol technique that the very small and consistent spot i size sought for dot-matxix characters is neither necess-ary nor desirable. A spot in which about 75% of the - -energ~ emits from a region of dlameter d is easily achiev~
ed in commercial video monitors and close to ideal for ` the application of the present invention.
The organization of a system employing the present em~odiment is illustrated in Figure 4~ As shown therein, stored information structures are fetched from informa-tion storage 10 by character display processor 11 which basically controls the communication between storage 10 and the display system of the present invention. Charac-ter codes are transferred to character ~uffer 12 for ~easons that ~ill be more thoroughly described below.
Char~cter codes then drive character generator 13 in - ~hich are stored the character font signals. These character font signals are mixed by ~ideo synthesizer 3b 14 with other signals such as synchronization signals to pro~ide the composite video signals supplied to standard video monitor 15. Image display processor 16 and image 2~51!~
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- buffer 17 are ~rovided in pa~allel with character display processor 11 and chaxact~r buffer 1~ when it is desired ~o superimpose character text upon some'other image.
Thus, the system of Fi~ure 4 accomodates modular inclu-sion o~ additional ~acilities as dictated by any specific application.
~ideo monitox 15 is the transducer which conver s a composite video signal to an image that can be viewed.
Becau~e the composite video signal corlorms to some standard, other ~ideo devices and systems may be used in conjunction wlth this signal such as video tape to store the signal, cable tele~ision or a transmitter or tele-` ~ision receiver to conve~ the image to another location ; and various video devices to process the signal.
Video synthesizer 14 is a s~mpled data signal s~nthesizer ~hich converts and combines the digital image specification and synchronizin~ signals to the single composite ~ideo signal. This hybrid digital-analog ; ' system operates ~rom a clock and system timing unit 18 which clock corresponds to the picture element rate that in the present in~ention is 12.3 MHz. The derivation of the timing signals are mo~e thoroughly described ~elow.
The cycle time o~ ~ideo synthesizer,l4 which in the present invention is 81 nanoseconds r places a practical limit on the complexity of the functions that can be per~ormed even though relatively high-speed logic is employed. Howe~er, the image combining operations in various modes and output conversion are pipe-lined through a series ofintermediate registers containing - ~ 30 partial results so that a ~ery high data thxoughput is mai-ntained. Because the timing cycle is typically too small for the sources of image point data, the data is -j - 12 ~
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- ` typically provided ~ith a number of image points in p~rallel and parallel to serial conversion is performed pxior to interfacing ~ith ~ideo synthesizer 14.
The character generatox 13 contains the stored image of each character that may be displayed4 It is particular ly effecti~e to oxganize this storage so that the image points across the scan lines ara read in parallel, select-ed by the character code and vertical position information, and converted to serial ~orm for ir1put to video synthesi-zer 14. Either fixed or variable horizontal pitch charac-ters may be employed.
Character buffer 12 al1Ows the lowest data rate from the processox and consists of two or more inter-changeable shit register t~pe buffers in which the dis-pla~ is refreshed from one bufXer ~hil the processor fills another buffer ~ith the next character line. ~ach shift Legister t~pe buffer contains character code and po~sibly some disp1ay mode information. ~he r9fresh ~rocess general1y re~u1res multiple cycles through the bu~fer corresponding to the multiple sequenti~l scan lines for each char~cter line. The loading of the next buf~:er shift register should be complete by the time the display of the character line is complete so that the control of the respective shift register buffer may be switched.
Character displa~ pxocessor ll is a micro-processor~
based system whose primary role is to move ~ext strin~s from the stored in~ormation structure of storage lO to character ~uffer L2, In the implementation of the present system, display processor ll is a programmable device which, by its power tG compute and axt.ract infor-mation from a complex information structure, assists in the formatiny of the text display and provides character l3 X
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line parametexs such as the hei~ht and origin position of the character line, a mask that is useful in scrolling text smoothly, mode infoxmation, blink information and the control of the vertical synchronization.
As was indicated above, the digital video charact-ers generated by the character display processor 11, character buffer 12 and character generator 13 may be combined in video synthesizer 14 with other digital video images. Tha general combining rule allows ormating of the full~screen display either ~y text codes which key other ~ideo sources ox b~ luminance codes which cause - character or symbol display to be overlayed or superim-posed~
Some o~ the charactexistiGs of the system of Figure 4 and ~ariations therein will now be discussed. Since the video medium must be refreshed at its characteristic field and frame rate, and in raster order, the~system m~st produce the image repetitively and in raster order.
The repetitions required to refresh the display are to ~0 be at least partly independent so that changes in the infoxmation structure will be reflected immediately in the displayed image. One o the bene~its of such a dis~
play system as opposed to hard copy is the ability to change the display in accordance with the users interact-ion.
I~ all o~ the display information is not extracted ~rom the information structure on each frame or field, the refresh function occurs from character buffer 12/
~or image buffer 17 as the case may be). In this situa-- , 30 tion, it is not important whether informatio~ is provided XrQm display processor 11 in xaster order as buffer 12 ser~es also to implement a scan conversion function.
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~ `2~S8 This ~ariation re~uixes a large buffer, nominally in which each buffer location corxesponds to a character location or to a picture element, which bu~fer can be modified selectively.
If all of the display infoxmation is extracted from the inormation s~ructure on each frame or field, the re~resh operation may be regarded as occurring direct-ly from the information str~cture. If the information . .
provided from the display processor 11 from the informa-10 . tion structure is necessari~y uncorrelated from raster order, buffer 12 may be used to perform a scan conversion process~ If the information provided from the display processor 11 from the information structure is even approximately in xaster order, buffer 12 need only be a small buffer whose size depends on the most out-of-raster-order elements:and speed ma~ching considerations~
Certain types~o displays o~ characters and symbols have very wide application an~ can be accomodated by . raster order production, so lon~ as the character codes 20 axe provided from display processor 11 in the order in which the characters first appear in the raster. In this case, buffer 12 ~lill store character codes in order to repeat the character seguence across the multiple scan lines that subtend each character line. An alternative is to fetch the text sequence from the information structure repetitively.
Character and symbol display are of such wide :. ~ applicabilit~ as to be required for almost any system display. For example, a system for banking applications might well include sp~cial facilities for displaying facsimiles o~ ~inancial documents, signatures f or the like; but would cextainly require character display ox ., , . I .
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the contxol information related to a transaction. Simi-larly, engineering applications may require stylized dra~ings to be displayed, that will certainly require character display ~or legends.
DETAILED DESCRIPTION OF TE~E SYSTEM
Yideo synthesizer 14 of Figure 4 is illustrated in Figure 5 and includes display mode transform logic 20 which receives charactex data a,s well as ~he character mode signal and cursor signal ~or combination with othex image data, which ombined data is then transferrPd to digital-to~video con~erter 21 ~hich converts the data to the analog video signal in combination with the composite sync and composite blanking signals in order to produce the composite video signalO The monochrome composite ~ideo signal produc d thexeby may be optionally combined ; . :
~; at output summing~ampliier 22 with a chroma signal as will be more thoroughly explained below~ Thè synthesizer ~ust operate entirely at the pixel clock rate with new data ~ppearing at each clock cycle. However, this data is irrelevant during blanking periods. Data input appears one clock time eaxly in order to allow ~ox pipelining.
Display mode transform logia 20 of Figure S is illustrated in Figure 6 and includes read~only storage 23 that is addressed by the incorning character data, optional irnage data, mode signals and cursor. Read-only storage 23 ser~es to perform the various functions by mapping tha ~-bit character data to the 4-bit output data i in the various ways required. Thus, characters may be ; displayed in different display rnodes according to user j 30 preference or to highlight an area of particular interest.
Text displays also benefit from a cursor which can high-light a character in a text string to indicate visually 16 ~
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- the location of the text editing operation. Typical text modes are: white~on black r black-on-white, half-bright~
; white~on~gray, black~on-gray. For each of these modes it is necessary to have a contrastin~ cursor.
In addition, the text may ~e made to be in~isible in order to hide classifie~ information such as passwords.
- The text may al60 ~e made to blink betwae.n invisible and visib}e to draw attention to a particular item. This is accomplished by the receipt o~ blink ra~e and blink on .signals by AND gate 25 the output of which is supplied along with the in~isible signal to NOR gate 26. The out-put ~rom NOR gate 26 is then "ANDED" with respective character data bits supplied to read only storage 23.
Specifically, the input network consisting of A~D gate 25 and NOR gate 26 treats the various cases o~ invisible ; or blinking characters by orcing the character data in-: put to 000 when approprlate.
~ ~igure 7 is a table o~ some of the various trans-- ~ormations that ma~ be accomplished b~ reading out a portion of the contents o~ read only storage 23 of Figure 6. In this table, ].5 output levels ~0-14~ are used in order to have a middle le~el of 7. The ef~ect of the - ~ trans~ormation is to sc~le the character data by either ~2, -1, +1, or ~2 and to offset ito This is done in order to perform the trans~ormations readily and to use th~ same character data to display llght-on-dark as dark-on-light which requires that the internal representation as read out of read-only storage 23 be linear to the luminance required rather than its 2~2 root and the digit-al to~video co~erter thus must perform the yamma correc-tion O
By use o read~onl~ storage 23l the display mode - ~ 17 ~
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trans~orm logic o~ Figure 6 pxovides for any transforma-tion desired. It may also ~e used to mix digi~al video si~nals from diferent sources. For example, in one mode, characters can be o~erlayed in white on an image back-ground. For each luminance valu~ of the image, the char-acter value is linearly scaled to the proportionate lum-inance between the image luminance and the brightest value.
Similarly, mode information can~be used to key the image, or particular images values can be used to key to text thus giving complete and general contxol o~er the ~ull screening formatin~.
The output signals.of read~out storage 23 are then supplied to register 24 from which they are then clocked at the next pix~l clock time to the digital-to-video con~erter. ~ ~
The digital~to~iaeo converter 21 of Figure 4 is , illustrated in more detail in Figure 8. This converter is a digital-to-analog converter which must be ~ast enough to operate at the pixel clock rate and also to have a non-linear output in order to correct for the video gamma when the data represents luminance rather than the output Yolta~e. Furthermore, its output must be free of switching transients which are inevitable in the ladder network type digital-to-analog converter. These transi-ents would typically occur in the transition from values such as 0111 to lO00 in which case the signals driving - the resistive conversion network are changing in di~ferent dir~ctions and at slightly different times.
; The binary input signals recei~ed from the trans-~orm logic o Figure 6 are converted through a combina-tional mapping implemented in read only storage 27 to a unary or monadic opera~ion code. This mapping con~erts ~ ~Z4~i~
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four input signals to 15 dif~erent outputs in the follow-ing manner7 The input 0000 produces an output of all - zeros~ The input 0001 causes just the first o the fif~
teen outputs to become 1. The input 0010 causes the first two o~ the fifteen outputs to ~ecome 1, and so on until the input 1111 causes all fl~tePn output to be 1. This code has the property that the transition between any two inpu~ combinations can only cau'se a group o~ adjac~nt outputs to change in ~he same direction, Thus, when these outputs are weighted and summed through resistive network, after being reclocked, the analog output changes monotonically ~rom one ~alue to another without switching transients.
-~ The resistance net~ork is illustrated in Figure 8 - as being ~ormed of the plurality of resistors 29 which are of appropriately var~ing resistance values. The 16 output levels produced thereby are spaced ~y 15 steps, ; and the conductances of each of the fifteen weightingresistors 29 is proportional to the size of that step. If all of the conductance ~ere the same, the output would be linear with the data input. ~owever, any positi~e mono-tonic non-linear function can be produced just as easily by making each conductance proportional to the correspon-ing step size. Thus, the resistance ~alues may be calcu-lated to achiev coxr~ction ~or~whatever Yalue of gamma - is expectedO As has been indicated above, the voltage xepresentation of luminance in a video signal is not linear. Instead, according to U.S~ Standards, luminance is approximately the 2.2 power of the voltageO Conversely, the voltage is approximately 1/2.2 power ~2.2 root~ o~
the luminance. In Figure 8, the values o~ the respected resistances 29 are calculated accordingly. The values V` 19 -,X
z~
of the respective resistances are as ~ollowsO
. Bit position 1 - 4~5 ohms Bit position 2 - 9S3 ohms Bit position 3 ~ 1180 ohms . Bit position 4 - 1330 ohms Bit position 5 ~ 1500 ohms Bit position 6 ~ 1620 ohms Bit position 7 ~ 1740 ohms Bit position 8 - 1870 ohms E3it pOSitiQn 9 - 1960 ohms Bit position 10 - 2050 ohms Bit position 11 - 2150 ohms Bit position 12 - 2210 ohms Bit position 13 ~ 2260 ohms Bit position I4 - 2370 ohms ~` : Bit position 15 ~ 2430 ohms These values wer~ calculated with the g~ounded load resistance being 51.1 ohms. The composite sync resistance .~ is 221 ohms and the composite blank resistance is 1210 . 20 ohms. These values were calculated for a voltage output ranging Erom a minimum from 0.8 volts to 2 volts. Ths 15 resistances provided 15 intervals between 16 output signals ranging from 0 volts to 2 volts.
The ad~antages o~ ha~ing Yoltage output as the 2.2 root of luminance is that it allows the transmitter to compensate for a non-linearlty inherit in the receiver ; monitorO Secondly, the root functionr being a good approximation o~ the logarithmic r~sponse of tha eye, has the advantage that noise o~ parkicular amplitude has approximately the same subjective effect when superimpos~
l ed on dark and light areas. If a linear relationship : . ' existed betwe~n luminance and ~oltage, noise voltage ~ 20 ~
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:
5i3 ; would be more e~ident in the dark displa~ than in the light areas of the image. This technigue also gxeatly simplifies the computational transformation in regard to scaling, rotation, and arbitrary positioning o~ synthetic ~igu~es.
Another ad~antage o~ this type of con~erter resist-ance values i5 that the resis~ance ~alues need only be as precise as the steps size dlctates. Typically 5~ resist~
ance tolerances will be more than adequate. The switches likewise need not be particularly precise. In fact, the flip flop outputs of register 28 will generally serve as ~oltage sour~es to drive the weighting and summing net-works. Accordingly, the converter is easily made fast.
In general, the conversion techniques discussed above uses more components than the laddsr network type of converter. Ho~ever, components of much lower preci-- sion can be emplo~ed and the present con~ersion technique is well suited for int graked circuit implementation.
The composite s~nc and blanking signals are weighted into the summing net~ork in the same way as the data. In addition, the presence o~ the blanking signal gates the data input to O in order to reject any spurious informa-- tion on the data input during blanking periods.
Character generator 13 of Figure 4 is illustrated in more detail in Figure 9. This generator includes~ ~or illustration, from 1 to 8 ~ont storage elements 30 where each storage element stores the image of 32 characters or a total o 256 possible cnaracters. The generator ~lso includes decoder 31 to select one font storage element according to the incoming character code and control el~ment 32 that will be more thoroughl~ described below.
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The various font storage elements 30 of Figur~ 9 axe shown in more detail in Fi~ure 10. A digital video .` character is produced on character data ~us 41 in response to the receipt o~ the chaxacter code and vertical position aata. This in~ormation together forms the address to the respective xead-only storage elements 33. The image data for each character has been computed by techniques explain-ed abo~e and this data stored in the three similar read-; only storage sections 33 b~ khe usual mask process. It will be u~derstood that read-write storages may b~ employ-ed with pro~ision ~or lo~ding the contents from the char-acter dispLay pro~essor of Figure 4. When a load signal is produced by ~ND gate 39 of Figure 10, the data from i respective read-only storage elements 33 are trans~erred synchronously into their corresponding shift reg1ste~rs 34 rom where they are read out in~a seria1 digital video data sequence to the ~ideo synthesizer 14 of Figure 4 as :
~ was described above.
. .
The appearance o~ a start signal to an enabled storage element also sets the internal selèct flip flop 37 and the storage element will remain selected until -. another start signal is received with ena~le logical zero.
The signal input to the parallel to serial conversion shift registers 34 lS a logical zero and the selected . ~ storage element will simply output zeros to the charac-ter data bus 41 afte~ the prescribe~ number of picture elements have been produced from the corresponding . ~ storage element. In addLtion, the control may disable ; the output at times in oraer to o~erla~ an underline, crossout text, or cursor s~mbol.
; For variable - pitch characters, it is most natural to store the character width in the same element as the ~ 22 -~ Z~5~
- ~ - character image. ~or ~ariable pitch character~, optional read-only ~torage element 35 may ~e employed which contains 32 four-~it words which are masked to contain the charac-ter width as a prescri~ed number of picture elements. In this case, when an ena~led alement is started, the width of the selected character is transferred synchronously into a binary down counter 36 and the underflow signal ~rom this counter is gated onto a bus line which returnstothe control to indica~e the completion o the current characters.
~ontrol element 32 of Figure 9 is illustrated in more detail in Figure Il. The control element receives the parameters required to control such features as verti-cal format slow scrolling, underlining, or crossout text To this end, initial position and count parameters are recei~ed respectively by counting registers 42 and 43.
Mask counter 44 receives the mask parametex. These regis-ters are driven by a systems clock. The function o~ these parameters w~ e more thoroughly described below~ In addition, the control element is proYided with a decoder read-only store 48 which contains the data for underlining such as required. The last line and ~ield parameters from miscellaneous register 45 are used to control vertical sync counter 46 that drives decoder read-only store 47 to supp-ly a vertical sync and vertical blinking signals.
Slow scrolling, positioning and spacing of the text within any scan line pair will now be described. The stvred image is placed within a larger address space as illustrated graphically in Figure 12. Th~ addresses are allowed to "wrap around", i.e., modulus 2S6. For this
The most impo~tant reason why designers have a~oided the standard ~roadcast type o video raster i5 that`it is interlaced. B~ producing the complete frame with two interlaced ~ield~, broadcast ~ideo achieves twice the vertica]. resoLution than can be achieved at I that scan rate without interlace. However, dot-matrix charac~ers appear to "~licker" when interlaced fields are used, particularl~ if the great majority o dots o~er any local region happen to fall within on~ or the other ~.ield. Flicker is a problem when interlace is employed not only for dot-matrix charactels but also when there are ~ery high contrast images. Thus, even uhen a standard ~ideo mOnitor is employed as the display de~ice for a ~ideo terminal, it is used without inter-lace and is limited in its ~ertical resolution. Be-. ~ , cause this resoIution is inadequate to display a large number of good quality dot-matrix characters, some , systems must employ ~ideo rasters which are incompatible with ~tandard ~ideo monitors. It is desirable to employ standard video monitors because o their economy due to mass production.
Such dot-matrix raster scan video displays are disclosed for example in U.S. Patent No. 3,345,458 (October 3t 1967 ~ D.A Cole et al~ ~owe~er, the concept o~ dot-matrix character generation for video display goes bac~ to 1948 as evidence by the U.S. Patent 2,972,016 t~ebruary 14, 1961 - Gerald Dirks).
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It is, then, an object of the present invention to provide in at least olle embodiment a digital video display system which provides more natural display of charact~rs and other information.
It is ano~ler object o~ the present invention to provide in at least one e ~ociiment a digital video disL~lay syst:m having interlaced scan for higher resolution but whicl display is "flickerl' free.
It is still another object of ~he present invention to provide in at least one embodiment a video digital display sys~em that can employ standard commercial video monit~rs.
Accordingly, the present invention provides a vid~o synt~lesi2er for a digital video display system, said video syn~lesizer comprising: a summing network to provide in sequence a plurality of different voltage levels which levels ~ are selected from three or more such levels to designate ; different luminance values to be displayed, said su.~ning network having a pluralit~ of different input leads, said summlng network including a plurality of resistances coupled between said respective input leads and a common connection, said resistances having dif~erent resistance values to provide to said co.~non connection different - ~ voltage levels which increase proportionately to a root of the luminance to be displayed; a storage device having a plurality o~ output leads coupled to respective ones of said summing network input leads, said storage device stoxing different monadic operation codes to activate di~ferenl . . .
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combinations of said input leads, and means coupled to said - storage device to transmit a binary code to said stora~e device which blnary code desi~nates a monadic operation code to select the particular luminance to be displayed.
: An embodiment of the pr~QsQnt invention will no~ be described, by way of example, \lith reference to the accompa-nying drawings in which:-Figure 1 is a representation of a ~o~-matri~ character as em~loyed in the prior art;
Figure 2 is a representation of a character imaye as emplo~ed in the present embodi.ment;
- - . .'~igures 3A and 3B are representaticns of the transfor-mation of luminance values as employed in the present ~ . embodJ' ment;
-` E~igure 4 is a diagram of a system employiny the present .`~. embodiment;
.. ~ . .
Figure S is a diagram of the video synthesizer of the ~ present embodiment;
.. ~ Figure 6 is a diagram o the display mode transform logic of the present embodiment;
Figure 7 is an example of character data mapping as employed ln the present embodiment;
Figure ~ is a diagram of the digital-to-~ideo convertor of the present embodiment;
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-: Figure 9 is a diagram o~ the character generator of the present em~odiment;
Figure 10 is a diagxam o a front storage element asemployed in the present embodimen~;
Figure 11 is a diagram of the control element logic of the present embodiment;
Figure 12 is a representation of ~he "character wheel" of the present embocliment; and ~ igure 13 is a schematic diagram of the timing system of the present embodiment.
GENERAL DESCRIPTION O~ THE SYSTEM
~ or video repr sentation o~ an imaye, a signal must - ~ be provided which producës on a video monitor an approx-imation of that image which is close enough to what is perceived by the human eye. A video camera will convert - the image to à signal for the display of natural scenes For synthetic images, suc~ as character or graphic dis-- ~ plays, a synthetic video signal is produced electroni cally according to information stored within or delivered to the electronic system.
The usual analog video art requires that two discrete approximations be made to present an approxima-tion to a natural scene. The scene is composed of a ; sequence of discrete frames and each frame is composed first of a sequence of discrete scan lines. As the scan lines are traversed in sequence, the time-varying video signal is a representation of the luminance of the corresponding point in the scan. The justification for the discrete frames is the unconscious reconstruction of motion by the human observer and the justification for ~iscrete scan lines is the limited resolution of the human eye. ~
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For the displa~ o~ di~itally s~nthesized video images such as charactex and graphic displays, two additional discrete approximations are made. Each scan line is composed of a saquence of discrete picture elements (pixels). Each pix81 has a luminance value which in the present invention is approximated by one of a number o discrete values according to a sequence of binary digits~ The justification for the discrete - approximation of the pixeI is the limited resolution of the eye and equates through the sampling theorem to the bandwidth limit in an analog video signal. The justification for the discrete approximation o~ the .. ..
luminance ~alue is the limited ability of the eye to discriminate luminance when a sufficient number of levels of approximation are emplo~ed.
According to these additional approximations, an image may be represented as an array of values, either - discrete or continuous. If these values are extracted ~rom di~ital storage and produced in the order and rate corresponding to the adopted scanning order and rate, these values may be converted to an analog video signal conforming to some adopted standard and the image may be displayed using a standard ~ideo monitor.
In prior art video terminals, the chararter codes to be represented on the display screen are stored in a memory in the order in which they are to be displayed, each code representing a particular character. The code is fetched from the memory in synchronism with the raster scan and causes a character generator to generate the appropriate dot signals during that raster scan as described in the above referenced Cole patent. An ex~mple of the dot matrix type character formed in such J - 7 _ 1, X
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.
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; a system is illustrated in Figure 1. If a standard video monitor is employed,as the displa~ unit, then the video terminal must contain the appropriate charactex store in a video synthesizer outside of the display unit.
As distinct from the dot matrix type o~ character of the prior art, the present invention is adapted to employ the full resolution and gray-scale of the standard video monitor. The synthetic images rapresenting the characters to be displayed are stored outside of the standard video monitor and activate a video synthesi~er ~ to provide the appropriate signals to create an entire - picture of the character durin~ its display. An artistic rendition of a character as displayed by the present invention is illustrated in Fi~ure 2 for comparison with the dot matrix type character o~ Pigure 1.
Before generally describing the system of the , ~ ; present embodiment, the descrip~ion will be provided of the nature of the chaxacter images and how they are form-ed. As was explained above, the present invention utiliz-es the full resolution and gray-scale of a standard video monitor. Thus, the character image display employs all of the picture elements in the particular character space.
In the present invention, eight levels o~ gray-scale are employed correspondlng to eight different levels o~
luminance which eight states can be accomodated by a three-bit number in binary code. In addition, the eight different levels are directly proportional to the luminance to be displayed rather than to the signal oltage, which is nominall~ the 2.2 root of the lumin-i 30 ance. Eight discrete levels were experimently detexmin-¦ ed to be the least power-of-two number of levels suffi-cient to represent characters ~ithout any apparant ,;
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~2~5l3 jag~edness. More or less le~els might be employed de-pending on the ~ualit~ desired, character scale r display device, or other variables.
- Figures 3A and 3B illustrate the manner in which the eight levels of luminance are employed in the present invention to represent a given character, in this case 'IA". The process by which the table of numbers is deriv-ed from the character ima~e can,be mechanized in many ways by optical and electro-optical systems. The simplest method conceptually is to diyitize to eight levels the signal output of a video camera scanning the desired character at the de~ired scale. Unlike the dbt~
matrix character, which is "composed" ag a table of binary values; the fully-foxmed character is a stored image of a s~m~ol composed without re~erence to the underlying grid ~- of picture elemPnts. A fully-formed character font may either be designed or any existing printing or typewriter font may be employed. The individual characters are each captured and processed to form representations such as that ` 20 of Figure 3B.
Optimum results can ~e achieved only with great difficulty by digitizing the output of a video camera, because no camera has an ideal physical aperture. I~ the spot size of the camera i5 too small compared to the scan line spacing, the video image will contain higher spatial frequencies than sam~ling considerations allow. Convers-ely, if the spot ~ize of the camera is too large, the e~fecti~e aperture is non-isotropic depending on scanning direction, and the video image will be at too low a resolution~
In the present embodiment, the procedure employed is one in which the image of a character is captured ~, _ g _ z~
at approximatel~ ten times the resolution at which it~
` will appear on the video display, and this high resolution image is pro~essed digitally in orde~",,to simulate the e~ec~ o~ an ideal scanning aperture. Because the aper-ture itself is a spatial ~ilter, the process of computing ' ~he luminance values to represent the character image limits the spatial frequencies approximately to those limits required by the sampling, theorem. The proper luminance value for each picture alement is computed by weighing luminance contributions ~rom an area centered on - the picture element. The weig~ y function is exactly like a physical aperture. The weighted sum of the lumin-ance contributions from the area centered on'the picture element whose value is to be determined is rounded to ~ - ei~ht ~or some chosen number of) levels.
,' ~here are many choices of a weighing ~unction, or '~ aperture, that will produce satisfactory results. A
function that is unity within the picture element area, -I d by d, and ~ero el~ewhere, is the simplest weighing ~unction from the computational standpoint. Somewhat better results can be achieved by using a triangular 'weighingfunction with a base of 2d, which is equivalent to convolving the picture element aperture with itself.
; ~Other possibilities will occur to those skillad in the ar~ . The dlsplayed image shown in Figure 3B subtends 7 scan lines with eight gray levels, and the stored image was derived ~rom a computation based on the picture element aperture~
Tha images produced on a video monitor by the ~ 30 s~nthetic video signal derived ~rom such stored character - ima~es are technically indistinguishable ~rom those that would be produced by an ideal video camera pointed at a ~ 1 0 ~. X
page of text. ~cco~dingly, the video medium is used as it was intended to ~e used, and "flickerl' due to excess-i~e c~ntrast edges ~ith the interlaced display is absent.
The CRT spot o~ the video monitor employed is a physical aperture who~e size and shape determine a spatial filter exactly like the abstract apertures used to compute luminances~ In practice, the spot is not exactly uniform at all point~ in the raster, bu~ ~he spot size can be -` adjusted generally to minimize the scan line texture, and this adjustment produces a suitablè aperture ~or construct-in~ the im~ge from sampled data ~icture elements. It is ~n economically important property of the fully-formed symbol technique that the very small and consistent spot i size sought for dot-matxix characters is neither necess-ary nor desirable. A spot in which about 75% of the - -energ~ emits from a region of dlameter d is easily achiev~
ed in commercial video monitors and close to ideal for ` the application of the present invention.
The organization of a system employing the present em~odiment is illustrated in Figure 4~ As shown therein, stored information structures are fetched from informa-tion storage 10 by character display processor 11 which basically controls the communication between storage 10 and the display system of the present invention. Charac-ter codes are transferred to character ~uffer 12 for ~easons that ~ill be more thoroughly described below.
Char~cter codes then drive character generator 13 in - ~hich are stored the character font signals. These character font signals are mixed by ~ideo synthesizer 3b 14 with other signals such as synchronization signals to pro~ide the composite video signals supplied to standard video monitor 15. Image display processor 16 and image 2~51!~
. .
- buffer 17 are ~rovided in pa~allel with character display processor 11 and chaxact~r buffer 1~ when it is desired ~o superimpose character text upon some'other image.
Thus, the system of Fi~ure 4 accomodates modular inclu-sion o~ additional ~acilities as dictated by any specific application.
~ideo monitox 15 is the transducer which conver s a composite video signal to an image that can be viewed.
Becau~e the composite video signal corlorms to some standard, other ~ideo devices and systems may be used in conjunction wlth this signal such as video tape to store the signal, cable tele~ision or a transmitter or tele-` ~ision receiver to conve~ the image to another location ; and various video devices to process the signal.
Video synthesizer 14 is a s~mpled data signal s~nthesizer ~hich converts and combines the digital image specification and synchronizin~ signals to the single composite ~ideo signal. This hybrid digital-analog ; ' system operates ~rom a clock and system timing unit 18 which clock corresponds to the picture element rate that in the present in~ention is 12.3 MHz. The derivation of the timing signals are mo~e thoroughly described ~elow.
The cycle time o~ ~ideo synthesizer,l4 which in the present invention is 81 nanoseconds r places a practical limit on the complexity of the functions that can be per~ormed even though relatively high-speed logic is employed. Howe~er, the image combining operations in various modes and output conversion are pipe-lined through a series ofintermediate registers containing - ~ 30 partial results so that a ~ery high data thxoughput is mai-ntained. Because the timing cycle is typically too small for the sources of image point data, the data is -j - 12 ~
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- ` typically provided ~ith a number of image points in p~rallel and parallel to serial conversion is performed pxior to interfacing ~ith ~ideo synthesizer 14.
The character generatox 13 contains the stored image of each character that may be displayed4 It is particular ly effecti~e to oxganize this storage so that the image points across the scan lines ara read in parallel, select-ed by the character code and vertical position information, and converted to serial ~orm for ir1put to video synthesi-zer 14. Either fixed or variable horizontal pitch charac-ters may be employed.
Character buffer 12 al1Ows the lowest data rate from the processox and consists of two or more inter-changeable shit register t~pe buffers in which the dis-pla~ is refreshed from one bufXer ~hil the processor fills another buffer ~ith the next character line. ~ach shift Legister t~pe buffer contains character code and po~sibly some disp1ay mode information. ~he r9fresh ~rocess general1y re~u1res multiple cycles through the bu~fer corresponding to the multiple sequenti~l scan lines for each char~cter line. The loading of the next buf~:er shift register should be complete by the time the display of the character line is complete so that the control of the respective shift register buffer may be switched.
Character displa~ pxocessor ll is a micro-processor~
based system whose primary role is to move ~ext strin~s from the stored in~ormation structure of storage lO to character ~uffer L2, In the implementation of the present system, display processor ll is a programmable device which, by its power tG compute and axt.ract infor-mation from a complex information structure, assists in the formatiny of the text display and provides character l3 X
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line parametexs such as the hei~ht and origin position of the character line, a mask that is useful in scrolling text smoothly, mode infoxmation, blink information and the control of the vertical synchronization.
As was indicated above, the digital video charact-ers generated by the character display processor 11, character buffer 12 and character generator 13 may be combined in video synthesizer 14 with other digital video images. Tha general combining rule allows ormating of the full~screen display either ~y text codes which key other ~ideo sources ox b~ luminance codes which cause - character or symbol display to be overlayed or superim-posed~
Some o~ the charactexistiGs of the system of Figure 4 and ~ariations therein will now be discussed. Since the video medium must be refreshed at its characteristic field and frame rate, and in raster order, the~system m~st produce the image repetitively and in raster order.
The repetitions required to refresh the display are to ~0 be at least partly independent so that changes in the infoxmation structure will be reflected immediately in the displayed image. One o the bene~its of such a dis~
play system as opposed to hard copy is the ability to change the display in accordance with the users interact-ion.
I~ all o~ the display information is not extracted ~rom the information structure on each frame or field, the refresh function occurs from character buffer 12/
~or image buffer 17 as the case may be). In this situa-- , 30 tion, it is not important whether informatio~ is provided XrQm display processor 11 in xaster order as buffer 12 ser~es also to implement a scan conversion function.
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~ `2~S8 This ~ariation re~uixes a large buffer, nominally in which each buffer location corxesponds to a character location or to a picture element, which bu~fer can be modified selectively.
If all of the display infoxmation is extracted from the inormation s~ructure on each frame or field, the re~resh operation may be regarded as occurring direct-ly from the information str~cture. If the information . .
provided from the display processor 11 from the informa-10 . tion structure is necessari~y uncorrelated from raster order, buffer 12 may be used to perform a scan conversion process~ If the information provided from the display processor 11 from the information structure is even approximately in xaster order, buffer 12 need only be a small buffer whose size depends on the most out-of-raster-order elements:and speed ma~ching considerations~
Certain types~o displays o~ characters and symbols have very wide application an~ can be accomodated by . raster order production, so lon~ as the character codes 20 axe provided from display processor 11 in the order in which the characters first appear in the raster. In this case, buffer 12 ~lill store character codes in order to repeat the character seguence across the multiple scan lines that subtend each character line. An alternative is to fetch the text sequence from the information structure repetitively.
Character and symbol display are of such wide :. ~ applicabilit~ as to be required for almost any system display. For example, a system for banking applications might well include sp~cial facilities for displaying facsimiles o~ ~inancial documents, signatures f or the like; but would cextainly require character display ox ., , . I .
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the contxol information related to a transaction. Simi-larly, engineering applications may require stylized dra~ings to be displayed, that will certainly require character display ~or legends.
DETAILED DESCRIPTION OF TE~E SYSTEM
Yideo synthesizer 14 of Figure 4 is illustrated in Figure 5 and includes display mode transform logic 20 which receives charactex data a,s well as ~he character mode signal and cursor signal ~or combination with othex image data, which ombined data is then transferrPd to digital-to~video con~erter 21 ~hich converts the data to the analog video signal in combination with the composite sync and composite blanking signals in order to produce the composite video signalO The monochrome composite ~ideo signal produc d thexeby may be optionally combined ; . :
~; at output summing~ampliier 22 with a chroma signal as will be more thoroughly explained below~ Thè synthesizer ~ust operate entirely at the pixel clock rate with new data ~ppearing at each clock cycle. However, this data is irrelevant during blanking periods. Data input appears one clock time eaxly in order to allow ~ox pipelining.
Display mode transform logia 20 of Figure S is illustrated in Figure 6 and includes read~only storage 23 that is addressed by the incorning character data, optional irnage data, mode signals and cursor. Read-only storage 23 ser~es to perform the various functions by mapping tha ~-bit character data to the 4-bit output data i in the various ways required. Thus, characters may be ; displayed in different display rnodes according to user j 30 preference or to highlight an area of particular interest.
Text displays also benefit from a cursor which can high-light a character in a text string to indicate visually 16 ~
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- the location of the text editing operation. Typical text modes are: white~on black r black-on-white, half-bright~
; white~on~gray, black~on-gray. For each of these modes it is necessary to have a contrastin~ cursor.
In addition, the text may ~e made to be in~isible in order to hide classifie~ information such as passwords.
- The text may al60 ~e made to blink betwae.n invisible and visib}e to draw attention to a particular item. This is accomplished by the receipt o~ blink ra~e and blink on .signals by AND gate 25 the output of which is supplied along with the in~isible signal to NOR gate 26. The out-put ~rom NOR gate 26 is then "ANDED" with respective character data bits supplied to read only storage 23.
Specifically, the input network consisting of A~D gate 25 and NOR gate 26 treats the various cases o~ invisible ; or blinking characters by orcing the character data in-: put to 000 when approprlate.
~ ~igure 7 is a table o~ some of the various trans-- ~ormations that ma~ be accomplished b~ reading out a portion of the contents o~ read only storage 23 of Figure 6. In this table, ].5 output levels ~0-14~ are used in order to have a middle le~el of 7. The ef~ect of the - ~ trans~ormation is to sc~le the character data by either ~2, -1, +1, or ~2 and to offset ito This is done in order to perform the trans~ormations readily and to use th~ same character data to display llght-on-dark as dark-on-light which requires that the internal representation as read out of read-only storage 23 be linear to the luminance required rather than its 2~2 root and the digit-al to~video co~erter thus must perform the yamma correc-tion O
By use o read~onl~ storage 23l the display mode - ~ 17 ~
s~
trans~orm logic o~ Figure 6 pxovides for any transforma-tion desired. It may also ~e used to mix digi~al video si~nals from diferent sources. For example, in one mode, characters can be o~erlayed in white on an image back-ground. For each luminance valu~ of the image, the char-acter value is linearly scaled to the proportionate lum-inance between the image luminance and the brightest value.
Similarly, mode information can~be used to key the image, or particular images values can be used to key to text thus giving complete and general contxol o~er the ~ull screening formatin~.
The output signals.of read~out storage 23 are then supplied to register 24 from which they are then clocked at the next pix~l clock time to the digital-to-video con~erter. ~ ~
The digital~to~iaeo converter 21 of Figure 4 is , illustrated in more detail in Figure 8. This converter is a digital-to-analog converter which must be ~ast enough to operate at the pixel clock rate and also to have a non-linear output in order to correct for the video gamma when the data represents luminance rather than the output Yolta~e. Furthermore, its output must be free of switching transients which are inevitable in the ladder network type digital-to-analog converter. These transi-ents would typically occur in the transition from values such as 0111 to lO00 in which case the signals driving - the resistive conversion network are changing in di~ferent dir~ctions and at slightly different times.
; The binary input signals recei~ed from the trans-~orm logic o Figure 6 are converted through a combina-tional mapping implemented in read only storage 27 to a unary or monadic opera~ion code. This mapping con~erts ~ ~Z4~i~
,:
four input signals to 15 dif~erent outputs in the follow-ing manner7 The input 0000 produces an output of all - zeros~ The input 0001 causes just the first o the fif~
teen outputs to become 1. The input 0010 causes the first two o~ the fifteen outputs to ~ecome 1, and so on until the input 1111 causes all fl~tePn output to be 1. This code has the property that the transition between any two inpu~ combinations can only cau'se a group o~ adjac~nt outputs to change in ~he same direction, Thus, when these outputs are weighted and summed through resistive network, after being reclocked, the analog output changes monotonically ~rom one ~alue to another without switching transients.
-~ The resistance net~ork is illustrated in Figure 8 - as being ~ormed of the plurality of resistors 29 which are of appropriately var~ing resistance values. The 16 output levels produced thereby are spaced ~y 15 steps, ; and the conductances of each of the fifteen weightingresistors 29 is proportional to the size of that step. If all of the conductance ~ere the same, the output would be linear with the data input. ~owever, any positi~e mono-tonic non-linear function can be produced just as easily by making each conductance proportional to the correspon-ing step size. Thus, the resistance ~alues may be calcu-lated to achiev coxr~ction ~or~whatever Yalue of gamma - is expectedO As has been indicated above, the voltage xepresentation of luminance in a video signal is not linear. Instead, according to U.S~ Standards, luminance is approximately the 2.2 power of the voltageO Conversely, the voltage is approximately 1/2.2 power ~2.2 root~ o~
the luminance. In Figure 8, the values o~ the respected resistances 29 are calculated accordingly. The values V` 19 -,X
z~
of the respective resistances are as ~ollowsO
. Bit position 1 - 4~5 ohms Bit position 2 - 9S3 ohms Bit position 3 ~ 1180 ohms . Bit position 4 - 1330 ohms Bit position 5 ~ 1500 ohms Bit position 6 ~ 1620 ohms Bit position 7 ~ 1740 ohms Bit position 8 - 1870 ohms E3it pOSitiQn 9 - 1960 ohms Bit position 10 - 2050 ohms Bit position 11 - 2150 ohms Bit position 12 - 2210 ohms Bit position 13 ~ 2260 ohms Bit position I4 - 2370 ohms ~` : Bit position 15 ~ 2430 ohms These values wer~ calculated with the g~ounded load resistance being 51.1 ohms. The composite sync resistance .~ is 221 ohms and the composite blank resistance is 1210 . 20 ohms. These values were calculated for a voltage output ranging Erom a minimum from 0.8 volts to 2 volts. Ths 15 resistances provided 15 intervals between 16 output signals ranging from 0 volts to 2 volts.
The ad~antages o~ ha~ing Yoltage output as the 2.2 root of luminance is that it allows the transmitter to compensate for a non-linearlty inherit in the receiver ; monitorO Secondly, the root functionr being a good approximation o~ the logarithmic r~sponse of tha eye, has the advantage that noise o~ parkicular amplitude has approximately the same subjective effect when superimpos~
l ed on dark and light areas. If a linear relationship : . ' existed betwe~n luminance and ~oltage, noise voltage ~ 20 ~
pj~
:
5i3 ; would be more e~ident in the dark displa~ than in the light areas of the image. This technigue also gxeatly simplifies the computational transformation in regard to scaling, rotation, and arbitrary positioning o~ synthetic ~igu~es.
Another ad~antage o~ this type of con~erter resist-ance values i5 that the resis~ance ~alues need only be as precise as the steps size dlctates. Typically 5~ resist~
ance tolerances will be more than adequate. The switches likewise need not be particularly precise. In fact, the flip flop outputs of register 28 will generally serve as ~oltage sour~es to drive the weighting and summing net-works. Accordingly, the converter is easily made fast.
In general, the conversion techniques discussed above uses more components than the laddsr network type of converter. Ho~ever, components of much lower preci-- sion can be emplo~ed and the present con~ersion technique is well suited for int graked circuit implementation.
The composite s~nc and blanking signals are weighted into the summing net~ork in the same way as the data. In addition, the presence o~ the blanking signal gates the data input to O in order to reject any spurious informa-- tion on the data input during blanking periods.
Character generator 13 of Figure 4 is illustrated in more detail in Figure 9. This generator includes~ ~or illustration, from 1 to 8 ~ont storage elements 30 where each storage element stores the image of 32 characters or a total o 256 possible cnaracters. The generator ~lso includes decoder 31 to select one font storage element according to the incoming character code and control el~ment 32 that will be more thoroughl~ described below.
, . ..
, ~ 21 ~
X
': ' ; , 1,_., ,,~
.`;
The various font storage elements 30 of Figur~ 9 axe shown in more detail in Fi~ure 10. A digital video .` character is produced on character data ~us 41 in response to the receipt o~ the chaxacter code and vertical position aata. This in~ormation together forms the address to the respective xead-only storage elements 33. The image data for each character has been computed by techniques explain-ed abo~e and this data stored in the three similar read-; only storage sections 33 b~ khe usual mask process. It will be u~derstood that read-write storages may b~ employ-ed with pro~ision ~or lo~ding the contents from the char-acter dispLay pro~essor of Figure 4. When a load signal is produced by ~ND gate 39 of Figure 10, the data from i respective read-only storage elements 33 are trans~erred synchronously into their corresponding shift reg1ste~rs 34 rom where they are read out in~a seria1 digital video data sequence to the ~ideo synthesizer 14 of Figure 4 as :
~ was described above.
. .
The appearance o~ a start signal to an enabled storage element also sets the internal selèct flip flop 37 and the storage element will remain selected until -. another start signal is received with ena~le logical zero.
The signal input to the parallel to serial conversion shift registers 34 lS a logical zero and the selected . ~ storage element will simply output zeros to the charac-ter data bus 41 afte~ the prescribe~ number of picture elements have been produced from the corresponding . ~ storage element. In addLtion, the control may disable ; the output at times in oraer to o~erla~ an underline, crossout text, or cursor s~mbol.
; For variable - pitch characters, it is most natural to store the character width in the same element as the ~ 22 -~ Z~5~
- ~ - character image. ~or ~ariable pitch character~, optional read-only ~torage element 35 may ~e employed which contains 32 four-~it words which are masked to contain the charac-ter width as a prescri~ed number of picture elements. In this case, when an ena~led alement is started, the width of the selected character is transferred synchronously into a binary down counter 36 and the underflow signal ~rom this counter is gated onto a bus line which returnstothe control to indica~e the completion o the current characters.
~ontrol element 32 of Figure 9 is illustrated in more detail in Figure Il. The control element receives the parameters required to control such features as verti-cal format slow scrolling, underlining, or crossout text To this end, initial position and count parameters are recei~ed respectively by counting registers 42 and 43.
Mask counter 44 receives the mask parametex. These regis-ters are driven by a systems clock. The function o~ these parameters w~ e more thoroughly described below~ In addition, the control element is proYided with a decoder read-only store 48 which contains the data for underlining such as required. The last line and ~ield parameters from miscellaneous register 45 are used to control vertical sync counter 46 that drives decoder read-only store 47 to supp-ly a vertical sync and vertical blinking signals.
Slow scrolling, positioning and spacing of the text within any scan line pair will now be described. The stvred image is placed within a larger address space as illustrated graphically in Figure 12. Th~ addresses are allowed to "wrap around", i.e., modulus 2S6. For this
3~ reason, the address space is referred to as the "charac-ter wheel". Because of the interlaced scan, the lowest~
or~er binary digit o~ the address to the character wheel ~i - 23 -~, j¢
qLS8 .
is the signal called FIELD and this indicates whether~
the upper or lower scan line in the address ~can line pair is used for displ~.
The manner in which slo~ scrolling or smooth scroll-ing is achieved ~ill no~ be more specifically described in relation to ~igures ll and 12. The location of the character in the character wheel o~ Fi~ure 12 is defined b~ the three parameters supplied to ~he control element of Figure ll. As indicated abo~e, thase parameters are ,the initlal position, the cQurlt and the mask. ~he~e parameters are loaded inko the respecti~e registers of the control element at the beginning of each character line. By adjusting these parameters, the initial scan lines of the character line can be deleted with the re-maining scan lines ~utomaticaLl~ moving up with addition-al scan lines ~eing added at the ~ottom o~ the character space and the character appears to move up. Similarly the characters can be made to appear to move or scroll downwardly.
The function of the mask parameter is to mask out all portions of the character wheel e~cept that portion being displayed whichl in the case of Figure 12 is each scan line pairs 0-7. Thus, as the character is moved upwardly in the character line, it will appear to dis appear ~ehind the barrier. At the same time, in the previous character linel a different c,haracter wheel employed therefor as defined by its own parameters will give the appearance o~ the character m ving up from behind the barrier. Thus, the character can be made to appear to slowly move upward from character line to character line in a very smooth fashion. Conversel~, the character can be made to appear to move downward in - 2~ -5~
the same slow smooth manner. This is accomplished because position registex 42, count register 43, and mask regist~
er 44 are loaded at the beginning of each character line ~ith the actual loc~tion of the character line being deter-mined by character display p~ocessor 11 of Figure 4 which fetches the respective character codes and their corres-ponding parameters from storage 10 in a continuous manner.
Thus, there is no need to have another counter in the system to count out Yertical synchronization since it is the number of times pex field that the parameter reglsters are loaded that determines how ~any character lines there are plus one more to do the vertical ~ynchronization.
~n Figure 11, mask register 44 need only contain
or~er binary digit o~ the address to the character wheel ~i - 23 -~, j¢
qLS8 .
is the signal called FIELD and this indicates whether~
the upper or lower scan line in the address ~can line pair is used for displ~.
The manner in which slo~ scrolling or smooth scroll-ing is achieved ~ill no~ be more specifically described in relation to ~igures ll and 12. The location of the character in the character wheel o~ Fi~ure 12 is defined b~ the three parameters supplied to ~he control element of Figure ll. As indicated abo~e, thase parameters are ,the initlal position, the cQurlt and the mask. ~he~e parameters are loaded inko the respecti~e registers of the control element at the beginning of each character line. By adjusting these parameters, the initial scan lines of the character line can be deleted with the re-maining scan lines ~utomaticaLl~ moving up with addition-al scan lines ~eing added at the ~ottom o~ the character space and the character appears to move up. Similarly the characters can be made to appear to move or scroll downwardly.
The function of the mask parameter is to mask out all portions of the character wheel e~cept that portion being displayed whichl in the case of Figure 12 is each scan line pairs 0-7. Thus, as the character is moved upwardly in the character line, it will appear to dis appear ~ehind the barrier. At the same time, in the previous character linel a different c,haracter wheel employed therefor as defined by its own parameters will give the appearance o~ the character m ving up from behind the barrier. Thus, the character can be made to appear to slowly move upward from character line to character line in a very smooth fashion. Conversel~, the character can be made to appear to move downward in - 2~ -5~
the same slow smooth manner. This is accomplished because position registex 42, count register 43, and mask regist~
er 44 are loaded at the beginning of each character line ~ith the actual loc~tion of the character line being deter-mined by character display p~ocessor 11 of Figure 4 which fetches the respective character codes and their corres-ponding parameters from storage 10 in a continuous manner.
Thus, there is no need to have another counter in the system to count out Yertical synchronization since it is the number of times pex field that the parameter reglsters are loaded that determines how ~any character lines there are plus one more to do the vertical ~ynchronization.
~n Figure 11, mask register 44 need only contain
4-bits for the indi~idual 15 scan lines of the 8 scan line pairs ~hich make up the character frame. There is ; no harm in the mask parameter being periodic modulus 16.When the high order bit of the mask is zero, it allows the character to be ~isible through the mask. When the high order bit is one~ the ch~racter is invisible as this causes an output disable signal to be generated as indica-:, ~
- ~ ted in Figure 11.
~ Slow, smooth scrolling can be achieved without use; - of the mask register and operation by manipulation only of the initial ~alues of the position and count registers at the first and last character lines in a scrolling segment. Ho~e~er, i~ is possible in this case to dis-play only a single or ~ery small number of scan lines in a contracting character line, and the small numher of scan lines may consume so short a period of time that the ~rocessor may be unable to complete filling the next I character buffer before it is required for display.
Accordingly~ if smooth scrolling is to be performed with-- ~5 -- \
S~
out use of the m~sk ~egister, the character buffer must , have the capacit~ to stoxe three or more character lines, and the processor must be able to replenish this speed-matching ~uf~er mo~e rapidl~ than display depletes the buffer.
As ~as indicated abo~e~ the two fundamental para-meters which control the foxmat o~ the display are the initial position on the character wheel and the count cf the numbex of scan lines to ~e produced. For example, starting at address zero with a count o~ eight scan lines will result in the character lines being spaced verti-cally by their normal mini~um separation analogous to single spacing on a typewriter. Starting at address 252 ~- ~ith a count of 16 display lines, lines 252 through line 11, is similar to double-spaced typing~ Display of lines 254 through line 9 ~ith a cou~* of 12 scan line pairs along the chaxacter ~heel is similar to one-and-one-half ~` spacing on a type~xiter.
- The same functional mechanism is employed to provlde ~ program-controlled vertîcal synchronization. For example, 480 o~ 483 possible visible scan lines for text displa~ might be employed in a format in which 240 scan line pairs are used to produce 30 lines of single spaced text with a count parameter of eight. The vertical synchronization intervals will consist of either 2Z or - 23 scan lines depending upon which field is completed.
' In this vertical synchronization mode, the display is ; blanked ~vertical blanking~ and the vertical synchroni~a-i tion signal charac~eristic of the particular ~ideo stand-ard is produced beginning either one or two half scan lines later depending on the ~ield completed.
This techni~ue avoids the necessity of ha~ing a ~ I
~%4Sl5 .
s~an line counter and ~et allows pro~ram-controlled vertical synchronization to accomodate r with the same instrument, the multiple scan standards employed.
In the operation of the character generator control, the control element receives directly from the display processor, khe initial value and count parameters stored in the respective counting registers 42 and 43 and supp-lies vertical position information to the respective font storage elements 30 of Figure 9~ ControL element 32 ~
that ~igure detects when the character wheel address is within the active segment, nominall~ position 0-7 of the character wheel and initiates each character and advances the character line buf~e~ one position for the next char-acter~ The control element also receives the control bits for FIELD and L~ST LINE which indicates that the next :
haracter line i~ the ~ertical synchronization interval.
When the control element is to perform the under-line function or crossout text ~unction, these functions are produced by decoding the vertical position, disabling ~0 the font storage output and inserting data on the charac-ter data bus. ~ full bxight scan line with half-bright scan lines on either side produces very good underlining ~; ~ or crossout which does not flicker. The respective font storage elements are activated even when their outputs are not used in order to determine the character width in the variable-width case.
The mask parameter supplied to mask counter 44 of ` Figure ll is 4 bits for the scale of characters employed - -' in the present invention. Whenever the high~order bit of thi~ parameter is zero ~the register counts are 0-7~ dis-pla~ occurs as usual. When the hiyh-order bit is one Cthe register contents are 8-15) and the effect is the ~7 -:
` same as if the chaxacter ~heel ~exe in positions 8-255 and ~he displa~ is masked. If t~e mask parameter was the same ~s the four low-order bits of the initial position on the character wheel, the display would not be masked. How-ever~ if the mask paxametex were 12 and the initial posi~
tion were zero, the first four scan lines of the charact-er line display would be masked.
The timin~ system employed in the present inv ntion will now be described which system employs U.S~ broadcast or close-circuit standard ~ideo, the parameters of which are described in the Electronic Industries Association Standards RS-170 and RS-330. The report o the National Television Standards Committee CNTSC1 is the basic stand-ard applicable to color systems used in the United States.
While the present invention is not adapted as a color , . .
; system, the features invol~ed can be emplo~ed in such a~
syst~m.
; ~ Digital systems such as employed with the present - invention can be adapted to different standards by para-- 2~ metric variation without an~ change in the basic structure of the system. Such changes require only variations in such parameters as the modulus of the counter, the funs-tion produced by the combinatorial network and the fre-quency of the particular oscillator. As an example of ~- easily accomodated difference in standards, U.S. standards have 525 scan lines per frame and a~rame rate of 30Hz, ~hile ~he British standards have 625 scan lines per frame and a frame rate of 25 ~z~ This difference is explained by the predominance of 60Hz. A.C. power in the United i 30 States and 50Hz power in England. The number o~ scan lines produced per second ~15,750 in the United S~ates and 15 r 625 in England~ is similàr enough that even the , l 28 -,, ~
\
~24~
: same monltors can o~ten be used with either standard by adjustment onl~ of the ~ertical synchronization a~d si~e.
For the digital production of video signals, the following analysis is provided ~ased on the U.S. Standards.
There are 525 scan lines per ~rame, but which t~pically 483 are visible and the r~maining 42 used or vertical synchroniæation and the required ~ertical retrace time.
The scan linas arehorizontal from left to right and the horizontal~vertical aspect ratio o~ the ~isible image is 4~3. A square geometry coordinate s~stem, in whi.ch the :~ picture elements are spaced horizontally at the same ' pitch as the scan lines are spaced vertically, is desir-able both to equalize horizontal and ~ertical resolution :~ and to simplify digital computation of the coordinate.
- : T~us, the best choice of the number of picture elementsalong each scan line is C4~3~ X 483 - 644 picture elements pex scan line. The acti~e picture information portion of the sean is 33~40ths of the time H allowed for each scan, and the time P ~or each picture element is approximately 1~780ths o~ the scan line time. In the present invention, the picture element oscillator is approximately 12.27 MHZo If optional color timing is provided, the color oscillator ~- ~ is at a frequency of approximately 1~o32MHz~
The system timing generator is illustrated in Figure 13. As sho~n therein, the picture element clock 51 dri~es a 10-b.it binary counter ~2 whose outputs are mapped through : read-only storage device 53. The counter contents 779 t~rough 1023 cause one output o~ the read~only storage device to become a logical one, so that when connected b~ck to the s~nchronous clear input of counter S2, it causes the count o modulus 780. Yarious other conditions in the counting sequence from p~to 779 are mapped through v /\
~2~S~3 .
. .
read-only storage 53 and clocked into register S4 in order to produce timing indications o~ points in the horizontal scan. These include the horizontal synchronization pulse, horizontal blanking to define the active ~ideo area and the color burst gate~ All of these signals are constitu-t8nt5 of the composite video signal. One other signal t~PIX-n~ changes ~rom logical 0 to logical 1 n clock periods be~ore the beginning of the active video period and changes from a logical l to a logical 0 n clock periods before the end of the active video period so as to allow a sufficient number of clock steps in advance to start and stop the flow of digital video information through the sequence of intermediate registers described above in .. . . .
a pipeline fashion. Vertical synchroni2ation, blanking and the active video area are controlled by display pro-, cessor ll of Figure 4, ~he system timing generator of ~; Figure 13 goes no urther than a frequency division to l~H.
Combinatorial mapping is indicated here as implement-ed in a read-only storage device 53. However, a g~te net-work that produces the same set of func~ions of the given input address lines would ser~e as well. For a different ~ideo standard, the structure of Figure 13 would remain the same, except only the oscillator frequency and the contents of read-only storage device 53 would be different.
Also shown in Figure I3 is an optional timing system for a color system. The output of oscillator 55 is divid-- - ed by a modulus-4 Gray code counter 56 and 57 in order to produce a 4-phasa color subcarrier. Division of the out-j 30 put of oscillatox 55 by 7 in divider 58 can be employed to synchronize or lock each sixth cycle of the main picture element oscillator 51.
, ~ 30 -~`Z4S~
E~ILOGUE
A digital video display s~stem has been described whexein the vaxious characters to be displayed are dis~-played in the form o~ images o~ the complete character rather than the standaxd dot~matrix pattern of the prior art. A character generatox in the display system stores signals representing the various characters to be display-ed which are retrie~ed from sto}age in response to a character code~ The signals are in the form of a binary code having a sufficient number o~ bits to represent a different number of levels of gray~scale or lumlnance values or the ~arious picture elements making up the-character image.
The binary codes retriev~d ~rom storage are supp1ied to a ~ideo synthesi~er that generates the video signal to display the character images whlch may be displayed in a number of di~erent modes incIuding white-on-black, black-on-white, black-on-gray, and white-on-gray as well as different combinations of such modes to represent a cursor. The video synthesi er can generate output voltage levels in discrete steps ~or the different~luminances to be employed. The ~oltage output signals differ from level to level in accordance with the 2.2 root of luminance.
The display system is also providsd with a control element that includes position and count registers to specify the initial position of a scan line and the number of scan lines displayed whioh registers are supplied with incoming data to speci~y the position of each character lina so that the position of a character image on display can be adjusted upwardly or downwardly to give the appear-ance of smooth scrolling.
While but one embodiment has been disclosed it will , :J - 31 -. X
s~
~; ~
- be apparent to t~ose skilled in the art that changes and modifications can ~e made therein without depar~ing from the spirit and scope o~ the in~ention as claimed.
. ', .
. . .
.
"~ ,' ' ' 2~
... .
.
! 30 -- 32 ~
, ;i .
'' ~X -
- ~ ted in Figure 11.
~ Slow, smooth scrolling can be achieved without use; - of the mask register and operation by manipulation only of the initial ~alues of the position and count registers at the first and last character lines in a scrolling segment. Ho~e~er, i~ is possible in this case to dis-play only a single or ~ery small number of scan lines in a contracting character line, and the small numher of scan lines may consume so short a period of time that the ~rocessor may be unable to complete filling the next I character buffer before it is required for display.
Accordingly~ if smooth scrolling is to be performed with-- ~5 -- \
S~
out use of the m~sk ~egister, the character buffer must , have the capacit~ to stoxe three or more character lines, and the processor must be able to replenish this speed-matching ~uf~er mo~e rapidl~ than display depletes the buffer.
As ~as indicated abo~e~ the two fundamental para-meters which control the foxmat o~ the display are the initial position on the character wheel and the count cf the numbex of scan lines to ~e produced. For example, starting at address zero with a count o~ eight scan lines will result in the character lines being spaced verti-cally by their normal mini~um separation analogous to single spacing on a typewriter. Starting at address 252 ~- ~ith a count of 16 display lines, lines 252 through line 11, is similar to double-spaced typing~ Display of lines 254 through line 9 ~ith a cou~* of 12 scan line pairs along the chaxacter ~heel is similar to one-and-one-half ~` spacing on a type~xiter.
- The same functional mechanism is employed to provlde ~ program-controlled vertîcal synchronization. For example, 480 o~ 483 possible visible scan lines for text displa~ might be employed in a format in which 240 scan line pairs are used to produce 30 lines of single spaced text with a count parameter of eight. The vertical synchronization intervals will consist of either 2Z or - 23 scan lines depending upon which field is completed.
' In this vertical synchronization mode, the display is ; blanked ~vertical blanking~ and the vertical synchroni~a-i tion signal charac~eristic of the particular ~ideo stand-ard is produced beginning either one or two half scan lines later depending on the ~ield completed.
This techni~ue avoids the necessity of ha~ing a ~ I
~%4Sl5 .
s~an line counter and ~et allows pro~ram-controlled vertical synchronization to accomodate r with the same instrument, the multiple scan standards employed.
In the operation of the character generator control, the control element receives directly from the display processor, khe initial value and count parameters stored in the respective counting registers 42 and 43 and supp-lies vertical position information to the respective font storage elements 30 of Figure 9~ ControL element 32 ~
that ~igure detects when the character wheel address is within the active segment, nominall~ position 0-7 of the character wheel and initiates each character and advances the character line buf~e~ one position for the next char-acter~ The control element also receives the control bits for FIELD and L~ST LINE which indicates that the next :
haracter line i~ the ~ertical synchronization interval.
When the control element is to perform the under-line function or crossout text ~unction, these functions are produced by decoding the vertical position, disabling ~0 the font storage output and inserting data on the charac-ter data bus. ~ full bxight scan line with half-bright scan lines on either side produces very good underlining ~; ~ or crossout which does not flicker. The respective font storage elements are activated even when their outputs are not used in order to determine the character width in the variable-width case.
The mask parameter supplied to mask counter 44 of ` Figure ll is 4 bits for the scale of characters employed - -' in the present invention. Whenever the high~order bit of thi~ parameter is zero ~the register counts are 0-7~ dis-pla~ occurs as usual. When the hiyh-order bit is one Cthe register contents are 8-15) and the effect is the ~7 -:
` same as if the chaxacter ~heel ~exe in positions 8-255 and ~he displa~ is masked. If t~e mask parameter was the same ~s the four low-order bits of the initial position on the character wheel, the display would not be masked. How-ever~ if the mask paxametex were 12 and the initial posi~
tion were zero, the first four scan lines of the charact-er line display would be masked.
The timin~ system employed in the present inv ntion will now be described which system employs U.S~ broadcast or close-circuit standard ~ideo, the parameters of which are described in the Electronic Industries Association Standards RS-170 and RS-330. The report o the National Television Standards Committee CNTSC1 is the basic stand-ard applicable to color systems used in the United States.
While the present invention is not adapted as a color , . .
; system, the features invol~ed can be emplo~ed in such a~
syst~m.
; ~ Digital systems such as employed with the present - invention can be adapted to different standards by para-- 2~ metric variation without an~ change in the basic structure of the system. Such changes require only variations in such parameters as the modulus of the counter, the funs-tion produced by the combinatorial network and the fre-quency of the particular oscillator. As an example of ~- easily accomodated difference in standards, U.S. standards have 525 scan lines per frame and a~rame rate of 30Hz, ~hile ~he British standards have 625 scan lines per frame and a frame rate of 25 ~z~ This difference is explained by the predominance of 60Hz. A.C. power in the United i 30 States and 50Hz power in England. The number o~ scan lines produced per second ~15,750 in the United S~ates and 15 r 625 in England~ is similàr enough that even the , l 28 -,, ~
\
~24~
: same monltors can o~ten be used with either standard by adjustment onl~ of the ~ertical synchronization a~d si~e.
For the digital production of video signals, the following analysis is provided ~ased on the U.S. Standards.
There are 525 scan lines per ~rame, but which t~pically 483 are visible and the r~maining 42 used or vertical synchroniæation and the required ~ertical retrace time.
The scan linas arehorizontal from left to right and the horizontal~vertical aspect ratio o~ the ~isible image is 4~3. A square geometry coordinate s~stem, in whi.ch the :~ picture elements are spaced horizontally at the same ' pitch as the scan lines are spaced vertically, is desir-able both to equalize horizontal and ~ertical resolution :~ and to simplify digital computation of the coordinate.
- : T~us, the best choice of the number of picture elementsalong each scan line is C4~3~ X 483 - 644 picture elements pex scan line. The acti~e picture information portion of the sean is 33~40ths of the time H allowed for each scan, and the time P ~or each picture element is approximately 1~780ths o~ the scan line time. In the present invention, the picture element oscillator is approximately 12.27 MHZo If optional color timing is provided, the color oscillator ~- ~ is at a frequency of approximately 1~o32MHz~
The system timing generator is illustrated in Figure 13. As sho~n therein, the picture element clock 51 dri~es a 10-b.it binary counter ~2 whose outputs are mapped through : read-only storage device 53. The counter contents 779 t~rough 1023 cause one output o~ the read~only storage device to become a logical one, so that when connected b~ck to the s~nchronous clear input of counter S2, it causes the count o modulus 780. Yarious other conditions in the counting sequence from p~to 779 are mapped through v /\
~2~S~3 .
. .
read-only storage 53 and clocked into register S4 in order to produce timing indications o~ points in the horizontal scan. These include the horizontal synchronization pulse, horizontal blanking to define the active ~ideo area and the color burst gate~ All of these signals are constitu-t8nt5 of the composite video signal. One other signal t~PIX-n~ changes ~rom logical 0 to logical 1 n clock periods be~ore the beginning of the active video period and changes from a logical l to a logical 0 n clock periods before the end of the active video period so as to allow a sufficient number of clock steps in advance to start and stop the flow of digital video information through the sequence of intermediate registers described above in .. . . .
a pipeline fashion. Vertical synchroni2ation, blanking and the active video area are controlled by display pro-, cessor ll of Figure 4, ~he system timing generator of ~; Figure 13 goes no urther than a frequency division to l~H.
Combinatorial mapping is indicated here as implement-ed in a read-only storage device 53. However, a g~te net-work that produces the same set of func~ions of the given input address lines would ser~e as well. For a different ~ideo standard, the structure of Figure 13 would remain the same, except only the oscillator frequency and the contents of read-only storage device 53 would be different.
Also shown in Figure I3 is an optional timing system for a color system. The output of oscillator 55 is divid-- - ed by a modulus-4 Gray code counter 56 and 57 in order to produce a 4-phasa color subcarrier. Division of the out-j 30 put of oscillatox 55 by 7 in divider 58 can be employed to synchronize or lock each sixth cycle of the main picture element oscillator 51.
, ~ 30 -~`Z4S~
E~ILOGUE
A digital video display s~stem has been described whexein the vaxious characters to be displayed are dis~-played in the form o~ images o~ the complete character rather than the standaxd dot~matrix pattern of the prior art. A character generatox in the display system stores signals representing the various characters to be display-ed which are retrie~ed from sto}age in response to a character code~ The signals are in the form of a binary code having a sufficient number o~ bits to represent a different number of levels of gray~scale or lumlnance values or the ~arious picture elements making up the-character image.
The binary codes retriev~d ~rom storage are supp1ied to a ~ideo synthesi~er that generates the video signal to display the character images whlch may be displayed in a number of di~erent modes incIuding white-on-black, black-on-white, black-on-gray, and white-on-gray as well as different combinations of such modes to represent a cursor. The video synthesi er can generate output voltage levels in discrete steps ~or the different~luminances to be employed. The ~oltage output signals differ from level to level in accordance with the 2.2 root of luminance.
The display system is also providsd with a control element that includes position and count registers to specify the initial position of a scan line and the number of scan lines displayed whioh registers are supplied with incoming data to speci~y the position of each character lina so that the position of a character image on display can be adjusted upwardly or downwardly to give the appear-ance of smooth scrolling.
While but one embodiment has been disclosed it will , :J - 31 -. X
s~
~; ~
- be apparent to t~ose skilled in the art that changes and modifications can ~e made therein without depar~ing from the spirit and scope o~ the in~ention as claimed.
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Claims (10)
1. A video synthesizer for a digital video display system, said video synthesizer comprising:
a summing network to provide in sequence a plurality of different voltage levels which levels are selected from three or more such levels to designate different luminance values to be displayed, said summing network having a plurality of different input leads, said summing network including a plurality of resistances coupled between said respective input leads and a common connection, said resistances having different resistance values to provide to said common connection different voltage levels which increase proportionately to a root of the luminance to be displayed;
a storage device having a plurality of output leads coupled to respective ones of said summing network input leads, said storage device storing different monadic operation codes to activate different combinations of said input leads, and means coupled to said storage device to transmit a binary code to said storage device which binary code designates a monadic operation code to select the parti-cular luminance to be displayed.
a summing network to provide in sequence a plurality of different voltage levels which levels are selected from three or more such levels to designate different luminance values to be displayed, said summing network having a plurality of different input leads, said summing network including a plurality of resistances coupled between said respective input leads and a common connection, said resistances having different resistance values to provide to said common connection different voltage levels which increase proportionately to a root of the luminance to be displayed;
a storage device having a plurality of output leads coupled to respective ones of said summing network input leads, said storage device storing different monadic operation codes to activate different combinations of said input leads, and means coupled to said storage device to transmit a binary code to said storage device which binary code designates a monadic operation code to select the parti-cular luminance to be displayed.
2. A synthesizer according to Claim 1 wherein:
said summing network includes a plurality of resistances coupled between said respective input leads and a common connection to provide to said common connection different voltage levels which increase pro-portionately to the 2.2 root of luminance to be displayed.
said summing network includes a plurality of resistances coupled between said respective input leads and a common connection to provide to said common connection different voltage levels which increase pro-portionately to the 2.2 root of luminance to be displayed.
3. A synthesizer according to Claim 2 wherein said binary code is transmitted in parallel and has a number of bits which number is the least power of 2 required to represent the different luminance levels to be displayed and wherein:
the number of output leads from said storage device is greater than said least power of 2 so as to allow said binary code to select more than one luminance level to be displayed.
the number of output leads from said storage device is greater than said least power of 2 so as to allow said binary code to select more than one luminance level to be displayed.
4. A video synthesizer according to Claim 1 further including:
composite blank means coupled to said storage device to cause the output therefrom to be all zeros even though different binary codes are presented thereto.
composite blank means coupled to said storage device to cause the output therefrom to be all zeros even though different binary codes are presented thereto.
5. A video synthesizer according to Claim 1 further including:
a register coupled between the output leads of said storage device and the input leads to said summing network to receive said unary code prior to activation of the summing network.
a register coupled between the output leads of said storage device and the input leads to said summing network to receive said unary code prior to activation of the summing network.
6. A video synthesizer according to Claim 5 further including:
clock means coupled to said register to activate said summing network one clock time after receipt of the unary code by said register.
clock means coupled to said register to activate said summing network one clock time after receipt of the unary code by said register.
7. A digital-to-analog converter, said converter comprising:
a summing network to provide in sequence a plurality of different voltage levels which levels are selected from three or more such levels, said summing network having a plurality of different input leads, said summing network including a plurality of resistances coupled between said respective input leads and a common connection, said resistances having different resistance values to provide to said common connection different voltage levels which increase proportionately to a root of equally spaced values, which root is different from 1, rather than to equal differences in voltage levels;
a storage device having a plurality of output leads coupled to respective ones of said summing network input leads, said storage device storing different monadic operation codes to activate different combinations of said input leads; and means coupled to said storage device to transmit a binary code to said storage device which binary code designates a monadic operation code to select a particular voltage level.
a summing network to provide in sequence a plurality of different voltage levels which levels are selected from three or more such levels, said summing network having a plurality of different input leads, said summing network including a plurality of resistances coupled between said respective input leads and a common connection, said resistances having different resistance values to provide to said common connection different voltage levels which increase proportionately to a root of equally spaced values, which root is different from 1, rather than to equal differences in voltage levels;
a storage device having a plurality of output leads coupled to respective ones of said summing network input leads, said storage device storing different monadic operation codes to activate different combinations of said input leads; and means coupled to said storage device to transmit a binary code to said storage device which binary code designates a monadic operation code to select a particular voltage level.
8. A convertor according to Claim 7 wherein:
said summing network includes a plurality of resistances coupled between said respective input leads and a common connection to provide to said common connec-tion different voltage levels which increase proportionately to the 2.2 root of equally spaced values rather than to equal differences in voltage levels.
said summing network includes a plurality of resistances coupled between said respective input leads and a common connection to provide to said common connec-tion different voltage levels which increase proportionately to the 2.2 root of equally spaced values rather than to equal differences in voltage levels.
9. A convertor according to Claim 8 wherein said binary code is transmitted in parallel and has a number of bits which number is the least power of 2 required to represent the different voltage levels and wherein:
the number of output leads from said storage device is greater than said least power of 2 so as to allow said binary code to select more than one voltage level.
the number of output leads from said storage device is greater than said least power of 2 so as to allow said binary code to select more than one voltage level.
10. A convertor according to Claim 9 which further includes:
a register coupled between said storage output leads and said summing network input leads to temporarily store said unary code.
a register coupled between said storage output leads and said summing network input leads to temporarily store said unary code.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US83684277A | 1977-09-26 | 1977-09-26 | |
| US836,842 | 1977-09-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1102458A true CA1102458A (en) | 1981-06-02 |
Family
ID=25272868
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA310,784A Expired CA1102458A (en) | 1977-09-26 | 1978-09-06 | Video synthesizer for a digital video display system employing a plurality of grayscale levels displayed in discrete steps of luminance |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS5454533A (en) |
| CA (1) | CA1102458A (en) |
| DE (1) | DE2840005A1 (en) |
| FR (1) | FR2404361A1 (en) |
| GB (1) | GB2005500B (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4382254A (en) * | 1980-06-18 | 1983-05-03 | Nixdorf Computer Corporation | Video display control circuitry |
| US4464777A (en) * | 1980-10-22 | 1984-08-07 | Tokyo Shibaura Denki Kabushiki Kaisha | Radiography apparatus |
| JPS57101888A (en) * | 1980-12-16 | 1982-06-24 | Sony Corp | Character display |
| JPS57175186U (en) * | 1981-04-28 | 1982-11-05 | ||
| GB2108341B (en) * | 1981-10-28 | 1984-12-12 | Philips Electronic Associated | Decoding binary coded colour video signals |
| EP0132454A1 (en) * | 1983-07-29 | 1985-02-13 | DR.-ING. RUDOLF HELL GmbH | Method and device for the high definition typographical display of text |
| DE3375613D1 (en) * | 1983-07-29 | 1988-03-10 | Hell Rudolf Dr Ing Gmbh | Method and device to check the sentence quality of printed matter, in particular for newspapers |
| DE3614422A1 (en) * | 1986-04-29 | 1987-11-05 | Siemens Ag | Circuit arrangement for converting two digital signals into one analog signal for controlling the brightness of a display unit operating in accordance with the raster element method |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA830119A (en) * | 1963-10-16 | 1969-12-16 | A. Cole Donald | Digital storage and generation of video signals |
| US3527980A (en) * | 1968-03-28 | 1970-09-08 | Control Data Corp | Digital variable intensity display |
| US3811007A (en) * | 1971-11-11 | 1974-05-14 | Tektronix Inc | Facsimile method and apparatus |
| US3938139A (en) * | 1974-12-30 | 1976-02-10 | Young Communications Corporation | Miniature display communicator |
| US3991301A (en) * | 1975-05-29 | 1976-11-09 | Westinghouse Electric Corporation | Logarithmic frequency to voltage converter |
| SU734757A1 (en) * | 1976-12-22 | 1980-05-15 | Таганрогский Радиотехнический Институт | Device for displaying information on crt screen |
-
1978
- 1978-08-29 GB GB7834819A patent/GB2005500B/en not_active Expired
- 1978-09-06 CA CA310,784A patent/CA1102458A/en not_active Expired
- 1978-09-12 FR FR7826182A patent/FR2404361A1/en active Pending
- 1978-09-12 JP JP11287578A patent/JPS5454533A/en active Granted
- 1978-09-14 DE DE19782840005 patent/DE2840005A1/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5454533A (en) | 1979-04-28 |
| DE2840005C2 (en) | 1987-09-24 |
| GB2005500A (en) | 1979-04-19 |
| GB2005500B (en) | 1982-07-14 |
| JPH0258635B2 (en) | 1990-12-10 |
| DE2840005A1 (en) | 1979-04-05 |
| FR2404361A1 (en) | 1979-04-20 |
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