CA1089962A - Bit switching of word synchronized data - Google Patents
Bit switching of word synchronized dataInfo
- Publication number
- CA1089962A CA1089962A CA286,790A CA286790A CA1089962A CA 1089962 A CA1089962 A CA 1089962A CA 286790 A CA286790 A CA 286790A CA 1089962 A CA1089962 A CA 1089962A
- Authority
- CA
- Canada
- Prior art keywords
- data
- word
- switch
- information
- synchronization information
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
- H04J3/0614—Systems characterised by the synchronising information used the synchronising signal being characterised by the amplitude, duration or polarity
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
ABSTRACT
The invention relates to a digital data switch for serially bit-switching word synchronized Pulse Code Modulated (PCM) data from inlets to outlets of the switch. The switch is particularly intended for use in situations wherein PCM data words arriving at the switch on different inlets are not aligned in so far as word boundaries are concerned. The PCM data is bi-polar or diphase modulated and the synchronization information of each word consists of a violation of the modulation. The switch includes a demodulator on each inlet for demodulating the data and a synchronization detect circuit associated with each demodulator for detecting the synchronization information in each incoming data word. The switch has two functionally identical time division multiplexed switch paths; one being a data path and the other being a by-path for switching the syn-chronization information. The synchronization information is thereby switched simultaneously through the switch in parallel with the associated data word such that both the data word and synchronization information arrive at the appropriate outlet according to the connection required through the switch. Each outlet has a modulator for receiving the data word and syn-chronization information and bi-polar or diphase modulating the outgoing data from the switch and causing an appropriate violation of the modulation in response to the synchronization information. A method of switching data is also claimed.
The invention relates to a digital data switch for serially bit-switching word synchronized Pulse Code Modulated (PCM) data from inlets to outlets of the switch. The switch is particularly intended for use in situations wherein PCM data words arriving at the switch on different inlets are not aligned in so far as word boundaries are concerned. The PCM data is bi-polar or diphase modulated and the synchronization information of each word consists of a violation of the modulation. The switch includes a demodulator on each inlet for demodulating the data and a synchronization detect circuit associated with each demodulator for detecting the synchronization information in each incoming data word. The switch has two functionally identical time division multiplexed switch paths; one being a data path and the other being a by-path for switching the syn-chronization information. The synchronization information is thereby switched simultaneously through the switch in parallel with the associated data word such that both the data word and synchronization information arrive at the appropriate outlet according to the connection required through the switch. Each outlet has a modulator for receiving the data word and syn-chronization information and bi-polar or diphase modulating the outgoing data from the switch and causing an appropriate violation of the modulation in response to the synchronization information. A method of switching data is also claimed.
Description
8 ~3~ ~
The present invention relates to digital data transmission systems and more par~icularly to an improved method and means for sw;tching digital word synchronized data at intermed;ate d;g;tal exchanges.
Conventionally, means for sw;tching digital word synchronized or word formated data such as PCM data comprises a digital switch wherein the data is switched in word format by switch;ng the bits of each word in parallel through the sw;tch. Such a sw;~ch is inefficient in smaller applications in that it requires an identical switch path for each data bit of each word. Furthermore, if the analogue to digital (A/D) and digital to analogue (D/A) conversion is done in the terminals and the terminals are remote from the switch, the digital data is usually transmitted serially in a bipolar or diphase modulated form. This data must be demodulated before switching and modulated again after switching. It is also necessary to convert the serially transmitted data to parallel form for switching and vice versa. This further adds to the complexity a~d hence the cost of a parallel word switch.
In larger switches, internal speed limltations necessitate the use of word switches which are generally multi-stage, for example, 3 stage (Time-Space-Time) word swl~ches. However, in the small exchanges considerecl here, switching is done serially, one bit at a time. The description belc~w re~ers to a single stage (Time) serial blt switch but the principles described apply equa11y to a mult~-stage serial b~t switch such as a Time-Space-Time switch for ' . .
~ 9 6 ~
, . .
example.
Of course bit switches for switching unsynchronized data such as delta modulated data are well known and are widely used in small exchanges. However, such switches are unsuitable for switching word formated data as there is no provision for transferring word synchronizing information.
It is therefore an object of the present invention to provide a switch or exchange for use in smaller applications (for example PABX's) for switching word synchronized data in serial bit format thus avoiding the a-forementioned dis-advantages of word formated switches.
It is a further object of this invention to provide a method for switching word synchronized data in serial bit format thus avoiding the aforementioned disadvantages of word formated switches.
Accordingly the invention provides a method for serially bit-switching word synchronized digital data in a digital switch comprising separating synchronizing information from each word prior to switching, serially bit-switching the word via a single 2Q data path to a required outlet and simul~aneously switching said synchronization in~formation via a switch by-path to said outlet to enable recombining of said synchronization information wlth the appropriate word at said outlet.
According to a further form the invention provldes a digital switch for serially bit-switching word synchronized dlgital data between a plurality of inlets and outlets to said switch comprislng a word synchronization extract circuit associated with each inlet for extracting synchronization information from .
.
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, each data word a~ each inlet, a switch data path for serially bit-sw;tchi ng data from a partieular inlet to a particular outlet, a switch by-path for serially bit-switching said synchronization information simultaneously wi~h its associated data to said particular outlet and a word synchronization insert circuit associated with each outlet ~or inserting said synchronization information with each data word out of said switch.
In order that the invention may be more readily under-stood one particular embodiment will now be described with reference to the accompanying drawings wherein:
Figure 1 is a simplified circuit block diagram oF a termlnal and the input to a digital switch according to the embodiment, and Figure 2 is a simplified circuit block diagram of the switch according to the embodiment.
Referring now to Figure 1 there is shown a typical terminal of a digital telephone system, namely a digltal telephone 10, wherein analogue VF signals received by microphone 11 are converted into a digital bit stream by encoder 12.
Encoder 12 is an eight-bit PCM encoder. The e1ght-bit parallel data from encoder 12 is converted to serial form in parallel to serial (P/S) convertor 13 under control oF a three-b~t outgoing counter 14. The output of P/S convertor 13, which ~ncidentally is~a.multiplexor, is non-return to zero (NRZ) data which is converted to diphased data in convertor 15 also under control from counter 14. Gate circuits (not shown) in connect~on.16 cause the diphasing in convertor 15 t~ be ~(J8 ~
Violated on the least signi~icant bit (LSB) of each PCM word.
In other words the LSB bit of each PCM word is sent to line undiphased in order to provide a word synchroniz;ng bit for each data word. This form of synchronization is kno~n as in-band synchronization. Hybrid 17 separates incoming and outgoing data on line 18 which is a two wire transmission line connected to digital exchange or switch 19 (part of which is shown in Figure 1) via a further hybrid 20. Alternatively the connection may be 4-wire thus obviating the need for hybrids.
In a converse manner data received at the terminal 10 passes via hybrid 17 to convertor 21 which converts diphased data to NRZ data. Prior to this conversion however the data is applied to an oscillator (not shown) tuned to twice the incoming line frequency from which a Further circuit (not shown) is adapted to generate clock signal for the devices oF the terminal. The further circuit also generates a reverse clock phase signal c as there is no reference between incoming data and the extracted clock in this method of clock generation.
A word synchronization detector 22 selects the pulses in the incoming data corresponding to the diphase violation and uses this information to reset incoming counter 23. A serial to parallel (S/P) convertor 24 converts the bit stream to parallel form under contr~ol of counter 23~ The reversed cl ock phase s~ynal c is appli`ed to S/P convertor 2~ on 25 to restore the b~t whose diphase was violated, to its correct NRZ value. The analogue signal is restored in decoder 26 and applied to receiver 27i;
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~ The above description of Figure 1 relates to the genera- -~
tion and reception, in terminal devices (telephones) of the sys-tem, of a word formated digital bit stream in the form of an eight-bit PCM word. The data is diphased data of 64 KHz and synchronization is achieved by diphase violation of one of the eight bits, say the least significant bit (LSB) which may be also used for in band signalling. As will be appreciated from the following description other forms of word formated data may be - switched according to the method and apparatus o the invention.
10Reference should now be made to the part of Fig. 1 relating to switch 19 and to Fig. 2 which show the digital switch `
according to this embodiment. Data received at the switch from a terminal is firstly converted Erom diphased data to NRZ data b~ diph~se demodulator 28 and the synchronization signals are detected by word synchronization extractor 29 which provides `
word synchronization pulses on connection 30 for switchlng through the switch as will be apparenthereinbelow. The NRZ da-ta from demodulator 28 is reclocked in buffer 31 -to provide a de-diphased serial data bit stream for switching in the switch.
\In a converse manner data which has been switched in the switch 1~ is converted from NRZ -to diphase in modulator 32 where word synchronization in~ormation on 33, which has been correspondingly ~`
-witched, is ccmbined with the ' .
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:
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.
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outgoing data to the terminal lo.
The switch 19 is shown more fully in Fig. 2 and includes a bi~ switch in the general ~orm of a single stage menlory switch as has been previously used fo~ switching non word for~ated data. Only one switch group colllprising sixty-four inlets and outlets is shown, as the switch may be readily increased in size by adding similar modules. Sixty-four incoming lines provide the data to a similar number of the demodulators 28, synchronization extractors 29 and buffers 31 as shown, which perform the functions described above. The de-diphased data is applied to respective inlets of sixty-four input data multiplexor 34 whereby the ~ Kb/s data is time multiple.~ed onto a single data highway 35 at 4 Mb/s.
The data is re-arranged on the hi~hway 35 in order to switch lS inlet lines to outlet lines by means of a single stage RAM data store 36 controlled by RAM control store 37. The output oF
RAM 36 is switched via the highway 35 to data demultiplexor 38 where the data bits at 4 Mb/s are distributed to -the outgoing channels at 64 Kb/s. Diphasing and synchronization takes place ~0 in modulators 32. The above described sw;tching part of swlt,ch 19 is known per se.
In order to switch word ~ormated data the word synchronization or word boundary must be preserved across the switch (the switch introduces a delay on some connections, depending an rel~tion o~ incoming and outgoing addresses) and in this regard the exchan~e according to the invention is made "transparent" as Far as the word boundary ls concerned.
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This means that incoming lines to the switch are not word aligned and that word synchronization is not generated in the switch. Synchroniiation bits are simply repeated from exchange inlet to outlet and any correction for loss of synchronlz~tlon ls le~t to the term-lnals. Sin(e t.he ~wltch cannot handle diphase signals it cannot therefore transfer word boundary information in the form of diphase violations ~rom inlet to outlet.
To this ~nd the switch includes a word boundary or synchronization by-path which is functionally identical to the main data switch path described above. The by-path consists essentially of word boundary multiplexor 39, RAM
word boundary store 40 and word boundary demultiplexor 41 all of which combine to switch the word boundary information via a single highway 42 under control from RAM control store 37.
; The occurrence of a synchronization bit in incoming word formated data ~s detected before the data is reclocked by buffer 31 as otherwise the diphase violations would be lost.
Furthermore, the synchron~zation bit must be attached to the correct data bit at the output of the switch.
For this purpose the word synchronization extract unit 29 extracts the synchronization information and produces a signal ONE when the corresponding data bit has ~ts diphase violated. This information is sw~tched through from ~nlet ~o 25 ~ outlet simultanè~usly and ln parallel wikh the correspondiny data bit so that both data and synchronizatlon appear auto-matically at the correct outlet. The synchronization infor-;~
; .. .. . .
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.
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-mation is used to re-diphase violate the outgoing bit in the relevant modulat~r 32.
The use of the by-path in no way changes the remainder of the switch and in fact the control system for the switch (not shown) need not be aware of the presence of a by-path. The control system provides control information on connection 42 causing the control store 37 to put the appropriate address on connection 43 thus causing the data bits relevant to a particular connection to be wrltten into a particular location in RAM 36 and the synchronization bit to be written into a corresponding location in RP~I ~O.
An address counter ~4 provides address information to the relevant units of the switch as shown in the drawings.
A further feature of the above described embodiment relates to signalling information which, conveniently, is located in a predetermined position relative to the synchroniza-tion bit of each PCM word, thus enabling its ready identification ;`
at any point in the system. For example the signalling bit may ~
be the bit which actually carries the synchroniæa-tion informa- ;
tion in which case signalling and synchronization occurs during the LS~ of the PCM word.
The advantage of the synchronization by-path Eor sig- ;
nalling is that the appearance of a synchronization pulse on the by-path higllway may be used d: a label to divert a .
1. ' ~ ' ': , ~
_ 9 _ signalling bit from the data path at the inlet to RAM 36 to a central signalling processor and to insert the signallîng bit from the signalling processor onto the data path at the outlet side of RAM 36. This can be achieved by simple gating (not shown).
It should be ap-parent that the present invention provides a simple bit switch suitable ~or switching word formated data in serial ~orm thus avoidiny parallel paths through the switch for each data bit in each word. Of course the switch of the invention does require effectively a duplica-tion of the data path through the switch for the purpose of switching synchronization information but for smaller switches this duplication, and the ineffic;ency result,lng fr4m the by-path not being used to its full capacity, is insignificant when compared with a parallel data word switch. Use of the invention in digital data systems such as subsçriber-to- "
subscriber telephone systems facilitates a system having end-to-end transmission of digital, word synchronized data, without the need for synchronization or word alignment at ~ntermediate digital exchanges which are functionally "~rans-parent" to the synchronization information.
It should be pointed out that in the foregoing descrip-tion it was assumed that analogue to dig~tal and digltal to analogue conversion was carried out at remote terlllinals or telephones and t`hat bipolar and diphase modulation was necessary for reasons of transmlssion between the terminals and the digital switch.
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, .
The present invention relates to digital data transmission systems and more par~icularly to an improved method and means for sw;tching digital word synchronized data at intermed;ate d;g;tal exchanges.
Conventionally, means for sw;tching digital word synchronized or word formated data such as PCM data comprises a digital switch wherein the data is switched in word format by switch;ng the bits of each word in parallel through the sw;tch. Such a sw;~ch is inefficient in smaller applications in that it requires an identical switch path for each data bit of each word. Furthermore, if the analogue to digital (A/D) and digital to analogue (D/A) conversion is done in the terminals and the terminals are remote from the switch, the digital data is usually transmitted serially in a bipolar or diphase modulated form. This data must be demodulated before switching and modulated again after switching. It is also necessary to convert the serially transmitted data to parallel form for switching and vice versa. This further adds to the complexity a~d hence the cost of a parallel word switch.
In larger switches, internal speed limltations necessitate the use of word switches which are generally multi-stage, for example, 3 stage (Time-Space-Time) word swl~ches. However, in the small exchanges considerecl here, switching is done serially, one bit at a time. The description belc~w re~ers to a single stage (Time) serial blt switch but the principles described apply equa11y to a mult~-stage serial b~t switch such as a Time-Space-Time switch for ' . .
~ 9 6 ~
, . .
example.
Of course bit switches for switching unsynchronized data such as delta modulated data are well known and are widely used in small exchanges. However, such switches are unsuitable for switching word formated data as there is no provision for transferring word synchronizing information.
It is therefore an object of the present invention to provide a switch or exchange for use in smaller applications (for example PABX's) for switching word synchronized data in serial bit format thus avoiding the a-forementioned dis-advantages of word formated switches.
It is a further object of this invention to provide a method for switching word synchronized data in serial bit format thus avoiding the aforementioned disadvantages of word formated switches.
Accordingly the invention provides a method for serially bit-switching word synchronized digital data in a digital switch comprising separating synchronizing information from each word prior to switching, serially bit-switching the word via a single 2Q data path to a required outlet and simul~aneously switching said synchronization in~formation via a switch by-path to said outlet to enable recombining of said synchronization information wlth the appropriate word at said outlet.
According to a further form the invention provldes a digital switch for serially bit-switching word synchronized dlgital data between a plurality of inlets and outlets to said switch comprislng a word synchronization extract circuit associated with each inlet for extracting synchronization information from .
.
24~E 3 9~J~
, each data word a~ each inlet, a switch data path for serially bit-sw;tchi ng data from a partieular inlet to a particular outlet, a switch by-path for serially bit-switching said synchronization information simultaneously wi~h its associated data to said particular outlet and a word synchronization insert circuit associated with each outlet ~or inserting said synchronization information with each data word out of said switch.
In order that the invention may be more readily under-stood one particular embodiment will now be described with reference to the accompanying drawings wherein:
Figure 1 is a simplified circuit block diagram oF a termlnal and the input to a digital switch according to the embodiment, and Figure 2 is a simplified circuit block diagram of the switch according to the embodiment.
Referring now to Figure 1 there is shown a typical terminal of a digital telephone system, namely a digltal telephone 10, wherein analogue VF signals received by microphone 11 are converted into a digital bit stream by encoder 12.
Encoder 12 is an eight-bit PCM encoder. The e1ght-bit parallel data from encoder 12 is converted to serial form in parallel to serial (P/S) convertor 13 under control oF a three-b~t outgoing counter 14. The output of P/S convertor 13, which ~ncidentally is~a.multiplexor, is non-return to zero (NRZ) data which is converted to diphased data in convertor 15 also under control from counter 14. Gate circuits (not shown) in connect~on.16 cause the diphasing in convertor 15 t~ be ~(J8 ~
Violated on the least signi~icant bit (LSB) of each PCM word.
In other words the LSB bit of each PCM word is sent to line undiphased in order to provide a word synchroniz;ng bit for each data word. This form of synchronization is kno~n as in-band synchronization. Hybrid 17 separates incoming and outgoing data on line 18 which is a two wire transmission line connected to digital exchange or switch 19 (part of which is shown in Figure 1) via a further hybrid 20. Alternatively the connection may be 4-wire thus obviating the need for hybrids.
In a converse manner data received at the terminal 10 passes via hybrid 17 to convertor 21 which converts diphased data to NRZ data. Prior to this conversion however the data is applied to an oscillator (not shown) tuned to twice the incoming line frequency from which a Further circuit (not shown) is adapted to generate clock signal for the devices oF the terminal. The further circuit also generates a reverse clock phase signal c as there is no reference between incoming data and the extracted clock in this method of clock generation.
A word synchronization detector 22 selects the pulses in the incoming data corresponding to the diphase violation and uses this information to reset incoming counter 23. A serial to parallel (S/P) convertor 24 converts the bit stream to parallel form under contr~ol of counter 23~ The reversed cl ock phase s~ynal c is appli`ed to S/P convertor 2~ on 25 to restore the b~t whose diphase was violated, to its correct NRZ value. The analogue signal is restored in decoder 26 and applied to receiver 27i;
249E ~ 5 ~
_ _ . ~ . _ _ . .. .... .. _ .. _ . __ ..... .. .. ... . . . . . .. .. . . .. .... .. .. . . .. .. . , . . , .
. ___ _ ~ , .: ......... .
. . .~. , 89~6~ :
~ The above description of Figure 1 relates to the genera- -~
tion and reception, in terminal devices (telephones) of the sys-tem, of a word formated digital bit stream in the form of an eight-bit PCM word. The data is diphased data of 64 KHz and synchronization is achieved by diphase violation of one of the eight bits, say the least significant bit (LSB) which may be also used for in band signalling. As will be appreciated from the following description other forms of word formated data may be - switched according to the method and apparatus o the invention.
10Reference should now be made to the part of Fig. 1 relating to switch 19 and to Fig. 2 which show the digital switch `
according to this embodiment. Data received at the switch from a terminal is firstly converted Erom diphased data to NRZ data b~ diph~se demodulator 28 and the synchronization signals are detected by word synchronization extractor 29 which provides `
word synchronization pulses on connection 30 for switchlng through the switch as will be apparenthereinbelow. The NRZ da-ta from demodulator 28 is reclocked in buffer 31 -to provide a de-diphased serial data bit stream for switching in the switch.
\In a converse manner data which has been switched in the switch 1~ is converted from NRZ -to diphase in modulator 32 where word synchronization in~ormation on 33, which has been correspondingly ~`
-witched, is ccmbined with the ' .
' ~ ~ ".
:
`:
.
JI~46'~
outgoing data to the terminal lo.
The switch 19 is shown more fully in Fig. 2 and includes a bi~ switch in the general ~orm of a single stage menlory switch as has been previously used fo~ switching non word for~ated data. Only one switch group colllprising sixty-four inlets and outlets is shown, as the switch may be readily increased in size by adding similar modules. Sixty-four incoming lines provide the data to a similar number of the demodulators 28, synchronization extractors 29 and buffers 31 as shown, which perform the functions described above. The de-diphased data is applied to respective inlets of sixty-four input data multiplexor 34 whereby the ~ Kb/s data is time multiple.~ed onto a single data highway 35 at 4 Mb/s.
The data is re-arranged on the hi~hway 35 in order to switch lS inlet lines to outlet lines by means of a single stage RAM data store 36 controlled by RAM control store 37. The output oF
RAM 36 is switched via the highway 35 to data demultiplexor 38 where the data bits at 4 Mb/s are distributed to -the outgoing channels at 64 Kb/s. Diphasing and synchronization takes place ~0 in modulators 32. The above described sw;tching part of swlt,ch 19 is known per se.
In order to switch word ~ormated data the word synchronization or word boundary must be preserved across the switch (the switch introduces a delay on some connections, depending an rel~tion o~ incoming and outgoing addresses) and in this regard the exchan~e according to the invention is made "transparent" as Far as the word boundary ls concerned.
259~ 7 .. ..... .. .. l .
, . . . .. . .
. ~ . , .. , : ~ ..... . . .. -.,::
, . . . .. . .
- , ~ ~ 9 9 6 ~
This means that incoming lines to the switch are not word aligned and that word synchronization is not generated in the switch. Synchroniiation bits are simply repeated from exchange inlet to outlet and any correction for loss of synchronlz~tlon ls le~t to the term-lnals. Sin(e t.he ~wltch cannot handle diphase signals it cannot therefore transfer word boundary information in the form of diphase violations ~rom inlet to outlet.
To this ~nd the switch includes a word boundary or synchronization by-path which is functionally identical to the main data switch path described above. The by-path consists essentially of word boundary multiplexor 39, RAM
word boundary store 40 and word boundary demultiplexor 41 all of which combine to switch the word boundary information via a single highway 42 under control from RAM control store 37.
; The occurrence of a synchronization bit in incoming word formated data ~s detected before the data is reclocked by buffer 31 as otherwise the diphase violations would be lost.
Furthermore, the synchron~zation bit must be attached to the correct data bit at the output of the switch.
For this purpose the word synchronization extract unit 29 extracts the synchronization information and produces a signal ONE when the corresponding data bit has ~ts diphase violated. This information is sw~tched through from ~nlet ~o 25 ~ outlet simultanè~usly and ln parallel wikh the correspondiny data bit so that both data and synchronizatlon appear auto-matically at the correct outlet. The synchronization infor-;~
; .. .. . .
~ . '., '.' ,', ,, ~
.. . . . . . . . . . ..
.
6~
-mation is used to re-diphase violate the outgoing bit in the relevant modulat~r 32.
The use of the by-path in no way changes the remainder of the switch and in fact the control system for the switch (not shown) need not be aware of the presence of a by-path. The control system provides control information on connection 42 causing the control store 37 to put the appropriate address on connection 43 thus causing the data bits relevant to a particular connection to be wrltten into a particular location in RAM 36 and the synchronization bit to be written into a corresponding location in RP~I ~O.
An address counter ~4 provides address information to the relevant units of the switch as shown in the drawings.
A further feature of the above described embodiment relates to signalling information which, conveniently, is located in a predetermined position relative to the synchroniza-tion bit of each PCM word, thus enabling its ready identification ;`
at any point in the system. For example the signalling bit may ~
be the bit which actually carries the synchroniæa-tion informa- ;
tion in which case signalling and synchronization occurs during the LS~ of the PCM word.
The advantage of the synchronization by-path Eor sig- ;
nalling is that the appearance of a synchronization pulse on the by-path higllway may be used d: a label to divert a .
1. ' ~ ' ': , ~
_ 9 _ signalling bit from the data path at the inlet to RAM 36 to a central signalling processor and to insert the signallîng bit from the signalling processor onto the data path at the outlet side of RAM 36. This can be achieved by simple gating (not shown).
It should be ap-parent that the present invention provides a simple bit switch suitable ~or switching word formated data in serial ~orm thus avoidiny parallel paths through the switch for each data bit in each word. Of course the switch of the invention does require effectively a duplica-tion of the data path through the switch for the purpose of switching synchronization information but for smaller switches this duplication, and the ineffic;ency result,lng fr4m the by-path not being used to its full capacity, is insignificant when compared with a parallel data word switch. Use of the invention in digital data systems such as subsçriber-to- "
subscriber telephone systems facilitates a system having end-to-end transmission of digital, word synchronized data, without the need for synchronization or word alignment at ~ntermediate digital exchanges which are functionally "~rans-parent" to the synchronization information.
It should be pointed out that in the foregoing descrip-tion it was assumed that analogue to dig~tal and digltal to analogue conversion was carried out at remote terlllinals or telephones and t`hat bipolar and diphase modulation was necessary for reasons of transmlssion between the terminals and the digital switch.
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, .
Claims (5)
EXCLUSIVE PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED
AS FOLLOWS:
1. A method for serially bit-switching word synchronized digital data whereby the synchronization information is separated from its associated data word prior to switching, each data word is serially bit switched via a single data path to a re-quired outlet and information relevant to said synchronization information is switched simultaneously with said associated data word, via a switch by-path, to said outlet to provide for appropriate re-combination of synchronization information with said related data word at said outlet, said word synchronized data being bi-polar or diphase modulated data and said synch-ronization information being in-band and being a violation of said modulation, said synchronization information being separated from its associated data word by demodulating said data to provide non return to zero data prior to switching.
2. A method as defined in claim 1 characterized in that said synchronization information is used to identify signalling information in said data words.
3. A digital data switch for serially bit-switching word synchronized digital data between a plurality of inlets and outlets to said switch, said switch including word synchroniza-tion extract circuitry associated with each said inlet for extracting synchronization information from each data word at each inlet and providing digital information relevant to the occurrence of said synchronization information, a switch data path for serially bit switching the data of each data word from a particular inlet to a particular outlet, a switch by-path for switching said digital information relevant to the occurrence of said synchronization information simultaneously with its associated data word to said particular outlet and word synchron-ization insert circuitry associated with each said outlet for appropriately re-combining said synchronization information with each data word in response to said digital information relevant to the occurrence of said synchronization information, said word synchronized data being bi-polar or diphase modulated data and said synchronization information being in-band and consisting of violations of said modulation, each said word synchronization extract circuitry detecting said violations and providing said digital information relevant to the occurrence of said synchron-ization information, each said word synchronization extract circuitry including further circuitry for converting said bi-polar modulated data to non return to zero (NRZ) data for bit switching via said data path.
4. A digital data switch as defined in claim 3 wherein said switch data path includes a multiplexor for time multiplex-ing data from said inlets onto a common data highway, a data store on said highway for re-arranging the order of the data on said highway under control from a control store and a demulti-plexor for receiving the re-arranged data from said highway and time demultiplexing the data to said outlets, said switch by-path including a multiplexor, data store, highway and demulti-plexor arranged the same as said data path and the data store of said by-path being controlled by said control store.
5. A digital data switch as defined in claim 4, wherein said synchronization information of each data word is adapted to identify signalling information in said data.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| AUPC7387 | 1976-09-16 | ||
| AU738776 | 1976-09-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1089962A true CA1089962A (en) | 1980-11-18 |
Family
ID=3698061
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA286,790A Expired CA1089962A (en) | 1976-09-16 | 1977-09-15 | Bit switching of word synchronized data |
Country Status (2)
| Country | Link |
|---|---|
| CA (1) | CA1089962A (en) |
| GB (1) | GB1545637A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| ZA804387B (en) * | 1979-08-10 | 1981-07-29 | Plessey Co Ltd | Channel zero switching arrangements for digital telecommunication exchanges |
-
1977
- 1977-09-15 CA CA286,790A patent/CA1089962A/en not_active Expired
- 1977-09-16 GB GB38820/77A patent/GB1545637A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| GB1545637A (en) | 1979-05-10 |
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