CA1061003A - Display inhibition means for dynamic multi-digit display in two-speed calculators or the like - Google Patents
Display inhibition means for dynamic multi-digit display in two-speed calculators or the likeInfo
- Publication number
- CA1061003A CA1061003A CA259,817A CA259817A CA1061003A CA 1061003 A CA1061003 A CA 1061003A CA 259817 A CA259817 A CA 259817A CA 1061003 A CA1061003 A CA 1061003A
- Authority
- CA
- Canada
- Prior art keywords
- display
- display inhibition
- signals
- spurious
- high frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/04—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Calculators And Similar Devices (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
Two-speed calculators and the like employing an arithmetic processor and a time-sharing multi-digit display are clocked with high frequency pulses during an arithmetic mode and with low frequency pulses during a subsequent display mode. Display inhibition means are provided within the two-speed calculators to create cut signals effective to erase spurious indications on a multi-digit display. The display inhibition means are under control of the high frequency pulses and operate to control the pulse width or phase of the cut sig-nals.
Two-speed calculators and the like employing an arithmetic processor and a time-sharing multi-digit display are clocked with high frequency pulses during an arithmetic mode and with low frequency pulses during a subsequent display mode. Display inhibition means are provided within the two-speed calculators to create cut signals effective to erase spurious indications on a multi-digit display. The display inhibition means are under control of the high frequency pulses and operate to control the pulse width or phase of the cut sig-nals.
Description
The present invention relates to spurious display inhibition means for use with two-speed calculators and the like.
Generally speaking, within a variety of electronic apparatus items having a time sharing multi-digit display, in-cluding calculators, there is a possibility that undesired characters, numerals, etc. will be displayed due to a rounding off of the leading and trailing edges of digit selection or segment selection signals. In order to overcome this problem, display inhibition signals, herein referred to as cut signals, should be employed to inhibit a spurious display due to such rounded waveforms occurring at a transitional interval from one specific digit selection time slot to the next.
In order to keep computation times short, operational speeds are of great importance in calculators, particularly those in which word lengths are great or in which required operations are complicated. Therefore, the pulse repetition rate, or frequency, of a controlling clock pulse should be high in order to ensure a high speed of operation. Since displays for use with calculators generally do not have a high frequency response capability, the frequency of the clock pulses will be limited largely by the response of the displays. In this respect, known two-speed calculators which are clocked with high frequency pulses during their arithmetic mode and with low frequency pulses during their subsequent display mode are described in U.S. patent No. 3,453,601 TWO SPEED ARITHMETIC
CALCULATOR issued on July 1, 1969 to Howard Z. Bogert and assigned to Philco-Ford Corporation.
It is a principal object of the present invention to provide an improved spurious display inhibition means which will reduce the disadvantages associated with the aforenoted 106iO03 prior art.
The aforenoted problems associated with the prior art may be substantially overcome and the foregoing object achieved by recourse to the invention which relates to spurious display inhibition means for use with two-speed calculators and the like which are clocked with high frequency pulses during an arithmetic mode and with low frequency pulses during a subsequent display mode. The spurious display inhibition means comprise first circuit means for receiving timing signals in synchronization with the low frequency pulses and second circuit means for transferring the timing signals through the first circuit means in response to the high frequency pulses, the transferred timing signalsbeingconditioned therebyfor use as display inhibition signals.
The invention will now be more particularly described with reference to embodiments thereof shown, by way of example, in the accompanying drawing in which:
FIG. 1 is a block diagram of an arithmetic mode control clock pulse/display mode control clock pulse generator in accordance with one embodiment of the present invention;
FIG. 2 is a timing diagram for illustrating the operation of the circuit of FIG. 3;
FIG. 3 is a detailed circuit diagram of a display inhibition circuit of the present invention; and FIG. 4 is a detailed circuit diagram of another embodiment of the display inhibition circuit of FIG. 3.
Referring now to FIG. 1, there is illustrated a pulse generator 1 and other circuitry, herein to be described, which develops high frequency master clock pul5es ~1' and ~2' for controlling an arithmetic mode of a calculator and low fre-quency clock pulses ~1 and ~2 for controlling a display mode .~
of the calculator.
As previously stated, clock pulses controlling the display are governed with respect to an upper pulse repetition rate or frequency limit by the response characteristic of the display, particularly if it is a time sharing multi-digit dis-play. The clock pulses must therefore have a frequency com-patible with the response speed of the displays employed. In the example given in the figures, the display mode controlling clock pulses have a frequency one half that of the arithmetic mode controlling clock pulses or master clock pulses and are derived from the master clock pulses.
In FIG. 1, a binary counter 2 provides signals C
shown in a timing chart of FIG. 2. The signals C are applied to one input terminal of an AND gate 3 and also to one input terminal of an AND gate 5 via an inverter 4. Other inputs to the AND gates 3 and 5 are, respectively, signals ~1 " Hs and ~2 " Hs wherein Hs represents signals that are at a low level or 1 during the display mode.
With the foregoing arrangement, when Hs = 1 during the display mode, the outputs ~1 and ~2 of the AND gates 3 and 5 occur at half the frequency of the master clock pulses ~1' and ~2' and are employed as low frequency clock pulses for controlling the display mode. Digit selection signals and segment selection signals required for time sharing display operation are produced in synchronization with the display mode controlling clock pulses. In addition, shifting of one or more shift registers, etc. comes under control of the low frequency clock pulses ~1 and ~2.
While in the above illustrated example a binary counter is employed and the display mode controlling clock pulses are halved in frequency as compared with the arithmetic A~
1~61003 mode controlling clock pulses, any frequency ratio may be chosen provided it is compatible with the response characteristic of the displays.
Display inhibition signals to preclude spurious display are produced by delaying specific bit timing signals t4 by means of the arithmetic mode controlling clock pulses ~1' and ~2' rather than the display mode controlling clock pulses ~1 and ~2. FIG. 3 illustrates a spurious display in-hibition signal generator circuit. As shown therein, by trans-ferring the bit timing signals t4 through the use of or insynchronization with the arithmetic mode controlling high frequency clock pulses ~1 " desired display inhibition signals D are obtained which are 1/4 bit delayed in time with reference to the bit timing signals t4 shown in FIG. 2.
Logical products B, which comprise the output of an AND gate 6, are supplied to the dynamic or time sharing display. It will be seen in FIG. 3 that the products B are derived from the signals D and segment selection signals which are input to the gate 6. The bit timing signals t4 are applied to a field effect transistor 7 which is gated by the arithmetic mode controlling clock pulses ~1' In this way the bit timing signals t4 are transferred to an inverting field effect trans-istor 8 having a load comprising a field effect transistor 9.
An alternative circuit is shown in FIG. 4 wherein identical components are identically numbered. In the al-ternative arrangement, the bit timing signals t4 are firstly transferred through the transistor 7 which is gated by the first of the arithmetic mode controlling clock pulses ~1' Secondly, the gated signals t4 are then transferred through a second field effect transistor 7' which is gated by the second arithmetic mode controlling clock pulses ~2 " The bit timing lQ61003 signals t~ are then transferred to an inverting field effect transistor 8' having a load comprising a field effect trans-istor 9'. The output from the transistor 8' is in turn ap-plied to one input of the gate 6. The display inhibition sig-nals are thus 1/2 bit time delayed with reference to the bit timing signals t4.
While the foregoing description relates to control-ling only the phase of the display mode inhibition signals by utilizing the arithmetic mode controlling clock pulses, the pulse width of the display mode inhibition signals may also be controlled by utilizing the arithmetic mode controlling clock pulses.
Although there have been described herein specific arrangements of the spurious display inhibition means in accordance with the invention for the purpose of illustrating the manner in which the invention may be used to advantage, it will be appreciated that the invention is not limited thereto. Accordingly, any modific~tions, variations or equiv-alent arrangements which may occur to those skilled in the art in light of the present disclosure should be considered to be within the scope of the invention.
. - 5 -
Generally speaking, within a variety of electronic apparatus items having a time sharing multi-digit display, in-cluding calculators, there is a possibility that undesired characters, numerals, etc. will be displayed due to a rounding off of the leading and trailing edges of digit selection or segment selection signals. In order to overcome this problem, display inhibition signals, herein referred to as cut signals, should be employed to inhibit a spurious display due to such rounded waveforms occurring at a transitional interval from one specific digit selection time slot to the next.
In order to keep computation times short, operational speeds are of great importance in calculators, particularly those in which word lengths are great or in which required operations are complicated. Therefore, the pulse repetition rate, or frequency, of a controlling clock pulse should be high in order to ensure a high speed of operation. Since displays for use with calculators generally do not have a high frequency response capability, the frequency of the clock pulses will be limited largely by the response of the displays. In this respect, known two-speed calculators which are clocked with high frequency pulses during their arithmetic mode and with low frequency pulses during their subsequent display mode are described in U.S. patent No. 3,453,601 TWO SPEED ARITHMETIC
CALCULATOR issued on July 1, 1969 to Howard Z. Bogert and assigned to Philco-Ford Corporation.
It is a principal object of the present invention to provide an improved spurious display inhibition means which will reduce the disadvantages associated with the aforenoted 106iO03 prior art.
The aforenoted problems associated with the prior art may be substantially overcome and the foregoing object achieved by recourse to the invention which relates to spurious display inhibition means for use with two-speed calculators and the like which are clocked with high frequency pulses during an arithmetic mode and with low frequency pulses during a subsequent display mode. The spurious display inhibition means comprise first circuit means for receiving timing signals in synchronization with the low frequency pulses and second circuit means for transferring the timing signals through the first circuit means in response to the high frequency pulses, the transferred timing signalsbeingconditioned therebyfor use as display inhibition signals.
The invention will now be more particularly described with reference to embodiments thereof shown, by way of example, in the accompanying drawing in which:
FIG. 1 is a block diagram of an arithmetic mode control clock pulse/display mode control clock pulse generator in accordance with one embodiment of the present invention;
FIG. 2 is a timing diagram for illustrating the operation of the circuit of FIG. 3;
FIG. 3 is a detailed circuit diagram of a display inhibition circuit of the present invention; and FIG. 4 is a detailed circuit diagram of another embodiment of the display inhibition circuit of FIG. 3.
Referring now to FIG. 1, there is illustrated a pulse generator 1 and other circuitry, herein to be described, which develops high frequency master clock pul5es ~1' and ~2' for controlling an arithmetic mode of a calculator and low fre-quency clock pulses ~1 and ~2 for controlling a display mode .~
of the calculator.
As previously stated, clock pulses controlling the display are governed with respect to an upper pulse repetition rate or frequency limit by the response characteristic of the display, particularly if it is a time sharing multi-digit dis-play. The clock pulses must therefore have a frequency com-patible with the response speed of the displays employed. In the example given in the figures, the display mode controlling clock pulses have a frequency one half that of the arithmetic mode controlling clock pulses or master clock pulses and are derived from the master clock pulses.
In FIG. 1, a binary counter 2 provides signals C
shown in a timing chart of FIG. 2. The signals C are applied to one input terminal of an AND gate 3 and also to one input terminal of an AND gate 5 via an inverter 4. Other inputs to the AND gates 3 and 5 are, respectively, signals ~1 " Hs and ~2 " Hs wherein Hs represents signals that are at a low level or 1 during the display mode.
With the foregoing arrangement, when Hs = 1 during the display mode, the outputs ~1 and ~2 of the AND gates 3 and 5 occur at half the frequency of the master clock pulses ~1' and ~2' and are employed as low frequency clock pulses for controlling the display mode. Digit selection signals and segment selection signals required for time sharing display operation are produced in synchronization with the display mode controlling clock pulses. In addition, shifting of one or more shift registers, etc. comes under control of the low frequency clock pulses ~1 and ~2.
While in the above illustrated example a binary counter is employed and the display mode controlling clock pulses are halved in frequency as compared with the arithmetic A~
1~61003 mode controlling clock pulses, any frequency ratio may be chosen provided it is compatible with the response characteristic of the displays.
Display inhibition signals to preclude spurious display are produced by delaying specific bit timing signals t4 by means of the arithmetic mode controlling clock pulses ~1' and ~2' rather than the display mode controlling clock pulses ~1 and ~2. FIG. 3 illustrates a spurious display in-hibition signal generator circuit. As shown therein, by trans-ferring the bit timing signals t4 through the use of or insynchronization with the arithmetic mode controlling high frequency clock pulses ~1 " desired display inhibition signals D are obtained which are 1/4 bit delayed in time with reference to the bit timing signals t4 shown in FIG. 2.
Logical products B, which comprise the output of an AND gate 6, are supplied to the dynamic or time sharing display. It will be seen in FIG. 3 that the products B are derived from the signals D and segment selection signals which are input to the gate 6. The bit timing signals t4 are applied to a field effect transistor 7 which is gated by the arithmetic mode controlling clock pulses ~1' In this way the bit timing signals t4 are transferred to an inverting field effect trans-istor 8 having a load comprising a field effect transistor 9.
An alternative circuit is shown in FIG. 4 wherein identical components are identically numbered. In the al-ternative arrangement, the bit timing signals t4 are firstly transferred through the transistor 7 which is gated by the first of the arithmetic mode controlling clock pulses ~1' Secondly, the gated signals t4 are then transferred through a second field effect transistor 7' which is gated by the second arithmetic mode controlling clock pulses ~2 " The bit timing lQ61003 signals t~ are then transferred to an inverting field effect transistor 8' having a load comprising a field effect trans-istor 9'. The output from the transistor 8' is in turn ap-plied to one input of the gate 6. The display inhibition sig-nals are thus 1/2 bit time delayed with reference to the bit timing signals t4.
While the foregoing description relates to control-ling only the phase of the display mode inhibition signals by utilizing the arithmetic mode controlling clock pulses, the pulse width of the display mode inhibition signals may also be controlled by utilizing the arithmetic mode controlling clock pulses.
Although there have been described herein specific arrangements of the spurious display inhibition means in accordance with the invention for the purpose of illustrating the manner in which the invention may be used to advantage, it will be appreciated that the invention is not limited thereto. Accordingly, any modific~tions, variations or equiv-alent arrangements which may occur to those skilled in the art in light of the present disclosure should be considered to be within the scope of the invention.
. - 5 -
Claims (6)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. Spurious display inhibition means for use with two-speed calculators and the like which are clocked with high frequency pulses during an arithmetic mode and with low frequency pulses during a subsequent display mode, said spurious display inhibition means comprising:
first circuit means for receiving timing signals in synchronization with the low frequency pulses; and second circuit means for transferring the timing sig-nals through the first circuit means in response to said high frequency pulses, the transferred timing signals being conditioned thereby for use as display inhibition signals.
first circuit means for receiving timing signals in synchronization with the low frequency pulses; and second circuit means for transferring the timing sig-nals through the first circuit means in response to said high frequency pulses, the transferred timing signals being conditioned thereby for use as display inhibition signals.
2. Spurious display inhibition means as claimed in Claim 1 further comprising means for producing a logical product of the display inhibition signals and segment selection signals including means for applying said product to a display.
3. Spurious display inhibition means as claimed in Claim 1 wherein the second circuit means comprise a field effect transistor for receiving the arithmetic mode controlling high frequency clock pulses.
4. Spurious display inhibition means as claimed in Claim 2 wherein the means for producing the logical product comprise an AND gate.
5. Spurious display inhibition means as claimed in Claim 3 further comprising a field effect inverting transistor coupled to the output of the field effect transferring transistor.
6. Spurious display inhibition means as claimed in Claim 1 wherein the arithmetic mode controlling high frequency clock pulses are two differently phased clock pulses and the timing signals are transferred in response to the two-phase high frequency clock pulses.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11952675U JPS5233228U (en) | 1975-08-29 | 1975-08-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1061003A true CA1061003A (en) | 1979-08-21 |
Family
ID=14763451
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA259,817A Expired CA1061003A (en) | 1975-08-29 | 1976-08-25 | Display inhibition means for dynamic multi-digit display in two-speed calculators or the like |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPS5233228U (en) |
| CA (1) | CA1061003A (en) |
| DE (1) | DE2638502C3 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3149521A1 (en) * | 1981-12-14 | 1983-06-16 | Braun Ag, 6000 Frankfurt | Display device for different values |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5247650B2 (en) * | 1971-12-29 | 1977-12-03 | ||
| JPS5319178B2 (en) * | 1972-03-29 | 1978-06-19 | ||
| JPS5439974B2 (en) * | 1973-01-18 | 1979-11-30 | ||
| JPS5093341A (en) * | 1973-12-18 | 1975-07-25 |
-
1975
- 1975-08-29 JP JP11952675U patent/JPS5233228U/ja active Pending
-
1976
- 1976-08-25 CA CA259,817A patent/CA1061003A/en not_active Expired
- 1976-08-26 DE DE19762638502 patent/DE2638502C3/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5233228U (en) | 1977-03-09 |
| DE2638502A1 (en) | 1977-03-17 |
| DE2638502C3 (en) | 1979-03-22 |
| DE2638502B2 (en) | 1978-07-13 |
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