CA1044765A - Broadcast receiver - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
A broadcast receiver having a tuner with a variable local osci-llator for generating a local frequency signal, a divider for dividing the local frequency signal at a variable dividing ratio, a comparator for com-paring the divided local frequency output with a reference signal by which the local oscillator frequency is controlled, a counter having a variable content by which the dividing ratio of the divider is determined for establishing the radio broadcast frequency to which the receiver is tuned, a pulse generator operative to vary the counter content, and a detector circuit for producing an audio signal in response to an output from the tuner., The broadcast receiver further provides with non-voltaic memory device for memorizing contents of the counter at the time when the counter contents change, means for reading out the signal stored in the non-voltaic memory means and presetting the read out signal in the counter when a power source for the receiver is made ON, and a muting circuit for muting the audio signal during the operation of counter for selection.

Description

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, ~4'7165 .. .~ .: .
. ~ BACKGROUND OF THE INVENTION .

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This:inv~ention relate:s to:a broadcast receiver, and more parti~
oularly :to a no~el broadcast~ r eceiver having phase locl~ed circuits j~ memory and display~means.
--escription oS the Prior Art general~ the ~adio wave broadcasted from any desired station :
is sele~ted by varying the 1 ocal: ~requenoy o~ a looal osciUator incorporated `~
in a recei~rer,: As means of varying the local frequency of the abova ~ .
mentioned local osoillator~ it has been well know~i to use a ~ariable conden~
ser, I~ such a ca~eJ if the user does not know the frequency o~ the ra~io

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wave broadcasted from the station, it is impossible to correctly reproduce the radio wave broadcasted irom the desired station~ ior example~ sound in case oi radio receivers and video signal in case of television receiversc As a result, many users must look at the broadcast frequencies of the stations mentioned in the program oi the news papers or magazines or must operate ~ .
the variable condenser oi a tuner so as to search the broa.dcast frequency In this case, however~ the variable condenser is manually operatedJ and as a result~ even ir the receiver is provided with a tuning meter~ a correct tuning is not always possible" Moreover~ it is trouble~
10 some for the us~r to rotate the knob of the tuner every time the turling is .
e~fected"
In order to obviate such a disadvantage a system of detecting the .. .
output of an intermediate frequency amplifier incorporated in the receiver or detecting the output of a detector and hence varying the received condition . ~ . :
in dependence w.ith the output thus detected~ that is9 an automatic tuning system, has been available in market. The receiver adopted this kind of automatic tuning system is often used in an auto-use radio mounted on auto- :
mobiles rather than a house-use radio for use in household, The receiver : ~ adopted the automatic tuning system has disadvantages that search-stop ope-r- .
20 ations must frequently be repeated when many stations are present~ and ;
that a correct tuning is not always ensured, . -l A receiver without interfered by adjacent stations is particularly . .
1 desirous for users who live in a district ~here extremely many stations are : present" The receiver for use in such district is required to have a higher . ::
freque~cy sensitivityO In ~rder to sol~e this problem" an AM and FM
recei~er ~isin~. a phase locked technique has been introduced by Jp Stinehe~fer and J. Nichols wherein the FM synthesizer tuned mainly consists . .:~
of a voltage-controlled oscillator, divider, frequency `:

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" ~3 ., , .~Q'~ J~Si and phase comparator~ and reference frequency generator. The comparator is an element for changing at its output the radio frequency. The divider is an element for determining the radio îrequency~ The voltage-controlled oscillator i3 a local oscillator incorporated in the tuner~, More particularly, -;
the output signal of the voltage-controlled oscillator is divided by the divider~
and the signal thus divided is compared in frequency and phase with the crys-tal-controlled reference signalu The output of the frequency and phase comparator is the controlled voltage for the voltage-controlled oscillator~, - The equation that indicates this operation is gilren by (VCO) = fre~ (t) The output of the frequency and phase comparator forces the equality~ If both sides oî the equation (1) are multiplied by N~ the equation (VC0) fre~- N ~ 0 ~
indicates that frequency may be generated that is integer multiplies of 15 the reference frequency~ The frequency generated is determined b~ the .. . . . .
divide ratio of the dividerO -The FM broadcast band consists of 100 channels with 200 KHz -wide starting at 88~0 ~I~ in U~SoAo The carrier for the first chalmel is o~ 88.1MHz~ and the carrier for the last channel is Of 10709MHzo The ~
divider u~ed in this design is considered as-a down counterO This counter islcaded with the value of the divide ratio on the next clock pulse after the counter has counted down to one. All other clock pulses will result in the ;
counter counting down by one. I~ one state of this counter is used to produce a~ output9 then that output will occur once for every N input pulser where N is the value present to the counter, For better understanding~ consider -an example in which the counter is preset to Iive aQd counts down ~o 1 then repeats the cycle, The counter counts as 54321 54321 etc. M
course~ it ma~ be possible to use an up counter as the diYiderO In thi~
case9 the countcr counts as 12345 12345 etcO
A~ described above~ the osciLlator controlled by the output o~ the ~ ' , ''':

~ 4~5 comparator is capable of generating an accurate local frequency so that it is ~ -possible to effect a correct tuning In this case, however, there may occur a fear that, during the operation of counter~ noise signals are ampliîied by the audio ampli~ier and then reproduced through a loud speaker~ In gene-ral~ such n~ise signals are muted by a muting circuit, the muting circuit being controlled by the output from the intermediate frequency ~ gnal amp~
fier or FM discrirninator. However, even if the output is obtained from the IF ampliiier or FM discriminator, it is not ascertained that the phase-locked - -loop is stable completely.
Such a radio receiver has been also proposed that a broadcast radio frequency signal is stored in memory means or device~ and a tuner i~ tuned to the read out signal from the memory device when the radio signal is used again, However, since a number oi memory devices used in the prior art is voltaic memory elements, after the electric power for the radio receiver is cut off once~ it must be necessary to store the broadcast fre- ~;
quency signal inthe memory device again, In order to avoid such an inconvenience, the inventor of the pre-sent invention proposed to use a non-voltaic memory device in the above-mentioned receiver by Stinehelfer and Nichols. However, with this prior invention, it is necessary after the electric power .
source is cut off once, the pow~r source is made on again that the broadcast station which is new}y received is operated by :, ` a push button.
SU~LARY OF THE INVENTION ::`..... :
It is an object of the present invention to provide a broadcast -recei~er which can positively receive the radio waves transmitted from broadcasting stationsO
It is another object oi the invention to provide a broadcast recei-ver which has provided with means for dividing the broadcast frequency band into a number of sections and means for select~g a frequency band of a desired sec ion by the phase-locked technique a~d produces an audio . .
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signal during time when the phase-locked loop is operative,, It is a further object of the invention to prov;de a broadcast receiver which has provided with a divider for dividing the broadcast frequency band into a number of sections and means for supplying pulse 5, signals to the divider to drive the sasne in accordance with the pulse signals~
whereby an audio signal is reproduced therefrorn during the time interval within which the pulse signals are applied to the divider and also during a predetermined time period after the supply of pulse sign~ls to the divider is stopped as to achieve the muting operation positively.
- 10 It is a further object of the invention to provide a broadcast receiver convenient in handling which has provided with memory means for storing received frequency signals~ a switch for station selection~ and non-voltaic memory means for storing therein the content of station select counter in accordanoe with the change of contents and in which after an electric power source is cut off once~ the electric power source is made on again~ the read out signal from the non-voltaic memory means is used ;; to drive the station select counter for selection of stations to receive immediately the broadcast wave which was transmitted from the previous station ~ithout operating the station-selection switch.
It is a yet further object of the invention to provide a broadcast ` receiver whioh can receive a broadcast frequency wave~ which is not stored in memory means~ positively.
It is a still further object of the invention to provide a broadcast receiver which correctly receive broadcast frequency sign~l, with no error operation~, . . In accordance with the fore~oing objects, there is ~ .
provided a broadcast receiver comprising . . .
a~ a front end having a variable local oscillator ~ -for generating a local frequency signal;
b) a programable divider consisting of dividing means and a ,'`, ' ' ':, ' . . ~ .

, ~ . . :

counter~ said dividing means operating to div;de said local fre-quency signal in response to contents oi said counter; . :
c) a pulse generator for producing a pulse which change the content of said counter;
d~ a comparator for comparing the divided local frequency signal derived from said programable divider with a reierence signal to produce a control signal to which said iront end is tuned; . :
e~ means for converting an output signal from said front end to a low frequency signal and then delivering said low frequency , . .
signal to output means; : :
f) a muting circuit connected to said means delivering said low frequency signal; and g) means for controlIing said muting circuit such that sflid low frequency signal is not delivered to said output means during ~ .
a.time interval in which the content of said aounter is changed by the pulse from said pulse generator. i ~

The additional aDd other objects~ features and advantages o~ the . : ~ -present in~ention will be apparent from the following description taken in .
conjurlction witb the accompanying drawing," ;; ~
BRIEF DESCRIPTION OF THE DRAWING :; :
Figure 1 is a block diagram showing the essential component of , ~ : ;

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a broadcast receiver according to the invention;
Figure 2 is a block diagram of the station select counter and divider shown in Figure 1;
Figure 3 is a table showing the relationship among the fre quencies of the several stations of the broadcast band~ di~iding ratios~
and c:ontents of the counter that correspond to such stations;
Figure 4 is a circuit diagram showing connectiDns among the ;.
decoder of Figure 1~ the detector circuit for switches of the display panel and the circuit for producing address signals;
;; t0 Figure 5 is a circuit diagram showing connections between thedecoder of .Figure t and the circuit for producing address signals;
Figure 6 is a circuit diagram of a memory made up of the memory .
element~ arranged to form a matrix;
Figure 7 is a graph uhowing characteristic curves of the memory elements;
Figure 8 is a diagram of a memory control circuit îor controlling ~ -the memory shown in Figure 6;
Figure 9 is a plan view Or a panel display device for use in the ~ .:
broadcast receiver according to the invention; ~ . .
Figure 10 is a cirouit diagram of the panel display device;
P~igure 11 is a diagram Or a memory. circuit for storing the - :
content Or the counter and for driving the counter together with a muting control oircuit for controlling the muting oircuit of Figure 1; ~ :
. . Figures 1 2A to 1 2D are waveform diagrams used ~or e~:plaining 25: ~ the operation of the muting signa} control circuit shown in Figure 11; ~ .
. ~ Figure 13 is a circi~t diagram of the mutin~ circuit shown in , ~ : , i. . ~: .
, Fi6~ure 1;
Fi~ure 14 is a front view of the broadcast receiTer o~ the i~ven~
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, ~ion;
;' 30 . Figure 15 is a con~eotion diagram o~ a push button group show~ .

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in Figure 14;
Figure 16 is a logic systematic block diagram of the control oircuit shown in Figure 1; and Figures 17A to 17K, 18A to 18D, 19A to 19I, and 20A to 20Ig inclusive~ are waveform diagrams used for explaining the operation of the broadcast receiver of the in~rentionO
DESCRIPTION OF THE PREFERRED EMBODIMENTS
- The invention will now be described in detail with reference to `
an embodiment thereof applied to an FM receiver~
As shown on FiglLre 1~ in such an FM - recelver~, radio waves broadcast from a number Or stations are received by an antenna AT whose output is supplied to a front end 1 which includes a RF amplifier~ a voltage-oontrolled local oscillator and a mixer. The voltage-controlled osoillator of front end 1 has a variable capacity diode and is adapted to change its o~cillating frequenc~ in response to changes in the level of a control voltage within a range~ for example~ from98"8 to 118~6MHz To the ~ront end 1 are connected~ in order~an intermediate frequency amplifier 2~ an FM
discriminator 3~ a mutin~ circuit 4~ and a stereo multiplexer 5 having output terminals 5R and 5L from which are obtained a right stereo signal and a .;, . . ~0 le~t stereo signal~ respectivelyO
I~ general~ the oscillating frequency of the voltaga-controlled local oscillator of front end 1 is extracted and divided~ and the resulting divided signal is compared ie} fraquency and phase ~vith a reference signal.
The compared output is fed back to the local oscillator as a control ~oltage -25 therefor so as to select a desired station, In practice~ the frequency band , j , i~ o~ the local osc~1lator output is a VHF band so that the local oscillating ., . ~, .
output is~ in tha first place~ su~plied to a mixeP 7 through a buffer amplifier 6 and to a 2 divider 8 so as to ef~ect frequency demultiplication a~cl then ~upplied through a programable divider Pl) consisting of an N divider 30 and a ~tation seleot computer 18 to a freque~cy and phase comparator 1V.

-- 8 -- ~
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-~L~,7~5 The mixer 7 is supplied with the output of an oscillator 11 consisting of a crystal oscillator through a frequency doubler 12~ and wh;ch has a suitably selected frequency~ for example, 60MHz, so that the mixe:r 7 is supplied with a frequency Or 120MH~o The mixer 7 feeds to the divider 8 the frequency difference between the frequency of the local oscillator in front end 1 and `
the frequency doubler 120 The frequency and phase comparator 10 receives : .
the oscillating output9 for e2cample~ with a frequency of 100KHz~ generated by a reference signal generator 13 and supplied to comparator 10 through a Schmitt trigger circuit 1~, The frequency phase comparator 10 produces . ~ -a direct current voltage output depending upon the phase difference between the two input signals from divider 9 and circuit 14~ this direct current ~ : -voltage being emp~oyed as the control voltage of the local oscillator in .
~ront end 1 for determining the oscillating ~requency thereof~, The above mentioned circuit arrangement is well known~ and therefore its details will not be described.
. .
the stable state of the phase-locked-loop for effecting the ~requency comparison~ the following equation~ results from the above values for the frsquencies of the outputs of frequency doublei~ 12 and reference 8ignal generator 13:
; . _ 1 20MHz ~ fL
2N ~1 00KHz . o . ~ o t3) where fL is the o~cillating frequency of the voltage-controlled local osoi~
,, ~tor in front and 1~, Equation (3) can be rewritten as: -fL ~ 1 20 - 00 2N rMHZ ~ 4) Thus~ if the divide ratio N of the 1tN divider-9 is changed over the range from 7 to 106~ fL can be changed from 118.6 to 9808~Iz i~ steps oi~ 200KHZ., ~ ; :
example o~ the--N: div~der 9 will be SlOW described with . :
: , , , re~erence to Figure 2" In Figure 2, reference numex~al 8a indicates a . , " .
.~ tern~i~al to which the pulse signal ~rom the 2 divider 8 is applied~, The : ~
, ~ :

3 t) pulse signal is then applied to decimal counters 1 5a~, 1 5b and a binary colmter .
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_. _ . _ . _ .. _ .. .. : ....... . , , . . ~ . . ., . . .... .. , ., . ,, , , ,, , . ,, , , , ", _ __ , _ , 15c, respectivel~. The output~ ~rom t~ counters 15a, 15b and 15c are supplîed to a discriminator.l6 ~hich discriminates or detects : ~ .
that the outputs ~rom the counter~ 15a, 15b and 15c are a decimal number of a predetermined nUm~e. The output from the discrimin-ator 16 is ~pplied to a gate circuit 17 to control the latter. In : :
other ~ords, when the outputs ~rom counters 15a, 15b and lSc are .~ -the predetermined number, the gate circuit 17 is.opene~ or con- ;
ductive through which the conten ~ of counters~;l8a and 18b, which ...
form a station selection counter 18, in accordance ~ith the re~ :
`( 1~ spective figures of counter 18 are set~in the counters 15a, 15b and 15c, respectively. In thi~ case, since the contents of station .~.:
selection counter 18 is two fi~ures as ~ill be described Iater, the binary counter 15c is al~ays reset by the output from the ...
discriminator 16. Further, since the station selection counter 18 is suficient to count from ~00] to 19~, it includes two stages ~ .
I of counters only. Next, w~en the contents of counters 15a, 15b and .:
J 15c reach the predetermined numbers, respectively~, ~he opera~ion .:.., ,:
described above will.be repeated. In th;s case, the content of 1 sta~ion select counter 18 is~determined by the numher o~ station .i 2Q select pulse~ produced by a control circuit 20 (refer to Figure 1), which includes a pulse generator, in synchronism with clock pulses ;, for operating the counter, the station select pulses being i supplled through a terminal 2Qa.. to the counter 18.
. Thus, when the.~ ~ signal, which is formed by sub-~ tracting the content oi station selection counter 18 from the pre- .
-~ determîned num~er ~106], is applied to the terminal 8a, one pulse signal.is obtained at an output terminal 16a of discriminator 16. ... ~.
Accordingly,~the:divide ratii~ N of l ~Ivlder 9 can be determined .~-~y t~e content of station select counter 18.
J 30 In this em~odim~nt, the:c~ntent of station s~ect ... ;.~
~ counter 18 is determined:to satis~y the following equation for the ~:

, : respective received freque~cies o~ ~M broadcast waves. . :.
lContent of counter 18] ~ 'El06] - Idivide ratio.. N~
; The relationship among the div.ide xatio~ N, the content .
of station -la-..
select counter 18 and so on for the respective received frequencies can be shown in the table o~ Figure 3a By way of example~ in the case where an FM broadcast wave of 88.1~Iz is received~ if the station select pulse signal is applied through the terminal 20a to set the station select counter 18 at the content of CO~
when the pu}se signals from 2 divider 8 becomes to the predetermined number or 106~ the gate circuit 17 is opened to set the counters 15a9 15b and 1 5c to be~ 000~1~ respectively~ and one pulse signal is obtained at the .
: - terminal 16aO Next~ whenthe contents of counters 15a, 15b and 15c becorne to 106~ one pulse signal is again obtained at the terminal 16a~, Similarly5 ~ ~
when lQ6 of pulse signals are fed through the terminal 8a~ one pulse signal ~ :
is obtained or the pulse signal applied to the terminal 8a is divided to ~.
It FM broadcast waves of other frequencies ~8802MHz to 10709MH i) :
are desired to be received~ the station select counter 18 is set at numbers corresponding to the desired FM broadcast waves to be received~ similarly, Further~ if the content Gf station select counter 18 is varied from C 1. to t 99~ ~ sequentially~ the sweep can be achieved through the received fre-quency band from 8801MHz to 107~9MHz"
The dr~ing signal for MHz-figure o~ a panel display device 47 whioh wlll be described later and the address signal in the X-direction for memory means or devices 29 and 30 are formed of the output from the I0-figure oounter 18a in the station select counter 18 (~-figure of received frequency)0 .~ - The content of station select counter 18 ~is applied to binary~
decimal decoders 21a and 21b~ respectively~ and therein converted to the ; ::
deoimal output. The decimal output thsrefrom is applied to the non-voltaic -: :
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memory device 29 and to the panel display device 47 as the address signalO ~ :
The memory device 29 memorizes whether chalmel the broadcast wave belong to~ while the panel display device 47 displays it visuallyO The display 30 devica 47 includes a switch. Whenthe switch of display device 47 is operated~;- , , , : , ,'"
'' ' ' - 1 1 -- ; ' , 6~ii , . .
a stop signal is applied to the pulse generator of control circuit 20 to stop the apply of station select pulses to station select counter 180 Thus~ the reception is achieved thereO
With the present invention~ during the time interval when the ~:
above-mentioned phase-locked loop is operated or the station sielect pulse is applied for searching the desired broadcast waveJ means such as a circuit 76 which will be described later is provided for making the muting ~ .
circult 4 operative~ so as to stop the appearance of undesired signals at the output terminals 5L and 5R duringthe broadcast wave searching"
Further~ a non-voltaic mamory means or device 56 is provided ~ ;
for memorizing the content o~ counter 18 at every time when the content Or oounter 18 changes.~ so that when the pow~er source is cut off once and thereaiter the power source is made on~ the broadcast wave which was received previously is received immediately9 From the above description~ the outline of the present inrention 1 will be understood4 j Parts of the present invention will be now described in detail f with reference to Figure6 4 to 16~ sequentially~, . .
In Figure 4~, reierence numeral 21a indicates the decoder which : 20 convert9 the content applied from counter 18a as a BCD code to a decimal numberO ~he decoder 21a has ten output terminals and one oi the ten output terminals from which a decoded output is obtained is formed as OV (zero ` .
Yolts)O This output termiQal7 for example, the output terminal from which ~ : :
.the decoded outputCOl is obtained is connected through resistors 22 and 23 25 to a power source terminal Vcc with~, ior e~nple~ +180Vo The connec-tion point between the resistors 22 and 23 is co~Qected to the base electrode . o~or example~ a PNP-type trRnsistor 2~ and to its emitter electrode through a dliode 25 with the polarity shown in the ~igureq The collector electrode of transis~or 24 is led out as a driving terminal IJO ror the MHz-figure of the ~- 30 pallal display device 47 and also as a X-address teriTIinal X~ for the memory ',"' ~
--~2 -~o~
devices 29 and 30 after being divided by resistors 26 and 27. The other output terminals C1~ to~9~of decoder 21a are similarly connected with cir -cuits and led out as driving terminals L1 to L9 and X-address terminals X
to Xg~ respectively. The emitter electrodes of transistors 24 connected to the respective output terminals of decoder 21a are connected together to a point P to which a predetermined voltage is applied for Idriving the panel display de~ice 47~ The point P is connected with a detector circuit 48 for detecting the operation of a switch provided in the display device 47~ The detector 48 will be -described later in detail With the circuit construction shown in Figure 4~ if the C 0~ output ;~ terminal OI decoder 21a~ for example~ becomes to OV and the other output i . ~ .
terminals become to 60V~ only the transistor 24 connected to the C 0 ~ output terminal is oonductive. At this time~ the Yoltage at point P becomes to 140V and hence DC voltage of 140V is generated at the driving terminal Lo Or display device 47~ while DC voltage of 30V is generated at the X~
addrei is terminal X0 of memory devices~ Similarly, as the content of station -select counter 1 8a is changed~ the predetermined voltages are generated at the driving and X-address terminals sequentially.
The binary output from the counter 18b of 1-Iigure (100~CHz) in the station select counter 18 is applied to a decimal decoder as in the case Or decimal decoder 21aO In Figure 5~ reference numeral 21b indicate the above decoder. The~ 0 ) output terminal of decoder 21b~ by way of esample, i9 connected to the base electrode of a PNP-type transistor 28 the emitter ~ . .
electrode of which is supplied with a voltage of 1 5Y from a power source terminal Vcc. When a decoded output is derived from the~ 0~ output termi~
; nal o~ dec oder 21b~ it becomes to OV from 60V to make the transistor 28 ; ;
conductive and hence an output ol 1 5V from the power source Vcc appeiars at the collector electrode of transistor 28, The output of 1 5V is applied -: . , . -to a Y-address terminal Y0 of memo~r devices 29 and 30!~ respectivel~O The memory de~rice 29 consi ts of memory member~ 29a and 29b each of whis~h has . ~ 1 . , .

provided with non-voltaic memory elements such as MAOS elements arranged in 5 rows and 10 columns to form 100-bit one as a whole~, Similarly" the other memory device 30 consists of memory members 30a and 30b with non-voltaic memory elements arranged in 5 rows and 10 column.sO The memory device 29 is automatica1ly written with contents~ while the other memory deri¢e 30 can change its content as a desired one~ The Y-address terminals of memory members 29a~ 29b~ 30a and 30b are connected commonO
The X-address terminals Df memory member 29a in memory device 29 and memory mem~ber 30a in memo~y device 30 are supplied with the :
X-address signal obtained at the terminals X0 to X4 which are produced as described in connection with Figure 4~ while the memory members 29b and 30b are supplied with the address signals obtained at terminals X5 to X9, In the example of Figure 5, read-out terminals for the memory s devices 29 and 3Q~ and so on are omitted for the sake of brevity, As in the case of ~ 0~ output terminal of decoder 21b~ the other output terminals thereof are connected with PNP-type transistors 28~ :
respectively~ and thair collector electrodes are connected to Y-address terminals Y1 to Yg of memory devices 29 and 3Q~ respectively~ The collec~
tor electrodes of transistor 28 are grounded through a series connection o- resistors 31 and 32~ respectively~ and the connection point bstween resis-tors 31 and 32 is connected to the base electrode of an NPN-type transistor 33~, The collector electrodes of all the transistors 33 are led out as driving :
terminals No to Ng for 100KHs-Eigure of panel display de~rice 47 and the emitter electrodes of transistors ~33 are grou~ded through the collector-1 25 emitter path of a transistor 34, A terminal 35 lèd out from the base electrode of transistor 34 is supplied with a contxol signal of high level which is produced by the control circuit 20 ba~ed upon th~ read out output from the memory device 29 or 30. That iS9 unless the transistor 34 is made ON by the co~ltrol signal~ even ii the decoded output is produced at any output -!
terminal of decoder 21b~ the transistor 33 corresponding to the output ter-., .
minal is not made ON, As a result~ no driving signal for 100KHss-figu:re of panel display device 47 is applied to1, ~. :

L~ 7 ~; 5 A practical embodiment of 9 for example~ the memory member 29a will be now described with reference to Figure 6, As shown in Figure 6 Q11' Q21'-~- Q510 are arranged in 5 rows and 10 columns or a matrix to form a memory member of 50 bits. To the X-address terminals X0~ X1~ ~- X4 there are connected the gate ellectrodes of MAOS
elements (Q11~ Q12~ Q110)~ (Q21~ Q22~ ' Q210)7 (Q51~ Q52 Q510) in the respective rows commonly, while the Y-address terminals Y0~
Y~ Y9 are connected to the gate electrodes of junction type field effect transistors (which will be hereinafter referred as to FET) Ty0~ Ty1~ ~J~
Ty9~ respectivelyO The source electrodes of FETs Ty0~ Ty1~ ~o-~ Ty9 ~:
are grounded~ respectively~ and the drain electrodes oî FETs Ty0J Ty1~
Ty9 are connected to the source electrodes of MAOS elements Q11~ Q21~ ~9~ ;
Q51; Q12~ Q52; -~ Q110J ~4~1 Q510intherespectivecolumns~ commonly~
. The drain electrodes of MAOS elements in the respective columns are .. . . .
connected together and then to the gate electrodes of FETs T10~ T
Tloo~ respectively. The FETs T10, T20~ o-~ Tlo~ are connected in series and the source electrode of FET T100 is groundedO The drain electrode of FET T10 is connected to the gate electrode of FET T1 and to a power source termi~al VDD through a load FET T2. The ~ource electrode of FET Tl is grounded and its drain electrode is connected to a read-out ;~ ~ terminal 36 and to a power source of 5V through a resistor, The connection po~nt~ of drain of the respecti~e MAOS elements in the respective aolumns ;~ are connected to the power source termi~al VDD through load FE$s T3 and ; ~
.~ to the drain electrodes of FETs T49 ~3 T13 provided îor the respective ~:
columnsy respectively. The source electrodes of F:ETs T49 o ~ T13 are I ~ grounded and their gate electrodes are connected together to an erase J terminal E~1 " As an example of a suitable non-~oltaic memory element~
melltion may be made o~ a field effect element~ for e~ample~ a MAOS element~
having a gate constructed o~ mult-layered insulation films for shifting the threshold voltage before and after the voltage is app~ied to the gate~, W;th ,' ' ' ' ~ ~ ' ' :

' , . . ... ~.

J~o~ s such a MAOS element9 as shown in Figure 7~ the drain current begins to flow from the first threshold voltage V1 at the gate voltage of ~ for example9 2V~ and if the critical voltage, for example, a voltage higher than 22V~ is applied to the gate electrode the threshold voltage is shifted. This pheno menon occurs at both positive and negative critical voltages~, That is9 if the gate voltage is increased to values higher than the positive critical voltage~ the threshold voltage is g~adually shifted in the positive direc tion9 while if the g~te voltage is increased to values higher than the negat;ve critical voltage~ the threshold voltage is gradually shifted in the negative direction" The second threshold voltage V2 shown in Figure 7 is the threshold voltage produced when the positive voltage of 30V~ which is higher than the .:
; oritical voltage~ is applied to the gate electrode~, ~Vhen the threshold voltnge i~ shifted as above described~ it is not changed even when the .:
voltage applied to the gate electrode is removed., The second threshold ..
: ~ : 15 voltage V2 may be restored to the first threshold voltage V1 by applying a voltage higher than the negative critical voltage~ for example~ a voltage of ~ .
-45V~ to the gate electrode~ If the voltage Vr which is substantially inter-mediate between the first threshold voltage V1 and the second threshold voltage V;2 of the MAOS element1 for example~ a ~roltage of 10V, is ~pp1ied to 20 the gate electrodel it is possible to a9certain the condition of the MAOS ~. .
element by the presenoe or absence of the drain current~, If this voltage Vr . .:
(10V) is used as the read out voltage~ the first threshold voltage V1 and the second threshold voltage V2 csn be made as the conditions correspond-ing to C 0~ and ~ respectivelyO The voltage (~30V) higher than the :. .
25 positive critical voltage in order to obtain this oondition C 1~ may be used as : : ~
. .
` .the write voltage" and tbe voltage (-45V) higher than the negative critical . voltage in:order to restore .the ~OS element to the conditionC 0~ may be ~: used as the erase Yoltage) and therefore~ the MAOS element may be usecl as : ~ an erasable memor~ element, .
~`. 30 Smce such MAOS elements are connected as men~;oned abo~re~ the . . ' :

.. . . . .

'76~
X-address signals which are produced by decoder 21a are isupplied to X-address terminals X0~ X1~ ~o-~ X4~ respecti~ely9 to achieve the sci nning in the row direction~ while the Y-address signals produced in the decoder 21b are supplied to Y-address terminals Y0~ Y~ Y9~ Thus~ write in~ read out and erase operations are carried out by varying the level of X-address signals~ ~
When the memory 29a is in inoperatiYe condition, the X-address ~ ;
terminals X0~ X~ X4 are 0V and the Y address terminals are opened~
While~ whenthe memory 29a is in write i[l and read out conditions~ the :~
erase terminal E1 is made 0V~ so that the FETs T~ ~ T5~ oo-~ T13 are in .
OFF-stateO Now~ if a pulse signal of 30V is applied to the X-address terminal X0 and a pulse signal of 1 5V is applied to the Y-address terminal the FET Ty1 is ma~le ON~ the FETs T10~ T20) ~- ~ T100 are OFF and the MAOS element Q11 is supplied with a voltage of 30V at its gate . ~:
~5 electrode~ Thus9 "1" is written in the MAOS element Q11 In the case .
where a pulse signal of 13V is applied to~ for example, the X-address ter-minal X0 and a pulse signal of 1 5V ia applied to the Y-address terminal Y0, ir the MAOS element Q11 is 'i1"~ no drain current flows~ so that the FETs T10~ T20~ T100 are made ON and consequently the FET T1 is rnade , 20 OFFo Thu~l~ an output o~ 5V is obtained at the read out termillal 36 from the ;:
:. power sourbe terminal VDD. On the contrary, if the MAOS element Q11 is 1l01l? the drain current ~lows to make the FETs T1o~ T20~ o-~ T1oo OFF ~.
and hence the FET T1 is made ON to make the read out terminal 36 0VO
In the case of erasing the stored content in the memory 29a~ a signal Or ~ov is applied to the X-address terminals sequentially and a sign~
of 1 5V is applied to the erase te~ al E1 0 Accordingly, the FETs T ~
T5J ~ T13 co~ected to the respeotive columns are all made ON. Ihus~ . .
at the time when the supply of 40V pulse signal to the X-address terminals i8 stopped~ the content stored in memory 29a is erasedO The reaso~l why :
~ 90 the drain eleotrodes of all the MAOS elements are made to be the ground voltage ~ .
"' ~ ' ' , . , ~.. :' --17 ~
,' ' ' . ~ . .
- . - --_, ,.. , .. , ........ , . ~,~,, 7~

from 1 5V upon erasing is to avoid the damage OI MAOS elements by expess vol-tage applied across their gate-drain electrodes when a voltage of -40V is :~
applied to the gate electrodes ~
With the memory 29a9 the le~el of signals applied to the X-address terminals XO~ X1 ~ o ~ X4 are varied in accordance with write~ read and erase operations, as mentioned above. In the present invention, a memory control circuit 38a which may be described later is provided to simplify the i ~
construction of whole memory device~ ~ :
The other memories 29b, 30a and 30b are constructed similar to that 29a and memory control circuits are also provided for memory de~ices ;
,, 29 .and 30"

An embodiment of the memory control circuit 38a for the memory device 29 will be now described with reference to Figure 8~, As shown in Figure 5~ the X-address terminals for the memory . ..
. .
15 device 29" by way o~ example, are connected through resistors 41 an.l diodes ~ :
il to an output terminal M1 of memory control circuit 38a9 The memory con- ~:
trol circuit 28a has provided with control terminals 37a~ 37b and 37c so as to control the operative condition of memory device 290 The control terminal 37b aots to control the operation and inoperation of memory device ~290 20 That is~ the terminal 37b is in the ground potential during operation~ but in a predetermined positi~Te potential during inoperation~ In other words, when the predetermined positive voltage is applied to the control terminal 37b,, the output terminal Mt is grounded through a diode and an NPN-type tran4istor 39 which is made ON~ a~l the X-addres~ termirlals XO - Xg are . ~5 . ~5rounded~ and the memor~r device 29 is made inoperative" The control ter-~: minal 37a is used to control the write in and read out to the memory device:.

. ~, ~ ; . .
`' . 29~ That is~ :when the control terminal 37a is made at the ground potential~

~-I an NPN~ype transistor 40 is made ~OFF and the Xvaddress terminals is . put islto a level of 30V witAout being attenuated" On the contrary~ when the : ;

~30 control te~ al 37a is made at a positivè potential~ the transi~;tor 4:) is ~

:. . .
- --~8-- . : .

765 ~ ~
made ON and the X-address signal becomes to ha~e a write in level o~, for . ~:
example~, 13Y which is divided by the resistor 41 inserted into the X-address signal supply line (refer to Figure 5) and a resistor 42, Further~ if the ~ ~
control te~ninals 37a and 37b are opened and the control terminal 37c is ~ -supplied with a positive voltage of 1 5V, the erase terminal E~ is made at . 15V and NPN-type transistors 43 and 45 and a PNP-type transistor 44 are made ON Thus~ the output terminal Ml is connected to an erase ~oltage . ~ :
.; supply terminal 46 to which an erase voltage of -40V is applied~ and hence the X-address sign~l becomes to -40Vo In Figure 5~ the output terminal of a memory control circuit 38b ror tho memory device 30 is shown by M2 and its erase terminal is shown by E2-In the pre~ent invention~ the display devioe 47 is used in oorres-; pondence with the mernor~ device 29 or 30O . :
~15 An example of panel display device 47 will be now described with :
reference to Figure 9. The panel display device 47 consists of a common . ~;
base plate and lamp switches Loo, Lo1/ ~o~ L49 disposed on the base plate .: -the number of which is the number of received frequencies or 100 and which ~:
are arranged in a matrix of 5 rows and 20 columns The lamp switches correspond to the received frequencies by 1 ~
The lamp switches Loo~ Lo~ L~.9 L~tersections of 10 lines led out from the 10 driving terminals No to Ng s for 100KHz-~igure and 10 lines led out from the 10 driving terminals Lo to ` : .
L9 for MHz-figure. That is~ series oonnections of neon lamp P0 to P99 ~:
and resistors are colmected between the two line groups~ a~d series con-ne~tions of push button switches S0 to S99 and~resistors are connected in ~ .
parall~lto the former series connections~ respectively~ as shown in Figure - ~.
10,, As described just above9 the eleotric. conn~ctions are made of 10 rows ~ and 10 columns~
. :
A~ mentioned previously~ the driving terminals Lo to Lg are ~: :

19~ ~ . :

s :~
sequentia~ly supplied with the outputs which a3 e made by decoding the contents stored in the counter 18a of the station select counter 18 for 10~unit ~Iz-figure) shown in Figure 4 and the level thereo~ is the potential at the point P in Figure 4 or about 140V~ While~ the driving terminals No to Ng are sequentially supplied with the outputs which are produced by decod-ing the contents stored in the counter 18b of station select counter 18 for 1-unit (100K~Iz-figure)3 as shown in Figure 5. The outputs are the ground level (0V) ones~, Accordingly, when the contents of station select counter 18 is changed from C J to~ 99;1 or the receiving frequency band from 88~,1 MHz to 10709MHz is swept in synchronism therewith~ the neon lamps P0~, F'l 3 P2~-o~ are lit sequentially in this order. In this case~ on the assumption that in correspondence with the respective neon lamps the read out output of the memory ~ is supplied through the control circuit 20 to the terminal 35 (refer to Figure 5)~ the neon lamps are litq The fact that any one of switches S0 to S99 is pushed down is detected by the detecting circuit 48 shown in Figure ~O That is5~ when any one of switches S0 to S99 is made ON as shown in Figure 109 the load in~
serted between the driving terminals~ Lo to L9 and the ground becomes low as compared with that when the switches S0 to S99 are OFF~ and hence 2~ the potential at point P is lowered~ whioh fact is used to detect the pushing down the switch.
When any of switches S0 to Sg9 is pushed down to lower the pote~tial at point P abruptly~ the base potential ~ a PNP--type transistor 49 i8 also lowered abruptly" Howe~er~ since a oapacitor 50 is conneoted to the emitter electrode of transistor 49~ the emitter potential thereof is kept at the potential of the power source voltage divided by resistors 51 52 and a ~ariable resistor 53 for a short time period9 Accordingly~ the ~an~stor 49 is changed îrom OFF-state to ON-state for a predetermined time period~ and consequently an NP~-type transistor 54 is made ON.
The emitter electrode of tra~lsistor 54 is grounded and its collector electrode .

`~l :
~Q~'~76~
isf connected to a detecting terminal 55. The detecting terminal 55 is changed from the open-state to the ground potential for a predetermined time period `~ fwhen the switches are pushed down.
As shown in Figure 10~ in an embodiment of the invention~ common - 5 co l~OtS Mo~ hS1 - c ~ ~ . Mg are provided on the panel display device 47 for ~ ;~
every set of 10 lamp switches~, By way of example~ the contact Mo is ~ormed to be closed when any one of the lamp switches on the first and second columns is pushed downO A terminal C1 is connected in common to the contacts Mog M~ Mg at their one terminals~ and a terminal C2 is con-nected in common to the contacts MoJ M~ M9 at their other terminals. ~
Thus~ when any one of switches on the panel display device 47 is pushed down ;;to be ONt the terminals C1 and C2 are short-circuited~ A signal produced by the short-circuiting of terminals C1 and C2 is supplied to the control circuit 20 to initiate the generation of station select pulse and to light all f -the neon lam~s. Thus~ it becomes possible that a switch corresponding to ~ -~
;, :. ..
f any Or neon lamps is pushed down to receive the frequency signal corres-ponding thereto . ;` ! ~
It will be noted that, with the present invention a memory device ~ `
56 ror memorizing the f~tation which is received now isf Fovided in addition 20 to the memory devlce 29 or 30 of 100 bits and the display device 47 with 100 '~ , lamp~J ................ ' ' ;`' `
; f An example of the memory device 56 will be now described with ~
,~ .
reference to Figfure 11. Ill order to memorize the received station it is 8u~fioient to 9tore the contents in the counters 18a~ and 18b of station select 25 - cofunter 18 at reception. In Figure 11~, reference symbol Q1 indicates a f M~OS element for storing the first bit of counter 18a<, Simil~rly9 three `~; . : -1 ~ ~ MAOS elements which may store second~ 1hird and fou~th bits of counter 1 8a ~ ;
and four MAOS elements which may store first to fourth bits of counter 18b are provided. Further~ a ~AOS element Qg is ~also provided which memoriz;es 3~ that ~ny one of memory dev~es 29 and 30 is operated, .. . . . ....
- 21 ~

:
.. . : .
.

Ths source electrode Or MAOS element Ql is grounded and its drain electrode is connected to a power source Vcc1 OI 5V and to a preset . ~
terminal of first unit counter 18a in the station select counter 18. At the ;: ~ :
drain electrode of MAOS element Q1 there is obtained an output o~ 5V if the element Ql is ~'0"~ but an output of OV if the element Q1 is "1~ at the , time when the read out output is produced, The gate electrode of MAOS ; .:
element Q1 is connected through a diode and a variable resistor 57 to the colleotor electrode of an NPN-type transistor 58 the emitter electrode of -which is g:rounded and further to the collector electrode of an NPN-type ~transistor 59 which is connected at its collector electrode to a power source ;:
terminal Vcc2 of 35V and at its emitter electrode to a power source Vcc3 of ~QVo The base electrode of transistor 59 is connected through a resistor to it9 emitter electrode and also through a resistor to the collector electrode v~ a PNP-ty~e transistor 6Q" The base electrode of transistor 60 is supplied .i 15 with the output from the counter 18a corresponding to the first bit and con-neoted through a diode 61 to the collector electrDde o~ a PNP-type transistor 62, The elriitter eiectrode of transistor 62 is connected to the power sourc e -Vcc1 and its base electrode is connected a resistor and a diode to the collec-tor electrode or transistor 58~
The other MAOS element9 or seven MAOS elements are similarly connected and their read out outputs are supplied to the preset terminals : of counters 18a and 18b~ while their write in outputs are derived from therespective bits of counters 1~a and 18bV As mentioned previously~ the ,1~ outputs Or oountera 18a and 18b are al90 supplied to the counters 15a~ 15b ~ ~ :
: 25 and de¢oders 21a and 21b, respectively. :: ~.
A manner how to co~trol, ~or e~ample~ the MAOS element Q l .
or how to write ~ or ~0~ will be now described~ When erasing~ ~o ~ran-,.;: - : .
ai~tor 58 is mada OFF and hence the transistar 62 is made OFF~ the `:
fir3t ~lt output of the~counter 18a is ~ 5V), the transistor 60 i~ made C)FF
30; ~ and co~equently the transistor 59 is made OFF with the result that the gate ~: -, 3~

. .

~' >~6S
electrode of MAOS element Qt is supplied with ~oltage of 35V from the power source Vcc2 and hence "1 " is written in. On the contrary, if the first bit output of counter 1 8a is "0" (0V), the transistor 60 is made ON and hence the transistor 59 is made ON with the result that ~he gate electrode of MAOS
element Q1 is supplied with erase voltage of 4-0V from the power source Vcc3. When reading out, the transistor 58 is made ON to make the tran-sistor 62 ON but the transistors 60 and 59 are made OFF. At this time the gate electrode of MAOS element Q1 is suppLied with voltage of 13V
which is made by dividing the voltage of 35V from the source Vcc2 with the resistor and ~ariable resistor 57 to achieve the read out operation. The same control is also performed to the other seven MAOS elements.
L~ this case, in order to memoriæe the station which is now received in the memory 56~ the transistor 58 is made OFF when receiving only. To this end~ a station select pulse shoun ir Figure 12A is applied througha terminal 2Qb to the base electrode of an NPN-type transistor 63 to produce ~ , .
at its collector electrode a phase-reversed pulse shown in Figure 12B~, -The phase-re~ersed pulse is appLied to the base electrode oî a transistor 64, ~ The station select pulse is a repeating pulse with a predetermined period during station select operation~ but upon reception the sweep is stopped and hence the pulse becomes to such one with a predetermined level~ If an integrating circuit consisting of a resistor 65 and a capacitor 66 is connected between the collector electrode OI transistor 64 and the ground~ an ;1 output shown i~ Figure 1 2C is obtained which is applied to the base electrode - o~ a PNP-type transistor 67~ Where~ ir the time constant o~ the integrating -i 25 cirouit i8 selected suitably~ the output level of tha integrat~g circuit is not m~Lde ~u~ricient to make the transistor 67 ON upon selection b~t made suffi-ciellt to make the transistor 67 ON upon reception with respect to the repeated pulse. Acco~dingly~ if the txansistor 67 is cor~ected ~vith an NPN-type .. , - ~ . :
, ~ ~ tran~i3tox 68~ at a terminal 69 led out Y~om the ~ollector electrode oY tran-30 sisto~ 68 there is obtained a signal shown in Figure 1 2D which become~; o~r .~:~ , .
;~ ' , , ~ ,' '. . .
~ --23 --'": . . , ' '. ', '. ~

at a time delayed by a time interval t1 fromthe signal reception~ The signal shown in Figure 1 2D is used as a signal for controlling the muting circuit 4 so that the above circuit will be referred as to a muting control circuit 76 v :
The signal obtained at the terminal 69 is phase-reversed by a transistor 70, then differentiated and supplied to the trigger terminal of a monostable multivibrator 71 which produces a square waveform Or about ~ .
100 ms (milli-seconds~ This square waveform is phase-reversed by a transistor 72 and then applied to the base electrode of transistor 58~ Thus~ - r .
the transistor 58 is made OFF delayed by the time interval t1 from the recep-10 . tion for the time interval of about 100ms during which the content of s~ation select counter 18 corresponding to the received frequency is written in the memory device 56 consisting of MAOS element Q1~ ~
The MAOS element Qg~ which memorizes that any of memory devices 29 and 30 is operated is controlled by the ON and OFF operations t5 Or transistor 58 in the s~ame timing as that 8-bit MAOS elements Q1~
The write in operation of "1 " or '0l' to the MAOS element Qg is performed by a signal supplied to a terminal 73 and the read out dutput therefrom is delivered to a terminal 74~ The terminal 73 is supplied with the output .,i .
/ ~rom the flip-rlop in the control circuit 20 which memori~es which memory device i9 u9edO The output appeared at the terminal 74 is used to control the flip-~lop upon the supply of powercl However~ it is not limlted to the reception that the memory device is changed~ so that a'trigger pulse genera~
ted at the change of memory device is apphed to the mo~ostable multivibrator i ' , ~ '. :' .
~: 71 through terminals 75. ~ ~ ~
:25 As mentioned aboveg since non-voll:aic memory elements are used ~ ::
in the memory device 56, the memori~ed content therein is not erased even --i~ the ~upply o~ power is cut off~ When the power is supplied again~ the ~ :~- content ~tored in the memory device 56 is automatically preset in the station ~ : :
~elect counter 18 and a memory element to be used is pointed outO If the .
received station is memori~ed in the ~memory device 56 as described above~

.
.

.

7~

when the power supply is stopped once and thereafter the power is supplied again, it is omitted to search the station received previously~ Instead of making the memory de~ice 56 of non-voltaic elements~ if a separate electric power source is provided for the memory device 56, the s;ame effect can be achieved.
An example of the muting circuit 4 will be now described with ;~
reference to Figure 13 in detail. In Figure 133 reference letter T indi~
oates an N-channel type FET, 77 an input terminal connected through a capa-, . .:
citor 79 to the drain electrode of FET T and 78 an output terminal con-nected through a capacitor 80 to the source electrode of FET T . To a ~.
terminal 69 which is led out from the source electrode of FET T through a diode 80~ there is applied a signal which becomes 0V at once when being not tuned but becomes a predetermined level (1 5V) delayed by the time inter-val t1 when being tuned' as shown in Figure 12D,, Accordingly, during reception the FET T becomes ON and a low frequency signal is delivered to ~1 .
the output terminal 78 to produce a sound, while during selection of stations ! the FET T becomes OFF a~d hence no sound is produced~, Witb the muting oircuit 4 shown in Figure ~3~ a predetermined DC voltage from the power source Vcc is applied to the drain and source electrodes of FET T through resistors 83 and 84, respectively, after being divided bg resistors 81 and 82O In this case~ the connection point between resistors 83 and 84 is grounded through a capacitor 85.
. : .
On the assumption that the DC potentials at the drain and solLrce . . .. ~ , electrodes of FET T are made equal3 when the FET T is changed îrom ~5~ OFF-state to ON-state, Yariation of DC potential is avoided and hence c1ick .
noise i8 also prevented rrom being generated~ The capacitor 85 serves to ` ~
avoid that the low frequency signal from the input terminal 77 leaks to 1he ;
output terminal 78 when the FET T is OFF~

A~ described sbove~ since the muting oircuit 4 iq controlled by 30 the muting control clrcuit 76~ the muting operation can be carried out suitabl~.
''s' ' ~.' . i ' .

'î'6~i That is~ the signal obtained at the terminal 69 shown in Figure 1 21D is fallen down instantaneously when being deviated from tuning but rises up after being delayed by the time interval tl when being tunedl, Accordinglyg the disadvantage~ which occurs in the prior art where the muting operation is carried out based upon the output from the IF amplifier 2 or frequency modu-lator 3 and the DC component is varied when a sound is produced to sound a cliclc noise through a speaker~ is avoided by the present inventionO
Further~ with the invention since the low frequency signal is passed after being delayed by the time interval t1 from the tuning~ the phase-locked loop consisting of phase comparator 10 and so on becomes operative at sufficiently stable condition or after tuning being completed9 and hence the generation of click noise is prevented complete~y., .
Further~, with the present invention such a muting control is carried out that no soun~:l is produced when the power source is connected ¦ 15 and disconnected~ which is though not shown, With the present invention exemplified as above~ the FM receiver (synthesizer receiver) which uses the frequency synthesizing techniques .
is provided. By varying the divlde ratio N of N divider 9 the local osci-.~l llation frequency of front end 1 is changed and hence the received channel l 20 is switched, The divide ration N Or--divider 9 is determined by the l content which corresponds to the received frequency in each channel of station select counter 18 by 1: 1~ The content of station select counter 18 . is converted to a deoimal output by binary-decimal decoders 21a and 21b~
and the deoimal output is used to drive the panel display device 47 and to ..
1. . .
point the add~esses of memory devices 29 and 30 of 100 bitso The push button switches are provided in association with the respecti~e neon lamps :
or panel display deYice 47 and when the push~button switch is pushed down iLt i~ detected by the detecting circuit 48" The memory 56 is provided ;n .
sssociation with the station select counter 18 and the content of station : 30 select counter 18 in correspondenoe with the received frequency is automatically , .
--2~

....... ,.. , , ~ .. . . .... ... .. . .

7~
stored in the memory 56 the content of which is changed at every time when the received frequency is switched The manner how to control the synthesizer receiver including the memories 29 and 30, panel display device 47 and memo~y 'j6 by the control circuit 20 with operating button group will be now described. With the present invention the panel display device 47 is provided on the ~ront panel~
and a power source switch 90 and si~ button switches 913 92, 93, 94, 95 and 96 are provided on the front panel around the display device 47, as shown in Figure 140 Marks "SEARCH"~ "NEXT", "AUTO", "PROGRAM", "INI' and "RESET" are made in connection with the switches 91 to 96. When - these button switches are operated~ the receiver is ¢ontrolled by the control oircuit 20 to perform predeter~nined functionsO
These functions will be now described on their outline flrstlyO
The button switch 9 (SEARCH~ is operated in the case that the received rrequency is switched from a certain frequency to another frequency. At - ;
this time a frequency which could be received or a frequency which is programmed is displayed by a lamp of the display device 47 corresponding ;
theretoO The button switch 92 (NEXT) is pushed down when the frequency displayed on the display device 47 is required to be changed sequentially by one station~ The above conditions o~ receiverwill be referred to "SEARCH
MODE~ and ~NEXT MODE~ respectivelyO The button switches 93 (AUTO) ; and 94 (PROGRAM) are used to point which of the memory devices 29 or 30 ~ ;
iY used~, That is~ when the button switch 93 is pushed down~, the memory device 29 is made operative and at this time all of the stations capable of :,, . ,~ , .
25 being received are displayed on the panel display device 47" while when the button switch 94 is pushed down the memory devlce 30 is made operative and `~ at this time the staticns which are programmed are displayed on the display davice 47. These conditions will b,e referred as "~UTO MODE" and "PROG~AM MGDE"~ respectively. When the button switch 95 tTN) i~
30 operated durin~ the receptio~ of a certain ~requency signal~ the receivled ` ~
. ' ; - 27 -76~i -frequency signal is stored in the memory device 30 to achi.eve the prog~amme"
When the button switch 96 (RESET) is pushed down during the "AUTO MODE", a received band between 88.1 and 107,9MHz is swept and a frequency which has an electric field over a predetermined one and is capable of being re- . -cei~ed is automatically written in the memory device 290 Thereafter~ the mode is changed to "SEARCH MODE~" and the stored îrequency is displayed on the display device 47~ While~ when the button switch 96 is pushed dow.n during "PROGRAM MODE", the memory device 30 is made clear or the - . -content stored therein is erased~ ~:
Figure 16 is a logic systematic diagram for showing whole of . ~ :~
the control circuit 20 which achieves the above functions, In Figure 16~
re~erence numerals 91a~ 92~-u~ 96a show terminals to which the outputs of button 9witches 91~ 92~ ~oo~ 96 are applied~ respectively, and a termi-nal 97a (START) is supplied with the outputs at the common contacts Mol . :
M~ o~ Mg of displaydevice 47 ~refer to Figure 10)0 The above button switches are a single-pole single -throw switch o~ non-lock typeO One contact of each switch is connected common and led out as a terminal 98~ - ;.
as shown in Figure 159 Whenthe terminal 98 is grounded as 0V (which will be hereinafter as to ~'0~ an output of 0V is obtained through any one of sw~tche~ while when the terminal 98 is supplied with~ for example~ 5V
(which will be hereinafter as to ~ no button switches are effectiveO
Further~ in Figure 16 reference numerals 100 and 101 indicate .i , .
3tation select pulse generators ~vhich are formed as astable multivibra~orsr .. respect~vely. The station select pulse generator 100 p:roduces a st~tion i25 select pulse o~ about 3KHz~ while the station select pulse generator 101 produces a station select pulse of about 17Hz~ said station select pulses ~ -being delivered to the terminal 20a" The pulse generators 100 and 101 start ; ~:
their oscillation when the control signal of "0" is applied thereto~ As mentioned previously~ the station seleot pulse is ~ed to the N divider 9 . 30 oP the station select counter 18~ To the terminal 36 there is applied the ' ' , ' : : . ' ~ ~ -7~5 read out signal from the memory device 29 or 30 (re~er to Figure 6)1 while îrom the terminal 35 there is obtained a signal which is used to control whether lamp of display device 47 is lit or not by the output from the decoder 21b ~refer to Figure 5)0 A terminal 55 is the output terminal of detector cir-;5 cuit 48 (refer to Figure 4~ which detects that any of lamp switches in the display device 47 is pushedO Reference numeral 102 is such a terminal that when it is "0" the content of station select counter 18 is ~;00~ or the counter 18 is made clear and the receiving frequency becomes to 8801MHzo Reîe-rence numeral 103 indicates a terminal to which a carry signal "1 " for the .:
10 counter~ generated at the state where the content of counter 18 is 99 ~ is fed~ and 104 a detector circuit the output of which becomes ~0" when the IF ampliYier 2 produces a sufficient IF output at tuning~ but becomes " I ~i at not tuningO In Figure 16 reference numerals 38a and 38b are the memory ;`
control circuits (refer to Figure 8) îor memory devices 29 and 30, When the signal ~0~ is applied to the terminals 37bg the memory device~ are made ' ,: -operative while when the terminals 37a are at "0" and '~1", the write in and re~Ld out operations are achieved, When the terminals 37c are at "1", erase Or memory is carried out.
i'. ... . .
The operation by the actuation of each button switch will herein-20 after be de9cribed. With reference to Figure 17~ a description will be given first Or the ~AUTO RESET" mode Or operation in which the button switch 96 (RESET) is depressed in the "AUTO" mode of operation. In the ''AUTO"
mode of operation~ s~nce the output ~t the terminal 93a is held at the level "0~' by the actuation ot the switch 93~ the flip-flop FF1 is reset~ whose output Q is at the level "0" and whose output Q is the at $he level ~ The output Q is applied to the terminal 37b of the memory control circuit 38a to hold the memor~r device 29 in its operativ~ condihon.
Then~ upon depression o~ the butto~ switch 96, tne ou~put at the terminal 96a ha~ the level "0" as shown in Figure 17A. This output is differentiated and the resulting differentiated output depicted in Figure 17B
is applied to a NOR gate G11 and the output there~rom~ shown in FigFe 17C~

--29 ~

is supp~ied to an inverter I7~ the terminal S of a flip-flop FF5 and the terminal 37c of the m0mory control circuit 38a and the terminal E1~ By the output derived at the $erminal 102 of the inverter I7, depicted in Figure 17K, the station select counter t8 is cleared to alter its content to ~00 and the flip-nop FF5 is set at the fall of the output from the inverter I7 and its output Q becomes "0" as shown in Figure 17D and~ further~ the content of the memory 29 is entirely eraseda Since the output Q from the flip-flop FF5 becomes "0", the station select pulse generator 101 . :
starts to oscillate to generate a station select pulse such as shown in .. ; .
Figure 17E which has a frequency of 17Hz. When the output Q is led to -a terminal 9~ through an inverter I8, even if the other buttons are aatuated .
in the AUTO RESET" mode, it is made ineffective~ The station select pulse depicted in Figure 17E is ~ed to the terminal 20a through an ~ND
- . . .
gate G4 and then supplied to the station select counter 180 Where the - . .
~15 station select pulse generator 100 does not oscillate~ the output îrom the ANl) gate G4 is "1~ so that this AND gate is openu Consequently~ the con- `
tent of the station select counter 18 sequentially changes from too~ to~o1J, Co2 Of course~ the received Irequency is varied at intervals OI 200KHz . 20 wlth the change in the content o~ the station select oounter 18. When the .. received frequency has reaohed a valua at which a sufficient intermediate ~requency output can be obtained, an output at the level "0" depicted in . ~ . Figure 17F is derived from a deteotor OLrCUit 104, The outputs from the : . . .
detector circuit 104 and the station select pulse generator 101 are both :~
applied to an OR gate G12 to deriva therei~om an output shown in Figure ~ -. 17G~ which i5 applied to the te~minal 37a of ~the mem~ry contro} circuit 38a"
Accordillgly~ this trequency is ~vritten i~ the memory device 299 Namely~
: a ~llustrated in Figura 17H, when the button 96 is depressed" the outppt . . .:
derivad at the t~rminal M1 ~ the colltrol circuit 38a~ which is applied to the - 30 . memor~r dsvice 2~ becomes -40V and the content of the memory devioe 29 :-: :
. .: .
. --30 -- -.
~'~ . . . ...
. .

is entirely erased and then the received frequency band is swept9 by which receivable frequencies are sequentially written in the memory device 290 When the received frequency band has thus been entirely swept, ~ carry pulse for the station select counter 18, depicted in Figure 17I~ is ..
delivered to the terminal 103, The carry pulse is clifferentiated and applied to the reset terminal of the flip-flop FF5 to reset it at the fall of the cliffe-rentiated pulse and the output Q from the ~lip-flop FF5 becomes 1l1 " as `
illustrated in Figure 17Do Thus~ the station select pulse generator 101 stops its oscillation as shown in Figure 17E, terminating the sweeping ope-ration.
Furthert in the above 'IAUTO RESET~ mode~ a flip-flop FF2 is reset by the output from the inverter I7~ that is~ the signal depictecl in Figure 17K~ and the output Q from the flip-flop FF2 becomes "1 " as shown in Figure 17J~ An output derived from the station select pulse generator 101 after completion of the sweeping operation9 which is opposite in pola rity to the output Q from the flip-flop FF2~, is dif~erentiated and applied through the AND gate C2 to the flip-flop FF2 to set it and its output Q
become~ '!0". The control of the nip-flop FF2 is the same as that i~l the SEARCH" mode in whioh the button switch 91 is depressed as will be des-oribed later on. Upon completion of the sweep in the received ~requency band~ the operation i9 automatically altered to the "SEARCH" modeO The above description has been given in connection with the case where the button ~; ~ switch 96 (~ESET) is~depressed in the ~AUTO" mode. T~Lrning now to Figure 189 a description will be made with regard to the case where the J 25 button switch 96 is depressed in the "PROGRAM" modeO
the ~PROGRAMI' mode, by the actuatlon Or the button switch 94~ the potential at the terminal 94a becomes ~'0~ as depicted in Figure 18~ an~l the fllp-nop FF1 is set and its output Q bscomes "0"~ Consequently~
the output Q is applied to the terminal 37b of ;the memory control circult 38b~ thereby pUttiflg the ~lemory device 30 in its operative conditionl, Then~

, . ~ .

depressing the button switch 96 as shown in Figure 18B9 a difEerentiated pulse such as depicted in Figure 18C, which is derived at the fall of the ~.
output at the terminal 96a, is applied to a NOR gate G10 to derive there- -~- ~rom an output such as shown in Figure 18Do The output thus obtained from :
5 the NOR gate G10 is appl~ed to the terminal 37c of the melmory control circuit 38b and the terminal E29 by which the content of t.he memory deYice 30 is erased. . ~ ..
The output Q o~ the flip-flop FF1 I which stores whether the memory device 29 (AUTO MoDE3; or 30 (PROGRAM MODE) is operative, is led to ~ .
1 0 a terminal 73 to store the operative condition of the memor~ device in the MAOS element of the 9th bit of the memory device 56~ Namely~, the output . .`
Q of the flip-flop FF1 is "1~' or "2" dependent in whether the memory de~ice 29 or 30 i~ in it~ operatire condition" At the same time~ the outputs Q and Q Or the flip-flop FF1 are applied to the terminals 105 and 106 through . . ~.
15 the inverters I3 and I4~ respectively9 and lamps~ which are proYided in assooiation with the button switches 93 and 94, are turned on and off under ~ the control of.the outputs derived at the terminals 105 and 1069 ; ::
:. . Referring now to Figure 19~ a descriptioQ will be gi~en with :.
~ regard to the case where the received frequerlcy stored in the memory : ~20 device 29 in the aforesaid "A;UTO RESET" mode or the content stored in :

the memory device 30 by the actuation of the button switch 95 (IN) ir~i the ~PRO(~RAM~ mode described later on its displayed on the panel display device 47 ('7SEARCH" mode) and any one of the indicated lamp switches is depressed `::
;: to receive the frequency ("SEARCH STOP" mode), :: .. .:
.~ , . .
Upon depression o$ the button switoh 91 (SEARCH)~ the output at the terminal 91a: becomes "0" as shown in Figure 19A~, Ths output at :~
tho terminal 91a is applied to the set terminal of the ïlip-flop FF~2 through : :

the AND gate G2 to ~et the flip-nop FF2~ whose output Q becomes "0" ~s depicted in Figure 1 9Bv (This condition is the same as that wheni the sweep ~ . :
-: 30: in the recei~ed îrequency band has been completed in the "AUTO l~ESET"

--3Z ~

~L~ 4 L~
mode,~, The output Q of the flip-flop FF2 is applied as a control signal to the station select pulse generator 100 through an AND gate G7 and an OR . . :
gate G8 and the station select pulse generator 100 is caused thereby to start :
osc;llation to generate a station select pulse such as depic:ted in Figure 19C, which normally has a period t2 of about 3msO The station select pulse is applied to the AND gate G4, Since the other input to the AND gate G4 is . .
the station select pulse is applied from the terminal 20a to the station ~ ~ .
select counter to switch the received frequency~
Now, let it be assumed that a read output depicted in Figure 1 9:D .
t0 is applied to the terminal 36 from the memory device 29 or 30. In the ~:
present example~ the read output is continuously applied from the memol:y . :
device 29 or 30. The read output is applied through the AND gate G3, an inverter I10 and a differentiation circuit to a monostable multivibrator 107 :
to trigge~ it. The monostable multivibrator 107 has a delay time t3 o:l 5ms and is controlled by the output Q of a flip-~lop FF4, Namely~ the monostable multivibrator 107 generates:a pulse only when the output Q of ; the ~lip-flop FF4 is "1"~ In the present example, since the output at the terminaI 91a (Figure 19A) is supplied to an AND gate q5~ the output .' . derived tberefrom is "0" ~ by which the flip-flop FF~ is reset to derive . 20 ~herefrom the output Q at the level "1 " and its output Q at the level "0" as shown in Figure 19Io The positive o~tput from the monostable multivibrator 107~
shown in Figure 19F~ is applied through the OR gate G8 to ~he station select pulse generator 100 to stop its o~cillation during the delay time .
pe~iod t3~, Further~ the output trom the OR gate G8 is applied through ~, n OR gate Gg to the tern~inal 35 to derive thereat an output depicted in Figure 19G. ~IVhen the output at the terminal 35 is 111-lJ the transistor 34 in :
.1 Figure 5 is turned ON and,. only at this time, the corresponding lamp switch ~ .
'; . o~ tha display de~ice 47 is lighted, Wlien the output from the monostable ` .
.
~ `30 multivibrator 107 is altered to "0" after the time period t39 the station :!:
: i `
1 . _ 33 _ ~ ~
.. . .

~. ~

~elect pulse genera,tor 100 resumes its oscillation to repeat the above ope- :
ration, In this case~ i~ the read output from the memory device 29 or 30 remains at the level "1" as shown in Figure 19D~ there is the possibility that the monostable multivibrator 107 is not triggered l'o eliminate such possibilityJ the AND gate G3 is provided~ which is supplied with the . .:
memory read output from the terminal 36 and the output from the station select pulse generator 100 to provide an output such as shown in Figure ~ ' 19E~ which is differentiated and by which the monostable multivibrator 107 ~ :
;.10 is triggeredO
Then~ depressing any one of the lighted lamp switches of the display device 47, it is detected by the detector circuit ~8 (refer to Figure

4) and the output at the terminal 55 is altered from "1 " to "0" as illustrated ::
in'Figure 19H Thus~ the flip-~lop FF2 is reset to alter its output Q to . ~
~ as shown in Figure 19B~, With this oper~tion~ the oscillation oî the ' :' ... .. . . ..
:: statior~ select pulse generator 100 is stopped and the frequency correspond~
" ing to the depressed lamp switch is'received and~ at the same time~ this '~
`l lamp switch is lightedO ..
In the l'SEARCH STOP" mode of operation described above~ by ':::
once employing the ~'SEARCH" modeJ all the receivable frequencies or . ~ ' :
programmed' frequenoies are displayed on the panel display device ~7 and .. ' . ' then a desired one Or the frequencies is receivedO Therefore, it might be said that the above operation mode is the most oommon one~ In practice~
however~ whe~e a desired recei~ed frequency is previously k~o~n or where .:: ' : 25 a station oannot be completely received but is desired to be recei~red~ it ~ :
. . , :
is de~irable that the desired frequency can be recai~ed by depressing a lamp vitch corresponding to the desLred frequency on the display device 47 :, .
~' without usi~g the "SEARCH" mode of opera;tionO
To this end~ outputs of the common co~tacts Mo to ~ pro~sided in the panel display de vice 47 are employed, Namely~, depre~ising any one ~:
" :: .
, . . .
' ~ 34 ~

:: ' ~ t,f3~7~ ~
o the lamp switches onthe panel display device 47~ the output at the terminal 97a is altered from "1" to "0"~, The output at the terminal 97a is applied to the AND gate G2 through a chattering preventive circuit 108 and~ by the output of "1" derived from the AND gate G2~ the flip-flop FF2 is set, . .
performing the same operation as that in the aforesaid "SEARCH" mode i~
which the button switch 91a is depressedO Then~ the deslred ~requency ~ is received by the detected output from the termLnal 55 ~refer to Figure 1 g) .
In this case, however, the flip-flop FF4 is set and its output Q becomes .
"0"~ so that the monostable multivibrator 107 does not operate and the output ; 10 Q of the flip-flop FF4 is led to the terminal 35 through the OR gate G9, thus `-. lighting all of the neon lamps of the panel display device 470 The reason why ill the neon lamps are lighted~is to enable detection of the depression o~ any lamp switches~ With the provision of such oommon contacts Mo to M9 in the display device 47~ it is possible to receive any frequency onl~r by . 15 depressing the corresponding lamp switch regardless of the conte~t of the memory 29 or 3~
Now~ the "NE:XT~' mode OI operation in which the button 3witch 92 (NEXT) is actuated will be described~ In this mode.of operation~ the output at the terminal 92a is altered from ~1" to ~0~ which is then rendered into ~ by an inverter I6~ the output ~rom which is differentiated and applied ; to the set terminal of a flip-flop FF3 to set the flip-flop FF30 Consequently~
its output Q becomes "0" and the outputs ~rom the AND gate G7 and the OR
. gate G8 become "0"~ As a result of this~ the station select pulse gene~
rator 100 starts its osci~lation to produce the station select pulse and the . --~
.:~7~ 25 ~weeping operation is achieved. When the read output from the memory devi~e- 29 or 30 through the terminal 36 becomes "1~ the monostable multi~
. . . .
. . . vibrator 107 is triggered and its ~egative output is supplied to au AND ~ :
gate Ç;6 Accordingly~ the output from the AND gate G6 becomes ~0~ by which the flip-nOp FF3 is reset to alter its output Q to ~ Thus~ the . .
~; 30 sts~ioQ s7elect pulse generator 100 stop~7 oscillatior~ to provide the receivi~g :, . . , :~
: .:

:

7~S

conditionu Depressing the button switch 92 again9 the next frequency stored in the memory device 29 or 30 is received~ ~:
In the above-described "SEARCH" mode and "NEXT" modes of operation and in the "START" mode of operation employinlg the common ~ :
contacts of the panel display device 47, a signal of the level "1~ is applied to the terminal 37a of the memory control circuit 38a or 38b to read the content of the memory device 29 or 30.
Turning now to Figure 20~ a description will be given oî the .
"IN" mode of operation in which a desired frequency is written in the memory device 30 by actuating the button switch 95 (IN), Depressing the button switch 95 when a frequency desired to be written in the memory device 30 is being received~ the output at the terminal 95a is altered from "1~' to "0"
as depicted inFigure 20A, The output at the ter~ninal 95a is differentiated and supplied to the set terminal of the flip-flop FFl and~ at the same time to an inverter I1 o Consequently~ the flip-flop FF1 is set at the fall of the ;difrerentiated output applied thereto and the output Q of the nip-fll~p FF~
becomes "1" as shown in Figure 20Bc~ The output 52 (~0") of the flip-nop :
FF1 is applied to the terminal 37b of the memory control circuit 38b~ by which the memory device 30 is put in its operative condition but the memory device 29 is made in operative~ Further~ the inverter I1 derives there~
from an output depicted.in Figure 20C~ which is applied to an AND gate G
and dirferentiated~ an`d a differentiated pulse shown in Figure 20D is fed to a~ inverter I2 to derive thererom an output of the level "0" depicted in Figure 20E. The output from the inverter I2 is applied to the terminal 37a `. 25 Or the memory control circuit 38b3, thus wri~ing in the memory device 30 the - : :
; ~requency being receivedO Further~ the output from the inverter I2 is -~i . dlifferentiated to provide a differentiated pulse ~hown in Figure 20F~ which ~ ..
i~ supplied to an inverter I5 to derire therefrom an output "0" illus~ated in Figure 20G4 The output thus de~ved from the inverter I5 is applied tc> :the set termi~al of the nip-nOp FF2 to set the ~ip-nOp FF29 and hence ~ .

. ~

alter it3 output Q to "0" as depicted in Figure 20H~ With the alteration of the output Q from the nip-flop FF2 to "0", the station select pulse gene-rator 100 starts oscillation to bring about the aforesaid "SEARCH" mode ., Or operation and the frequency written in the memory device 30 is dis-played on the panel display device 47, ~:
The AND gate G1 is provided to prevent that even iî the button switch 95 is depressed in the "SEARCH" mode of operation~ that is~ while ; the output Q of the flip-flop FF2 is "0"~ the "IN~' mode of operation is brought - .
about9 ~, 10 The muting circuit 4 may be provided at the output end of the ' multiplex oircuit 5, It will be apparent that many modifications and variation~ may 7 be ef~ected without departing from the scope of the novel concepts of this inventionO

''. ' ' .'~ :." :'.'' .
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Claims (3)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A broadcast receiver comprising.
a) a front end having a variable local oscillator for generating a local frequency signal;
a programable divider consisting of dividing means and a counter, said dividing means operating to divide said local frequency signal in response to contents of said counter;
c) a pulse generator for producing a pulse which change the content of said counter;
d) a comparator for comparing the divided local frequency signal derived from said programable divider with a reference signal to produce a control signal to which said front end is tuned;
e) means for converting an output signal from said front end to a low frequency signal and then delivering said low frequency signal to output means;
f) a muting circuit connected to said means deliver-ing said low frequency signal; and g) means for controlling said muting circuit such that said low frequency signal is not delivered to said output means during a time interval in which the content of said counter is changed by the pulse from said pulse generator.

2. A broadcast receiver according to claim 1 wherein said means for controlling the muting circuit include a circuit which produces a square wave in accordance with the number of pulses from said pulse generator.

3. A broadcast receiver according to claim 2 wherein said means for controlling. the muting circuit further include a time constant circuit by which said square wave generating circuit generates a square wave with a time duration longer than a time duration corresponding to the number of pulses from said pulse generator.